LLVM  15.0.0git
AArch64AsmPrinter.cpp
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1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the AArch64 assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64MCInstLower.h"
17 #include "AArch64RegisterInfo.h"
18 #include "AArch64Subtarget.h"
26 #include "Utils/AArch64BaseInfo.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/BinaryFormat/COFF.h"
33 #include "llvm/BinaryFormat/ELF.h"
35 #include "llvm/CodeGen/FaultMaps.h"
42 #include "llvm/CodeGen/StackMaps.h"
44 #include "llvm/IR/DataLayout.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCInst.h"
49 #include "llvm/MC/MCInstBuilder.h"
50 #include "llvm/MC/MCSectionELF.h"
51 #include "llvm/MC/MCStreamer.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/MC/TargetRegistry.h"
54 #include "llvm/Support/Casting.h"
59 #include <algorithm>
60 #include <cassert>
61 #include <cstdint>
62 #include <map>
63 #include <memory>
64 
65 using namespace llvm;
66 
67 #define DEBUG_TYPE "asm-printer"
68 
69 namespace {
70 
71 class AArch64AsmPrinter : public AsmPrinter {
72  AArch64MCInstLower MCInstLowering;
73  StackMaps SM;
74  FaultMaps FM;
75  const AArch64Subtarget *STI;
76  bool ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags = false;
77 
78 public:
79  AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
80  : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
81  SM(*this), FM(*this) {}
82 
83  StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
84 
85  /// Wrapper for MCInstLowering.lowerOperand() for the
86  /// tblgen'erated pseudo lowering.
87  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
88  return MCInstLowering.lowerOperand(MO, MCOp);
89  }
90 
91  void emitStartOfAsmFile(Module &M) override;
92  void emitJumpTableInfo() override;
93 
94  void emitFunctionEntryLabel() override;
95 
96  void LowerJumpTableDest(MCStreamer &OutStreamer, const MachineInstr &MI);
97 
98  void LowerMOPS(MCStreamer &OutStreamer, const MachineInstr &MI);
99 
100  void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
101  const MachineInstr &MI);
102  void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
103  const MachineInstr &MI);
104  void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
105  const MachineInstr &MI);
106  void LowerFAULTING_OP(const MachineInstr &MI);
107 
108  void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
109  void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
110  void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
111 
112  typedef std::tuple<unsigned, bool, uint32_t> HwasanMemaccessTuple;
113  std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
114  void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
115  void emitHwasanMemaccessSymbols(Module &M);
116 
117  void emitSled(const MachineInstr &MI, SledKind Kind);
118 
119  /// tblgen'erated driver function for lowering simple MI->MC
120  /// pseudo instructions.
121  bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
122  const MachineInstr *MI);
123 
124  void emitInstruction(const MachineInstr *MI) override;
125 
126  void emitFunctionHeaderComment() override;
127 
128  void getAnalysisUsage(AnalysisUsage &AU) const override {
130  AU.setPreservesAll();
131  }
132 
133  bool runOnMachineFunction(MachineFunction &MF) override {
134  AArch64FI = MF.getInfo<AArch64FunctionInfo>();
135  STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
136 
137  SetupMachineFunction(MF);
138 
139  if (STI->isTargetCOFF()) {
140  bool Internal = MF.getFunction().hasInternalLinkage();
143  int Type =
145 
146  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
147  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
148  OutStreamer->EmitCOFFSymbolType(Type);
149  OutStreamer->EndCOFFSymbolDef();
150  }
151 
152  // Emit the rest of the function body.
153  emitFunctionBody();
154 
155  // Emit the XRay table for this function.
156  emitXRayTable();
157 
158  // We didn't modify anything.
159  return false;
160  }
161 
162 private:
163  void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
164  bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
165  bool printAsmRegInClass(const MachineOperand &MO,
166  const TargetRegisterClass *RC, unsigned AltName,
167  raw_ostream &O);
168 
169  bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
170  const char *ExtraCode, raw_ostream &O) override;
171  bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
172  const char *ExtraCode, raw_ostream &O) override;
173 
174  void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
175 
176  void emitFunctionBodyEnd() override;
177 
178  MCSymbol *GetCPISymbol(unsigned CPID) const override;
179  void emitEndOfAsmFile(Module &M) override;
180 
181  AArch64FunctionInfo *AArch64FI = nullptr;
182 
183  /// Emit the LOHs contained in AArch64FI.
184  void emitLOHs();
185 
186  /// Emit instruction to set float register to zero.
187  void emitFMov0(const MachineInstr &MI);
188 
189  using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
190 
191  MInstToMCSymbol LOHInstToLabel;
192 
193  bool shouldEmitWeakSwiftAsyncExtendedFramePointerFlags() const override {
194  return ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags;
195  }
196 };
197 
198 } // end anonymous namespace
199 
200 void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
201  const Triple &TT = TM.getTargetTriple();
202 
203  if (TT.isOSBinFormatCOFF()) {
204  // Emit an absolute @feat.00 symbol. This appears to be some kind of
205  // compiler features bitfield read by link.exe.
206  MCSymbol *S = MMI->getContext().getOrCreateSymbol(StringRef("@feat.00"));
207  OutStreamer->BeginCOFFSymbolDef(S);
208  OutStreamer->EmitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_STATIC);
209  OutStreamer->EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_NULL);
210  OutStreamer->EndCOFFSymbolDef();
211  int64_t Feat00Flags = 0;
212 
213  if (M.getModuleFlag("cfguard")) {
214  Feat00Flags |= 0x800; // Object is CFG-aware.
215  }
216 
217  if (M.getModuleFlag("ehcontguard")) {
218  Feat00Flags |= 0x4000; // Object also has EHCont.
219  }
220 
221  OutStreamer->emitSymbolAttribute(S, MCSA_Global);
222  OutStreamer->emitAssignment(
223  S, MCConstantExpr::create(Feat00Flags, MMI->getContext()));
224  }
225 
226  if (!TT.isOSBinFormatELF())
227  return;
228 
229  // Assemble feature flags that may require creation of a note section.
230  unsigned Flags = 0;
231  if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
232  M.getModuleFlag("branch-target-enforcement")))
233  if (BTE->getZExtValue())
235 
236  if (const auto *Sign = mdconst::extract_or_null<ConstantInt>(
237  M.getModuleFlag("sign-return-address")))
238  if (Sign->getZExtValue())
240 
241  if (Flags == 0)
242  return;
243 
244  // Emit a .note.gnu.property section with the flags.
245  if (auto *TS = static_cast<AArch64TargetStreamer *>(
246  OutStreamer->getTargetStreamer()))
247  TS->emitNoteSection(Flags);
248 }
249 
250 void AArch64AsmPrinter::emitFunctionHeaderComment() {
251  const AArch64FunctionInfo *FI = MF->getInfo<AArch64FunctionInfo>();
252  Optional<std::string> OutlinerString = FI->getOutliningStyle();
253  if (OutlinerString != None)
254  OutStreamer->GetCommentOS() << ' ' << OutlinerString;
255 }
256 
257 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
258 {
259  const Function &F = MF->getFunction();
260  if (F.hasFnAttribute("patchable-function-entry")) {
261  unsigned Num;
262  if (F.getFnAttribute("patchable-function-entry")
263  .getValueAsString()
264  .getAsInteger(10, Num))
265  return;
266  emitNops(Num);
267  return;
268  }
269 
270  emitSled(MI, SledKind::FUNCTION_ENTER);
271 }
272 
273 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
274  emitSled(MI, SledKind::FUNCTION_EXIT);
275 }
276 
277 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
278  emitSled(MI, SledKind::TAIL_CALL);
279 }
280 
281 void AArch64AsmPrinter::emitSled(const MachineInstr &MI, SledKind Kind) {
282  static const int8_t NoopsInSledCount = 7;
283  // We want to emit the following pattern:
284  //
285  // .Lxray_sled_N:
286  // ALIGN
287  // B #32
288  // ; 7 NOP instructions (28 bytes)
289  // .tmpN
290  //
291  // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
292  // over the full 32 bytes (8 instructions) with the following pattern:
293  //
294  // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
295  // LDR W0, #12 ; W0 := function ID
296  // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
297  // BLR X16 ; call the tracing trampoline
298  // ;DATA: 32 bits of function ID
299  // ;DATA: lower 32 bits of the address of the trampoline
300  // ;DATA: higher 32 bits of the address of the trampoline
301  // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
302  //
303  OutStreamer->emitCodeAlignment(4, &getSubtargetInfo());
304  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
305  OutStreamer->emitLabel(CurSled);
306  auto Target = OutContext.createTempSymbol();
307 
308  // Emit "B #32" instruction, which jumps over the next 28 bytes.
309  // The operand has to be the number of 4-byte instructions to jump over,
310  // including the current instruction.
311  EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
312 
313  for (int8_t I = 0; I < NoopsInSledCount; I++)
314  EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
315 
316  OutStreamer->emitLabel(Target);
317  recordSled(CurSled, MI, Kind, 2);
318 }
319 
320 void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
321  Register Reg = MI.getOperand(0).getReg();
322  bool IsShort =
323  MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
324  uint32_t AccessInfo = MI.getOperand(1).getImm();
325  MCSymbol *&Sym =
326  HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, IsShort, AccessInfo)];
327  if (!Sym) {
328  // FIXME: Make this work on non-ELF.
329  if (!TM.getTargetTriple().isOSBinFormatELF())
330  report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
331 
332  std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
333  utostr(AccessInfo);
334  if (IsShort)
335  SymName += "_short_v2";
336  Sym = OutContext.getOrCreateSymbol(SymName);
337  }
338 
339  EmitToStreamer(*OutStreamer,
341  .addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
342 }
343 
344 void AArch64AsmPrinter::emitHwasanMemaccessSymbols(Module &M) {
345  if (HwasanMemaccessSymbols.empty())
346  return;
347 
348  const Triple &TT = TM.getTargetTriple();
349  assert(TT.isOSBinFormatELF());
350  std::unique_ptr<MCSubtargetInfo> STI(
351  TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
352  assert(STI && "Unable to create subtarget info");
353 
354  MCSymbol *HwasanTagMismatchV1Sym =
355  OutContext.getOrCreateSymbol("__hwasan_tag_mismatch");
356  MCSymbol *HwasanTagMismatchV2Sym =
357  OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
358 
359  const MCSymbolRefExpr *HwasanTagMismatchV1Ref =
360  MCSymbolRefExpr::create(HwasanTagMismatchV1Sym, OutContext);
361  const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
362  MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
363 
364  for (auto &P : HwasanMemaccessSymbols) {
365  unsigned Reg = std::get<0>(P.first);
366  bool IsShort = std::get<1>(P.first);
367  uint32_t AccessInfo = std::get<2>(P.first);
368  const MCSymbolRefExpr *HwasanTagMismatchRef =
369  IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref;
370  MCSymbol *Sym = P.second;
371 
372  bool HasMatchAllTag =
373  (AccessInfo >> HWASanAccessInfo::HasMatchAllShift) & 1;
374  uint8_t MatchAllTag =
375  (AccessInfo >> HWASanAccessInfo::MatchAllShift) & 0xff;
376  unsigned Size =
377  1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
378  bool CompileKernel =
379  (AccessInfo >> HWASanAccessInfo::CompileKernelShift) & 1;
380 
381  OutStreamer->SwitchSection(OutContext.getELFSection(
382  ".text.hot", ELF::SHT_PROGBITS,
384  Sym->getName(), /*IsComdat=*/true));
385 
386  OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
387  OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
388  OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
389  OutStreamer->emitLabel(Sym);
390 
391  OutStreamer->emitInstruction(MCInstBuilder(AArch64::SBFMXri)
392  .addReg(AArch64::X16)
393  .addReg(Reg)
394  .addImm(4)
395  .addImm(55),
396  *STI);
397  OutStreamer->emitInstruction(
398  MCInstBuilder(AArch64::LDRBBroX)
399  .addReg(AArch64::W16)
400  .addReg(IsShort ? AArch64::X20 : AArch64::X9)
401  .addReg(AArch64::X16)
402  .addImm(0)
403  .addImm(0),
404  *STI);
405  OutStreamer->emitInstruction(
406  MCInstBuilder(AArch64::SUBSXrs)
407  .addReg(AArch64::XZR)
408  .addReg(AArch64::X16)
409  .addReg(Reg)
411  *STI);
412  MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
413  OutStreamer->emitInstruction(
414  MCInstBuilder(AArch64::Bcc)
416  .addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
417  OutContext)),
418  *STI);
419  MCSymbol *ReturnSym = OutContext.createTempSymbol();
420  OutStreamer->emitLabel(ReturnSym);
421  OutStreamer->emitInstruction(
422  MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
423  OutStreamer->emitLabel(HandleMismatchOrPartialSym);
424 
425  if (HasMatchAllTag) {
426  OutStreamer->emitInstruction(MCInstBuilder(AArch64::UBFMXri)
427  .addReg(AArch64::X16)
428  .addReg(Reg)
429  .addImm(56)
430  .addImm(63),
431  *STI);
432  OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSXri)
433  .addReg(AArch64::XZR)
434  .addReg(AArch64::X16)
435  .addImm(MatchAllTag)
436  .addImm(0),
437  *STI);
438  OutStreamer->emitInstruction(
439  MCInstBuilder(AArch64::Bcc)
441  .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
442  *STI);
443  }
444 
445  if (IsShort) {
446  OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWri)
447  .addReg(AArch64::WZR)
448  .addReg(AArch64::W16)
449  .addImm(15)
450  .addImm(0),
451  *STI);
452  MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
453  OutStreamer->emitInstruction(
454  MCInstBuilder(AArch64::Bcc)
456  .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
457  *STI);
458 
459  OutStreamer->emitInstruction(
460  MCInstBuilder(AArch64::ANDXri)
461  .addReg(AArch64::X17)
462  .addReg(Reg)
464  *STI);
465  if (Size != 1)
466  OutStreamer->emitInstruction(MCInstBuilder(AArch64::ADDXri)
467  .addReg(AArch64::X17)
468  .addReg(AArch64::X17)
469  .addImm(Size - 1)
470  .addImm(0),
471  *STI);
472  OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWrs)
473  .addReg(AArch64::WZR)
474  .addReg(AArch64::W16)
475  .addReg(AArch64::W17)
476  .addImm(0),
477  *STI);
478  OutStreamer->emitInstruction(
479  MCInstBuilder(AArch64::Bcc)
481  .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
482  *STI);
483 
484  OutStreamer->emitInstruction(
485  MCInstBuilder(AArch64::ORRXri)
486  .addReg(AArch64::X16)
487  .addReg(Reg)
489  *STI);
490  OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRBBui)
491  .addReg(AArch64::W16)
492  .addReg(AArch64::X16)
493  .addImm(0),
494  *STI);
495  OutStreamer->emitInstruction(
496  MCInstBuilder(AArch64::SUBSXrs)
497  .addReg(AArch64::XZR)
498  .addReg(AArch64::X16)
499  .addReg(Reg)
501  *STI);
502  OutStreamer->emitInstruction(
503  MCInstBuilder(AArch64::Bcc)
505  .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
506  *STI);
507 
508  OutStreamer->emitLabel(HandleMismatchSym);
509  }
510 
511  OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXpre)
512  .addReg(AArch64::SP)
513  .addReg(AArch64::X0)
514  .addReg(AArch64::X1)
515  .addReg(AArch64::SP)
516  .addImm(-32),
517  *STI);
518  OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXi)
519  .addReg(AArch64::FP)
520  .addReg(AArch64::LR)
521  .addReg(AArch64::SP)
522  .addImm(29),
523  *STI);
524 
525  if (Reg != AArch64::X0)
526  OutStreamer->emitInstruction(MCInstBuilder(AArch64::ORRXrs)
527  .addReg(AArch64::X0)
528  .addReg(AArch64::XZR)
529  .addReg(Reg)
530  .addImm(0),
531  *STI);
532  OutStreamer->emitInstruction(
533  MCInstBuilder(AArch64::MOVZXi)
534  .addReg(AArch64::X1)
536  .addImm(0),
537  *STI);
538 
539  if (CompileKernel) {
540  // The Linux kernel's dynamic loader doesn't support GOT relative
541  // relocations, but it doesn't support late binding either, so just call
542  // the function directly.
543  OutStreamer->emitInstruction(
544  MCInstBuilder(AArch64::B).addExpr(HwasanTagMismatchRef), *STI);
545  } else {
546  // Intentionally load the GOT entry and branch to it, rather than possibly
547  // late binding the function, which may clobber the registers before we
548  // have a chance to save them.
549  OutStreamer->emitInstruction(
551  .addReg(AArch64::X16)
553  HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE,
554  OutContext)),
555  *STI);
556  OutStreamer->emitInstruction(
557  MCInstBuilder(AArch64::LDRXui)
558  .addReg(AArch64::X16)
559  .addReg(AArch64::X16)
561  HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12,
562  OutContext)),
563  *STI);
564  OutStreamer->emitInstruction(
565  MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI);
566  }
567  }
568 }
569 
570 void AArch64AsmPrinter::emitEndOfAsmFile(Module &M) {
571  emitHwasanMemaccessSymbols(M);
572 
573  const Triple &TT = TM.getTargetTriple();
574  if (TT.isOSBinFormatMachO()) {
575  // Funny Darwin hack: This flag tells the linker that no global symbols
576  // contain code that falls through to other global symbols (e.g. the obvious
577  // implementation of multiple entry points). If this doesn't occur, the
578  // linker can safely perform dead code stripping. Since LLVM never
579  // generates code that does this, it is always safe to set.
580  OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
581  }
582 
583  // Emit stack and fault map information.
584  emitStackMaps(SM);
585  FM.serializeToFaultMapSection();
586 
587 }
588 
589 void AArch64AsmPrinter::emitLOHs() {
591 
592  for (const auto &D : AArch64FI->getLOHContainer()) {
593  for (const MachineInstr *MI : D.getArgs()) {
594  MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
595  assert(LabelIt != LOHInstToLabel.end() &&
596  "Label hasn't been inserted for LOH related instruction");
597  MCArgs.push_back(LabelIt->second);
598  }
599  OutStreamer->emitLOHDirective(D.getKind(), MCArgs);
600  MCArgs.clear();
601  }
602 }
603 
604 void AArch64AsmPrinter::emitFunctionBodyEnd() {
605  if (!AArch64FI->getLOHRelated().empty())
606  emitLOHs();
607 }
608 
609 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
610 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
611  // Darwin uses a linker-private symbol name for constant-pools (to
612  // avoid addends on the relocation?), ELF has no such concept and
613  // uses a normal private symbol.
614  if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
615  return OutContext.getOrCreateSymbol(
616  Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
617  Twine(getFunctionNumber()) + "_" + Twine(CPID));
618 
619  return AsmPrinter::GetCPISymbol(CPID);
620 }
621 
622 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
623  raw_ostream &O) {
624  const MachineOperand &MO = MI->getOperand(OpNum);
625  switch (MO.getType()) {
626  default:
627  llvm_unreachable("<unknown operand type>");
629  Register Reg = MO.getReg();
631  assert(!MO.getSubReg() && "Subregs should be eliminated!");
633  break;
634  }
636  O << MO.getImm();
637  break;
638  }
640  PrintSymbolOperand(MO, O);
641  break;
642  }
644  MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
645  Sym->print(O, MAI);
646  break;
647  }
648  }
649 }
650 
652  raw_ostream &O) {
653  Register Reg = MO.getReg();
654  switch (Mode) {
655  default:
656  return true; // Unknown mode.
657  case 'w':
659  break;
660  case 'x':
662  break;
663  case 't':
665  break;
666  }
667 
669  return false;
670 }
671 
672 // Prints the register in MO using class RC using the offset in the
673 // new register class. This should not be used for cross class
674 // printing.
675 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
676  const TargetRegisterClass *RC,
677  unsigned AltName, raw_ostream &O) {
678  assert(MO.isReg() && "Should only get here with a register!");
679  const TargetRegisterInfo *RI = STI->getRegisterInfo();
680  Register Reg = MO.getReg();
681  unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
682  if (!RI->regsOverlap(RegToPrint, Reg))
683  return true;
684  O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
685  return false;
686 }
687 
688 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
689  const char *ExtraCode, raw_ostream &O) {
690  const MachineOperand &MO = MI->getOperand(OpNum);
691 
692  // First try the generic code, which knows about modifiers like 'c' and 'n'.
693  if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
694  return false;
695 
696  // Does this asm operand have a single letter operand modifier?
697  if (ExtraCode && ExtraCode[0]) {
698  if (ExtraCode[1] != 0)
699  return true; // Unknown modifier.
700 
701  switch (ExtraCode[0]) {
702  default:
703  return true; // Unknown modifier.
704  case 'w': // Print W register
705  case 'x': // Print X register
706  if (MO.isReg())
707  return printAsmMRegister(MO, ExtraCode[0], O);
708  if (MO.isImm() && MO.getImm() == 0) {
709  unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
711  return false;
712  }
713  printOperand(MI, OpNum, O);
714  return false;
715  case 'b': // Print B register.
716  case 'h': // Print H register.
717  case 's': // Print S register.
718  case 'd': // Print D register.
719  case 'q': // Print Q register.
720  case 'z': // Print Z register.
721  if (MO.isReg()) {
722  const TargetRegisterClass *RC;
723  switch (ExtraCode[0]) {
724  case 'b':
725  RC = &AArch64::FPR8RegClass;
726  break;
727  case 'h':
728  RC = &AArch64::FPR16RegClass;
729  break;
730  case 's':
731  RC = &AArch64::FPR32RegClass;
732  break;
733  case 'd':
734  RC = &AArch64::FPR64RegClass;
735  break;
736  case 'q':
737  RC = &AArch64::FPR128RegClass;
738  break;
739  case 'z':
740  RC = &AArch64::ZPRRegClass;
741  break;
742  default:
743  return true;
744  }
745  return printAsmRegInClass(MO, RC, AArch64::NoRegAltName, O);
746  }
747  printOperand(MI, OpNum, O);
748  return false;
749  }
750  }
751 
752  // According to ARM, we should emit x and v registers unless we have a
753  // modifier.
754  if (MO.isReg()) {
755  Register Reg = MO.getReg();
756 
757  // If this is a w or x register, print an x register.
758  if (AArch64::GPR32allRegClass.contains(Reg) ||
759  AArch64::GPR64allRegClass.contains(Reg))
760  return printAsmMRegister(MO, 'x', O);
761 
762  // If this is an x register tuple, print an x register.
763  if (AArch64::GPR64x8ClassRegClass.contains(Reg))
764  return printAsmMRegister(MO, 't', O);
765 
766  unsigned AltName = AArch64::NoRegAltName;
767  const TargetRegisterClass *RegClass;
768  if (AArch64::ZPRRegClass.contains(Reg)) {
769  RegClass = &AArch64::ZPRRegClass;
770  } else if (AArch64::PPRRegClass.contains(Reg)) {
771  RegClass = &AArch64::PPRRegClass;
772  } else {
773  RegClass = &AArch64::FPR128RegClass;
774  AltName = AArch64::vreg;
775  }
776 
777  // If this is a b, h, s, d, or q register, print it as a v register.
778  return printAsmRegInClass(MO, RegClass, AltName, O);
779  }
780 
781  printOperand(MI, OpNum, O);
782  return false;
783 }
784 
785 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
786  unsigned OpNum,
787  const char *ExtraCode,
788  raw_ostream &O) {
789  if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
790  return true; // Unknown modifier.
791 
792  const MachineOperand &MO = MI->getOperand(OpNum);
793  assert(MO.isReg() && "unexpected inline asm memory operand");
794  O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
795  return false;
796 }
797 
798 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
799  raw_ostream &OS) {
800  unsigned NOps = MI->getNumOperands();
801  assert(NOps == 4);
802  OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
803  // cast away const; DIetc do not take const operands for some reason.
804  OS << MI->getDebugVariable()->getName();
805  OS << " <- ";
806  // Frame address. Currently handles register +- offset only.
807  assert(MI->isIndirectDebugValue());
808  OS << '[';
809  for (unsigned I = 0, E = std::distance(MI->debug_operands().begin(),
810  MI->debug_operands().end());
811  I < E; ++I) {
812  if (I != 0)
813  OS << ", ";
814  printOperand(MI, I, OS);
815  }
816  OS << ']';
817  OS << "+";
818  printOperand(MI, NOps - 2, OS);
819 }
820 
821 void AArch64AsmPrinter::emitJumpTableInfo() {
822  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
823  if (!MJTI) return;
824 
825  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
826  if (JT.empty()) return;
827 
828  const TargetLoweringObjectFile &TLOF = getObjFileLowering();
829  MCSection *ReadOnlySec = TLOF.getSectionForJumpTable(MF->getFunction(), TM);
830  OutStreamer->SwitchSection(ReadOnlySec);
831 
832  auto AFI = MF->getInfo<AArch64FunctionInfo>();
833  for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
834  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
835 
836  // If this jump table was deleted, ignore it.
837  if (JTBBs.empty()) continue;
838 
839  unsigned Size = AFI->getJumpTableEntrySize(JTI);
840  emitAlignment(Align(Size));
841  OutStreamer->emitLabel(GetJTISymbol(JTI));
842 
843  const MCSymbol *BaseSym = AArch64FI->getJumpTableEntryPCRelSymbol(JTI);
844  const MCExpr *Base = MCSymbolRefExpr::create(BaseSym, OutContext);
845 
846  for (auto *JTBB : JTBBs) {
847  const MCExpr *Value =
848  MCSymbolRefExpr::create(JTBB->getSymbol(), OutContext);
849 
850  // Each entry is:
851  // .byte/.hword (LBB - Lbase)>>2
852  // or plain:
853  // .word LBB - Lbase
854  Value = MCBinaryExpr::createSub(Value, Base, OutContext);
855  if (Size != 4)
857  Value, MCConstantExpr::create(2, OutContext), OutContext);
858 
859  OutStreamer->emitValue(Value, Size);
860  }
861  }
862 }
863 
864 void AArch64AsmPrinter::emitFunctionEntryLabel() {
865  if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall ||
866  MF->getFunction().getCallingConv() ==
868  STI->getRegisterInfo()->hasSVEArgsOrReturn(MF)) {
869  auto *TS =
870  static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
871  TS->emitDirectiveVariantPCS(CurrentFnSym);
872  }
873 
875 }
876 
877 /// Small jump tables contain an unsigned byte or half, representing the offset
878 /// from the lowest-addressed possible destination to the desired basic
879 /// block. Since all instructions are 4-byte aligned, this is further compressed
880 /// by counting in instructions rather than bytes (i.e. divided by 4). So, to
881 /// materialize the correct destination we need:
882 ///
883 /// adr xDest, .LBB0_0
884 /// ldrb wScratch, [xTable, xEntry] (with "lsl #1" for ldrh).
885 /// add xDest, xDest, xScratch (with "lsl #2" for smaller entries)
886 void AArch64AsmPrinter::LowerJumpTableDest(llvm::MCStreamer &OutStreamer,
887  const llvm::MachineInstr &MI) {
888  Register DestReg = MI.getOperand(0).getReg();
889  Register ScratchReg = MI.getOperand(1).getReg();
890  Register ScratchRegW =
891  STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
892  Register TableReg = MI.getOperand(2).getReg();
893  Register EntryReg = MI.getOperand(3).getReg();
894  int JTIdx = MI.getOperand(4).getIndex();
895  int Size = AArch64FI->getJumpTableEntrySize(JTIdx);
896 
897  // This has to be first because the compression pass based its reachability
898  // calculations on the start of the JumpTableDest instruction.
899  auto Label =
900  MF->getInfo<AArch64FunctionInfo>()->getJumpTableEntryPCRelSymbol(JTIdx);
901 
902  // If we don't already have a symbol to use as the base, use the ADR
903  // instruction itself.
904  if (!Label) {
905  Label = MF->getContext().createTempSymbol();
906  AArch64FI->setJumpTableEntryInfo(JTIdx, Size, Label);
907  OutStreamer.emitLabel(Label);
908  }
909 
910  auto LabelExpr = MCSymbolRefExpr::create(Label, MF->getContext());
911  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR)
912  .addReg(DestReg)
913  .addExpr(LabelExpr));
914 
915  // Load the number of instruction-steps to offset from the label.
916  unsigned LdrOpcode;
917  switch (Size) {
918  case 1: LdrOpcode = AArch64::LDRBBroX; break;
919  case 2: LdrOpcode = AArch64::LDRHHroX; break;
920  case 4: LdrOpcode = AArch64::LDRSWroX; break;
921  default:
922  llvm_unreachable("Unknown jump table size");
923  }
924 
925  EmitToStreamer(OutStreamer, MCInstBuilder(LdrOpcode)
926  .addReg(Size == 4 ? ScratchReg : ScratchRegW)
927  .addReg(TableReg)
928  .addReg(EntryReg)
929  .addImm(0)
930  .addImm(Size == 1 ? 0 : 1));
931 
932  // Add to the already materialized base label address, multiplying by 4 if
933  // compressed.
934  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADDXrs)
935  .addReg(DestReg)
936  .addReg(DestReg)
937  .addReg(ScratchReg)
938  .addImm(Size == 4 ? 0 : 2));
939 }
940 
941 void AArch64AsmPrinter::LowerMOPS(llvm::MCStreamer &OutStreamer,
942  const llvm::MachineInstr &MI) {
943  unsigned Opcode = MI.getOpcode();
944  assert(STI->hasMOPS());
945  assert(STI->hasMTE() || Opcode != AArch64::MOPSMemorySetTaggingPseudo);
946 
947  const auto Ops = [Opcode]() -> std::array<unsigned, 3> {
948  if (Opcode == AArch64::MOPSMemoryCopyPseudo)
949  return {AArch64::CPYFP, AArch64::CPYFM, AArch64::CPYFE};
950  if (Opcode == AArch64::MOPSMemoryMovePseudo)
951  return {AArch64::CPYP, AArch64::CPYM, AArch64::CPYE};
952  if (Opcode == AArch64::MOPSMemorySetPseudo)
953  return {AArch64::SETP, AArch64::SETM, AArch64::SETE};
954  if (Opcode == AArch64::MOPSMemorySetTaggingPseudo)
955  return {AArch64::SETGP, AArch64::SETGM, AArch64::MOPSSETGE};
956  llvm_unreachable("Unhandled memory operation pseudo");
957  }();
958  const bool IsSet = Opcode == AArch64::MOPSMemorySetPseudo ||
959  Opcode == AArch64::MOPSMemorySetTaggingPseudo;
960 
961  for (auto Op : Ops) {
962  int i = 0;
963  auto MCIB = MCInstBuilder(Op);
964  // Destination registers
965  MCIB.addReg(MI.getOperand(i++).getReg());
966  MCIB.addReg(MI.getOperand(i++).getReg());
967  if (!IsSet)
968  MCIB.addReg(MI.getOperand(i++).getReg());
969  // Input registers
970  MCIB.addReg(MI.getOperand(i++).getReg());
971  MCIB.addReg(MI.getOperand(i++).getReg());
972  MCIB.addReg(MI.getOperand(i++).getReg());
973 
974  EmitToStreamer(OutStreamer, MCIB);
975  }
976 }
977 
978 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
979  const MachineInstr &MI) {
980  unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
981 
982  auto &Ctx = OutStreamer.getContext();
983  MCSymbol *MILabel = Ctx.createTempSymbol();
984  OutStreamer.emitLabel(MILabel);
985 
986  SM.recordStackMap(*MILabel, MI);
987  assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
988 
989  // Scan ahead to trim the shadow.
990  const MachineBasicBlock &MBB = *MI.getParent();
992  ++MII;
993  while (NumNOPBytes > 0) {
994  if (MII == MBB.end() || MII->isCall() ||
995  MII->getOpcode() == AArch64::DBG_VALUE ||
996  MII->getOpcode() == TargetOpcode::PATCHPOINT ||
997  MII->getOpcode() == TargetOpcode::STACKMAP)
998  break;
999  ++MII;
1000  NumNOPBytes -= 4;
1001  }
1002 
1003  // Emit nops.
1004  for (unsigned i = 0; i < NumNOPBytes; i += 4)
1005  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
1006 }
1007 
1008 // Lower a patchpoint of the form:
1009 // [<def>], <id>, <numBytes>, <target>, <numArgs>
1010 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
1011  const MachineInstr &MI) {
1012  auto &Ctx = OutStreamer.getContext();
1013  MCSymbol *MILabel = Ctx.createTempSymbol();
1014  OutStreamer.emitLabel(MILabel);
1015  SM.recordPatchPoint(*MILabel, MI);
1016 
1017  PatchPointOpers Opers(&MI);
1018 
1019  int64_t CallTarget = Opers.getCallTarget().getImm();
1020  unsigned EncodedBytes = 0;
1021  if (CallTarget) {
1022  assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
1023  "High 16 bits of call target should be zero.");
1024  Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
1025  EncodedBytes = 16;
1026  // Materialize the jump address:
1027  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
1028  .addReg(ScratchReg)
1029  .addImm((CallTarget >> 32) & 0xFFFF)
1030  .addImm(32));
1031  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
1032  .addReg(ScratchReg)
1033  .addReg(ScratchReg)
1034  .addImm((CallTarget >> 16) & 0xFFFF)
1035  .addImm(16));
1036  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
1037  .addReg(ScratchReg)
1038  .addReg(ScratchReg)
1039  .addImm(CallTarget & 0xFFFF)
1040  .addImm(0));
1041  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
1042  }
1043  // Emit padding.
1044  unsigned NumBytes = Opers.getNumPatchBytes();
1045  assert(NumBytes >= EncodedBytes &&
1046  "Patchpoint can't request size less than the length of a call.");
1047  assert((NumBytes - EncodedBytes) % 4 == 0 &&
1048  "Invalid number of NOP bytes requested!");
1049  for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
1050  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
1051 }
1052 
1053 void AArch64AsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
1054  const MachineInstr &MI) {
1055  StatepointOpers SOpers(&MI);
1056  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1057  assert(PatchBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
1058  for (unsigned i = 0; i < PatchBytes; i += 4)
1059  EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
1060  } else {
1061  // Lower call target and choose correct opcode
1062  const MachineOperand &CallTarget = SOpers.getCallTarget();
1063  MCOperand CallTargetMCOp;
1064  unsigned CallOpcode;
1065  switch (CallTarget.getType()) {
1068  MCInstLowering.lowerOperand(CallTarget, CallTargetMCOp);
1069  CallOpcode = AArch64::BL;
1070  break;
1072  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
1073  CallOpcode = AArch64::BL;
1074  break;
1076  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1077  CallOpcode = AArch64::BLR;
1078  break;
1079  default:
1080  llvm_unreachable("Unsupported operand type in statepoint call target");
1081  break;
1082  }
1083 
1084  EmitToStreamer(OutStreamer,
1085  MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp));
1086  }
1087 
1088  auto &Ctx = OutStreamer.getContext();
1089  MCSymbol *MILabel = Ctx.createTempSymbol();
1090  OutStreamer.emitLabel(MILabel);
1091  SM.recordStatepoint(*MILabel, MI);
1092 }
1093 
1094 void AArch64AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI) {
1095  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
1096  // <opcode>, <operands>
1097 
1098  Register DefRegister = FaultingMI.getOperand(0).getReg();
1100  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1101  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1102  unsigned Opcode = FaultingMI.getOperand(3).getImm();
1103  unsigned OperandsBeginIdx = 4;
1104 
1105  auto &Ctx = OutStreamer->getContext();
1106  MCSymbol *FaultingLabel = Ctx.createTempSymbol();
1107  OutStreamer->emitLabel(FaultingLabel);
1108 
1109  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
1110  FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel);
1111 
1112  MCInst MI;
1113  MI.setOpcode(Opcode);
1114 
1115  if (DefRegister != (Register)0)
1116  MI.addOperand(MCOperand::createReg(DefRegister));
1117 
1118  for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
1119  E = FaultingMI.operands_end();
1120  I != E; ++I) {
1121  MCOperand Dest;
1122  lowerOperand(*I, Dest);
1123  MI.addOperand(Dest);
1124  }
1125 
1126  OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1127  OutStreamer->emitInstruction(MI, getSubtargetInfo());
1128 }
1129 
1130 void AArch64AsmPrinter::emitFMov0(const MachineInstr &MI) {
1131  Register DestReg = MI.getOperand(0).getReg();
1132  if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround() &&
1133  STI->hasNEON()) {
1134  // Convert H/S register to corresponding D register
1135  if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
1136  DestReg = AArch64::D0 + (DestReg - AArch64::H0);
1137  else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
1138  DestReg = AArch64::D0 + (DestReg - AArch64::S0);
1139  else
1140  assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
1141 
1142  MCInst MOVI;
1143  MOVI.setOpcode(AArch64::MOVID);
1144  MOVI.addOperand(MCOperand::createReg(DestReg));
1145  MOVI.addOperand(MCOperand::createImm(0));
1146  EmitToStreamer(*OutStreamer, MOVI);
1147  } else {
1148  MCInst FMov;
1149  switch (MI.getOpcode()) {
1150  default: llvm_unreachable("Unexpected opcode");
1151  case AArch64::FMOVH0:
1152  FMov.setOpcode(AArch64::FMOVWHr);
1153  FMov.addOperand(MCOperand::createReg(DestReg));
1154  FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1155  break;
1156  case AArch64::FMOVS0:
1157  FMov.setOpcode(AArch64::FMOVWSr);
1158  FMov.addOperand(MCOperand::createReg(DestReg));
1159  FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1160  break;
1161  case AArch64::FMOVD0:
1162  FMov.setOpcode(AArch64::FMOVXDr);
1163  FMov.addOperand(MCOperand::createReg(DestReg));
1164  FMov.addOperand(MCOperand::createReg(AArch64::XZR));
1165  break;
1166  }
1167  EmitToStreamer(*OutStreamer, FMov);
1168  }
1169 }
1170 
1171 // Simple pseudo-instructions have their lowering (with expansion to real
1172 // instructions) auto-generated.
1173 #include "AArch64GenMCPseudoLowering.inc"
1174 
1175 void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
1176  // Do any auto-generated pseudo lowerings.
1177  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1178  return;
1179 
1180  if (MI->getOpcode() == AArch64::ADRP) {
1181  for (auto &Opd : MI->operands()) {
1182  if (Opd.isSymbol() && StringRef(Opd.getSymbolName()) ==
1183  "swift_async_extendedFramePointerFlags") {
1184  ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags = true;
1185  }
1186  }
1187  }
1188 
1189  if (AArch64FI->getLOHRelated().count(MI)) {
1190  // Generate a label for LOH related instruction
1191  MCSymbol *LOHLabel = createTempSymbol("loh");
1192  // Associate the instruction with the label
1193  LOHInstToLabel[MI] = LOHLabel;
1194  OutStreamer->emitLabel(LOHLabel);
1195  }
1196 
1197  AArch64TargetStreamer *TS =
1198  static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
1199  // Do any manual lowerings.
1200  switch (MI->getOpcode()) {
1201  default:
1202  break;
1203  case AArch64::HINT: {
1204  // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
1205  // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
1206  // non-empty. If MI is the initial BTI, place the
1207  // __patchable_function_entries label after BTI.
1208  if (CurrentPatchableFunctionEntrySym &&
1209  CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
1210  MI == &MF->front().front()) {
1211  int64_t Imm = MI->getOperand(0).getImm();
1212  if ((Imm & 32) && (Imm & 6)) {
1213  MCInst Inst;
1214  MCInstLowering.Lower(MI, Inst);
1215  EmitToStreamer(*OutStreamer, Inst);
1216  CurrentPatchableFunctionEntrySym = createTempSymbol("patch");
1217  OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym);
1218  return;
1219  }
1220  }
1221  break;
1222  }
1223  case AArch64::MOVMCSym: {
1224  Register DestReg = MI->getOperand(0).getReg();
1225  const MachineOperand &MO_Sym = MI->getOperand(1);
1226  MachineOperand Hi_MOSym(MO_Sym), Lo_MOSym(MO_Sym);
1227  MCOperand Hi_MCSym, Lo_MCSym;
1228 
1229  Hi_MOSym.setTargetFlags(AArch64II::MO_G1 | AArch64II::MO_S);
1230  Lo_MOSym.setTargetFlags(AArch64II::MO_G0 | AArch64II::MO_NC);
1231 
1232  MCInstLowering.lowerOperand(Hi_MOSym, Hi_MCSym);
1233  MCInstLowering.lowerOperand(Lo_MOSym, Lo_MCSym);
1234 
1235  MCInst MovZ;
1236  MovZ.setOpcode(AArch64::MOVZXi);
1237  MovZ.addOperand(MCOperand::createReg(DestReg));
1238  MovZ.addOperand(Hi_MCSym);
1239  MovZ.addOperand(MCOperand::createImm(16));
1240  EmitToStreamer(*OutStreamer, MovZ);
1241 
1242  MCInst MovK;
1243  MovK.setOpcode(AArch64::MOVKXi);
1244  MovK.addOperand(MCOperand::createReg(DestReg));
1245  MovK.addOperand(MCOperand::createReg(DestReg));
1246  MovK.addOperand(Lo_MCSym);
1248  EmitToStreamer(*OutStreamer, MovK);
1249  return;
1250  }
1251  case AArch64::MOVIv2d_ns:
1252  // If the target has <rdar://problem/16473581>, lower this
1253  // instruction to movi.16b instead.
1254  if (STI->hasZeroCycleZeroingFPWorkaround() &&
1255  MI->getOperand(1).getImm() == 0) {
1256  MCInst TmpInst;
1257  TmpInst.setOpcode(AArch64::MOVIv16b_ns);
1258  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1259  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
1260  EmitToStreamer(*OutStreamer, TmpInst);
1261  return;
1262  }
1263  break;
1264 
1265  case AArch64::DBG_VALUE:
1266  case AArch64::DBG_VALUE_LIST: {
1267  if (isVerbose() && OutStreamer->hasRawTextSupport()) {
1268  SmallString<128> TmpStr;
1269  raw_svector_ostream OS(TmpStr);
1270  PrintDebugValueComment(MI, OS);
1271  OutStreamer->emitRawText(StringRef(OS.str()));
1272  }
1273  return;
1274 
1275  case AArch64::EMITBKEY: {
1276  ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
1277  if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
1278  ExceptionHandlingType != ExceptionHandling::ARM)
1279  return;
1280 
1281  if (getFunctionCFISectionType(*MF) == CFISection::None)
1282  return;
1283 
1284  OutStreamer->emitCFIBKeyFrame();
1285  return;
1286  }
1287  }
1288 
1289  // Tail calls use pseudo instructions so they have the proper code-gen
1290  // attributes (isCall, isReturn, etc.). We lower them to the real
1291  // instruction here.
1292  case AArch64::TCRETURNri:
1293  case AArch64::TCRETURNriBTI:
1294  case AArch64::TCRETURNriALL: {
1295  MCInst TmpInst;
1296  TmpInst.setOpcode(AArch64::BR);
1297  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1298  EmitToStreamer(*OutStreamer, TmpInst);
1299  return;
1300  }
1301  case AArch64::TCRETURNdi: {
1302  MCOperand Dest;
1303  MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
1304  MCInst TmpInst;
1305  TmpInst.setOpcode(AArch64::B);
1306  TmpInst.addOperand(Dest);
1307  EmitToStreamer(*OutStreamer, TmpInst);
1308  return;
1309  }
1310  case AArch64::SpeculationBarrierISBDSBEndBB: {
1311  // Print DSB SYS + ISB
1312  MCInst TmpInstDSB;
1313  TmpInstDSB.setOpcode(AArch64::DSB);
1314  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
1315  EmitToStreamer(*OutStreamer, TmpInstDSB);
1316  MCInst TmpInstISB;
1317  TmpInstISB.setOpcode(AArch64::ISB);
1318  TmpInstISB.addOperand(MCOperand::createImm(0xf));
1319  EmitToStreamer(*OutStreamer, TmpInstISB);
1320  return;
1321  }
1322  case AArch64::SpeculationBarrierSBEndBB: {
1323  // Print SB
1324  MCInst TmpInstSB;
1325  TmpInstSB.setOpcode(AArch64::SB);
1326  EmitToStreamer(*OutStreamer, TmpInstSB);
1327  return;
1328  }
1329  case AArch64::TLSDESC_CALLSEQ: {
1330  /// lower this to:
1331  /// adrp x0, :tlsdesc:var
1332  /// ldr x1, [x0, #:tlsdesc_lo12:var]
1333  /// add x0, x0, #:tlsdesc_lo12:var
1334  /// .tlsdesccall var
1335  /// blr x1
1336  /// (TPIDR_EL0 offset now in x0)
1337  const MachineOperand &MO_Sym = MI->getOperand(0);
1338  MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
1339  MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
1340  MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
1341  MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
1342  MCInstLowering.lowerOperand(MO_Sym, Sym);
1343  MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
1344  MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
1345 
1346  MCInst Adrp;
1347  Adrp.setOpcode(AArch64::ADRP);
1348  Adrp.addOperand(MCOperand::createReg(AArch64::X0));
1349  Adrp.addOperand(SymTLSDesc);
1350  EmitToStreamer(*OutStreamer, Adrp);
1351 
1352  MCInst Ldr;
1353  if (STI->isTargetILP32()) {
1354  Ldr.setOpcode(AArch64::LDRWui);
1355  Ldr.addOperand(MCOperand::createReg(AArch64::W1));
1356  } else {
1357  Ldr.setOpcode(AArch64::LDRXui);
1358  Ldr.addOperand(MCOperand::createReg(AArch64::X1));
1359  }
1360  Ldr.addOperand(MCOperand::createReg(AArch64::X0));
1361  Ldr.addOperand(SymTLSDescLo12);
1363  EmitToStreamer(*OutStreamer, Ldr);
1364 
1365  MCInst Add;
1366  if (STI->isTargetILP32()) {
1367  Add.setOpcode(AArch64::ADDWri);
1368  Add.addOperand(MCOperand::createReg(AArch64::W0));
1369  Add.addOperand(MCOperand::createReg(AArch64::W0));
1370  } else {
1371  Add.setOpcode(AArch64::ADDXri);
1372  Add.addOperand(MCOperand::createReg(AArch64::X0));
1373  Add.addOperand(MCOperand::createReg(AArch64::X0));
1374  }
1375  Add.addOperand(SymTLSDescLo12);
1377  EmitToStreamer(*OutStreamer, Add);
1378 
1379  // Emit a relocation-annotation. This expands to no code, but requests
1380  // the following instruction gets an R_AARCH64_TLSDESC_CALL.
1381  MCInst TLSDescCall;
1382  TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
1383  TLSDescCall.addOperand(Sym);
1384  EmitToStreamer(*OutStreamer, TLSDescCall);
1385 
1386  MCInst Blr;
1387  Blr.setOpcode(AArch64::BLR);
1388  Blr.addOperand(MCOperand::createReg(AArch64::X1));
1389  EmitToStreamer(*OutStreamer, Blr);
1390 
1391  return;
1392  }
1393 
1394  case AArch64::JumpTableDest32:
1395  case AArch64::JumpTableDest16:
1396  case AArch64::JumpTableDest8:
1397  LowerJumpTableDest(*OutStreamer, *MI);
1398  return;
1399 
1400  case AArch64::FMOVH0:
1401  case AArch64::FMOVS0:
1402  case AArch64::FMOVD0:
1403  emitFMov0(*MI);
1404  return;
1405 
1406  case AArch64::MOPSMemoryCopyPseudo:
1407  case AArch64::MOPSMemoryMovePseudo:
1408  case AArch64::MOPSMemorySetPseudo:
1409  case AArch64::MOPSMemorySetTaggingPseudo:
1410  LowerMOPS(*OutStreamer, *MI);
1411  return;
1412 
1413  case TargetOpcode::STACKMAP:
1414  return LowerSTACKMAP(*OutStreamer, SM, *MI);
1415 
1416  case TargetOpcode::PATCHPOINT:
1417  return LowerPATCHPOINT(*OutStreamer, SM, *MI);
1418 
1419  case TargetOpcode::STATEPOINT:
1420  return LowerSTATEPOINT(*OutStreamer, SM, *MI);
1421 
1422  case TargetOpcode::FAULTING_OP:
1423  return LowerFAULTING_OP(*MI);
1424 
1425  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1426  LowerPATCHABLE_FUNCTION_ENTER(*MI);
1427  return;
1428 
1429  case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
1430  LowerPATCHABLE_FUNCTION_EXIT(*MI);
1431  return;
1432 
1433  case TargetOpcode::PATCHABLE_TAIL_CALL:
1434  LowerPATCHABLE_TAIL_CALL(*MI);
1435  return;
1436 
1437  case AArch64::HWASAN_CHECK_MEMACCESS:
1438  case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
1439  LowerHWASAN_CHECK_MEMACCESS(*MI);
1440  return;
1441 
1442  case AArch64::SEH_StackAlloc:
1443  TS->emitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
1444  return;
1445 
1446  case AArch64::SEH_SaveFPLR:
1447  TS->emitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
1448  return;
1449 
1450  case AArch64::SEH_SaveFPLR_X:
1451  assert(MI->getOperand(0).getImm() < 0 &&
1452  "Pre increment SEH opcode must have a negative offset");
1453  TS->emitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
1454  return;
1455 
1456  case AArch64::SEH_SaveReg:
1457  TS->emitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
1458  MI->getOperand(1).getImm());
1459  return;
1460 
1461  case AArch64::SEH_SaveReg_X:
1462  assert(MI->getOperand(1).getImm() < 0 &&
1463  "Pre increment SEH opcode must have a negative offset");
1464  TS->emitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
1465  -MI->getOperand(1).getImm());
1466  return;
1467 
1468  case AArch64::SEH_SaveRegP:
1469  if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 &&
1470  MI->getOperand(0).getImm() <= 28) {
1471  assert((MI->getOperand(0).getImm() - 19) % 2 == 0 &&
1472  "Register paired with LR must be odd");
1473  TS->emitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(),
1474  MI->getOperand(2).getImm());
1475  return;
1476  }
1477  assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1478  "Non-consecutive registers not allowed for save_regp");
1479  TS->emitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
1480  MI->getOperand(2).getImm());
1481  return;
1482 
1483  case AArch64::SEH_SaveRegP_X:
1484  assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1485  "Non-consecutive registers not allowed for save_regp_x");
1486  assert(MI->getOperand(2).getImm() < 0 &&
1487  "Pre increment SEH opcode must have a negative offset");
1488  TS->emitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
1489  -MI->getOperand(2).getImm());
1490  return;
1491 
1492  case AArch64::SEH_SaveFReg:
1493  TS->emitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
1494  MI->getOperand(1).getImm());
1495  return;
1496 
1497  case AArch64::SEH_SaveFReg_X:
1498  assert(MI->getOperand(1).getImm() < 0 &&
1499  "Pre increment SEH opcode must have a negative offset");
1500  TS->emitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
1501  -MI->getOperand(1).getImm());
1502  return;
1503 
1504  case AArch64::SEH_SaveFRegP:
1505  assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1506  "Non-consecutive registers not allowed for save_regp");
1507  TS->emitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
1508  MI->getOperand(2).getImm());
1509  return;
1510 
1511  case AArch64::SEH_SaveFRegP_X:
1512  assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1513  "Non-consecutive registers not allowed for save_regp_x");
1514  assert(MI->getOperand(2).getImm() < 0 &&
1515  "Pre increment SEH opcode must have a negative offset");
1516  TS->emitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
1517  -MI->getOperand(2).getImm());
1518  return;
1519 
1520  case AArch64::SEH_SetFP:
1521  TS->emitARM64WinCFISetFP();
1522  return;
1523 
1524  case AArch64::SEH_AddFP:
1525  TS->emitARM64WinCFIAddFP(MI->getOperand(0).getImm());
1526  return;
1527 
1528  case AArch64::SEH_Nop:
1529  TS->emitARM64WinCFINop();
1530  return;
1531 
1532  case AArch64::SEH_PrologEnd:
1534  return;
1535 
1536  case AArch64::SEH_EpilogStart:
1538  return;
1539 
1540  case AArch64::SEH_EpilogEnd:
1542  return;
1543  }
1544 
1545  // Finally, do the automated lowerings for everything else.
1546  MCInst TmpInst;
1547  MCInstLowering.Lower(MI, TmpInst);
1548  EmitToStreamer(*OutStreamer, TmpInst);
1549 }
1550 
1551 // Force static initialization.
1558 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
i
i
Definition: README.txt:29
llvm::HWASanAccessInfo::AccessSizeShift
@ AccessSizeShift
Definition: HWAddressSanitizer.h:59
llvm::ELF::SHF_EXECINSTR
@ SHF_EXECINSTR
Definition: ELF.h:1029
AsmPrinter.h
llvm::AArch64MCExpr::create
static const AArch64MCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
Definition: AArch64MCExpr.cpp:27
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
AArch64RegisterInfo.h
MachineModuleInfoImpls.h
llvm::AArch64MCInstLower::lowerOperand
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Definition: AArch64MCInstLower.cpp:258
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::AArch64CC::HI
@ HI
Definition: AArch64BaseInfo.h:263
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCStreamer::EmitCOFFSymbolStorageClass
virtual void EmitCOFFSymbolStorageClass(int StorageClass)
Emit the storage class of the symbol.
Definition: MCStreamer.cpp:1159
llvm::StackMapOpers
MI-level stackmap operands.
Definition: StackMaps.h:35
AArch64MachineFunctionInfo.h
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
AArch64.h
llvm::StackMaps::recordStatepoint
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:555
llvm::AArch64CC::NE
@ NE
Definition: AArch64BaseInfo.h:256
llvm::ARM::PredBlockMask::TT
@ TT
llvm::MCStreamer::EndCOFFSymbolDef
virtual void EndCOFFSymbolDef()
Marks the end of the symbol definition.
Definition: MCStreamer.cpp:1152
llvm::AArch64II::MO_G1
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
Definition: AArch64BaseInfo.h:697
LLVMInitializeAArch64AsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmPrinter()
Definition: AArch64AsmPrinter.cpp:1552
llvm::COFF::IMAGE_SYM_CLASS_STATIC
@ IMAGE_SYM_CLASS_STATIC
Static.
Definition: COFF.h:209
DebugInfoMetadata.h
llvm::AArch64TargetStreamer::emitARM64WinCFISaveRegPX
virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:53
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::Function
Definition: Function.h:60
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::ELF::GNU_PROPERTY_AARCH64_FEATURE_1_PAC
@ GNU_PROPERTY_AARCH64_FEATURE_1_PAC
Definition: ELF.h:1608
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MCStreamer::hasRawTextSupport
virtual bool hasRawTextSupport() const
Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText.
Definition: MCStreamer.h:325
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFPLRX
virtual void emitARM64WinCFISaveFPLRX(int Offset)
Definition: AArch64TargetStreamer.h:49
MCSectionELF.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:241
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
AArch64MCExpr.h
llvm::COFF::IMAGE_SYM_CLASS_EXTERNAL
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Definition: COFF.h:208
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::FaultMaps
Definition: FaultMaps.h:21
llvm::AArch64InstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
AArch64BaseInfo.h
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
MCInstBuilder.h
llvm::COFF::SCT_COMPLEX_TYPE_SHIFT
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:264
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
COFF.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:232
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::HWASanAccessInfo::CompileKernelShift
@ CompileKernelShift
Definition: HWAddressSanitizer.h:64
MachineJumpTableInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
printOperand
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
Definition: SelectionDAGDumper.cpp:952
llvm::AArch64TargetStreamer::emitARM64WinCFISetFP
virtual void emitARM64WinCFISetFP()
Definition: AArch64TargetStreamer.h:59
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional< std::string >
llvm::ELF::SHF_ALLOC
@ SHF_ALLOC
Definition: ELF.h:1026
llvm::MachineInstr::operands_end
mop_iterator operands_end()
Definition: MachineInstr.h:615
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AArch64TargetStreamer::emitARM64WinCFISaveRegP
virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:52
llvm::AArch64ISD::TLSDESC_CALLSEQ
@ TLSDESC_CALLSEQ
Definition: AArch64ISelLowering.h:62
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
llvm::StackMaps
Definition: StackMaps.h:251
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64II::MO_TLS
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
Definition: AArch64BaseInfo.h:727
llvm::StackMaps::recordStackMap
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:524
llvm::COFF::SymbolStorageClass
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:202
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::TargetLoweringObjectFile
Definition: TargetLoweringObjectFile.h:45
llvm::AArch64TargetStreamer::emitARM64WinCFISaveReg
virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:50
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:57
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:201
llvm::AArch64TargetStreamer::emitARM64WinCFIAddFP
virtual void emitARM64WinCFIAddFP(unsigned Size)
Definition: AArch64TargetStreamer.h:60
llvm::AArch64II::MO_G0
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
Definition: AArch64BaseInfo.h:701
ELF.h
llvm::CallingConv::AArch64_VectorCall
@ AArch64_VectorCall
Definition: CallingConv.h:239
TargetMachine.h
llvm::StackMapOpers::getNumPatchBytes
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
llvm::AArch64MCInstLower
AArch64MCInstLower - This class is used to lower an MachineInstr into an MCInst.
Definition: AArch64MCInstLower.h:26
HWAddressSanitizer.h
SmallString.h
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::ExceptionHandling
ExceptionHandling
Definition: MCTargetOptions.h:18
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
Twine.h
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:416
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFPLR
virtual void emitARM64WinCFISaveFPLR(int Offset)
Definition: AArch64TargetStreamer.h:48
llvm::AsmPrinter::emitFunctionEntryLabel
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: AsmPrinter.cpp:1011
MCSymbol.h
llvm::AArch64TargetStreamer::emitARM64WinCFISaveRegX
virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:51
MCInst.h
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:36
llvm::AArch64_AM::getShifterImm
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
Definition: AArch64AddressingModes.h:99
AArch64TargetObjectFile.h
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::AArch64_AM::getShiftValue
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
Definition: AArch64AddressingModes.h:86
llvm::MCSA_Hidden
@ MCSA_Hidden
.hidden (ELF)
Definition: MCDirectives.h:33
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:448
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::AArch64TargetStreamer::emitDirectiveVariantPCS
virtual void emitDirectiveVariantPCS(MCSymbol *Symbol)
Callback used to implement the .variant_pcs directive.
Definition: AArch64TargetStreamer.h:44
llvm::AArch64TargetStreamer::emitARM64WinCFIEpilogEnd
virtual void emitARM64WinCFIEpilogEnd()
Definition: AArch64TargetStreamer.h:65
llvm::TargetLoweringObjectFile::getSectionForJumpTable
virtual MCSection * getSectionForJumpTable(const Function &F, const TargetMachine &TM) const
Definition: TargetLoweringObjectFile.cpp:348
llvm::MCSymbol::print
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString< 128 >
AArch64AddressingModes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::AArch64II::MO_S
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
Definition: AArch64BaseInfo.h:736
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::MachineJumpTableInfo::getJumpTables
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Definition: MachineJumpTableInfo.h:99
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFReg
virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:55
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:417
llvm::MCAF_SubsectionsViaSymbols
@ MCAF_SubsectionsViaSymbols
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:53
llvm::AsmPrinter::GetCPISymbol
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
Definition: AsmPrinter.cpp:3330
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::M68kISD::TAIL_CALL
@ TAIL_CALL
Definition: M68kISelLowering.h:37
llvm::MCStreamer::emitCFIBKeyFrame
virtual void emitCFIBKeyFrame()
Definition: MCStreamer.cpp:248
llvm::MCStreamer::emitRawText
void emitRawText(const Twine &String)
If this file is backed by a assembly streamer, this dumps the specified string in the output ....
Definition: MCStreamer.cpp:986
llvm::AArch64II::MO_NC
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
Definition: AArch64BaseInfo.h:721
llvm::HWASanAccessInfo::RuntimeMask
@ RuntimeMask
Definition: HWAddressSanitizer.h:67
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::AArch64II::MO_PAGEOFF
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
Definition: AArch64BaseInfo.h:685
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1091
llvm::AArch64TargetStreamer::emitARM64WinCFINop
virtual void emitARM64WinCFINop()
Definition: AArch64TargetStreamer.h:61
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:38
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineInstr::operands_begin
mop_iterator operands_begin()
Definition: MachineInstr.h:614
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFRegPX
virtual void emitARM64WinCFISaveFRegPX(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:57
llvm::AArch64TargetStreamer
Definition: AArch64TargetStreamer.h:20
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MCBinaryExpr::createLShr
static const MCBinaryExpr * createLShr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:605
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::ELF::SHF_GROUP
@ SHF_GROUP
Definition: ELF.h:1048
llvm::MachineFunction
Definition: MachineFunction.h:241
Triple.h
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::AArch64_AM::encodeLogicalImmediate
static uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize)
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of th...
Definition: AArch64AddressingModes.h:283
llvm::MCStreamer::EmitCOFFSymbolType
virtual void EmitCOFFSymbolType(int Type)
Emit the type of the symbol.
Definition: MCStreamer.cpp:1162
llvm::AArch64TargetStreamer::emitARM64WinCFISaveLRPair
virtual void emitARM64WinCFISaveLRPair(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:54
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
MCAsmInfo.h
AArch64InstPrinter.h
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AsmPrinter::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
Record analysis usage.
Definition: AsmPrinter.cpp:423
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm::AArch64TargetStreamer::emitARM64WinCFIAllocStack
virtual void emitARM64WinCFIAllocStack(unsigned Size)
Definition: AArch64TargetStreamer.h:46
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
llvm::AArch64ISD::MOVI
@ MOVI
Definition: AArch64ISelLowering.h:163
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:64
llvm::MCSection
Instances of this class represent a uniqued identifier for a section in the current translation unit.
Definition: MCSection.h:39
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::FaultMaps::FaultKindMax
@ FaultKindMax
Definition: FaultMaps.h:27
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
llvm::CallingConv::AArch64_SVE_VectorCall
@ AArch64_SVE_VectorCall
Calling convention between AArch64 SVE functions.
Definition: CallingConv.h:242
printAsmMRegister
static bool printAsmMRegister(const X86AsmPrinter &P, const MachineOperand &MO, char Mode, raw_ostream &O)
Definition: X86AsmPrinter.cpp:414
llvm::AArch64CC::EQ
@ EQ
Definition: AArch64BaseInfo.h:255
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFRegP
virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:57
llvm::AArch64TargetStreamer::emitARM64WinCFIPrologEnd
virtual void emitARM64WinCFIPrologEnd()
Definition: AArch64TargetStreamer.h:63
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::getXRegFromXRegTuple
static unsigned getXRegFromXRegTuple(unsigned RegTuple)
Definition: AArch64BaseInfo.h:109
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::getXRegFromWReg
static unsigned getXRegFromWReg(unsigned Reg)
Definition: AArch64BaseInfo.h:69
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:268
llvm::pdb::PDB_SymType::Label
@ Label
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::ELF::SHT_PROGBITS
@ SHT_PROGBITS
Definition: ELF.h:946
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:326
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:975
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:86
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
Casting.h
llvm::AArch64TargetStreamer::emitARM64WinCFISaveFRegX
virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset)
Definition: AArch64TargetStreamer.h:56
llvm::StackMaps::recordPatchPoint
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:534
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
StackMaps.h
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:81
AArch64MCTargetDesc.h
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:591
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
AArch64TargetStreamer.h
llvm::MCSA_Global
@ MCSA_Global
.type _foo, @gnu_unique_object
Definition: MCDirectives.h:30
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::AArch64ISD::ADRP
@ ADRP
Definition: AArch64ISelLowering.h:63
llvm::MCStreamer::BeginCOFFSymbolDef
virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol)
Start emitting COFF symbol definition.
Definition: MCStreamer.cpp:1149
llvm::MCSA_ELF_TypeFunction
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Definition: MCDirectives.h:23
llvm::FaultMaps::FaultKind
FaultKind
Definition: FaultMaps.h:23
llvm::MCSA_Weak
@ MCSA_Weak
.weak
Definition: MCDirectives.h:45
llvm::getWRegFromXReg
static unsigned getWRegFromXReg(unsigned Reg)
Definition: AArch64BaseInfo.h:29
AArch64Subtarget.h
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition: MCStreamer.h:282
SmallVector.h
llvm::HWASanAccessInfo::MatchAllShift
@ MatchAllShift
Definition: HWAddressSanitizer.h:62
llvm::MCStreamer::getTargetStreamer
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:289
llvm::COFF::IMAGE_SYM_DTYPE_NULL
@ IMAGE_SYM_DTYPE_NULL
No complex type; simple scalar variable.
Definition: COFF.h:258
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
MCStreamer.h
llvm::AArch64FunctionInfo::getOutliningStyle
Optional< std::string > getOutliningStyle() const
Definition: AArch64MachineFunctionInfo.h:230
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:662
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
FaultMaps.h
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1359
llvm::AArch64TargetStreamer::emitARM64WinCFIEpilogStart
virtual void emitARM64WinCFIEpilogStart()
Definition: AArch64TargetStreamer.h:64
llvm::HWASanAccessInfo::HasMatchAllShift
@ HasMatchAllShift
Definition: HWAddressSanitizer.h:63
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
raw_ostream.h
MachineFunction.h
llvm::COFF::IMAGE_SYM_DTYPE_FUNCTION
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
Definition: COFF.h:260
llvm::ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI
@ GNU_PROPERTY_AARCH64_FEATURE_1_BTI
Definition: ELF.h:1607
llvm::MachineInstrBundleIterator< const MachineInstr >
TargetRegistry.h
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:467
llvm::MCStreamer::AddComment
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:344
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::AArch64II::MO_PAGE
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
Definition: AArch64BaseInfo.h:680
AArch64TargetInfo.h
AArch64MCInstLower.h