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LoongArchISelLowering.cpp
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1 //=- LoongArchISelLowering.cpp - LoongArch DAG Lowering Implementation ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that LoongArch uses to lower LLVM code into
10 // a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "LoongArchISelLowering.h"
15 #include "LoongArch.h"
17 #include "LoongArchRegisterInfo.h"
18 #include "LoongArchSubtarget.h"
19 #include "LoongArchTargetMachine.h"
20 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "loongarch-isel-lowering"
27 
29  const LoongArchSubtarget &STI)
30  : TargetLowering(TM), Subtarget(STI) {
31 
32  MVT GRLenVT = Subtarget.getGRLenVT();
33  // Set up the register classes.
34  addRegisterClass(GRLenVT, &LoongArch::GPRRegClass);
35  if (Subtarget.hasBasicF())
36  addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass);
37  if (Subtarget.hasBasicD())
38  addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
39 
40  // TODO: add necessary setOperationAction calls later.
44 
45  if (Subtarget.is64Bit()) {
49  }
50 
51  static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE,
53 
54  if (Subtarget.hasBasicF()) {
55  setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
57  }
58  if (Subtarget.hasBasicD()) {
59  setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
61  }
62 
65 
66  // Compute derived properties from the register classes.
68 
70 
72 
73  // Function alignments.
74  const Align FunctionAlignment(4);
75  setMinFunctionAlignment(FunctionAlignment);
76 
79 }
80 
82  SelectionDAG &DAG) const {
83  switch (Op.getOpcode()) {
84  default:
85  report_fatal_error("unimplemented operand");
86  case ISD::SHL_PARTS:
87  return lowerShiftLeftParts(Op, DAG);
88  case ISD::SRA_PARTS:
89  return lowerShiftRightParts(Op, DAG, true);
90  case ISD::SRL_PARTS:
91  return lowerShiftRightParts(Op, DAG, false);
92  case ISD::SHL:
93  case ISD::SRA:
94  case ISD::SRL:
95  // This can be called for an i32 shift amount that needs to be promoted.
96  assert(Op.getOperand(1).getValueType() == MVT::i32 && Subtarget.is64Bit() &&
97  "Unexpected custom legalisation");
98  return SDValue();
99  }
100 }
101 
102 SDValue LoongArchTargetLowering::lowerShiftLeftParts(SDValue Op,
103  SelectionDAG &DAG) const {
104  SDLoc DL(Op);
105  SDValue Lo = Op.getOperand(0);
106  SDValue Hi = Op.getOperand(1);
107  SDValue Shamt = Op.getOperand(2);
108  EVT VT = Lo.getValueType();
109 
110  // if Shamt-GRLen < 0: // Shamt < GRLen
111  // Lo = Lo << Shamt
112  // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (GRLen-1 ^ Shamt))
113  // else:
114  // Lo = 0
115  // Hi = Lo << (Shamt-GRLen)
116 
117  SDValue Zero = DAG.getConstant(0, DL, VT);
118  SDValue One = DAG.getConstant(1, DL, VT);
119  SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
120  SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
121  SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
122  SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
123 
124  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
125  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
126  SDValue ShiftRightLo =
127  DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, GRLenMinus1Shamt);
128  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
129  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
130  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusGRLen);
131 
132  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
133 
134  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
135  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
136 
137  SDValue Parts[2] = {Lo, Hi};
138  return DAG.getMergeValues(Parts, DL);
139 }
140 
141 SDValue LoongArchTargetLowering::lowerShiftRightParts(SDValue Op,
142  SelectionDAG &DAG,
143  bool IsSRA) const {
144  SDLoc DL(Op);
145  SDValue Lo = Op.getOperand(0);
146  SDValue Hi = Op.getOperand(1);
147  SDValue Shamt = Op.getOperand(2);
148  EVT VT = Lo.getValueType();
149 
150  // SRA expansion:
151  // if Shamt-GRLen < 0: // Shamt < GRLen
152  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ GRLen-1))
153  // Hi = Hi >>s Shamt
154  // else:
155  // Lo = Hi >>s (Shamt-GRLen);
156  // Hi = Hi >>s (GRLen-1)
157  //
158  // SRL expansion:
159  // if Shamt-GRLen < 0: // Shamt < GRLen
160  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (ShAmt ^ GRLen-1))
161  // Hi = Hi >>u Shamt
162  // else:
163  // Lo = Hi >>u (Shamt-GRLen);
164  // Hi = 0;
165 
166  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
167 
168  SDValue Zero = DAG.getConstant(0, DL, VT);
169  SDValue One = DAG.getConstant(1, DL, VT);
170  SDValue MinusGRLen = DAG.getConstant(-(int)Subtarget.getGRLen(), DL, VT);
171  SDValue GRLenMinus1 = DAG.getConstant(Subtarget.getGRLen() - 1, DL, VT);
172  SDValue ShamtMinusGRLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusGRLen);
173  SDValue GRLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, GRLenMinus1);
174 
175  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
176  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
177  SDValue ShiftLeftHi =
178  DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, GRLenMinus1Shamt);
179  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
180  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
181  SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusGRLen);
182  SDValue HiFalse =
183  IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero;
184 
185  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT);
186 
187  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
188  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
189 
190  SDValue Parts[2] = {Lo, Hi};
191  return DAG.getMergeValues(Parts, DL);
192 }
193 
194 // Returns the opcode of the target-specific SDNode that implements the 32-bit
195 // form of the given Opcode.
197  switch (Opcode) {
198  default:
199  llvm_unreachable("Unexpected opcode");
200  case ISD::SHL:
201  return LoongArchISD::SLL_W;
202  case ISD::SRA:
203  return LoongArchISD::SRA_W;
204  case ISD::SRL:
205  return LoongArchISD::SRL_W;
206  }
207 }
208 
209 // Converts the given i8/i16/i32 operation to a target-specific SelectionDAG
210 // node. Because i8/i16/i32 isn't a legal type for LA64, these operations would
211 // otherwise be promoted to i64, making it difficult to select the
212 // SLL_W/.../*W later one because the fact the operation was originally of
213 // type i8/i16/i32 is lost.
215  unsigned ExtOpc = ISD::ANY_EXTEND) {
216  SDLoc DL(N);
217  LoongArchISD::NodeType WOpcode = getLoongArchWOpcode(N->getOpcode());
218  SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0));
219  SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1));
220  SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
221  // ReplaceNodeResults requires we maintain the same type for the return value.
222  return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
223 }
224 
227  SDLoc DL(N);
228  switch (N->getOpcode()) {
229  default:
230  llvm_unreachable("Don't know how to legalize this operation");
231  case ISD::SHL:
232  case ISD::SRA:
233  case ISD::SRL:
234  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
235  "Unexpected custom legalisation");
236  if (N->getOperand(1).getOpcode() != ISD::Constant) {
237  Results.push_back(customLegalizeToWOp(N, DAG));
238  break;
239  }
240  break;
241  }
242 }
243 
246  const LoongArchSubtarget &Subtarget) {
247  if (DCI.isBeforeLegalizeOps())
248  return SDValue();
249 
250  SDValue FirstOperand = N->getOperand(0);
251  SDValue SecondOperand = N->getOperand(1);
252  unsigned FirstOperandOpc = FirstOperand.getOpcode();
253  EVT ValTy = N->getValueType(0);
254  SDLoc DL(N);
255  uint64_t lsb, msb;
256  unsigned SMIdx, SMLen;
257  ConstantSDNode *CN;
258  SDValue NewOperand;
259  MVT GRLenVT = Subtarget.getGRLenVT();
260 
261  // Op's second operand must be a shifted mask.
262  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)) ||
263  !isShiftedMask_64(CN->getZExtValue(), SMIdx, SMLen))
264  return SDValue();
265 
266  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
267  // Pattern match BSTRPICK.
268  // $dst = and ((sra or srl) $src , lsb), (2**len - 1)
269  // => BSTRPICK $dst, $src, msb, lsb
270  // where msb = lsb + len - 1
271 
272  // The second operand of the shift must be an immediate.
273  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
274  return SDValue();
275 
276  lsb = CN->getZExtValue();
277 
278  // Return if the shifted mask does not start at bit 0 or the sum of its
279  // length and lsb exceeds the word's size.
280  if (SMIdx != 0 || lsb + SMLen > ValTy.getSizeInBits())
281  return SDValue();
282 
283  NewOperand = FirstOperand.getOperand(0);
284  } else {
285  // Pattern match BSTRPICK.
286  // $dst = and $src, (2**len- 1) , if len > 12
287  // => BSTRPICK $dst, $src, msb, lsb
288  // where lsb = 0 and msb = len - 1
289 
290  // If the mask is <= 0xfff, andi can be used instead.
291  if (CN->getZExtValue() <= 0xfff)
292  return SDValue();
293 
294  // Return if the mask doesn't start at position 0.
295  if (SMIdx)
296  return SDValue();
297 
298  lsb = 0;
299  NewOperand = FirstOperand;
300  }
301  msb = lsb + SMLen - 1;
302  return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy, NewOperand,
303  DAG.getConstant(msb, DL, GRLenVT),
304  DAG.getConstant(lsb, DL, GRLenVT));
305 }
306 
309  const LoongArchSubtarget &Subtarget) {
310  if (DCI.isBeforeLegalizeOps())
311  return SDValue();
312 
313  // $dst = srl (and $src, Mask), Shamt
314  // =>
315  // BSTRPICK $dst, $src, MaskIdx+MaskLen-1, Shamt
316  // when Mask is a shifted mask, and MaskIdx <= Shamt <= MaskIdx+MaskLen-1
317  //
318 
319  SDValue FirstOperand = N->getOperand(0);
320  ConstantSDNode *CN;
321  EVT ValTy = N->getValueType(0);
322  SDLoc DL(N);
323  MVT GRLenVT = Subtarget.getGRLenVT();
324  unsigned MaskIdx, MaskLen;
325  uint64_t Shamt;
326 
327  // The first operand must be an AND and the second operand of the AND must be
328  // a shifted mask.
329  if (FirstOperand.getOpcode() != ISD::AND ||
330  !(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
331  !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen))
332  return SDValue();
333 
334  // The second operand (shift amount) must be an immediate.
335  if (!(CN = dyn_cast<ConstantSDNode>(N->getOperand(1))))
336  return SDValue();
337 
338  Shamt = CN->getZExtValue();
339  if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1)
340  return DAG.getNode(LoongArchISD::BSTRPICK, DL, ValTy,
341  FirstOperand->getOperand(0),
342  DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT),
343  DAG.getConstant(Shamt, DL, GRLenVT));
344 
345  return SDValue();
346 }
347 
349  DAGCombinerInfo &DCI) const {
350  SelectionDAG &DAG = DCI.DAG;
351  switch (N->getOpcode()) {
352  default:
353  break;
354  case ISD::AND:
355  return performANDCombine(N, DAG, DCI, Subtarget);
356  case ISD::SRL:
357  return performSRLCombine(N, DAG, DCI, Subtarget);
358  }
359  return SDValue();
360 }
361 
362 const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
363  switch ((LoongArchISD::NodeType)Opcode) {
365  break;
366 
367 #define NODE_NAME_CASE(node) \
368  case LoongArchISD::node: \
369  return "LoongArchISD::" #node;
370 
371  // TODO: Add more target-dependent nodes later.
377  }
378 #undef NODE_NAME_CASE
379  return nullptr;
380 }
381 
382 //===----------------------------------------------------------------------===//
383 // Calling Convention Implementation
384 //===----------------------------------------------------------------------===//
385 // FIXME: Now, we only support CallingConv::C with fixed arguments which are
386 // passed with integer or floating-point registers.
387 const MCPhysReg ArgGPRs[] = {LoongArch::R4, LoongArch::R5, LoongArch::R6,
388  LoongArch::R7, LoongArch::R8, LoongArch::R9,
389  LoongArch::R10, LoongArch::R11};
390 const MCPhysReg ArgFPR32s[] = {LoongArch::F0, LoongArch::F1, LoongArch::F2,
391  LoongArch::F3, LoongArch::F4, LoongArch::F5,
392  LoongArch::F6, LoongArch::F7};
393 const MCPhysReg ArgFPR64s[] = {
394  LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
395  LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64};
396 
397 // Implements the LoongArch calling convention. Returns true upon failure.
398 static bool CC_LoongArch(unsigned ValNo, MVT ValVT,
399  CCValAssign::LocInfo LocInfo, CCState &State) {
400  // Allocate to a register if possible.
401  Register Reg;
402 
403  if (ValVT == MVT::f32)
404  Reg = State.AllocateReg(ArgFPR32s);
405  else if (ValVT == MVT::f64)
406  Reg = State.AllocateReg(ArgFPR64s);
407  else
408  Reg = State.AllocateReg(ArgGPRs);
409  if (Reg) {
410  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, ValVT, LocInfo));
411  return false;
412  }
413 
414  // TODO: Handle arguments passed without register.
415  return true;
416 }
417 
418 void LoongArchTargetLowering::analyzeInputArgs(
420  LoongArchCCAssignFn Fn) const {
421  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
422  MVT ArgVT = Ins[i].VT;
423 
424  if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {
425  LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
426  << EVT(ArgVT).getEVTString() << '\n');
427  llvm_unreachable("");
428  }
429  }
430 }
431 
432 void LoongArchTargetLowering::analyzeOutputArgs(
433  CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs,
434  LoongArchCCAssignFn Fn) const {
435  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
436  MVT ArgVT = Outs[i].VT;
437 
438  if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {
439  LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
440  << EVT(ArgVT).getEVTString() << "\n");
441  llvm_unreachable("");
442  }
443  }
444 }
445 
447  const CCValAssign &VA, const SDLoc &DL,
448  const LoongArchTargetLowering &TLI) {
450  MachineRegisterInfo &RegInfo = MF.getRegInfo();
451  EVT LocVT = VA.getLocVT();
452  const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT());
453  Register VReg = RegInfo.createVirtualRegister(RC);
454  RegInfo.addLiveIn(VA.getLocReg(), VReg);
455 
456  return DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
457 }
458 
459 // Transform physical registers into virtual registers.
461  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
463  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
464 
466 
467  switch (CallConv) {
468  default:
469  llvm_unreachable("Unsupported calling convention");
470  case CallingConv::C:
471  break;
472  }
473 
474  // Assign locations to all of the incoming arguments.
475  SmallVector<CCValAssign> ArgLocs;
476  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
477 
478  analyzeInputArgs(CCInfo, Ins, CC_LoongArch);
479 
480  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
481  InVals.push_back(unpackFromRegLoc(DAG, Chain, ArgLocs[i], DL, *this));
482 
483  return Chain;
484 }
485 
487  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
489  // Any return value split in to more than two values can't be returned
490  // directly.
491  return Outs.size() <= 2;
492 }
493 
495  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
497  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
498  SelectionDAG &DAG) const {
499  // Stores the assignment of the return value to a location.
501 
502  // Info about the registers and stack slot.
503  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
504  *DAG.getContext());
505 
506  analyzeOutputArgs(CCInfo, Outs, CC_LoongArch);
507 
508  SDValue Glue;
509  SmallVector<SDValue, 4> RetOps(1, Chain);
510 
511  // Copy the result values into the output registers.
512  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
513  CCValAssign &VA = RVLocs[i];
514  assert(VA.isRegLoc() && "Can only return in registers!");
515 
516  // Handle a 'normal' return.
517  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue);
518 
519  // Guarantee that all emitted copies are stuck together.
520  Glue = Chain.getValue(1);
521  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
522  }
523 
524  RetOps[0] = Chain; // Update chain.
525 
526  // Add the glue node if we have it.
527  if (Glue.getNode())
528  RetOps.push_back(Glue);
529 
530  return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
531 }
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
llvm::LoongArchSubtarget::getRegisterInfo
const LoongArchRegisterInfo * getRegisterInfo() const override
Definition: LoongArchSubtarget.h:70
i
i
Definition: README.txt:29
getLoongArchWOpcode
static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode)
Definition: LoongArchISelLowering.cpp:196
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1424
llvm::LoongArchTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LoongArchISelLowering.cpp:81
llvm::LoongArchISD::SRA_W
@ SRA_W
Definition: LoongArchISelLowering.h:34
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::LoongArchTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LoongArchISelLowering.cpp:362
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:750
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::LoongArchSubtarget::getGRLen
unsigned getGRLen() const
Definition: LoongArchSubtarget.h:84
LoongArchRegisterInfo.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3812
R4
#define R4(n)
llvm::LoongArchSubtarget::is64Bit
bool is64Bit() const
Definition: LoongArchSubtarget.h:76
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::LoongArchISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: LoongArchISelLowering.h:27
LoongArchSubtarget.h
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2447
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::LoongArchISD::SLL_W
@ SLL_W
Definition: LoongArchISelLowering.h:33
llvm::LoongArchTargetLowering::LoongArchTargetLowering
LoongArchTargetLowering(const TargetMachine &TM, const LoongArchSubtarget &STI)
Definition: LoongArchISelLowering.cpp:28
ArgFPR64s
const MCPhysReg ArgFPR64s[]
Definition: LoongArchISelLowering.cpp:393
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:462
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2439
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps
bool isBeforeLegalizeOps() const
Definition: TargetLowering.h:3818
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
LoongArchISelLowering.h
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::isShiftedMask_64
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:485
performANDCombine
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:244
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3412
llvm::LoongArchTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: LoongArchISelLowering.cpp:225
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3806
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2284
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::LoongArchSubtarget::hasBasicF
bool hasBasicF() const
Definition: LoongArchSubtarget.h:77
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
unpackFromRegLoc
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
Definition: LoongArchISelLowering.cpp:446
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1423
NODE_NAME_CASE
#define NODE_NAME_CASE(node)
llvm::LoongArchTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: LoongArchISelLowering.cpp:494
customLegalizeToWOp
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, unsigned ExtOpc=ISD::ANY_EXTEND)
Definition: LoongArchISelLowering.cpp:214
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2301
llvm::LoongArchSubtarget::hasBasicD
bool hasBasicD() const
Definition: LoongArchSubtarget.h:78
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
uint64_t
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:776
llvm::LoongArchTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: LoongArchISelLowering.cpp:460
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2250
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:908
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8851
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1415
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::LoongArchTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LoongArchISelLowering.cpp:348
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1579
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1411
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
R6
#define R6(n)
llvm::LoongArchTargetLowering
Definition: LoongArchISelLowering.h:42
llvm::LoongArchSubtarget::getGRLenVT
MVT getGRLenVT() const
Definition: LoongArchSubtarget.h:83
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
LoongArch.h
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:349
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1133
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LoongArchISD::RET
@ RET
Definition: LoongArchISelLowering.h:30
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1434
llvm::LoongArchISD::NodeType
NodeType
Definition: LoongArchISelLowering.h:26
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
ArgFPR32s
const MCPhysReg ArgFPR32s[]
Definition: LoongArchISelLowering.cpp:390
ISDOpcodes.h
llvm::LoongArchISD::BSTRPICK
@ BSTRPICK
Definition: LoongArchISelLowering.h:37
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
LoongArchMachineFunctionInfo.h
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
llvm::LoongArchISD::SRL_W
@ SRL_W
Definition: LoongArchISelLowering.h:35
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
CC_LoongArch
static bool CC_LoongArch(unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, CCState &State)
Definition: LoongArchISelLowering.cpp:398
performSRLCombine
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
Definition: LoongArchISelLowering.cpp:307
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2218
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1416
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:77
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
LoongArchTargetMachine.h
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1277
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetLoweringBase::setCondCodeAction
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
Definition: TargetLowering.h:2401
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:891
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:1121
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
ArgGPRs
const MCPhysReg ArgGPRs[]
Definition: LoongArchISelLowering.cpp:387
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
Debug.h
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1079
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7531
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::LoongArchTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: LoongArchISelLowering.cpp:486