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24 #define DEBUG_TYPE "processimpdefs"
61 "Process Implicit Definitions",
false,
false)
63 void ProcessImplicitDefs::getAnalysisUsage(
AnalysisUsage &AU)
const {
69 bool ProcessImplicitDefs::canTurnIntoImplicitDef(
MachineInstr *
MI) {
70 if (!
MI->isCopyLike() &&
71 !
MI->isInsertSubreg() &&
72 !
MI->isRegSequence() &&
76 if (MO.isReg() && MO.isUse() && MO.readsReg())
85 if (
Reg.isVirtual()) {
91 if (!canTurnIntoImplicitDef(UserMI))
94 UserMI->
setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
95 WorkList.insert(UserMI);
97 MI->eraseFromParent();
106 for (++UserMI; UserMI != UserE; ++UserMI) {
125 MI->eraseFromParent();
131 for (
unsigned i =
MI->getNumOperands() - 1;
i; --
i)
132 MI->removeOperand(
i);
140 LLVM_DEBUG(
dbgs() <<
"********** PROCESS IMPLICIT DEFS **********\n"
141 <<
"********** Function: " << MF.
getName() <<
'\n');
143 bool Changed =
false;
148 assert(WorkList.empty() &&
"Inconsistent worklist state");
153 if (
MI.isImplicitDef())
154 WorkList.insert(&
MI);
156 if (WorkList.empty())
160 <<
" implicit defs.\n");
164 do processImplicitDef(WorkList.pop_back_val());
165 while (!WorkList.empty());
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual const TargetInstrInfo * getInstrInfo() const
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Properties which a MachineFunction may have at a given point in time.
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Representation of each machine instruction.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
void initializeProcessImplicitDefsPass(PassRegistry &)
const MachineBasicBlock * getParent() const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
Iterator for intrusive lists based on ilist_node.
INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE, "Process Implicit Definitions", false, false) void ProcessImplicitDefs
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
A SetVector that performs no allocations if smaller than a certain size.