LLVM  17.0.0git
ProcessImplicitDefs.cpp
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1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/ADT/SetVector.h"
16 #include "llvm/InitializePasses.h"
17 #include "llvm/Pass.h"
18 #include "llvm/PassRegistry.h"
19 #include "llvm/Support/Debug.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "processimpdefs"
25 
26 namespace {
27 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
28 /// for each use. Add isUndef marker to implicit_def defs and their uses.
29 class ProcessImplicitDefs : public MachineFunctionPass {
30  const TargetInstrInfo *TII;
31  const TargetRegisterInfo *TRI;
33 
35 
36  void processImplicitDef(MachineInstr *MI);
37  bool canTurnIntoImplicitDef(MachineInstr *MI);
38 
39 public:
40  static char ID;
41 
42  ProcessImplicitDefs() : MachineFunctionPass(ID) {
44  }
45 
46  void getAnalysisUsage(AnalysisUsage &au) const override;
47 
48  bool runOnMachineFunction(MachineFunction &MF) override;
49 
50  MachineFunctionProperties getRequiredProperties() const override {
53  }
54 };
55 } // end anonymous namespace
56 
59 
60 INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
61  "Process Implicit Definitions", false, false)
62 
63 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
64  AU.setPreservesCFG();
65  AU.addPreserved<AAResultsWrapperPass>();
67 }
68 
69 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
70  if (!MI->isCopyLike() &&
71  !MI->isInsertSubreg() &&
72  !MI->isRegSequence() &&
73  !MI->isPHI())
74  return false;
75  for (const MachineOperand &MO : MI->operands())
76  if (MO.isReg() && MO.isUse() && MO.readsReg())
77  return false;
78  return true;
79 }
80 
81 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
82  LLVM_DEBUG(dbgs() << "Processing " << *MI);
83  Register Reg = MI->getOperand(0).getReg();
84 
85  if (Reg.isVirtual()) {
86  // For virtual registers, mark all uses as <undef>, and convert users to
87  // implicit-def when possible.
89  MO.setIsUndef();
90  MachineInstr *UserMI = MO.getParent();
91  if (!canTurnIntoImplicitDef(UserMI))
92  continue;
93  LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
94  UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
95  WorkList.insert(UserMI);
96  }
97  MI->eraseFromParent();
98  return;
99  }
100 
101  // This is a physreg implicit-def.
102  // Look for the first instruction to use or define an alias.
103  MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
104  MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
105  bool Found = false;
106  for (++UserMI; UserMI != UserE; ++UserMI) {
107  for (MachineOperand &MO : UserMI->operands()) {
108  if (!MO.isReg())
109  continue;
110  Register UserReg = MO.getReg();
111  if (!UserReg.isPhysical() || !TRI->regsOverlap(Reg, UserReg))
112  continue;
113  // UserMI uses or redefines Reg. Set <undef> flags on all uses.
114  Found = true;
115  if (MO.isUse())
116  MO.setIsUndef();
117  }
118  if (Found)
119  break;
120  }
121 
122  // If we found the using MI, we can erase the IMPLICIT_DEF.
123  if (Found) {
124  LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
125  MI->eraseFromParent();
126  return;
127  }
128 
129  // Using instr wasn't found, it could be in another block.
130  // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
131  for (unsigned i = MI->getNumOperands() - 1; i; --i)
132  MI->removeOperand(i);
133  LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
134 }
135 
136 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
137 /// <undef> operands.
138 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
139 
140  LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
141  << "********** Function: " << MF.getName() << '\n');
142 
143  bool Changed = false;
144 
145  TII = MF.getSubtarget().getInstrInfo();
147  MRI = &MF.getRegInfo();
148  assert(WorkList.empty() && "Inconsistent worklist state");
149 
150  for (MachineBasicBlock &MBB : MF) {
151  // Scan the basic block for implicit defs.
152  for (MachineInstr &MI : MBB)
153  if (MI.isImplicitDef())
154  WorkList.insert(&MI);
155 
156  if (WorkList.empty())
157  continue;
158 
159  LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
160  << " implicit defs.\n");
161  Changed = true;
162 
163  // Drain the WorkList to recursively process any new implicit defs.
164  do processImplicitDef(WorkList.pop_back_val());
165  while (!WorkList.empty());
166  }
167  return Changed;
168 }
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:824
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:118
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
TargetInstrInfo.h
llvm::MachineFunctionProperties::Property::IsSSA
@ IsSSA
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:128
PassRegistry.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
AliasAnalysis.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:682
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:548
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
DEBUG_TYPE
#define DEBUG_TYPE
Definition: ProcessImplicitDefs.cpp:24
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:197
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:421
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:582
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:58
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::initializeProcessImplicitDefsPass
void initializeProcessImplicitDefsPass(PassRegistry &)
TargetSubtargetInfo.h
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
INITIALIZE_PASS
INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE, "Process Implicit Definitions", false, false) void ProcessImplicitDefs
Definition: ProcessImplicitDefs.cpp:60
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1771
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:933
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:300
raw_ostream.h
InitializePasses.h
Debug.h
SetVector.h