LLVM  14.0.0git
R600ExpandSpecialInstrs.cpp
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1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
11 /// group to work correctly. This pass expands these individual instructions
12 /// into several instructions that will completely fill the instruction group.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "R600.h"
18 #include "R600Defines.h"
19 #include "R600Subtarget.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "r600-expand-special-instrs"
24 
25 namespace {
26 
27 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
28 private:
29  const R600InstrInfo *TII = nullptr;
30 
31  void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
32  unsigned Op);
33 
34 public:
35  static char ID;
36 
37  R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
38 
39  bool runOnMachineFunction(MachineFunction &MF) override;
40 
41  StringRef getPassName() const override {
42  return "R600 Expand special instructions pass";
43  }
44 };
45 
46 } // end anonymous namespace
47 
48 INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
49  "R600 Expand Special Instrs", false, false)
50 INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
52 
53 char R600ExpandSpecialInstrsPass::ID = 0;
54 
55 char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
56 
58  return new R600ExpandSpecialInstrsPass();
59 }
60 
61 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
62  const MachineInstr *OldMI, unsigned Op) {
63  int OpIdx = TII->getOperandIdx(*OldMI, Op);
64  if (OpIdx > -1) {
65  uint64_t Val = OldMI->getOperand(OpIdx).getImm();
66  TII->setImmOperand(*NewMI, Op, Val);
67  }
68 }
69 
70 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
72  TII = ST.getInstrInfo();
73 
74  const R600RegisterInfo &TRI = TII->getRegisterInfo();
75 
76  for (MachineBasicBlock &MBB : MF) {
78  while (I != MBB.end()) {
79  MachineInstr &MI = *I;
80  I = std::next(I);
81 
82  // Expand LDS_*_RET instructions
83  if (TII->isLDSRetInstr(MI.getOpcode())) {
84  int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
85  assert(DstIdx != -1);
86  MachineOperand &DstOp = MI.getOperand(DstIdx);
87  MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
88  DstOp.getReg(), R600::OQAP);
89  DstOp.setReg(R600::OQAP);
90  int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
91  R600::OpName::pred_sel);
92  int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
93  R600::OpName::pred_sel);
94  // Copy the pred_sel bit
95  Mov->getOperand(MovPredSelIdx).setReg(
96  MI.getOperand(LDSPredSelIdx).getReg());
97  }
98 
99  switch (MI.getOpcode()) {
100  default: break;
101  // Expand PRED_X to one of the PRED_SET instructions.
102  case R600::PRED_X: {
103  uint64_t Flags = MI.getOperand(3).getImm();
104  // The native opcode used by PRED_X is stored as an immediate in the
105  // third operand.
106  MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
107  MI.getOperand(2).getImm(), // opcode
108  MI.getOperand(0).getReg(), // dst
109  MI.getOperand(1).getReg(), // src0
110  R600::ZERO); // src1
111  TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
112  if (Flags & MO_FLAG_PUSH) {
113  TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
114  } else {
115  TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
116  }
117  MI.eraseFromParent();
118  continue;
119  }
120  case R600::DOT_4: {
121 
122  const R600RegisterInfo &TRI = TII->getRegisterInfo();
123 
124  Register DstReg = MI.getOperand(0).getReg();
125  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
126 
127  for (unsigned Chan = 0; Chan < 4; ++Chan) {
128  bool Mask = (Chan != TRI.getHWRegChan(DstReg));
129  unsigned SubDstReg =
130  R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
131  MachineInstr *BMI =
132  TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
133  if (Chan > 0) {
134  BMI->bundleWithPred();
135  }
136  if (Mask) {
137  TII->addFlag(*BMI, 0, MO_FLAG_MASK);
138  }
139  if (Chan != 3)
140  TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
141  unsigned Opcode = BMI->getOpcode();
142  // While not strictly necessary from hw point of view, we force
143  // all src operands of a dot4 inst to belong to the same slot.
144  Register Src0 =
145  BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
146  .getReg();
147  Register Src1 =
148  BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
149  .getReg();
150  (void) Src0;
151  (void) Src1;
152  if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
153  (TRI.getEncodingValue(Src1) & 0xff) < 127)
154  assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
155  }
156  MI.eraseFromParent();
157  continue;
158  }
159  }
160 
161  bool IsReduction = TII->isReductionOp(MI.getOpcode());
162  bool IsVector = TII->isVector(MI);
163  bool IsCube = TII->isCubeOp(MI.getOpcode());
164  if (!IsReduction && !IsVector && !IsCube) {
165  continue;
166  }
167 
168  // Expand the instruction
169  //
170  // Reduction instructions:
171  // T0_X = DP4 T1_XYZW, T2_XYZW
172  // becomes:
173  // TO_X = DP4 T1_X, T2_X
174  // TO_Y (write masked) = DP4 T1_Y, T2_Y
175  // TO_Z (write masked) = DP4 T1_Z, T2_Z
176  // TO_W (write masked) = DP4 T1_W, T2_W
177  //
178  // Vector instructions:
179  // T0_X = MULLO_INT T1_X, T2_X
180  // becomes:
181  // T0_X = MULLO_INT T1_X, T2_X
182  // T0_Y (write masked) = MULLO_INT T1_X, T2_X
183  // T0_Z (write masked) = MULLO_INT T1_X, T2_X
184  // T0_W (write masked) = MULLO_INT T1_X, T2_X
185  //
186  // Cube instructions:
187  // T0_XYZW = CUBE T1_XYZW
188  // becomes:
189  // TO_X = CUBE T1_Z, T1_Y
190  // T0_Y = CUBE T1_Z, T1_X
191  // T0_Z = CUBE T1_X, T1_Z
192  // T0_W = CUBE T1_Y, T1_Z
193  for (unsigned Chan = 0; Chan < 4; Chan++) {
194  Register DstReg =
195  MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
196  Register Src0 =
197  MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
198  unsigned Src1 = 0;
199 
200  // Determine the correct source registers
201  if (!IsCube) {
202  int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
203  if (Src1Idx != -1) {
204  Src1 = MI.getOperand(Src1Idx).getReg();
205  }
206  }
207  if (IsReduction) {
208  unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan);
209  Src0 = TRI.getSubReg(Src0, SubRegIndex);
210  Src1 = TRI.getSubReg(Src1, SubRegIndex);
211  } else if (IsCube) {
212  static const int CubeSrcSwz[] = {2, 2, 0, 1};
213  unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]);
214  unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
215  Src1 = TRI.getSubReg(Src0, SubRegIndex1);
216  Src0 = TRI.getSubReg(Src0, SubRegIndex0);
217  }
218 
219  // Determine the correct destination registers;
220  bool Mask = false;
221  bool NotLast = true;
222  if (IsCube) {
223  unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan);
224  DstReg = TRI.getSubReg(DstReg, SubRegIndex);
225  } else {
226  // Mask the write if the original instruction does not write to
227  // the current Channel.
228  Mask = (Chan != TRI.getHWRegChan(DstReg));
229  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
230  DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
231  }
232 
233  // Set the IsLast bit
234  NotLast = (Chan != 3 );
235 
236  // Add the new instruction
237  unsigned Opcode = MI.getOpcode();
238  switch (Opcode) {
239  case R600::CUBE_r600_pseudo:
240  Opcode = R600::CUBE_r600_real;
241  break;
242  case R600::CUBE_eg_pseudo:
243  Opcode = R600::CUBE_eg_real;
244  break;
245  default:
246  break;
247  }
248 
249  MachineInstr *NewMI =
250  TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
251 
252  if (Chan != 0)
253  NewMI->bundleWithPred();
254  if (Mask) {
255  TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
256  }
257  if (NotLast) {
258  TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
259  }
260  SetFlagInNewMI(NewMI, &MI, R600::OpName::clamp);
261  SetFlagInNewMI(NewMI, &MI, R600::OpName::literal);
262  SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_abs);
263  SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_abs);
264  SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg);
265  SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg);
266  }
267  MI.eraseFromParent();
268  }
269  }
270  return false;
271 }
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FunctionPass * createR600ExpandSpecialInstrsPass()
Definition: R600ExpandSpecialInstrs.cpp:57
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INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE, "R600 Expand Special Instrs", false, false) INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass
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void bundleWithPred()
Bundle this instruction with its predecessor.
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uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
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static unsigned getSubRegFromChannel(unsigned Channel)
Definition: R600RegisterInfo.cpp:24
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Definition: R600Defines.h:19
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Definition: R600Subtarget.h:35
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Definition: R600ExpandSpecialInstrs.cpp:23
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Definition: R600ExpandSpecialInstrs.cpp:51
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Definition: MachineOperand.cpp:55
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