25 #define DEBUG_TYPE "r600-expand-special-instrs"
44 return "R600 Expand special instructions pass";
51 "R600 Expand Special Instrs",
false,
false)
55 char R600ExpandSpecialInstrsPass::
ID = 0;
60 return new R600ExpandSpecialInstrsPass();
63 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(
MachineInstr *NewMI,
65 int OpIdx =
TII->getOperandIdx(*OldMI,
Op);
68 TII->setImmOperand(*NewMI,
Op, Val);
72 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(
MachineFunction &MF) {
74 TII =
ST.getInstrInfo();
85 if (
TII->isLDSRetInstr(
MI.getOpcode())) {
86 int DstIdx =
TII->getOperandIdx(
MI.getOpcode(), R600::OpName::dst);
91 DstOp.setReg(R600::OQAP);
92 int LDSPredSelIdx =
TII->getOperandIdx(
MI.getOpcode(),
93 R600::OpName::pred_sel);
95 R600::OpName::pred_sel);
98 MI.getOperand(LDSPredSelIdx).getReg());
101 switch (
MI.getOpcode()) {
109 MI.getOperand(2).getImm(),
110 MI.getOperand(0).getReg(),
111 MI.getOperand(1).getReg(),
115 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
117 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
119 MI.eraseFromParent();
129 for (
unsigned Chan = 0; Chan < 4; ++Chan) {
130 bool Mask = (Chan !=
TRI.getHWRegChan(DstReg));
132 R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
134 TII->buildSlotOfVectorInstruction(
MBB, &
MI, Chan, SubDstReg);
147 BMI->
getOperand(
TII->getOperandIdx(Opcode, R600::OpName::src0))
150 BMI->
getOperand(
TII->getOperandIdx(Opcode, R600::OpName::src1))
156 assert(
TRI.getHWRegChan(Src0) ==
TRI.getHWRegChan(Src1));
158 MI.eraseFromParent();
163 bool IsReduction =
TII->isReductionOp(
MI.getOpcode());
164 bool IsVector =
TII->isVector(
MI);
165 bool IsCube =
TII->isCubeOp(
MI.getOpcode());
166 if (!IsReduction && !IsVector && !IsCube) {
195 for (
unsigned Chan = 0; Chan < 4; Chan++) {
197 MI.getOperand(
TII->getOperandIdx(
MI, R600::OpName::dst)).getReg();
199 MI.getOperand(
TII->getOperandIdx(
MI, R600::OpName::src0)).getReg();
204 int Src1Idx =
TII->getOperandIdx(
MI, R600::OpName::src1);
206 Src1 =
MI.getOperand(Src1Idx).getReg();
214 static const int CubeSrcSwz[] = {2, 2, 0, 1};
230 Mask = (Chan !=
TRI.getHWRegChan(DstReg));
232 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
236 NotLast = (Chan != 3 );
239 unsigned Opcode =
MI.getOpcode();
241 case R600::CUBE_r600_pseudo:
242 Opcode = R600::CUBE_r600_real;
244 case R600::CUBE_eg_pseudo:
245 Opcode = R600::CUBE_eg_real;
252 TII->buildDefaultInstruction(
MBB,
I, Opcode, DstReg, Src0, Src1);
263 SetFlagInNewMI(NewMI, &
MI, R600::OpName::literal);
264 SetFlagInNewMI(NewMI, &
MI, R600::OpName::src0_abs);
265 SetFlagInNewMI(NewMI, &
MI, R600::OpName::src1_abs);
266 SetFlagInNewMI(NewMI, &
MI, R600::OpName::src0_neg);
267 SetFlagInNewMI(NewMI, &
MI, R600::OpName::src1_neg);
269 MI.eraseFromParent();