LLVM  16.0.0git
SystemZAsmParser.cpp
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1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
12 #include "SystemZTargetStreamer.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstBuilder.h"
22 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Support/Casting.h"
33 #include "llvm/Support/SMLoc.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstddef>
37 #include <cstdint>
38 #include <iterator>
39 #include <memory>
40 #include <string>
41 
42 using namespace llvm;
43 
44 // Return true if Expr is in the range [MinValue, MaxValue]. If AllowSymbol
45 // is true any MCExpr is accepted (address displacement).
46 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue,
47  bool AllowSymbol = false) {
48  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
49  int64_t Value = CE->getValue();
50  return Value >= MinValue && Value <= MaxValue;
51  }
52  return AllowSymbol;
53 }
54 
55 namespace {
56 
57 enum RegisterKind {
58  GR32Reg,
59  GRH32Reg,
60  GR64Reg,
61  GR128Reg,
62  FP32Reg,
63  FP64Reg,
64  FP128Reg,
65  VR32Reg,
66  VR64Reg,
67  VR128Reg,
68  AR32Reg,
69  CR64Reg,
70 };
71 
72 enum MemoryKind {
73  BDMem,
74  BDXMem,
75  BDLMem,
76  BDRMem,
77  BDVMem
78 };
79 
80 class SystemZOperand : public MCParsedAsmOperand {
81 private:
82  enum OperandKind {
83  KindInvalid,
84  KindToken,
85  KindReg,
86  KindImm,
87  KindImmTLS,
88  KindMem
89  };
90 
91  OperandKind Kind;
92  SMLoc StartLoc, EndLoc;
93 
94  // A string of length Length, starting at Data.
95  struct TokenOp {
96  const char *Data;
97  unsigned Length;
98  };
99 
100  // LLVM register Num, which has kind Kind. In some ways it might be
101  // easier for this class to have a register bank (general, floating-point
102  // or access) and a raw register number (0-15). This would postpone the
103  // interpretation of the operand to the add*() methods and avoid the need
104  // for context-dependent parsing. However, we do things the current way
105  // because of the virtual getReg() method, which needs to distinguish
106  // between (say) %r0 used as a single register and %r0 used as a pair.
107  // Context-dependent parsing can also give us slightly better error
108  // messages when invalid pairs like %r1 are used.
109  struct RegOp {
110  RegisterKind Kind;
111  unsigned Num;
112  };
113 
114  // Base + Disp + Index, where Base and Index are LLVM registers or 0.
115  // MemKind says what type of memory this is and RegKind says what type
116  // the base register has (GR32Reg or GR64Reg). Length is the operand
117  // length for D(L,B)-style operands, otherwise it is null.
118  struct MemOp {
119  unsigned Base : 12;
120  unsigned Index : 12;
121  unsigned MemKind : 4;
122  unsigned RegKind : 4;
123  const MCExpr *Disp;
124  union {
125  const MCExpr *Imm;
126  unsigned Reg;
127  } Length;
128  };
129 
130  // Imm is an immediate operand, and Sym is an optional TLS symbol
131  // for use with a __tls_get_offset marker relocation.
132  struct ImmTLSOp {
133  const MCExpr *Imm;
134  const MCExpr *Sym;
135  };
136 
137  union {
138  TokenOp Token;
139  RegOp Reg;
140  const MCExpr *Imm;
141  ImmTLSOp ImmTLS;
142  MemOp Mem;
143  };
144 
145  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
146  // Add as immediates when possible. Null MCExpr = 0.
147  if (!Expr)
149  else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
150  Inst.addOperand(MCOperand::createImm(CE->getValue()));
151  else
152  Inst.addOperand(MCOperand::createExpr(Expr));
153  }
154 
155 public:
156  SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
157  : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
158 
159  // Create particular kinds of operand.
160  static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
161  SMLoc EndLoc) {
162  return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
163  }
164 
165  static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
166  auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
167  Op->Token.Data = Str.data();
168  Op->Token.Length = Str.size();
169  return Op;
170  }
171 
172  static std::unique_ptr<SystemZOperand>
173  createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
174  auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
175  Op->Reg.Kind = Kind;
176  Op->Reg.Num = Num;
177  return Op;
178  }
179 
180  static std::unique_ptr<SystemZOperand>
181  createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
182  auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
183  Op->Imm = Expr;
184  return Op;
185  }
186 
187  static std::unique_ptr<SystemZOperand>
188  createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
189  const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
190  unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
191  auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
192  Op->Mem.MemKind = MemKind;
193  Op->Mem.RegKind = RegKind;
194  Op->Mem.Base = Base;
195  Op->Mem.Index = Index;
196  Op->Mem.Disp = Disp;
197  if (MemKind == BDLMem)
198  Op->Mem.Length.Imm = LengthImm;
199  if (MemKind == BDRMem)
200  Op->Mem.Length.Reg = LengthReg;
201  return Op;
202  }
203 
204  static std::unique_ptr<SystemZOperand>
205  createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
206  SMLoc StartLoc, SMLoc EndLoc) {
207  auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
208  Op->ImmTLS.Imm = Imm;
209  Op->ImmTLS.Sym = Sym;
210  return Op;
211  }
212 
213  // Token operands
214  bool isToken() const override {
215  return Kind == KindToken;
216  }
217  StringRef getToken() const {
218  assert(Kind == KindToken && "Not a token");
219  return StringRef(Token.Data, Token.Length);
220  }
221 
222  // Register operands.
223  bool isReg() const override {
224  return Kind == KindReg;
225  }
226  bool isReg(RegisterKind RegKind) const {
227  return Kind == KindReg && Reg.Kind == RegKind;
228  }
229  unsigned getReg() const override {
230  assert(Kind == KindReg && "Not a register");
231  return Reg.Num;
232  }
233 
234  // Immediate operands.
235  bool isImm() const override {
236  return Kind == KindImm;
237  }
238  bool isImm(int64_t MinValue, int64_t MaxValue) const {
239  return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
240  }
241  const MCExpr *getImm() const {
242  assert(Kind == KindImm && "Not an immediate");
243  return Imm;
244  }
245 
246  // Immediate operands with optional TLS symbol.
247  bool isImmTLS() const {
248  return Kind == KindImmTLS;
249  }
250 
251  const ImmTLSOp getImmTLS() const {
252  assert(Kind == KindImmTLS && "Not a TLS immediate");
253  return ImmTLS;
254  }
255 
256  // Memory operands.
257  bool isMem() const override {
258  return Kind == KindMem;
259  }
260  bool isMem(MemoryKind MemKind) const {
261  return (Kind == KindMem &&
262  (Mem.MemKind == MemKind ||
263  // A BDMem can be treated as a BDXMem in which the index
264  // register field is 0.
265  (Mem.MemKind == BDMem && MemKind == BDXMem)));
266  }
267  bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
268  return isMem(MemKind) && Mem.RegKind == RegKind;
269  }
270  bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
271  return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
272  }
273  bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
274  return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
275  }
276  bool isMemDisp12Len4(RegisterKind RegKind) const {
277  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
278  }
279  bool isMemDisp12Len8(RegisterKind RegKind) const {
280  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
281  }
282 
283  const MemOp& getMem() const {
284  assert(Kind == KindMem && "Not a Mem operand");
285  return Mem;
286  }
287 
288  // Override MCParsedAsmOperand.
289  SMLoc getStartLoc() const override { return StartLoc; }
290  SMLoc getEndLoc() const override { return EndLoc; }
291  void print(raw_ostream &OS) const override;
292 
293  /// getLocRange - Get the range between the first and last token of this
294  /// operand.
295  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
296 
297  // Used by the TableGen code to add particular types of operand
298  // to an instruction.
299  void addRegOperands(MCInst &Inst, unsigned N) const {
300  assert(N == 1 && "Invalid number of operands");
302  }
303  void addImmOperands(MCInst &Inst, unsigned N) const {
304  assert(N == 1 && "Invalid number of operands");
305  addExpr(Inst, getImm());
306  }
307  void addBDAddrOperands(MCInst &Inst, unsigned N) const {
308  assert(N == 2 && "Invalid number of operands");
309  assert(isMem(BDMem) && "Invalid operand type");
310  Inst.addOperand(MCOperand::createReg(Mem.Base));
311  addExpr(Inst, Mem.Disp);
312  }
313  void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
314  assert(N == 3 && "Invalid number of operands");
315  assert(isMem(BDXMem) && "Invalid operand type");
316  Inst.addOperand(MCOperand::createReg(Mem.Base));
317  addExpr(Inst, Mem.Disp);
318  Inst.addOperand(MCOperand::createReg(Mem.Index));
319  }
320  void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
321  assert(N == 3 && "Invalid number of operands");
322  assert(isMem(BDLMem) && "Invalid operand type");
323  Inst.addOperand(MCOperand::createReg(Mem.Base));
324  addExpr(Inst, Mem.Disp);
325  addExpr(Inst, Mem.Length.Imm);
326  }
327  void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
328  assert(N == 3 && "Invalid number of operands");
329  assert(isMem(BDRMem) && "Invalid operand type");
330  Inst.addOperand(MCOperand::createReg(Mem.Base));
331  addExpr(Inst, Mem.Disp);
332  Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
333  }
334  void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
335  assert(N == 3 && "Invalid number of operands");
336  assert(isMem(BDVMem) && "Invalid operand type");
337  Inst.addOperand(MCOperand::createReg(Mem.Base));
338  addExpr(Inst, Mem.Disp);
339  Inst.addOperand(MCOperand::createReg(Mem.Index));
340  }
341  void addImmTLSOperands(MCInst &Inst, unsigned N) const {
342  assert(N == 2 && "Invalid number of operands");
343  assert(Kind == KindImmTLS && "Invalid operand type");
344  addExpr(Inst, ImmTLS.Imm);
345  if (ImmTLS.Sym)
346  addExpr(Inst, ImmTLS.Sym);
347  }
348 
349  // Used by the TableGen code to check for particular operand types.
350  bool isGR32() const { return isReg(GR32Reg); }
351  bool isGRH32() const { return isReg(GRH32Reg); }
352  bool isGRX32() const { return false; }
353  bool isGR64() const { return isReg(GR64Reg); }
354  bool isGR128() const { return isReg(GR128Reg); }
355  bool isADDR32() const { return isReg(GR32Reg); }
356  bool isADDR64() const { return isReg(GR64Reg); }
357  bool isADDR128() const { return false; }
358  bool isFP32() const { return isReg(FP32Reg); }
359  bool isFP64() const { return isReg(FP64Reg); }
360  bool isFP128() const { return isReg(FP128Reg); }
361  bool isVR32() const { return isReg(VR32Reg); }
362  bool isVR64() const { return isReg(VR64Reg); }
363  bool isVF128() const { return false; }
364  bool isVR128() const { return isReg(VR128Reg); }
365  bool isAR32() const { return isReg(AR32Reg); }
366  bool isCR64() const { return isReg(CR64Reg); }
367  bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
368  bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
369  bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
370  bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
371  bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
372  bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
373  bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
374  bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
375  bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
376  bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
377  bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
378  bool isU1Imm() const { return isImm(0, 1); }
379  bool isU2Imm() const { return isImm(0, 3); }
380  bool isU3Imm() const { return isImm(0, 7); }
381  bool isU4Imm() const { return isImm(0, 15); }
382  bool isU6Imm() const { return isImm(0, 63); }
383  bool isU8Imm() const { return isImm(0, 255); }
384  bool isS8Imm() const { return isImm(-128, 127); }
385  bool isU12Imm() const { return isImm(0, 4095); }
386  bool isU16Imm() const { return isImm(0, 65535); }
387  bool isS16Imm() const { return isImm(-32768, 32767); }
388  bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
389  bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
390  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
391 };
392 
393 class SystemZAsmParser : public MCTargetAsmParser {
394 #define GET_ASSEMBLER_HEADER
395 #include "SystemZGenAsmMatcher.inc"
396 
397 private:
398  MCAsmParser &Parser;
399  enum RegisterGroup {
400  RegGR,
401  RegFP,
402  RegV,
403  RegAR,
404  RegCR
405  };
406  struct Register {
407  RegisterGroup Group;
408  unsigned Num;
409  SMLoc StartLoc, EndLoc;
410  };
411 
412  SystemZTargetStreamer &getTargetStreamer() {
413  assert(getParser().getStreamer().getTargetStreamer() &&
414  "do not have a target streamer");
415  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
416  return static_cast<SystemZTargetStreamer &>(TS);
417  }
418 
419  bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
420 
421  bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
422 
424  RegisterKind Kind);
425 
426  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
427 
428  bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
429  Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
430  bool HasLength = false, bool HasVectorIndex = false);
431  bool parseAddressRegister(Register &Reg);
432 
433  bool ParseDirectiveInsn(SMLoc L);
434  bool ParseDirectiveMachine(SMLoc L);
435  bool ParseGNUAttribute(SMLoc L);
436 
438  MemoryKind MemKind,
439  RegisterKind RegKind);
440 
441  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
442  int64_t MaxVal, bool AllowTLS);
443 
444  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
445 
446  // Both the hlasm and att variants still rely on the basic gnu asm
447  // format with respect to inputs, clobbers, outputs etc.
448  //
449  // However, calling the overriden getAssemblerDialect() method in
450  // AsmParser is problematic. It either returns the AssemblerDialect field
451  // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
452  // unset, otherwise it returns the private AssemblerDialect field in
453  // AsmParser.
454  //
455  // The problematic part is because, we forcibly set the inline asm dialect
456  // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
457  // to the overriden getAssemblerDialect function in AsmParser.cpp, will
458  // not return the assembler dialect set in the respective MCAsmInfo instance.
459  //
460  // For this purpose, we explicitly query the SystemZMCAsmInfo instance
461  // here, to get the "correct" assembler dialect, and use it in various
462  // functions.
463  unsigned getMAIAssemblerDialect() {
464  return Parser.getContext().getAsmInfo()->getAssemblerDialect();
465  }
466 
467  // An alphabetic character in HLASM is a letter from 'A' through 'Z',
468  // or from 'a' through 'z', or '$', '_','#', or '@'.
469  inline bool isHLASMAlpha(char C) {
470  return isAlpha(C) || llvm::is_contained("_@#$", C);
471  }
472 
473  // A digit in HLASM is a number from 0 to 9.
474  inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
475 
476  // Are we parsing using the AD_HLASM dialect?
477  inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
478 
479  // Are we parsing using the AD_ATT dialect?
480  inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
481 
482 public:
483  SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
484  const MCInstrInfo &MII,
485  const MCTargetOptions &Options)
486  : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
488 
489  // Alias the .word directive to .short.
490  parser.addAliasForDirective(".word", ".short");
491 
492  // Initialize the set of available features.
493  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
494  }
495 
496  // Override MCTargetAsmParser.
497  bool ParseDirective(AsmToken DirectiveID) override;
498  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
499  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
500  bool RestoreOnFailure);
501  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
502  SMLoc &EndLoc) override;
503  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
504  SMLoc NameLoc, OperandVector &Operands) override;
505  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
508  bool MatchingInlineAsm) override;
509  bool isLabel(AsmToken &Token) override;
510 
511  // Used by the TableGen code to parse particular operand types.
513  return parseRegister(Operands, GR32Reg);
514  }
516  return parseRegister(Operands, GRH32Reg);
517  }
519  llvm_unreachable("GRX32 should only be used for pseudo instructions");
520  }
522  return parseRegister(Operands, GR64Reg);
523  }
525  return parseRegister(Operands, GR128Reg);
526  }
528  // For the AsmParser, we will accept %r0 for ADDR32 as well.
529  return parseRegister(Operands, GR32Reg);
530  }
532  // For the AsmParser, we will accept %r0 for ADDR64 as well.
533  return parseRegister(Operands, GR64Reg);
534  }
536  llvm_unreachable("Shouldn't be used as an operand");
537  }
539  return parseRegister(Operands, FP32Reg);
540  }
542  return parseRegister(Operands, FP64Reg);
543  }
545  return parseRegister(Operands, FP128Reg);
546  }
548  return parseRegister(Operands, VR32Reg);
549  }
551  return parseRegister(Operands, VR64Reg);
552  }
554  llvm_unreachable("Shouldn't be used as an operand");
555  }
557  return parseRegister(Operands, VR128Reg);
558  }
560  return parseRegister(Operands, AR32Reg);
561  }
563  return parseRegister(Operands, CR64Reg);
564  }
566  return parseAnyRegister(Operands);
567  }
569  return parseAddress(Operands, BDMem, GR32Reg);
570  }
572  return parseAddress(Operands, BDMem, GR64Reg);
573  }
574  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
575  return parseAddress(Operands, BDXMem, GR64Reg);
576  }
577  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
578  return parseAddress(Operands, BDLMem, GR64Reg);
579  }
580  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
581  return parseAddress(Operands, BDRMem, GR64Reg);
582  }
583  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
584  return parseAddress(Operands, BDVMem, GR64Reg);
585  }
587  return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
588  }
590  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
591  }
593  return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
594  }
596  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
597  }
598  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
599  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
600  }
601  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
602  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
603  }
604 };
605 
606 } // end anonymous namespace
607 
608 #define GET_REGISTER_MATCHER
609 #define GET_SUBTARGET_FEATURE_NAME
610 #define GET_MATCHER_IMPLEMENTATION
611 #define GET_MNEMONIC_SPELL_CHECKER
612 #include "SystemZGenAsmMatcher.inc"
613 
614 // Used for the .insn directives; contains information needed to parse the
615 // operands in the directive.
619  int32_t NumOperands;
620  MatchClassKind OperandKinds[7];
621 };
622 
623 // For equal_range comparison.
624 struct CompareInsn {
625  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
626  return LHS.Format < RHS;
627  }
628  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
629  return LHS < RHS.Format;
630  }
631  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
632  return LHS.Format < RHS.Format;
633  }
634 };
635 
636 // Table initializing information for parsing the .insn directive.
637 static struct InsnMatchEntry InsnMatchTable[] = {
638  /* Format, Opcode, NumOperands, OperandKinds */
639  { "e", SystemZ::InsnE, 1,
640  { MCK_U16Imm } },
641  { "ri", SystemZ::InsnRI, 3,
642  { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
643  { "rie", SystemZ::InsnRIE, 4,
644  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
645  { "ril", SystemZ::InsnRIL, 3,
646  { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
647  { "rilu", SystemZ::InsnRILU, 3,
648  { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
649  { "ris", SystemZ::InsnRIS, 5,
650  { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
651  { "rr", SystemZ::InsnRR, 3,
652  { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
653  { "rre", SystemZ::InsnRRE, 3,
654  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
655  { "rrf", SystemZ::InsnRRF, 5,
656  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
657  { "rrs", SystemZ::InsnRRS, 5,
658  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
659  { "rs", SystemZ::InsnRS, 4,
660  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
661  { "rse", SystemZ::InsnRSE, 4,
662  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
663  { "rsi", SystemZ::InsnRSI, 4,
664  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
665  { "rsy", SystemZ::InsnRSY, 4,
666  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
667  { "rx", SystemZ::InsnRX, 3,
668  { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
669  { "rxe", SystemZ::InsnRXE, 3,
670  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
671  { "rxf", SystemZ::InsnRXF, 4,
672  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
673  { "rxy", SystemZ::InsnRXY, 3,
674  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
675  { "s", SystemZ::InsnS, 2,
676  { MCK_U32Imm, MCK_BDAddr64Disp12 } },
677  { "si", SystemZ::InsnSI, 3,
678  { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
679  { "sil", SystemZ::InsnSIL, 3,
680  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
681  { "siy", SystemZ::InsnSIY, 3,
682  { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
683  { "ss", SystemZ::InsnSS, 4,
684  { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
685  { "sse", SystemZ::InsnSSE, 3,
686  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
687  { "ssf", SystemZ::InsnSSF, 4,
688  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
689  { "vri", SystemZ::InsnVRI, 6,
690  { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
691  { "vrr", SystemZ::InsnVRR, 7,
692  { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
693  MCK_U4Imm } },
694  { "vrs", SystemZ::InsnVRS, 5,
695  { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
696  { "vrv", SystemZ::InsnVRV, 4,
697  { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
698  { "vrx", SystemZ::InsnVRX, 4,
699  { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
700  { "vsi", SystemZ::InsnVSI, 4,
701  { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
702 };
703 
704 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
705  if (!E)
706  return;
707  if (auto *CE = dyn_cast<MCConstantExpr>(E))
708  OS << *CE;
709  else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
710  OS << *UE;
711  else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
712  OS << *BE;
713  else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
714  OS << *SRE;
715  else
716  OS << *E;
717 }
718 
719 void SystemZOperand::print(raw_ostream &OS) const {
720  switch (Kind) {
721  case KindToken:
722  OS << "Token:" << getToken();
723  break;
724  case KindReg:
725  OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
726  break;
727  case KindImm:
728  OS << "Imm:";
729  printMCExpr(getImm(), OS);
730  break;
731  case KindImmTLS:
732  OS << "ImmTLS:";
733  printMCExpr(getImmTLS().Imm, OS);
734  if (getImmTLS().Sym) {
735  OS << ", ";
736  printMCExpr(getImmTLS().Sym, OS);
737  }
738  break;
739  case KindMem: {
740  const MemOp &Op = getMem();
741  OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
742  if (Op.Base) {
743  OS << "(";
744  if (Op.MemKind == BDLMem)
745  OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
746  else if (Op.MemKind == BDRMem)
747  OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
748  if (Op.Index)
749  OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
751  OS << ")";
752  }
753  break;
754  }
755  case KindInvalid:
756  break;
757  }
758 }
759 
760 // Parse one register of the form %<prefix><number>.
761 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
762  Reg.StartLoc = Parser.getTok().getLoc();
763 
764  // Eat the % prefix.
765  if (Parser.getTok().isNot(AsmToken::Percent))
766  return Error(Parser.getTok().getLoc(), "register expected");
767  const AsmToken &PercentTok = Parser.getTok();
768  Parser.Lex();
769 
770  // Expect a register name.
771  if (Parser.getTok().isNot(AsmToken::Identifier)) {
772  if (RestoreOnFailure)
773  getLexer().UnLex(PercentTok);
774  return Error(Reg.StartLoc, "invalid register");
775  }
776 
777  // Check that there's a prefix.
778  StringRef Name = Parser.getTok().getString();
779  if (Name.size() < 2) {
780  if (RestoreOnFailure)
781  getLexer().UnLex(PercentTok);
782  return Error(Reg.StartLoc, "invalid register");
783  }
784  char Prefix = Name[0];
785 
786  // Treat the rest of the register name as a register number.
787  if (Name.substr(1).getAsInteger(10, Reg.Num)) {
788  if (RestoreOnFailure)
789  getLexer().UnLex(PercentTok);
790  return Error(Reg.StartLoc, "invalid register");
791  }
792 
793  // Look for valid combinations of prefix and number.
794  if (Prefix == 'r' && Reg.Num < 16)
795  Reg.Group = RegGR;
796  else if (Prefix == 'f' && Reg.Num < 16)
797  Reg.Group = RegFP;
798  else if (Prefix == 'v' && Reg.Num < 32)
799  Reg.Group = RegV;
800  else if (Prefix == 'a' && Reg.Num < 16)
801  Reg.Group = RegAR;
802  else if (Prefix == 'c' && Reg.Num < 16)
803  Reg.Group = RegCR;
804  else {
805  if (RestoreOnFailure)
806  getLexer().UnLex(PercentTok);
807  return Error(Reg.StartLoc, "invalid register");
808  }
809 
810  Reg.EndLoc = Parser.getTok().getLoc();
811  Parser.Lex();
812  return false;
813 }
814 
815 // Parse a register of kind Kind and add it to Operands.
817 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
818  Register Reg;
819  RegisterGroup Group;
820  switch (Kind) {
821  case GR32Reg:
822  case GRH32Reg:
823  case GR64Reg:
824  case GR128Reg:
825  Group = RegGR;
826  break;
827  case FP32Reg:
828  case FP64Reg:
829  case FP128Reg:
830  Group = RegFP;
831  break;
832  case VR32Reg:
833  case VR64Reg:
834  case VR128Reg:
835  Group = RegV;
836  break;
837  case AR32Reg:
838  Group = RegAR;
839  break;
840  case CR64Reg:
841  Group = RegCR;
842  break;
843  }
844 
845  // Handle register names of the form %<prefix><number>
846  if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
847  if (parseRegister(Reg))
848  return MatchOperand_ParseFail;
849 
850  // Check the parsed register group "Reg.Group" with the expected "Group"
851  // Have to error out if user specified wrong prefix.
852  switch (Group) {
853  case RegGR:
854  case RegFP:
855  case RegAR:
856  case RegCR:
857  if (Group != Reg.Group) {
858  Error(Reg.StartLoc, "invalid operand for instruction");
859  return MatchOperand_ParseFail;
860  }
861  break;
862  case RegV:
863  if (Reg.Group != RegV && Reg.Group != RegFP) {
864  Error(Reg.StartLoc, "invalid operand for instruction");
865  return MatchOperand_ParseFail;
866  }
867  break;
868  }
869  } else if (Parser.getTok().is(AsmToken::Integer)) {
870  if (parseIntegerRegister(Reg, Group))
871  return MatchOperand_ParseFail;
872  }
873  // Otherwise we didn't match a register operand.
874  else
875  return MatchOperand_NoMatch;
876 
877  // Determine the LLVM register number according to Kind.
878  const unsigned *Regs;
879  switch (Kind) {
880  case GR32Reg: Regs = SystemZMC::GR32Regs; break;
881  case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
882  case GR64Reg: Regs = SystemZMC::GR64Regs; break;
883  case GR128Reg: Regs = SystemZMC::GR128Regs; break;
884  case FP32Reg: Regs = SystemZMC::FP32Regs; break;
885  case FP64Reg: Regs = SystemZMC::FP64Regs; break;
886  case FP128Reg: Regs = SystemZMC::FP128Regs; break;
887  case VR32Reg: Regs = SystemZMC::VR32Regs; break;
888  case VR64Reg: Regs = SystemZMC::VR64Regs; break;
889  case VR128Reg: Regs = SystemZMC::VR128Regs; break;
890  case AR32Reg: Regs = SystemZMC::AR32Regs; break;
891  case CR64Reg: Regs = SystemZMC::CR64Regs; break;
892  }
893  if (Regs[Reg.Num] == 0) {
894  Error(Reg.StartLoc, "invalid register pair");
895  return MatchOperand_ParseFail;
896  }
897 
898  Operands.push_back(
899  SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
900  return MatchOperand_Success;
901 }
902 
903 // Parse any type of register (including integers) and add it to Operands.
905 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
906  SMLoc StartLoc = Parser.getTok().getLoc();
907 
908  // Handle integer values.
909  if (Parser.getTok().is(AsmToken::Integer)) {
910  const MCExpr *Register;
911  if (Parser.parseExpression(Register))
912  return MatchOperand_ParseFail;
913 
914  if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
915  int64_t Value = CE->getValue();
916  if (Value < 0 || Value > 15) {
917  Error(StartLoc, "invalid register");
918  return MatchOperand_ParseFail;
919  }
920  }
921 
922  SMLoc EndLoc =
923  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
924 
925  Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
926  }
927  else {
928  if (isParsingHLASM())
929  return MatchOperand_NoMatch;
930 
931  Register Reg;
932  if (parseRegister(Reg))
933  return MatchOperand_ParseFail;
934 
935  if (Reg.Num > 15) {
936  Error(StartLoc, "invalid register");
937  return MatchOperand_ParseFail;
938  }
939 
940  // Map to the correct register kind.
941  RegisterKind Kind;
942  unsigned RegNo;
943  if (Reg.Group == RegGR) {
944  Kind = GR64Reg;
945  RegNo = SystemZMC::GR64Regs[Reg.Num];
946  }
947  else if (Reg.Group == RegFP) {
948  Kind = FP64Reg;
949  RegNo = SystemZMC::FP64Regs[Reg.Num];
950  }
951  else if (Reg.Group == RegV) {
952  Kind = VR128Reg;
953  RegNo = SystemZMC::VR128Regs[Reg.Num];
954  }
955  else if (Reg.Group == RegAR) {
956  Kind = AR32Reg;
957  RegNo = SystemZMC::AR32Regs[Reg.Num];
958  }
959  else if (Reg.Group == RegCR) {
960  Kind = CR64Reg;
961  RegNo = SystemZMC::CR64Regs[Reg.Num];
962  }
963  else {
964  return MatchOperand_ParseFail;
965  }
966 
967  Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
968  Reg.StartLoc, Reg.EndLoc));
969  }
970  return MatchOperand_Success;
971 }
972 
973 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
974  RegisterGroup Group) {
975  Reg.StartLoc = Parser.getTok().getLoc();
976  // We have an integer token
977  const MCExpr *Register;
978  if (Parser.parseExpression(Register))
979  return true;
980 
981  const auto *CE = dyn_cast<MCConstantExpr>(Register);
982  if (!CE)
983  return true;
984 
985  int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
986  int64_t Value = CE->getValue();
987  if (Value < 0 || Value > MaxRegNum) {
988  Error(Parser.getTok().getLoc(), "invalid register");
989  return true;
990  }
991 
992  // Assign the Register Number
993  Reg.Num = (unsigned)Value;
994  Reg.Group = Group;
995  Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
996 
997  // At this point, successfully parsed an integer register.
998  return false;
999 }
1000 
1001 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
1002 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
1003  bool &HaveReg2, Register &Reg2,
1004  const MCExpr *&Disp, const MCExpr *&Length,
1005  bool HasLength, bool HasVectorIndex) {
1006  // Parse the displacement, which must always be present.
1007  if (getParser().parseExpression(Disp))
1008  return true;
1009 
1010  // Parse the optional base and index.
1011  HaveReg1 = false;
1012  HaveReg2 = false;
1013  Length = nullptr;
1014 
1015  // If we have a scenario as below:
1016  // vgef %v0, 0(0), 0
1017  // This is an example of a "BDVMem" instruction type.
1018  //
1019  // So when we parse this as an integer register, the register group
1020  // needs to be tied to "RegV". Usually when the prefix is passed in
1021  // as %<prefix><reg-number> its easy to check which group it should belong to
1022  // However, if we're passing in just the integer there's no real way to
1023  // "check" what register group it should belong to.
1024  //
1025  // When the user passes in the register as an integer, the user assumes that
1026  // the compiler is responsible for substituting it as the right kind of
1027  // register. Whereas, when the user specifies a "prefix", the onus is on
1028  // the user to make sure they pass in the right kind of register.
1029  //
1030  // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1031  // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1032  // (i.e. insn is of type BDVMem) is true.
1033  RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1034 
1035  if (getLexer().is(AsmToken::LParen)) {
1036  Parser.Lex();
1037 
1038  if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
1039  // Parse the first register.
1040  HaveReg1 = true;
1041  if (parseRegister(Reg1))
1042  return true;
1043  }
1044  // So if we have an integer as the first token in ([tok1], ..), it could:
1045  // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1046  // instructions)
1047  // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1048  else if (getLexer().is(AsmToken::Integer)) {
1049  if (HasLength) {
1050  // Instruction has a "Length" field, safe to parse the first token as
1051  // the "Length" field
1052  if (getParser().parseExpression(Length))
1053  return true;
1054  } else {
1055  // Otherwise, if the instruction has no "Length" field, parse the
1056  // token as a "Register". We don't have to worry about whether the
1057  // instruction is invalid here, because the caller will take care of
1058  // error reporting.
1059  HaveReg1 = true;
1060  if (parseIntegerRegister(Reg1, RegGroup))
1061  return true;
1062  }
1063  } else {
1064  // If its not an integer or a percent token, then if the instruction
1065  // is reported to have a "Length" then, parse it as "Length".
1066  if (HasLength) {
1067  if (getParser().parseExpression(Length))
1068  return true;
1069  }
1070  }
1071 
1072  // Check whether there's a second register.
1073  if (getLexer().is(AsmToken::Comma)) {
1074  Parser.Lex();
1075  HaveReg2 = true;
1076 
1077  if (getLexer().is(AsmToken::Integer)) {
1078  if (parseIntegerRegister(Reg2, RegGR))
1079  return true;
1080  } else {
1081  if (isParsingATT() && parseRegister(Reg2))
1082  return true;
1083  }
1084  }
1085 
1086  // Consume the closing bracket.
1087  if (getLexer().isNot(AsmToken::RParen))
1088  return Error(Parser.getTok().getLoc(), "unexpected token in address");
1089  Parser.Lex();
1090  }
1091  return false;
1092 }
1093 
1094 // Verify that Reg is a valid address register (base or index).
1095 bool
1096 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1097  if (Reg.Group == RegV) {
1098  Error(Reg.StartLoc, "invalid use of vector addressing");
1099  return true;
1100  } else if (Reg.Group != RegGR) {
1101  Error(Reg.StartLoc, "invalid address register");
1102  return true;
1103  }
1104  return false;
1105 }
1106 
1107 // Parse a memory operand and add it to Operands. The other arguments
1108 // are as above.
1110 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1111  RegisterKind RegKind) {
1112  SMLoc StartLoc = Parser.getTok().getLoc();
1113  unsigned Base = 0, Index = 0, LengthReg = 0;
1114  Register Reg1, Reg2;
1115  bool HaveReg1, HaveReg2;
1116  const MCExpr *Disp;
1117  const MCExpr *Length;
1118 
1119  bool HasLength = (MemKind == BDLMem) ? true : false;
1120  bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1121  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1122  HasVectorIndex))
1123  return MatchOperand_ParseFail;
1124 
1125  const unsigned *Regs;
1126  switch (RegKind) {
1127  case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1128  case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1129  default: llvm_unreachable("invalid RegKind");
1130  }
1131 
1132  switch (MemKind) {
1133  case BDMem:
1134  // If we have Reg1, it must be an address register.
1135  if (HaveReg1) {
1136  if (parseAddressRegister(Reg1))
1137  return MatchOperand_ParseFail;
1138  Base = Regs[Reg1.Num];
1139  }
1140  // There must be no Reg2.
1141  if (HaveReg2) {
1142  Error(StartLoc, "invalid use of indexed addressing");
1143  return MatchOperand_ParseFail;
1144  }
1145  break;
1146  case BDXMem:
1147  // If we have Reg1, it must be an address register.
1148  if (HaveReg1) {
1149  if (parseAddressRegister(Reg1))
1150  return MatchOperand_ParseFail;
1151  // If the are two registers, the first one is the index and the
1152  // second is the base.
1153  if (HaveReg2)
1154  Index = Regs[Reg1.Num];
1155  else
1156  Base = Regs[Reg1.Num];
1157  }
1158  // If we have Reg2, it must be an address register.
1159  if (HaveReg2) {
1160  if (parseAddressRegister(Reg2))
1161  return MatchOperand_ParseFail;
1162  Base = Regs[Reg2.Num];
1163  }
1164  break;
1165  case BDLMem:
1166  // If we have Reg2, it must be an address register.
1167  if (HaveReg2) {
1168  if (parseAddressRegister(Reg2))
1169  return MatchOperand_ParseFail;
1170  Base = Regs[Reg2.Num];
1171  }
1172  // We cannot support base+index addressing.
1173  if (HaveReg1 && HaveReg2) {
1174  Error(StartLoc, "invalid use of indexed addressing");
1175  return MatchOperand_ParseFail;
1176  }
1177  // We must have a length.
1178  if (!Length) {
1179  Error(StartLoc, "missing length in address");
1180  return MatchOperand_ParseFail;
1181  }
1182  break;
1183  case BDRMem:
1184  // We must have Reg1, and it must be a GPR.
1185  if (!HaveReg1 || Reg1.Group != RegGR) {
1186  Error(StartLoc, "invalid operand for instruction");
1187  return MatchOperand_ParseFail;
1188  }
1189  LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1190  // If we have Reg2, it must be an address register.
1191  if (HaveReg2) {
1192  if (parseAddressRegister(Reg2))
1193  return MatchOperand_ParseFail;
1194  Base = Regs[Reg2.Num];
1195  }
1196  break;
1197  case BDVMem:
1198  // We must have Reg1, and it must be a vector register.
1199  if (!HaveReg1 || Reg1.Group != RegV) {
1200  Error(StartLoc, "vector index required in address");
1201  return MatchOperand_ParseFail;
1202  }
1203  Index = SystemZMC::VR128Regs[Reg1.Num];
1204  // If we have Reg2, it must be an address register.
1205  if (HaveReg2) {
1206  if (parseAddressRegister(Reg2))
1207  return MatchOperand_ParseFail;
1208  Base = Regs[Reg2.Num];
1209  }
1210  break;
1211  }
1212 
1213  SMLoc EndLoc =
1214  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1215  Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1216  Index, Length, LengthReg,
1217  StartLoc, EndLoc));
1218  return MatchOperand_Success;
1219 }
1220 
1221 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1222  StringRef IDVal = DirectiveID.getIdentifier();
1223 
1224  if (IDVal == ".insn")
1225  return ParseDirectiveInsn(DirectiveID.getLoc());
1226  if (IDVal == ".machine")
1227  return ParseDirectiveMachine(DirectiveID.getLoc());
1228  if (IDVal.startswith(".gnu_attribute"))
1229  return ParseGNUAttribute(DirectiveID.getLoc());
1230 
1231  return true;
1232 }
1233 
1234 /// ParseDirectiveInsn
1235 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1236 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1237  MCAsmParser &Parser = getParser();
1238 
1239  // Expect instruction format as identifier.
1240  StringRef Format;
1241  SMLoc ErrorLoc = Parser.getTok().getLoc();
1242  if (Parser.parseIdentifier(Format))
1243  return Error(ErrorLoc, "expected instruction format");
1244 
1246 
1247  // Find entry for this format in InsnMatchTable.
1248  auto EntryRange =
1249  std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1250  Format, CompareInsn());
1251 
1252  // If first == second, couldn't find a match in the table.
1253  if (EntryRange.first == EntryRange.second)
1254  return Error(ErrorLoc, "unrecognized format");
1255 
1256  struct InsnMatchEntry *Entry = EntryRange.first;
1257 
1258  // Format should match from equal_range.
1259  assert(Entry->Format == Format);
1260 
1261  // Parse the following operands using the table's information.
1262  for (int i = 0; i < Entry->NumOperands; i++) {
1263  MatchClassKind Kind = Entry->OperandKinds[i];
1264 
1265  SMLoc StartLoc = Parser.getTok().getLoc();
1266 
1267  // Always expect commas as separators for operands.
1268  if (getLexer().isNot(AsmToken::Comma))
1269  return Error(StartLoc, "unexpected token in directive");
1270  Lex();
1271 
1272  // Parse operands.
1273  OperandMatchResultTy ResTy;
1274  if (Kind == MCK_AnyReg)
1275  ResTy = parseAnyReg(Operands);
1276  else if (Kind == MCK_VR128)
1277  ResTy = parseVR128(Operands);
1278  else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1279  ResTy = parseBDXAddr64(Operands);
1280  else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1281  ResTy = parseBDAddr64(Operands);
1282  else if (Kind == MCK_BDVAddr64Disp12)
1283  ResTy = parseBDVAddr64(Operands);
1284  else if (Kind == MCK_PCRel32)
1285  ResTy = parsePCRel32(Operands);
1286  else if (Kind == MCK_PCRel16)
1287  ResTy = parsePCRel16(Operands);
1288  else {
1289  // Only remaining operand kind is an immediate.
1290  const MCExpr *Expr;
1291  SMLoc StartLoc = Parser.getTok().getLoc();
1292 
1293  // Expect immediate expression.
1294  if (Parser.parseExpression(Expr))
1295  return Error(StartLoc, "unexpected token in directive");
1296 
1297  SMLoc EndLoc =
1298  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1299 
1300  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1301  ResTy = MatchOperand_Success;
1302  }
1303 
1304  if (ResTy != MatchOperand_Success)
1305  return true;
1306  }
1307 
1308  // Build the instruction with the parsed operands.
1309  MCInst Inst = MCInstBuilder(Entry->Opcode);
1310 
1311  for (size_t i = 0; i < Operands.size(); i++) {
1312  MCParsedAsmOperand &Operand = *Operands[i];
1313  MatchClassKind Kind = Entry->OperandKinds[i];
1314 
1315  // Verify operand.
1316  unsigned Res = validateOperandClass(Operand, Kind);
1317  if (Res != Match_Success)
1318  return Error(Operand.getStartLoc(), "unexpected operand type");
1319 
1320  // Add operands to instruction.
1321  SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1322  if (ZOperand.isReg())
1323  ZOperand.addRegOperands(Inst, 1);
1324  else if (ZOperand.isMem(BDMem))
1325  ZOperand.addBDAddrOperands(Inst, 2);
1326  else if (ZOperand.isMem(BDXMem))
1327  ZOperand.addBDXAddrOperands(Inst, 3);
1328  else if (ZOperand.isMem(BDVMem))
1329  ZOperand.addBDVAddrOperands(Inst, 3);
1330  else if (ZOperand.isImm())
1331  ZOperand.addImmOperands(Inst, 1);
1332  else
1333  llvm_unreachable("unexpected operand type");
1334  }
1335 
1336  // Emit as a regular instruction.
1337  Parser.getStreamer().emitInstruction(Inst, getSTI());
1338 
1339  return false;
1340 }
1341 
1342 /// ParseDirectiveMachine
1343 /// ::= .machine [ mcpu ]
1344 bool SystemZAsmParser::ParseDirectiveMachine(SMLoc L) {
1345  MCAsmParser &Parser = getParser();
1346  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1347  Parser.getTok().isNot(AsmToken::String))
1348  return Error(L, "unexpected token in '.machine' directive");
1349 
1350  StringRef CPU = Parser.getTok().getIdentifier();
1351  Parser.Lex();
1352  if (parseToken(AsmToken::EndOfStatement))
1353  return addErrorSuffix(" in '.machine' directive");
1354 
1355  MCSubtargetInfo &STI = copySTI();
1356  STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
1357  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1358 
1359  getTargetStreamer().emitMachine(CPU);
1360 
1361  return false;
1362 }
1363 
1364 bool SystemZAsmParser::ParseGNUAttribute(SMLoc L) {
1365  int64_t Tag;
1366  int64_t IntegerValue;
1367  if (!Parser.parseGNUAttribute(L, Tag, IntegerValue))
1368  return false;
1369 
1370  // Tag_GNU_S390_ABI_Vector tag is '8' and can be 0, 1, or 2.
1371  if (Tag != 8 || (IntegerValue < 0 || IntegerValue > 2)) {
1372  Error(Parser.getTok().getLoc(),
1373  "Unrecognized .gnu_attribute tag/value pair.");
1374  return false;
1375  }
1376 
1377  Parser.getStreamer().emitGNUAttribute(Tag, IntegerValue);
1378 
1379  return true;
1380 }
1381 
1382 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1383  SMLoc &EndLoc, bool RestoreOnFailure) {
1384  Register Reg;
1385  if (parseRegister(Reg, RestoreOnFailure))
1386  return true;
1387  if (Reg.Group == RegGR)
1388  RegNo = SystemZMC::GR64Regs[Reg.Num];
1389  else if (Reg.Group == RegFP)
1390  RegNo = SystemZMC::FP64Regs[Reg.Num];
1391  else if (Reg.Group == RegV)
1392  RegNo = SystemZMC::VR128Regs[Reg.Num];
1393  else if (Reg.Group == RegAR)
1394  RegNo = SystemZMC::AR32Regs[Reg.Num];
1395  else if (Reg.Group == RegCR)
1396  RegNo = SystemZMC::CR64Regs[Reg.Num];
1397  StartLoc = Reg.StartLoc;
1398  EndLoc = Reg.EndLoc;
1399  return false;
1400 }
1401 
1402 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1403  SMLoc &EndLoc) {
1404  return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1405 }
1406 
1407 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1408  SMLoc &StartLoc,
1409  SMLoc &EndLoc) {
1410  bool Result =
1411  ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1412  bool PendingErrors = getParser().hasPendingError();
1413  getParser().clearPendingErrors();
1414  if (PendingErrors)
1415  return MatchOperand_ParseFail;
1416  if (Result)
1417  return MatchOperand_NoMatch;
1418  return MatchOperand_Success;
1419 }
1420 
1421 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1422  StringRef Name, SMLoc NameLoc,
1424 
1425  // Apply mnemonic aliases first, before doing anything else, in
1426  // case the target uses it.
1427  applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1428 
1429  Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1430 
1431  // Read the remaining operands.
1432  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1433  // Read the first operand.
1434  if (parseOperand(Operands, Name)) {
1435  return true;
1436  }
1437 
1438  // Read any subsequent operands.
1439  while (getLexer().is(AsmToken::Comma)) {
1440  Parser.Lex();
1441 
1442  if (isParsingHLASM() && getLexer().is(AsmToken::Space))
1443  return Error(
1444  Parser.getTok().getLoc(),
1445  "No space allowed between comma that separates operand entries");
1446 
1447  if (parseOperand(Operands, Name)) {
1448  return true;
1449  }
1450  }
1451 
1452  // Under the HLASM variant, we could have the remark field
1453  // The remark field occurs after the operation entries
1454  // There is a space that separates the operation entries and the
1455  // remark field.
1456  if (isParsingHLASM() && getTok().is(AsmToken::Space)) {
1457  // We've confirmed that there is a Remark field.
1458  StringRef Remark(getLexer().LexUntilEndOfStatement());
1459  Parser.Lex();
1460 
1461  // If there is nothing after the space, then there is nothing to emit
1462  // We could have a situation as this:
1463  // " \n"
1464  // After lexing above, we will have
1465  // "\n"
1466  // This isn't an explicit remark field, so we don't have to output
1467  // this as a comment.
1468  if (Remark.size())
1469  // Output the entire Remarks Field as a comment
1470  getStreamer().AddComment(Remark);
1471  }
1472 
1473  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1474  SMLoc Loc = getLexer().getLoc();
1475  return Error(Loc, "unexpected token in argument list");
1476  }
1477  }
1478 
1479  // Consume the EndOfStatement.
1480  Parser.Lex();
1481  return false;
1482 }
1483 
1484 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1485  StringRef Mnemonic) {
1486  // Check if the current operand has a custom associated parser, if so, try to
1487  // custom parse the operand, or fallback to the general approach. Force all
1488  // features to be available during the operand check, or else we will fail to
1489  // find the custom parser, and then we will later get an InvalidOperand error
1490  // instead of a MissingFeature errror.
1491  FeatureBitset AvailableFeatures = getAvailableFeatures();
1493  All.set();
1494  setAvailableFeatures(All);
1495  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1496  setAvailableFeatures(AvailableFeatures);
1497  if (ResTy == MatchOperand_Success)
1498  return false;
1499 
1500  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1501  // there was a match, but an error occurred, in which case, just return that
1502  // the operand parsing failed.
1503  if (ResTy == MatchOperand_ParseFail)
1504  return true;
1505 
1506  // Check for a register. All real register operands should have used
1507  // a context-dependent parse routine, which gives the required register
1508  // class. The code is here to mop up other cases, like those where
1509  // the instruction isn't recognized.
1510  if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
1511  Register Reg;
1512  if (parseRegister(Reg))
1513  return true;
1514  Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1515  return false;
1516  }
1517 
1518  // The only other type of operand is an immediate or address. As above,
1519  // real address operands should have used a context-dependent parse routine,
1520  // so we treat any plain expression as an immediate.
1521  SMLoc StartLoc = Parser.getTok().getLoc();
1522  Register Reg1, Reg2;
1523  bool HaveReg1, HaveReg2;
1524  const MCExpr *Expr;
1525  const MCExpr *Length;
1526  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1527  /*HasLength*/ true, /*HasVectorIndex*/ true))
1528  return true;
1529  // If the register combination is not valid for any instruction, reject it.
1530  // Otherwise, fall back to reporting an unrecognized instruction.
1531  if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1532  && parseAddressRegister(Reg1))
1533  return true;
1534  if (HaveReg2 && parseAddressRegister(Reg2))
1535  return true;
1536 
1537  SMLoc EndLoc =
1538  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1539  if (HaveReg1 || HaveReg2 || Length)
1540  Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1541  else
1542  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1543  return false;
1544 }
1545 
1546 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1548  MCStreamer &Out,
1550  bool MatchingInlineAsm) {
1551  MCInst Inst;
1552  unsigned MatchResult;
1553 
1554  unsigned Dialect = getMAIAssemblerDialect();
1555 
1556  FeatureBitset MissingFeatures;
1557  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1558  MatchingInlineAsm, Dialect);
1559  switch (MatchResult) {
1560  case Match_Success:
1561  Inst.setLoc(IDLoc);
1562  Out.emitInstruction(Inst, getSTI());
1563  return false;
1564 
1565  case Match_MissingFeature: {
1566  assert(MissingFeatures.any() && "Unknown missing feature!");
1567  // Special case the error message for the very common case where only
1568  // a single subtarget feature is missing
1569  std::string Msg = "instruction requires:";
1570  for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1571  if (MissingFeatures[I]) {
1572  Msg += " ";
1574  }
1575  }
1576  return Error(IDLoc, Msg);
1577  }
1578 
1579  case Match_InvalidOperand: {
1580  SMLoc ErrorLoc = IDLoc;
1581  if (ErrorInfo != ~0ULL) {
1582  if (ErrorInfo >= Operands.size())
1583  return Error(IDLoc, "too few operands for instruction");
1584 
1585  ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1586  if (ErrorLoc == SMLoc())
1587  ErrorLoc = IDLoc;
1588  }
1589  return Error(ErrorLoc, "invalid operand for instruction");
1590  }
1591 
1592  case Match_MnemonicFail: {
1593  FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1594  std::string Suggestion = SystemZMnemonicSpellCheck(
1595  ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1596  return Error(IDLoc, "invalid instruction" + Suggestion,
1597  ((SystemZOperand &)*Operands[0]).getLocRange());
1598  }
1599  }
1600 
1601  llvm_unreachable("Unexpected match type");
1602 }
1603 
1605 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1606  int64_t MaxVal, bool AllowTLS) {
1607  MCContext &Ctx = getContext();
1608  MCStreamer &Out = getStreamer();
1609  const MCExpr *Expr;
1610  SMLoc StartLoc = Parser.getTok().getLoc();
1611  if (getParser().parseExpression(Expr))
1612  return MatchOperand_NoMatch;
1613 
1614  auto isOutOfRangeConstant = [&](const MCExpr *E, bool Negate) -> bool {
1615  if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1616  int64_t Value = CE->getValue();
1617  if (Negate)
1618  Value = -Value;
1619  if ((Value & 1) || Value < MinVal || Value > MaxVal)
1620  return true;
1621  }
1622  return false;
1623  };
1624 
1625  // For consistency with the GNU assembler, treat immediates as offsets
1626  // from ".".
1627  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1628  if (isParsingHLASM()) {
1629  Error(StartLoc, "Expected PC-relative expression");
1630  return MatchOperand_ParseFail;
1631  }
1632  if (isOutOfRangeConstant(CE, false)) {
1633  Error(StartLoc, "offset out of range");
1634  return MatchOperand_ParseFail;
1635  }
1636  int64_t Value = CE->getValue();
1637  MCSymbol *Sym = Ctx.createTempSymbol();
1638  Out.emitLabel(Sym);
1640  Ctx);
1641  Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1642  }
1643 
1644  // For consistency with the GNU assembler, conservatively assume that a
1645  // constant offset must by itself be within the given size range.
1646  if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1647  if (isOutOfRangeConstant(BE->getLHS(), false) ||
1648  isOutOfRangeConstant(BE->getRHS(),
1649  BE->getOpcode() == MCBinaryExpr::Sub)) {
1650  Error(StartLoc, "offset out of range");
1651  return MatchOperand_ParseFail;
1652  }
1653 
1654  // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1655  const MCExpr *Sym = nullptr;
1656  if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1657  Parser.Lex();
1658 
1659  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1660  Error(Parser.getTok().getLoc(), "unexpected token");
1661  return MatchOperand_ParseFail;
1662  }
1663 
1665  StringRef Name = Parser.getTok().getString();
1666  if (Name == "tls_gdcall")
1668  else if (Name == "tls_ldcall")
1670  else {
1671  Error(Parser.getTok().getLoc(), "unknown TLS tag");
1672  return MatchOperand_ParseFail;
1673  }
1674  Parser.Lex();
1675 
1676  if (Parser.getTok().isNot(AsmToken::Colon)) {
1677  Error(Parser.getTok().getLoc(), "unexpected token");
1678  return MatchOperand_ParseFail;
1679  }
1680  Parser.Lex();
1681 
1682  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1683  Error(Parser.getTok().getLoc(), "unexpected token");
1684  return MatchOperand_ParseFail;
1685  }
1686 
1687  StringRef Identifier = Parser.getTok().getString();
1689  Kind, Ctx);
1690  Parser.Lex();
1691  }
1692 
1693  SMLoc EndLoc =
1694  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1695 
1696  if (AllowTLS)
1697  Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1698  StartLoc, EndLoc));
1699  else
1700  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1701 
1702  return MatchOperand_Success;
1703 }
1704 
1705 bool SystemZAsmParser::isLabel(AsmToken &Token) {
1706  if (isParsingATT())
1707  return true;
1708 
1709  // HLASM labels are ordinary symbols.
1710  // An HLASM label always starts at column 1.
1711  // An ordinary symbol syntax is laid out as follows:
1712  // Rules:
1713  // 1. Has to start with an "alphabetic character". Can be followed by up to
1714  // 62 alphanumeric characters. An "alphabetic character", in this scenario,
1715  // is a letter from 'A' through 'Z', or from 'a' through 'z',
1716  // or '$', '_', '#', or '@'
1717  // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1718  // are all treated as the same symbol. However, the processing for the case
1719  // folding will not be done in this function.
1720  StringRef RawLabel = Token.getString();
1721  SMLoc Loc = Token.getLoc();
1722 
1723  // An HLASM label cannot be empty.
1724  if (!RawLabel.size())
1725  return !Error(Loc, "HLASM Label cannot be empty");
1726 
1727  // An HLASM label cannot exceed greater than 63 characters.
1728  if (RawLabel.size() > 63)
1729  return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1730 
1731  // A label must start with an "alphabetic character".
1732  if (!isHLASMAlpha(RawLabel[0]))
1733  return !Error(Loc, "HLASM Label has to start with an alphabetic "
1734  "character or the underscore character");
1735 
1736  // Now, we've established that the length is valid
1737  // and the first character is alphabetic.
1738  // Check whether remaining string is alphanumeric.
1739  for (unsigned I = 1; I < RawLabel.size(); ++I)
1740  if (!isHLASMAlnum(RawLabel[I]))
1741  return !Error(Loc, "HLASM Label has to be alphanumeric");
1742 
1743  return true;
1744 }
1745 
1746 // Force static initialization.
1749 }
llvm::MCTargetStreamer::getStreamer
MCStreamer & getStreamer()
Definition: MCStreamer.h:101
i
i
Definition: README.txt:29
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Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:124
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Definition: SystemZMCTargetDesc.cpp:56
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
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virtual MCStreamer & getStreamer()=0
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llvm
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Definition: AddressRanges.h:18
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Definition: MCSymbol.h:41
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Definition: MCInst.h:162
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Definition: MCParsedAsmOperand.h:24
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@ Prefix
Definition: CommandLine.h:160
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static MCOperand createImm(int64_t Val)
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Definition: MCContext.h:76
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const unsigned VR128Regs[32]
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Definition: SmallVector.h:1199
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Definition: SubtargetFeature.h:40
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RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:105
MCAsmParser.h
MCTargetAsmParser.h
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
SystemZTargetInfo.h
SystemZInstPrinter.h
SystemZTargetStreamer.h
applyMnemonicAliases
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:1218
llvm::MCParsedAsmOperand::getStartLoc
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
llvm::AsmToken::LParen
@ LParen
Definition: MCAsmMacro.h:48
llvm::MCAsmParser::Lex
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
InsnMatchEntry::Opcode
uint64_t Opcode
Definition: SystemZAsmParser.cpp:618
CompareInsn
Definition: SystemZAsmParser.cpp:624
printMCExpr
static void printMCExpr(const MCExpr *E, raw_ostream &OS)
Definition: SystemZAsmParser.cpp:704
llvm::MCAsmParser::parseExpression
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
llvm::RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...
Definition: TargetRegistry.h:1398
llvm::SystemZMC::CR64Regs
const unsigned CR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:124
llvm::MatchOperand_Success
@ MatchOperand_Success
Definition: MCTargetAsmParser.h:127
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::StringRef::startswith
bool startswith(StringRef Prefix) const
Definition: StringRef.h:260
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:521
InsnMatchEntry
Definition: SystemZAsmParser.cpp:616
llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
MCContext.h
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:421
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCSymbolRefExpr::VK_TLSLDM
@ VK_TLSLDM
Definition: MCExpr.h:211
llvm::AD_ATT
@ AD_ATT
Definition: SystemZMCAsmInfo.h:18
MCInst.h
llvm::SystemZMC::GR32Regs
const unsigned GR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:35
llvm::dwarf::Index
Index
Definition: Dwarf.h:490
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::MCAsmParser::getContext
virtual MCContext & getContext()=0
SMLoc.h
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCAsmParser::addAliasForDirective
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
getSubtargetFeatureName
static const char * getSubtargetFeatureName(uint64_t Val)
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
isNot
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
Definition: AMDGPULegalizerInfo.cpp:3206
llvm::AsmToken::Percent
@ Percent
Definition: MCAsmMacro.h:52
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
InsnMatchTable
static struct InsnMatchEntry InsnMatchTable[]
Definition: SystemZAsmParser.cpp:637
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
inRange
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue, bool AllowSymbol=false)
Definition: SystemZAsmParser.cpp:46
llvm::HighlightColor::Remark
@ Remark
MCAsmLexer.h
llvm::ParseInstructionInfo
Definition: MCTargetAsmParser.h:118
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
uint64_t
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:447
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::MCAsmParserExtension::Initialize
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Definition: MCAsmParserExtension.cpp:21
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1094
llvm::AsmToken::Colon
@ Colon
Definition: MCAsmMacro.h:43
llvm::MatchOperand_ParseFail
@ MatchOperand_ParseFail
Definition: MCTargetAsmParser.h:129
I
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMInitializeSystemZAsmParser
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser()
Definition: SystemZAsmParser.cpp:1747
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1868
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FeatureBitset::size
constexpr size_t size() const
Definition: SubtargetFeature.h:89
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::SystemZMC::FP64Regs
const unsigned FP64Regs[16]
Definition: SystemZMCTargetDesc.cpp:70
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:347
llvm::MCTargetOptions
Definition: MCTargetOptions.h:37
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::AsmToken::Comma
@ Comma
Definition: MCAsmMacro.h:49
llvm::print
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
Definition: GCNRegPressure.cpp:138
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::SystemZMC::GRH32Regs
const unsigned GRH32Regs[16]
Definition: SystemZMCTargetDesc.cpp:42
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:173
MCAsmInfo.h
llvm::MatchOperand_NoMatch
@ MatchOperand_NoMatch
Definition: MCTargetAsmParser.h:128
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::AsmToken::Space
@ Space
Definition: MCAsmMacro.h:44
llvm::AsmToken::RParen
@ RParen
Definition: MCAsmMacro.h:48
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
llvm::AsmToken::getString
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::OperandMatchResultTy
OperandMatchResultTy
Definition: MCTargetAsmParser.h:126
llvm::AD_HLASM
@ AD_HLASM
Definition: SystemZMCAsmInfo.h:18
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:203
llvm::AsmToken::Identifier
@ Identifier
Definition: MCAsmMacro.h:28
llvm::AsmToken::isNot
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
MCAsmParserExtension.h
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
llvm::MCBinaryExpr::Sub
@ Sub
Subtraction.
Definition: MCExpr.h:506
Casting.h
llvm::SystemZMC::VR64Regs
const unsigned VR64Regs[32]
Definition: SystemZMCTargetDesc.cpp:95
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:314
llvm::object::Identifier
@ Identifier
Definition: COFFModuleDefinition.cpp:34
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
SmallVector.h
llvm::MCStreamer::getTargetStreamer
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:300
llvm::MCAsmParser::parseGNUAttribute
bool parseGNUAttribute(SMLoc L, int64_t &Tag, int64_t &IntegerValue)
Parse a .gnu_attribute.
Definition: MCAsmParser.cpp:145
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
N
#define N
MCStreamer.h
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
llvm::MCSubtargetInfo::setDefaultFeatures
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
Definition: MCSubtargetInfo.cpp:220
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::AsmToken::String
@ String
Definition: MCAsmMacro.h:29
InsnMatchEntry::Format
StringRef Format
Definition: SystemZAsmParser.cpp:617
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::FeatureBitset::any
bool any() const
Definition: SubtargetFeature.h:91
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::SystemZMC::VR32Regs
const unsigned VR32Regs[32]
Definition: SystemZMCTargetDesc.cpp:84
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCStreamer::emitGNUAttribute
virtual void emitGNUAttribute(unsigned Tag, unsigned Value)
Emit a .gnu_attribute directive.
Definition: MCStreamer.h:664
SystemZMCAsmInfo.h