46 static bool inRange(
const MCExpr *Expr, int64_t MinValue, int64_t MaxValue,
47 bool AllowSymbol =
false) {
48 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
49 int64_t
Value = CE->getValue();
92 SMLoc StartLoc, EndLoc;
121 unsigned MemKind : 4;
122 unsigned RegKind : 4;
149 else if (
auto *CE = dyn_cast<MCConstantExpr>(Expr))
156 SystemZOperand(OperandKind kind,
SMLoc startLoc,
SMLoc endLoc)
157 :
Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
160 static std::unique_ptr<SystemZOperand> createInvalid(
SMLoc StartLoc,
162 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
165 static std::unique_ptr<SystemZOperand> createToken(
StringRef Str,
SMLoc Loc) {
166 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
167 Op->Token.Data = Str.data();
168 Op->Token.Length = Str.size();
172 static std::unique_ptr<SystemZOperand>
173 createReg(RegisterKind
Kind,
unsigned Num,
SMLoc StartLoc,
SMLoc EndLoc) {
174 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
180 static std::unique_ptr<SystemZOperand>
182 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
187 static std::unique_ptr<SystemZOperand>
188 createMem(MemoryKind MemKind, RegisterKind RegKind,
unsigned Base,
189 const MCExpr *Disp,
unsigned Index,
const MCExpr *LengthImm,
190 unsigned LengthReg,
SMLoc StartLoc,
SMLoc EndLoc) {
191 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
192 Op->Mem.MemKind = MemKind;
193 Op->Mem.RegKind = RegKind;
197 if (MemKind == BDLMem)
198 Op->Mem.Length.Imm = LengthImm;
199 if (MemKind == BDRMem)
200 Op->Mem.Length.Reg = LengthReg;
204 static std::unique_ptr<SystemZOperand>
207 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
208 Op->ImmTLS.Imm = Imm;
209 Op->ImmTLS.Sym = Sym;
214 bool isToken()
const override {
215 return Kind == KindToken;
219 return StringRef(Token.Data, Token.Length);
223 bool isReg()
const override {
224 return Kind == KindReg;
226 bool isReg(RegisterKind RegKind)
const {
227 return Kind == KindReg &&
Reg.Kind == RegKind;
229 unsigned getReg()
const override {
235 bool isImm()
const override {
236 return Kind == KindImm;
238 bool isImm(int64_t MinValue, int64_t MaxValue)
const {
239 return Kind == KindImm &&
inRange(Imm, MinValue, MaxValue);
241 const MCExpr *getImm()
const {
242 assert(
Kind == KindImm &&
"Not an immediate");
247 bool isImmTLS()
const {
248 return Kind == KindImmTLS;
251 const ImmTLSOp getImmTLS()
const {
252 assert(
Kind == KindImmTLS &&
"Not a TLS immediate");
257 bool isMem()
const override {
258 return Kind == KindMem;
260 bool isMem(MemoryKind MemKind)
const {
261 return (
Kind == KindMem &&
262 (Mem.MemKind == MemKind ||
265 (Mem.MemKind == BDMem && MemKind == BDXMem)));
267 bool isMem(MemoryKind MemKind, RegisterKind RegKind)
const {
268 return isMem(MemKind) && Mem.RegKind == RegKind;
270 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind)
const {
271 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, 0, 0xfff,
true);
273 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind)
const {
274 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, -524288, 524287,
true);
276 bool isMemDisp12Len4(RegisterKind RegKind)
const {
277 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length.Imm, 1, 0x10);
279 bool isMemDisp12Len8(RegisterKind RegKind)
const {
280 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length.Imm, 1, 0x100);
283 const MemOp& getMem()
const {
284 assert(
Kind == KindMem &&
"Not a Mem operand");
289 SMLoc getStartLoc()
const override {
return StartLoc; }
290 SMLoc getEndLoc()
const override {
return EndLoc; }
299 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
300 assert(
N == 1 &&
"Invalid number of operands");
303 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
304 assert(
N == 1 &&
"Invalid number of operands");
305 addExpr(Inst, getImm());
307 void addBDAddrOperands(
MCInst &Inst,
unsigned N)
const {
308 assert(
N == 2 &&
"Invalid number of operands");
311 addExpr(Inst, Mem.Disp);
313 void addBDXAddrOperands(
MCInst &Inst,
unsigned N)
const {
314 assert(
N == 3 &&
"Invalid number of operands");
317 addExpr(Inst, Mem.Disp);
320 void addBDLAddrOperands(
MCInst &Inst,
unsigned N)
const {
321 assert(
N == 3 &&
"Invalid number of operands");
324 addExpr(Inst, Mem.Disp);
325 addExpr(Inst, Mem.Length.Imm);
327 void addBDRAddrOperands(
MCInst &Inst,
unsigned N)
const {
328 assert(
N == 3 &&
"Invalid number of operands");
331 addExpr(Inst, Mem.Disp);
334 void addBDVAddrOperands(
MCInst &Inst,
unsigned N)
const {
335 assert(
N == 3 &&
"Invalid number of operands");
338 addExpr(Inst, Mem.Disp);
341 void addImmTLSOperands(
MCInst &Inst,
unsigned N)
const {
342 assert(
N == 2 &&
"Invalid number of operands");
343 assert(
Kind == KindImmTLS &&
"Invalid operand type");
344 addExpr(Inst, ImmTLS.Imm);
346 addExpr(Inst, ImmTLS.Sym);
350 bool isGR32()
const {
return isReg(GR32Reg); }
351 bool isGRH32()
const {
return isReg(GRH32Reg); }
352 bool isGRX32()
const {
return false; }
353 bool isGR64()
const {
return isReg(GR64Reg); }
354 bool isGR128()
const {
return isReg(GR128Reg); }
355 bool isADDR32()
const {
return isReg(GR32Reg); }
356 bool isADDR64()
const {
return isReg(GR64Reg); }
357 bool isADDR128()
const {
return false; }
358 bool isFP32()
const {
return isReg(FP32Reg); }
359 bool isFP64()
const {
return isReg(FP64Reg); }
360 bool isFP128()
const {
return isReg(FP128Reg); }
361 bool isVR32()
const {
return isReg(VR32Reg); }
362 bool isVR64()
const {
return isReg(VR64Reg); }
363 bool isVF128()
const {
return false; }
364 bool isVR128()
const {
return isReg(VR128Reg); }
365 bool isAR32()
const {
return isReg(AR32Reg); }
366 bool isCR64()
const {
return isReg(CR64Reg); }
367 bool isAnyReg()
const {
return (
isReg() ||
isImm(0, 15)); }
368 bool isBDAddr32Disp12()
const {
return isMemDisp12(BDMem, GR32Reg); }
369 bool isBDAddr32Disp20()
const {
return isMemDisp20(BDMem, GR32Reg); }
370 bool isBDAddr64Disp12()
const {
return isMemDisp12(BDMem, GR64Reg); }
371 bool isBDAddr64Disp20()
const {
return isMemDisp20(BDMem, GR64Reg); }
372 bool isBDXAddr64Disp12()
const {
return isMemDisp12(BDXMem, GR64Reg); }
373 bool isBDXAddr64Disp20()
const {
return isMemDisp20(BDXMem, GR64Reg); }
374 bool isBDLAddr64Disp12Len4()
const {
return isMemDisp12Len4(GR64Reg); }
375 bool isBDLAddr64Disp12Len8()
const {
return isMemDisp12Len8(GR64Reg); }
376 bool isBDRAddr64Disp12()
const {
return isMemDisp12(BDRMem, GR64Reg); }
377 bool isBDVAddr64Disp12()
const {
return isMemDisp12(BDVMem, GR64Reg); }
378 bool isU1Imm()
const {
return isImm(0, 1); }
379 bool isU2Imm()
const {
return isImm(0, 3); }
380 bool isU3Imm()
const {
return isImm(0, 7); }
381 bool isU4Imm()
const {
return isImm(0, 15); }
382 bool isU6Imm()
const {
return isImm(0, 63); }
383 bool isU8Imm()
const {
return isImm(0, 255); }
384 bool isS8Imm()
const {
return isImm(-128, 127); }
385 bool isU12Imm()
const {
return isImm(0, 4095); }
386 bool isU16Imm()
const {
return isImm(0, 65535); }
387 bool isS16Imm()
const {
return isImm(-32768, 32767); }
388 bool isU32Imm()
const {
return isImm(0, (1LL << 32) - 1); }
389 bool isS32Imm()
const {
return isImm(-(1LL << 31), (1LL << 31) - 1); }
390 bool isU48Imm()
const {
return isImm(0, (1LL << 48) - 1); }
394 #define GET_ASSEMBLER_HEADER
395 #include "SystemZGenAsmMatcher.inc"
409 SMLoc StartLoc, EndLoc;
413 assert(getParser().getStreamer().getTargetStreamer() &&
414 "do not have a target streamer");
419 bool parseRegister(
Register &
Reg,
bool RestoreOnFailure =
false);
421 bool parseIntegerRegister(
Register &
Reg, RegisterGroup Group);
428 bool parseAddress(
bool &HaveReg1,
Register &Reg1,
bool &HaveReg2,
430 bool HasLength =
false,
bool HasVectorIndex =
false);
433 bool ParseDirectiveInsn(
SMLoc L);
434 bool ParseDirectiveMachine(
SMLoc L);
438 RegisterKind RegKind);
441 int64_t MaxVal,
bool AllowTLS);
462 unsigned getMAIAssemblerDialect() {
468 inline bool isHLASMAlpha(
char C) {
473 inline bool isHLASMAlnum(
char C) {
return isHLASMAlpha(
C) ||
isDigit(
C); }
476 inline bool isParsingHLASM() {
return getMAIAssemblerDialect() ==
AD_HLASM; }
479 inline bool isParsingATT() {
return getMAIAssemblerDialect() ==
AD_ATT; }
492 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
496 bool ParseDirective(
AsmToken DirectiveID)
override;
497 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
498 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc,
499 bool RestoreOnFailure);
501 SMLoc &EndLoc)
override;
504 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
507 bool MatchingInlineAsm)
override;
508 bool isLabel(
AsmToken &Token)
override;
512 return parseRegister(
Operands, GR32Reg);
515 return parseRegister(
Operands, GRH32Reg);
521 return parseRegister(
Operands, GR64Reg);
524 return parseRegister(
Operands, GR128Reg);
528 return parseRegister(
Operands, GR32Reg);
532 return parseRegister(
Operands, GR64Reg);
538 return parseRegister(
Operands, FP32Reg);
541 return parseRegister(
Operands, FP64Reg);
544 return parseRegister(
Operands, FP128Reg);
547 return parseRegister(
Operands, VR32Reg);
550 return parseRegister(
Operands, VR64Reg);
556 return parseRegister(
Operands, VR128Reg);
559 return parseRegister(
Operands, AR32Reg);
562 return parseRegister(
Operands, CR64Reg);
568 return parseAddress(
Operands, BDMem, GR32Reg);
571 return parseAddress(
Operands, BDMem, GR64Reg);
574 return parseAddress(
Operands, BDXMem, GR64Reg);
577 return parseAddress(
Operands, BDLMem, GR64Reg);
580 return parseAddress(
Operands, BDRMem, GR64Reg);
583 return parseAddress(
Operands, BDVMem, GR64Reg);
586 return parsePCRel(
Operands, -(1LL << 12), (1LL << 12) - 1,
false);
589 return parsePCRel(
Operands, -(1LL << 16), (1LL << 16) - 1,
false);
592 return parsePCRel(
Operands, -(1LL << 24), (1LL << 24) - 1,
false);
595 return parsePCRel(
Operands, -(1LL << 32), (1LL << 32) - 1,
false);
598 return parsePCRel(
Operands, -(1LL << 16), (1LL << 16) - 1,
true);
601 return parsePCRel(
Operands, -(1LL << 32), (1LL << 32) - 1,
true);
607 #define GET_REGISTER_MATCHER
608 #define GET_SUBTARGET_FEATURE_NAME
609 #define GET_MATCHER_IMPLEMENTATION
610 #define GET_MNEMONIC_SPELL_CHECKER
611 #include "SystemZGenAsmMatcher.inc"
619 MatchClassKind OperandKinds[7];
631 return LHS.Format <
RHS.Format;
638 {
"e", SystemZ::InsnE, 1,
640 {
"ri", SystemZ::InsnRI, 3,
641 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
642 {
"rie", SystemZ::InsnRIE, 4,
643 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
644 {
"ril", SystemZ::InsnRIL, 3,
645 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
646 {
"rilu", SystemZ::InsnRILU, 3,
647 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
648 {
"ris", SystemZ::InsnRIS, 5,
649 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
650 {
"rr", SystemZ::InsnRR, 3,
651 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
652 {
"rre", SystemZ::InsnRRE, 3,
653 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
654 {
"rrf", SystemZ::InsnRRF, 5,
655 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
656 {
"rrs", SystemZ::InsnRRS, 5,
657 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
658 {
"rs", SystemZ::InsnRS, 4,
659 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
660 {
"rse", SystemZ::InsnRSE, 4,
661 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
662 {
"rsi", SystemZ::InsnRSI, 4,
663 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
664 {
"rsy", SystemZ::InsnRSY, 4,
665 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
666 {
"rx", SystemZ::InsnRX, 3,
667 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
668 {
"rxe", SystemZ::InsnRXE, 3,
669 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
670 {
"rxf", SystemZ::InsnRXF, 4,
671 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
672 {
"rxy", SystemZ::InsnRXY, 3,
673 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
674 {
"s", SystemZ::InsnS, 2,
675 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
676 {
"si", SystemZ::InsnSI, 3,
677 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
678 {
"sil", SystemZ::InsnSIL, 3,
679 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
680 {
"siy", SystemZ::InsnSIY, 3,
681 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
682 {
"ss", SystemZ::InsnSS, 4,
683 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
684 {
"sse", SystemZ::InsnSSE, 3,
685 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
686 {
"ssf", SystemZ::InsnSSF, 4,
687 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
688 {
"vri", SystemZ::InsnVRI, 6,
689 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
690 {
"vrr", SystemZ::InsnVRR, 7,
691 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
693 {
"vrs", SystemZ::InsnVRS, 5,
694 { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
695 {
"vrv", SystemZ::InsnVRV, 4,
696 { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
697 {
"vrx", SystemZ::InsnVRX, 4,
698 { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
699 {
"vsi", SystemZ::InsnVSI, 4,
700 { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
706 if (
auto *CE = dyn_cast<MCConstantExpr>(
E))
708 else if (
auto *UE = dyn_cast<MCUnaryExpr>(
E))
710 else if (
auto *BE = dyn_cast<MCBinaryExpr>(
E))
712 else if (
auto *SRE = dyn_cast<MCSymbolRefExpr>(
E))
721 OS <<
"Token:" << getToken();
733 if (getImmTLS().Sym) {
740 OS <<
"Mem:" << *cast<MCConstantExpr>(
Op.Disp);
743 if (
Op.MemKind == BDLMem)
744 OS << *cast<MCConstantExpr>(
Op.Length.Imm) <<
",";
745 else if (
Op.MemKind == BDRMem)
760 bool SystemZAsmParser::parseRegister(
Register &
Reg,
bool RestoreOnFailure) {
771 if (RestoreOnFailure)
772 getLexer().UnLex(PercentTok);
773 return Error(
Reg.StartLoc,
"invalid register");
778 if (
Name.size() < 2) {
779 if (RestoreOnFailure)
780 getLexer().UnLex(PercentTok);
781 return Error(
Reg.StartLoc,
"invalid register");
786 if (
Name.substr(1).getAsInteger(10,
Reg.Num)) {
787 if (RestoreOnFailure)
788 getLexer().UnLex(PercentTok);
789 return Error(
Reg.StartLoc,
"invalid register");
804 if (RestoreOnFailure)
805 getLexer().UnLex(PercentTok);
806 return Error(
Reg.StartLoc,
"invalid register");
846 if (parseRegister(
Reg))
856 if (Group !=
Reg.Group) {
857 Error(
Reg.StartLoc,
"invalid operand for instruction");
862 if (
Reg.Group != RegV &&
Reg.Group != RegFP) {
863 Error(
Reg.StartLoc,
"invalid operand for instruction");
869 if (parseIntegerRegister(
Reg, Group))
877 const unsigned *Regs;
892 if (Regs[
Reg.Num] == 0) {
893 Error(
Reg.StartLoc,
"invalid register pair");
898 SystemZOperand::createReg(
Kind, Regs[
Reg.Num],
Reg.StartLoc,
Reg.EndLoc));
913 if (
auto *CE = dyn_cast<MCConstantExpr>(
Register)) {
914 int64_t
Value =
CE->getValue();
916 Error(StartLoc,
"invalid register");
927 if (isParsingHLASM())
931 if (parseRegister(
Reg))
935 Error(StartLoc,
"invalid register");
942 if (
Reg.Group == RegGR) {
946 else if (
Reg.Group == RegFP) {
950 else if (
Reg.Group == RegV) {
954 else if (
Reg.Group == RegAR) {
958 else if (
Reg.Group == RegCR) {
966 Operands.push_back(SystemZOperand::createReg(
Kind, RegNo,
967 Reg.StartLoc,
Reg.EndLoc));
972 bool SystemZAsmParser::parseIntegerRegister(
Register &
Reg,
973 RegisterGroup Group) {
980 const auto *
CE = dyn_cast<MCConstantExpr>(
Register);
984 int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
985 int64_t
Value =
CE->getValue();
1001 bool SystemZAsmParser::parseAddress(
bool &HaveReg1,
Register &Reg1,
1004 bool HasLength,
bool HasVectorIndex) {
1006 if (getParser().parseExpression(Disp))
1032 RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1040 if (parseRegister(Reg1))
1051 if (getParser().parseExpression(Length))
1059 if (parseIntegerRegister(Reg1, RegGroup))
1066 if (getParser().parseExpression(Length))
1077 if (parseIntegerRegister(Reg2, RegGR))
1080 if (isParsingATT() && parseRegister(Reg2))
1095 SystemZAsmParser::parseAddressRegister(
Register &
Reg) {
1096 if (
Reg.Group == RegV) {
1097 Error(
Reg.StartLoc,
"invalid use of vector addressing");
1099 }
else if (
Reg.Group != RegGR) {
1100 Error(
Reg.StartLoc,
"invalid address register");
1110 RegisterKind RegKind) {
1112 unsigned Base = 0,
Index = 0, LengthReg = 0;
1114 bool HaveReg1, HaveReg2;
1118 bool HasLength = (MemKind == BDLMem) ?
true :
false;
1119 bool HasVectorIndex = (MemKind == BDVMem) ?
true :
false;
1120 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1124 const unsigned *Regs;
1135 if (parseAddressRegister(Reg1))
1137 Base = Regs[Reg1.Num];
1141 Error(StartLoc,
"invalid use of indexed addressing");
1148 if (parseAddressRegister(Reg1))
1153 Index = Regs[Reg1.Num];
1155 Base = Regs[Reg1.Num];
1159 if (parseAddressRegister(Reg2))
1161 Base = Regs[Reg2.Num];
1167 if (parseAddressRegister(Reg2))
1169 Base = Regs[Reg2.Num];
1172 if (HaveReg1 && HaveReg2) {
1173 Error(StartLoc,
"invalid use of indexed addressing");
1178 Error(StartLoc,
"missing length in address");
1184 if (!HaveReg1 || Reg1.Group != RegGR) {
1185 Error(StartLoc,
"invalid operand for instruction");
1191 if (parseAddressRegister(Reg2))
1193 Base = Regs[Reg2.Num];
1198 if (!HaveReg1 || Reg1.Group != RegV) {
1199 Error(StartLoc,
"vector index required in address");
1205 if (parseAddressRegister(Reg2))
1207 Base = Regs[Reg2.Num];
1214 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind,
Base, Disp,
1215 Index, Length, LengthReg,
1220 bool SystemZAsmParser::ParseDirective(
AsmToken DirectiveID) {
1223 if (IDVal ==
".insn")
1224 return ParseDirectiveInsn(DirectiveID.
getLoc());
1225 if (IDVal ==
".machine")
1226 return ParseDirectiveMachine(DirectiveID.
getLoc());
1233 bool SystemZAsmParser::ParseDirectiveInsn(
SMLoc L) {
1240 return Error(ErrorLoc,
"expected instruction format");
1250 if (EntryRange.first == EntryRange.second)
1251 return Error(ErrorLoc,
"unrecognized format");
1259 for (
int i = 0;
i < Entry->NumOperands;
i++) {
1260 MatchClassKind
Kind = Entry->OperandKinds[
i];
1266 return Error(StartLoc,
"unexpected token in directive");
1271 if (
Kind == MCK_AnyReg)
1273 else if (
Kind == MCK_VR128)
1275 else if (
Kind == MCK_BDXAddr64Disp12 ||
Kind == MCK_BDXAddr64Disp20)
1277 else if (
Kind == MCK_BDAddr64Disp12 ||
Kind == MCK_BDAddr64Disp20)
1279 else if (
Kind == MCK_BDVAddr64Disp12)
1281 else if (
Kind == MCK_PCRel32)
1283 else if (
Kind == MCK_PCRel16)
1292 return Error(StartLoc,
"unexpected token in directive");
1297 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1310 MatchClassKind
Kind = Entry->OperandKinds[
i];
1313 unsigned Res = validateOperandClass(Operand,
Kind);
1314 if (Res != Match_Success)
1318 SystemZOperand &ZOperand =
static_cast<SystemZOperand &
>(Operand);
1319 if (ZOperand.isReg())
1320 ZOperand.addRegOperands(Inst, 1);
1321 else if (ZOperand.isMem(BDMem))
1322 ZOperand.addBDAddrOperands(Inst, 2);
1323 else if (ZOperand.isMem(BDXMem))
1324 ZOperand.addBDXAddrOperands(Inst, 3);
1325 else if (ZOperand.isMem(BDVMem))
1326 ZOperand.addBDVAddrOperands(Inst, 3);
1327 else if (ZOperand.isImm())
1328 ZOperand.addImmOperands(Inst, 1);
1341 bool SystemZAsmParser::ParseDirectiveMachine(
SMLoc L) {
1345 return Error(L,
"unexpected token in '.machine' directive");
1350 return addErrorSuffix(
" in '.machine' directive");
1354 setAvailableFeatures(ComputeAvailableFeatures(STI.
getFeatureBits()));
1356 getTargetStreamer().emitMachine(CPU);
1361 bool SystemZAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
1362 SMLoc &EndLoc,
bool RestoreOnFailure) {
1364 if (parseRegister(
Reg, RestoreOnFailure))
1366 if (
Reg.Group == RegGR)
1368 else if (
Reg.Group == RegFP)
1370 else if (
Reg.Group == RegV)
1372 else if (
Reg.Group == RegAR)
1374 else if (
Reg.Group == RegCR)
1376 StartLoc =
Reg.StartLoc;
1377 EndLoc =
Reg.EndLoc;
1381 bool SystemZAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
1383 return ParseRegister(RegNo, StartLoc, EndLoc,
false);
1390 ParseRegister(RegNo, StartLoc, EndLoc,
true);
1391 bool PendingErrors = getParser().hasPendingError();
1392 getParser().clearPendingErrors();
1408 Operands.push_back(SystemZOperand::createToken(
Name, NameLoc));
1424 "No space allowed between comma that separates operand entries");
1449 getStreamer().AddComment(Remark);
1453 SMLoc Loc = getLexer().getLoc();
1454 return Error(Loc,
"unexpected token in argument list");
1473 setAvailableFeatures(
All);
1475 setAvailableFeatures(AvailableFeatures);
1491 if (parseRegister(
Reg))
1493 Operands.push_back(SystemZOperand::createInvalid(
Reg.StartLoc,
Reg.EndLoc));
1502 bool HaveReg1, HaveReg2;
1505 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1510 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1511 && parseAddressRegister(Reg1))
1513 if (HaveReg2 && parseAddressRegister(Reg2))
1518 if (HaveReg1 || HaveReg2 || Length)
1519 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1521 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1525 bool SystemZAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &
Opcode,
1529 bool MatchingInlineAsm) {
1531 unsigned MatchResult;
1533 unsigned Dialect = getMAIAssemblerDialect();
1537 MatchingInlineAsm, Dialect);
1538 switch (MatchResult) {
1544 case Match_MissingFeature: {
1545 assert(MissingFeatures.
any() &&
"Unknown missing feature!");
1548 std::string
Msg =
"instruction requires:";
1549 for (
unsigned I = 0,
E = MissingFeatures.
size();
I !=
E; ++
I) {
1550 if (MissingFeatures[
I]) {
1558 case Match_InvalidOperand: {
1559 SMLoc ErrorLoc = IDLoc;
1562 return Error(IDLoc,
"too few operands for instruction");
1565 if (ErrorLoc ==
SMLoc())
1568 return Error(ErrorLoc,
"invalid operand for instruction");
1571 case Match_MnemonicFail: {
1572 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1573 std::string Suggestion = SystemZMnemonicSpellCheck(
1574 ((SystemZOperand &)*
Operands[0]).getToken(), FBS, Dialect);
1575 return Error(IDLoc,
"invalid instruction" + Suggestion,
1576 ((SystemZOperand &)*
Operands[0]).getLocRange());
1585 int64_t MaxVal,
bool AllowTLS) {
1590 if (getParser().parseExpression(Expr))
1593 auto isOutOfRangeConstant = [&](
const MCExpr *
E,
bool Negate) ->
bool {
1594 if (
auto *CE = dyn_cast<MCConstantExpr>(
E)) {
1595 int64_t
Value =
CE->getValue();
1606 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1607 if (isParsingHLASM()) {
1608 Error(StartLoc,
"Expected PC-relative expression");
1611 if (isOutOfRangeConstant(CE,
false)) {
1612 Error(StartLoc,
"offset out of range");
1615 int64_t
Value =
CE->getValue();
1625 if (
const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1626 if (isOutOfRangeConstant(BE->getLHS(),
false) ||
1627 isOutOfRangeConstant(BE->getRHS(),
1629 Error(StartLoc,
"offset out of range");
1634 const MCExpr *Sym =
nullptr;
1645 if (
Name ==
"tls_gdcall")
1647 else if (
Name ==
"tls_ldcall")
1676 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1679 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1684 bool SystemZAsmParser::isLabel(
AsmToken &Token) {
1703 if (!RawLabel.
size())
1704 return !
Error(Loc,
"HLASM Label cannot be empty");
1707 if (RawLabel.
size() > 63)
1708 return !
Error(Loc,
"Maximum length for HLASM Label is 63 characters");
1711 if (!isHLASMAlpha(RawLabel[0]))
1712 return !
Error(Loc,
"HLASM Label has to start with an alphabetic "
1713 "character or the underscore character");
1718 for (
unsigned I = 1;
I < RawLabel.
size(); ++
I)
1719 if (!isHLASMAlnum(RawLabel[
I]))
1720 return !
Error(Loc,
"HLASM Label has to be alphanumeric");