LLVM 17.0.0git
AArch64RegisterBankInfo.h
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1//===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for AArch64.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
15
17
18#define GET_REGBANK_DECLARATIONS
19#include "AArch64GenRegisterBank.inc"
20
21namespace llvm {
22
23class TargetRegisterInfo;
24
26protected:
43 };
44
48
62 };
63
64 static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
65 unsigned ValLength, const RegisterBank &RB);
66 static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
67 unsigned Size, unsigned Offset);
69 PartialMappingIdx LastAlias,
71
72 static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
73
74 /// Get the pointer to the ValueMapping representing the RegisterBank
75 /// at \p RBIdx with a size of \p Size.
76 ///
77 /// The returned mapping works for instructions with the same kind of
78 /// operands for up to 3 operands.
79 ///
80 /// \pre \p RBIdx != PartialMappingIdx::None
83
84 /// Get the pointer to the ValueMapping of the operands of a copy
85 /// instruction from the \p SrcBankID register bank to the \p DstBankID
86 /// register bank with a size of \p Size.
88 getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
89
90 /// Get the instruction mapping for G_FPEXT.
91 ///
92 /// \pre (DstSize, SrcSize) pair is one of the following:
93 /// (32, 16), (64, 16), (64, 32), (128, 64)
94 ///
95 /// \return An InstructionMapping with statically allocated OperandsMapping.
97 getFPExtMapping(unsigned DstSize, unsigned SrcSize);
98
99#define GET_TARGET_REGBANK_CLASS
100#include "AArch64GenRegisterBank.inc"
101};
102
103/// This class provides the information for the target register banks.
105 /// See RegisterBankInfo::applyMapping.
106 void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
107
108 /// Get an instruction mapping where all the operands map to
109 /// the same register bank and have similar size.
110 ///
111 /// \pre MI.getNumOperands() <= 3
112 ///
113 /// \return An InstructionMappings with a statically allocated
114 /// OperandsMapping.
115 const InstructionMapping &
116 getSameKindOfOperandsMapping(const MachineInstr &MI) const;
117
118 /// Maximum recursion depth for hasFPConstraints.
119 const unsigned MaxFPRSearchDepth = 2;
120
121 /// \returns true if \p MI only uses and defines FPRs.
122 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
123 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
124
125 /// \returns true if \p MI only uses FPRs.
126 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
127 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
128
129 /// \returns true if \p MI only defines FPRs.
130 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
131 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
132
133public:
135
136 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
137 unsigned Size) const override;
138
140 LLT) const override;
141
143 getInstrAlternativeMappings(const MachineInstr &MI) const override;
144
145 const InstructionMapping &
146 getInstrMapping(const MachineInstr &MI) const override;
147};
148} // End llvm namespace.
149#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
static RegisterBankInfo::PartialMapping PartMappings[]
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static RegisterBankInfo::ValueMapping ValMappings[]
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static PartialMappingIdx BankIDToCopyMapIdx[]
static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank, unsigned Size, unsigned Offset)
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx, unsigned ValLength, const RegisterBank &RB)
This class provides the information for the target register banks.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.