LLVM  16.0.0git
AArch64RegisterBankInfo.cpp
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1 //===- AArch64RegisterBankInfo.cpp ----------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the RegisterBankInfo class for
10 /// AArch64.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
15 #include "AArch64RegisterInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/IR/IntrinsicsAArch64.h"
33 #include <algorithm>
34 #include <cassert>
35 
36 #define GET_TARGET_REGBANK_IMPL
37 #include "AArch64GenRegisterBank.inc"
38 
39 // This file will be TableGen'ed at some point.
40 #include "AArch64GenRegisterBankInfo.def"
41 
42 using namespace llvm;
43 
45  const TargetRegisterInfo &TRI) {
46  static llvm::once_flag InitializeRegisterBankFlag;
47 
48  static auto InitializeRegisterBankOnce = [&]() {
49  // We have only one set of register banks, whatever the subtarget
50  // is. Therefore, the initialization of the RegBanks table should be
51  // done only once. Indeed the table of all register banks
52  // (AArch64::RegBanks) is unique in the compiler. At some point, it
53  // will get tablegen'ed and the whole constructor becomes empty.
54 
55  const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
56  (void)RBGPR;
57  assert(&AArch64::GPRRegBank == &RBGPR &&
58  "The order in RegBanks is messed up");
59 
60  const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
61  (void)RBFPR;
62  assert(&AArch64::FPRRegBank == &RBFPR &&
63  "The order in RegBanks is messed up");
64 
65  const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
66  (void)RBCCR;
67  assert(&AArch64::CCRegBank == &RBCCR &&
68  "The order in RegBanks is messed up");
69 
70  // The GPR register bank is fully defined by all the registers in
71  // GR64all + its subclasses.
72  assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
73  "Subclass not added?");
74  assert(RBGPR.getSize() == 128 && "GPRs should hold up to 128-bit");
75 
76  // The FPR register bank is fully defined by all the registers in
77  // GR64all + its subclasses.
78  assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
79  "Subclass not added?");
80  assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
81  "Subclass not added?");
82  assert(RBFPR.getSize() == 512 &&
83  "FPRs should hold up to 512-bit via QQQQ sequence");
84 
85  assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
86  "Class not added?");
87  assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
88 
89  // Check that the TableGen'ed like file is in sync we our expectations.
90  // First, the Idx.
93  "PartialMappingIdx's are incorrectly ordered");
97  "PartialMappingIdx's are incorrectly ordered");
98 // Now, the content.
99 // Check partial mapping.
100 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
101  do { \
102  assert( \
103  checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
104  #Idx " is incorrectly initialized"); \
105  } while (false)
106 
107  CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
108  CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
109  CHECK_PARTIALMAP(PMI_GPR128, 0, 128, RBGPR);
110  CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
111  CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
112  CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
113  CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
114  CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
115  CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
116 
117 // Check value mapping.
118 #define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
119  do { \
120  assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
121  PartialMappingIdx::PMI_First##RBName, Size, \
122  Offset) && \
123  #RBName #Size " " #Offset " is incorrectly initialized"); \
124  } while (false)
125 
126 #define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
127 
128  CHECK_VALUEMAP(GPR, 32);
129  CHECK_VALUEMAP(GPR, 64);
130  CHECK_VALUEMAP(GPR, 128);
131  CHECK_VALUEMAP(FPR, 16);
132  CHECK_VALUEMAP(FPR, 32);
133  CHECK_VALUEMAP(FPR, 64);
134  CHECK_VALUEMAP(FPR, 128);
135  CHECK_VALUEMAP(FPR, 256);
136  CHECK_VALUEMAP(FPR, 512);
137 
138 // Check the value mapping for 3-operands instructions where all the operands
139 // map to the same value mapping.
140 #define CHECK_VALUEMAP_3OPS(RBName, Size) \
141  do { \
142  CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
143  CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
144  CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
145  } while (false)
146 
147  CHECK_VALUEMAP_3OPS(GPR, 32);
148  CHECK_VALUEMAP_3OPS(GPR, 64);
149  CHECK_VALUEMAP_3OPS(GPR, 128);
152  CHECK_VALUEMAP_3OPS(FPR, 128);
153  CHECK_VALUEMAP_3OPS(FPR, 256);
154  CHECK_VALUEMAP_3OPS(FPR, 512);
155 
156 #define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
157  do { \
158  unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
159  unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
160  (void)PartialMapDstIdx; \
161  (void)PartialMapSrcIdx; \
162  const ValueMapping *Map = getCopyMapping( \
163  AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
164  (void)Map; \
165  assert(Map[0].BreakDown == \
166  &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
167  Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
168  " Dst is incorrectly initialized"); \
169  assert(Map[1].BreakDown == \
170  &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
171  Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
172  " Src is incorrectly initialized"); \
173  \
174  } while (false)
175 
176  CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
178  CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
184 
185 #define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
186  do { \
187  unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
188  unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
189  (void)PartialMapDstIdx; \
190  (void)PartialMapSrcIdx; \
191  const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
192  (void)Map; \
193  assert(Map[0].BreakDown == \
194  &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
195  Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
196  " Dst is incorrectly initialized"); \
197  assert(Map[1].BreakDown == \
198  &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
199  Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
200  " Src is incorrectly initialized"); \
201  \
202  } while (false)
203 
204  CHECK_VALUEMAP_FPEXT(32, 16);
205  CHECK_VALUEMAP_FPEXT(64, 16);
206  CHECK_VALUEMAP_FPEXT(64, 32);
207  CHECK_VALUEMAP_FPEXT(128, 64);
208 
209  assert(verify(TRI) && "Invalid register bank information");
210  };
211 
212  llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
213 }
214 
216  const RegisterBank &B,
217  unsigned Size) const {
218  // What do we do with different size?
219  // copy are same size.
220  // Will introduce other hooks for different size:
221  // * extract cost.
222  // * build_sequence cost.
223 
224  // Copy from (resp. to) GPR to (resp. from) FPR involves FMOV.
225  // FIXME: This should be deduced from the scheduling model.
226  if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
227  // FMOVXDr or FMOVWSr.
228  return 5;
229  if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
230  // FMOVDXr or FMOVSWr.
231  return 4;
232 
233  return RegisterBankInfo::copyCost(A, B, Size);
234 }
235 
236 const RegisterBank &
238  LLT) const {
239  switch (RC.getID()) {
240  case AArch64::FPR8RegClassID:
241  case AArch64::FPR16RegClassID:
242  case AArch64::FPR16_loRegClassID:
243  case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
244  case AArch64::FPR32RegClassID:
245  case AArch64::FPR64RegClassID:
246  case AArch64::FPR64_loRegClassID:
247  case AArch64::FPR128RegClassID:
248  case AArch64::FPR128_loRegClassID:
249  case AArch64::DDRegClassID:
250  case AArch64::DDDRegClassID:
251  case AArch64::DDDDRegClassID:
252  case AArch64::QQRegClassID:
253  case AArch64::QQQRegClassID:
254  case AArch64::QQQQRegClassID:
255  return getRegBank(AArch64::FPRRegBankID);
256  case AArch64::GPR32commonRegClassID:
257  case AArch64::GPR32RegClassID:
258  case AArch64::GPR32spRegClassID:
259  case AArch64::GPR32sponlyRegClassID:
260  case AArch64::GPR32argRegClassID:
261  case AArch64::GPR32allRegClassID:
262  case AArch64::GPR64commonRegClassID:
263  case AArch64::GPR64RegClassID:
264  case AArch64::GPR64spRegClassID:
265  case AArch64::GPR64sponlyRegClassID:
266  case AArch64::GPR64argRegClassID:
267  case AArch64::GPR64allRegClassID:
268  case AArch64::GPR64noipRegClassID:
269  case AArch64::GPR64common_and_GPR64noipRegClassID:
270  case AArch64::GPR64noip_and_tcGPR64RegClassID:
271  case AArch64::tcGPR64RegClassID:
272  case AArch64::rtcGPR64RegClassID:
273  case AArch64::WSeqPairsClassRegClassID:
274  case AArch64::XSeqPairsClassRegClassID:
275  case AArch64::MatrixIndexGPR32_12_15RegClassID:
276  case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
277  return getRegBank(AArch64::GPRRegBankID);
278  case AArch64::CCRRegClassID:
279  return getRegBank(AArch64::CCRegBankID);
280  default:
281  llvm_unreachable("Register class not supported");
282  }
283 }
284 
287  const MachineInstr &MI) const {
288  const MachineFunction &MF = *MI.getParent()->getParent();
289  const TargetSubtargetInfo &STI = MF.getSubtarget();
290  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
291  const MachineRegisterInfo &MRI = MF.getRegInfo();
292 
293  switch (MI.getOpcode()) {
294  case TargetOpcode::G_OR: {
295  // 32 and 64-bit or can be mapped on either FPR or
296  // GPR for the same cost.
297  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
298  if (Size != 32 && Size != 64)
299  break;
300 
301  // If the instruction has any implicit-defs or uses,
302  // do not mess with it.
303  if (MI.getNumOperands() != 3)
304  break;
305  InstructionMappings AltMappings;
306  const InstructionMapping &GPRMapping = getInstructionMapping(
307  /*ID*/ 1, /*Cost*/ 1, getValueMapping(PMI_FirstGPR, Size),
308  /*NumOperands*/ 3);
309  const InstructionMapping &FPRMapping = getInstructionMapping(
310  /*ID*/ 2, /*Cost*/ 1, getValueMapping(PMI_FirstFPR, Size),
311  /*NumOperands*/ 3);
312 
313  AltMappings.push_back(&GPRMapping);
314  AltMappings.push_back(&FPRMapping);
315  return AltMappings;
316  }
317  case TargetOpcode::G_BITCAST: {
318  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
319  if (Size != 32 && Size != 64)
320  break;
321 
322  // If the instruction has any implicit-defs or uses,
323  // do not mess with it.
324  if (MI.getNumOperands() != 2)
325  break;
326 
327  InstructionMappings AltMappings;
328  const InstructionMapping &GPRMapping = getInstructionMapping(
329  /*ID*/ 1, /*Cost*/ 1,
330  getCopyMapping(AArch64::GPRRegBankID, AArch64::GPRRegBankID, Size),
331  /*NumOperands*/ 2);
332  const InstructionMapping &FPRMapping = getInstructionMapping(
333  /*ID*/ 2, /*Cost*/ 1,
334  getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size),
335  /*NumOperands*/ 2);
336  const InstructionMapping &GPRToFPRMapping = getInstructionMapping(
337  /*ID*/ 3,
338  /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
339  getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size),
340  /*NumOperands*/ 2);
341  const InstructionMapping &FPRToGPRMapping = getInstructionMapping(
342  /*ID*/ 3,
343  /*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
344  getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size),
345  /*NumOperands*/ 2);
346 
347  AltMappings.push_back(&GPRMapping);
348  AltMappings.push_back(&FPRMapping);
349  AltMappings.push_back(&GPRToFPRMapping);
350  AltMappings.push_back(&FPRToGPRMapping);
351  return AltMappings;
352  }
353  case TargetOpcode::G_LOAD: {
354  unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
355  if (Size != 64)
356  break;
357 
358  // If the instruction has any implicit-defs or uses,
359  // do not mess with it.
360  if (MI.getNumOperands() != 2)
361  break;
362 
363  InstructionMappings AltMappings;
364  const InstructionMapping &GPRMapping = getInstructionMapping(
365  /*ID*/ 1, /*Cost*/ 1,
367  // Addresses are GPR 64-bit.
369  /*NumOperands*/ 2);
370  const InstructionMapping &FPRMapping = getInstructionMapping(
371  /*ID*/ 2, /*Cost*/ 1,
373  // Addresses are GPR 64-bit.
375  /*NumOperands*/ 2);
376 
377  AltMappings.push_back(&GPRMapping);
378  AltMappings.push_back(&FPRMapping);
379  return AltMappings;
380  }
381  default:
382  break;
383  }
385 }
386 
387 void AArch64RegisterBankInfo::applyMappingImpl(
388  const OperandsMapper &OpdMapper) const {
389  switch (OpdMapper.getMI().getOpcode()) {
390  case TargetOpcode::G_OR:
391  case TargetOpcode::G_BITCAST:
392  case TargetOpcode::G_LOAD:
393  // Those ID must match getInstrAlternativeMappings.
394  assert((OpdMapper.getInstrMapping().getID() >= 1 &&
395  OpdMapper.getInstrMapping().getID() <= 4) &&
396  "Don't know how to handle that ID");
397  return applyDefaultMapping(OpdMapper);
398  default:
399  llvm_unreachable("Don't know how to handle that operation");
400  }
401 }
402 
403 /// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
404 /// having only floating-point operands.
405 static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
406  switch (Opc) {
407  case TargetOpcode::G_FADD:
408  case TargetOpcode::G_FSUB:
409  case TargetOpcode::G_FMUL:
410  case TargetOpcode::G_FMA:
411  case TargetOpcode::G_FDIV:
412  case TargetOpcode::G_FCONSTANT:
413  case TargetOpcode::G_FPEXT:
414  case TargetOpcode::G_FPTRUNC:
415  case TargetOpcode::G_FCEIL:
416  case TargetOpcode::G_FFLOOR:
417  case TargetOpcode::G_FNEARBYINT:
418  case TargetOpcode::G_FNEG:
419  case TargetOpcode::G_FCOS:
420  case TargetOpcode::G_FSIN:
421  case TargetOpcode::G_FLOG10:
422  case TargetOpcode::G_FLOG:
423  case TargetOpcode::G_FLOG2:
424  case TargetOpcode::G_FSQRT:
425  case TargetOpcode::G_FABS:
426  case TargetOpcode::G_FEXP:
427  case TargetOpcode::G_FRINT:
428  case TargetOpcode::G_INTRINSIC_TRUNC:
429  case TargetOpcode::G_INTRINSIC_ROUND:
430  case TargetOpcode::G_FMAXNUM:
431  case TargetOpcode::G_FMINNUM:
432  case TargetOpcode::G_FMAXIMUM:
433  case TargetOpcode::G_FMINIMUM:
434  return true;
435  }
436  return false;
437 }
438 
440 AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
441  const MachineInstr &MI) const {
442  const unsigned Opc = MI.getOpcode();
443  const MachineFunction &MF = *MI.getParent()->getParent();
444  const MachineRegisterInfo &MRI = MF.getRegInfo();
445 
446  unsigned NumOperands = MI.getNumOperands();
447  assert(NumOperands <= 3 &&
448  "This code is for instructions with 3 or less operands");
449 
450  LLT Ty = MRI.getType(MI.getOperand(0).getReg());
451  unsigned Size = Ty.getSizeInBits();
452  bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
453 
454  PartialMappingIdx RBIdx = IsFPR ? PMI_FirstFPR : PMI_FirstGPR;
455 
456 #ifndef NDEBUG
457  // Make sure all the operands are using similar size and type.
458  // Should probably be checked by the machine verifier.
459  // This code won't catch cases where the number of lanes is
460  // different between the operands.
461  // If we want to go to that level of details, it is probably
462  // best to check that the types are the same, period.
463  // Currently, we just check that the register banks are the same
464  // for each types.
465  for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
466  LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
467  assert(
469  RBIdx, OpTy.getSizeInBits()) ==
471  "Operand has incompatible size");
472  bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
473  (void)OpIsFPR;
474  assert(IsFPR == OpIsFPR && "Operand has incompatible type");
475  }
476 #endif // End NDEBUG.
477 
479  getValueMapping(RBIdx, Size), NumOperands);
480 }
481 
482 /// \returns true if a given intrinsic \p ID only uses and defines FPRs.
483 static bool isFPIntrinsic(unsigned ID) {
484  // TODO: Add more intrinsics.
485  switch (ID) {
486  default:
487  return false;
488  case Intrinsic::aarch64_neon_uaddlv:
489  return true;
490  }
491 }
492 
493 bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,
494  const MachineRegisterInfo &MRI,
495  const TargetRegisterInfo &TRI,
496  unsigned Depth) const {
497  unsigned Op = MI.getOpcode();
498  if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MI.getIntrinsicID()))
499  return true;
500 
501  // Do we have an explicit floating point instruction?
503  return true;
504 
505  // No. Check if we have a copy-like instruction. If we do, then we could
506  // still be fed by floating point instructions.
507  if (Op != TargetOpcode::COPY && !MI.isPHI() &&
509  return false;
510 
511  // Check if we already know the register bank.
512  auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
513  if (RB == &AArch64::FPRRegBank)
514  return true;
515  if (RB == &AArch64::GPRRegBank)
516  return false;
517 
518  // We don't know anything.
519  //
520  // If we have a phi, we may be able to infer that it will be assigned a FPR
521  // based off of its inputs.
522  if (!MI.isPHI() || Depth > MaxFPRSearchDepth)
523  return false;
524 
525  return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {
526  return Op.isReg() &&
527  onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
528  });
529 }
530 
531 bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
532  const MachineRegisterInfo &MRI,
533  const TargetRegisterInfo &TRI,
534  unsigned Depth) const {
535  switch (MI.getOpcode()) {
536  case TargetOpcode::G_FPTOSI:
537  case TargetOpcode::G_FPTOUI:
538  case TargetOpcode::G_FCMP:
539  case TargetOpcode::G_LROUND:
540  case TargetOpcode::G_LLROUND:
541  return true;
542  default:
543  break;
544  }
545  return hasFPConstraints(MI, MRI, TRI, Depth);
546 }
547 
548 bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
549  const MachineRegisterInfo &MRI,
550  const TargetRegisterInfo &TRI,
551  unsigned Depth) const {
552  switch (MI.getOpcode()) {
553  case AArch64::G_DUP:
554  case TargetOpcode::G_SITOFP:
555  case TargetOpcode::G_UITOFP:
556  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
557  case TargetOpcode::G_INSERT_VECTOR_ELT:
558  case TargetOpcode::G_BUILD_VECTOR:
559  case TargetOpcode::G_BUILD_VECTOR_TRUNC:
560  return true;
561  default:
562  break;
563  }
564  return hasFPConstraints(MI, MRI, TRI, Depth);
565 }
566 
569  const unsigned Opc = MI.getOpcode();
570 
571  // Try the default logic for non-generic instructions that are either copies
572  // or already have some operands assigned to banks.
573  if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
574  Opc == TargetOpcode::G_PHI) {
575  const RegisterBankInfo::InstructionMapping &Mapping =
577  if (Mapping.isValid())
578  return Mapping;
579  }
580 
581  const MachineFunction &MF = *MI.getParent()->getParent();
582  const MachineRegisterInfo &MRI = MF.getRegInfo();
583  const TargetSubtargetInfo &STI = MF.getSubtarget();
584  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
585 
586  switch (Opc) {
587  // G_{F|S|U}REM are not listed because they are not legal.
588  // Arithmetic ops.
589  case TargetOpcode::G_ADD:
590  case TargetOpcode::G_SUB:
591  case TargetOpcode::G_PTR_ADD:
592  case TargetOpcode::G_MUL:
593  case TargetOpcode::G_SDIV:
594  case TargetOpcode::G_UDIV:
595  // Bitwise ops.
596  case TargetOpcode::G_AND:
597  case TargetOpcode::G_OR:
598  case TargetOpcode::G_XOR:
599  // Floating point ops.
600  case TargetOpcode::G_FADD:
601  case TargetOpcode::G_FSUB:
602  case TargetOpcode::G_FMUL:
603  case TargetOpcode::G_FDIV:
604  case TargetOpcode::G_FMAXIMUM:
605  case TargetOpcode::G_FMINIMUM:
606  return getSameKindOfOperandsMapping(MI);
607  case TargetOpcode::G_FPEXT: {
608  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
609  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
610  return getInstructionMapping(
611  DefaultMappingID, /*Cost*/ 1,
612  getFPExtMapping(DstTy.getSizeInBits(), SrcTy.getSizeInBits()),
613  /*NumOperands*/ 2);
614  }
615  // Shifts.
616  case TargetOpcode::G_SHL:
617  case TargetOpcode::G_LSHR:
618  case TargetOpcode::G_ASHR: {
619  LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
620  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
621  if (ShiftAmtTy.getSizeInBits() == 64 && SrcTy.getSizeInBits() == 32)
623  &ValMappings[Shift64Imm], 3);
624  return getSameKindOfOperandsMapping(MI);
625  }
626  case TargetOpcode::COPY: {
627  Register DstReg = MI.getOperand(0).getReg();
628  Register SrcReg = MI.getOperand(1).getReg();
629  // Check if one of the register is not a generic register.
630  if ((Register::isPhysicalRegister(DstReg) ||
631  !MRI.getType(DstReg).isValid()) ||
632  (Register::isPhysicalRegister(SrcReg) ||
633  !MRI.getType(SrcReg).isValid())) {
634  const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
635  const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
636  if (!DstRB)
637  DstRB = SrcRB;
638  else if (!SrcRB)
639  SrcRB = DstRB;
640  // If both RB are null that means both registers are generic.
641  // We shouldn't be here.
642  assert(DstRB && SrcRB && "Both RegBank were nullptr");
643  unsigned Size = getSizeInBits(DstReg, MRI, TRI);
644  return getInstructionMapping(
645  DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
646  getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
647  // We only care about the mapping of the destination.
648  /*NumOperands*/ 1);
649  }
650  // Both registers are generic, use G_BITCAST.
651  [[fallthrough]];
652  }
653  case TargetOpcode::G_BITCAST: {
654  LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
655  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
656  unsigned Size = DstTy.getSizeInBits();
657  bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
658  bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
659  const RegisterBank &DstRB =
660  DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
661  const RegisterBank &SrcRB =
662  SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
663  return getInstructionMapping(
664  DefaultMappingID, copyCost(DstRB, SrcRB, Size),
665  getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
666  // We only care about the mapping of the destination for COPY.
667  /*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
668  }
669  default:
670  break;
671  }
672 
673  unsigned NumOperands = MI.getNumOperands();
674 
675  // Track the size and bank of each register. We don't do partial mappings.
676  SmallVector<unsigned, 4> OpSize(NumOperands);
677  SmallVector<PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
678  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
679  auto &MO = MI.getOperand(Idx);
680  if (!MO.isReg() || !MO.getReg())
681  continue;
682 
683  LLT Ty = MRI.getType(MO.getReg());
684  if (!Ty.isValid())
685  continue;
686  OpSize[Idx] = Ty.getSizeInBits();
687 
688  // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
689  // For floating-point instructions, scalars go in FPRs.
691  Ty.getSizeInBits() > 64)
692  OpRegBankIdx[Idx] = PMI_FirstFPR;
693  else
694  OpRegBankIdx[Idx] = PMI_FirstGPR;
695  }
696 
697  unsigned Cost = 1;
698  // Some of the floating-point instructions have mixed GPR and FPR operands:
699  // fine-tune the computed mapping.
700  switch (Opc) {
701  case AArch64::G_DUP: {
702  Register ScalarReg = MI.getOperand(1).getReg();
703  LLT ScalarTy = MRI.getType(ScalarReg);
704  auto ScalarDef = MRI.getVRegDef(ScalarReg);
705  // s8 is an exception for G_DUP, which we always want on gpr.
706  if (ScalarTy.getSizeInBits() != 8 &&
707  (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
708  onlyDefinesFP(*ScalarDef, MRI, TRI)))
709  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
710  else
711  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
712  break;
713  }
714  case TargetOpcode::G_TRUNC: {
715  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
716  if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)
717  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
718  break;
719  }
720  case TargetOpcode::G_SITOFP:
721  case TargetOpcode::G_UITOFP: {
722  if (MRI.getType(MI.getOperand(0).getReg()).isVector())
723  break;
724  // Integer to FP conversions don't necessarily happen between GPR -> FPR
725  // regbanks. They can also be done within an FPR register.
726  Register SrcReg = MI.getOperand(1).getReg();
727  if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank)
728  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
729  else
730  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
731  break;
732  }
733  case TargetOpcode::G_FPTOSI:
734  case TargetOpcode::G_FPTOUI:
735  if (MRI.getType(MI.getOperand(0).getReg()).isVector())
736  break;
737  OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
738  break;
739  case TargetOpcode::G_FCMP: {
740  // If the result is a vector, it must use a FPR.
742  MRI.getType(MI.getOperand(0).getReg()).isVector() ? PMI_FirstFPR
743  : PMI_FirstGPR;
744  OpRegBankIdx = {Idx0,
745  /* Predicate */ PMI_None, PMI_FirstFPR, PMI_FirstFPR};
746  break;
747  }
748  case TargetOpcode::G_BITCAST:
749  // This is going to be a cross register bank copy and this is expensive.
750  if (OpRegBankIdx[0] != OpRegBankIdx[1])
751  Cost = copyCost(
752  *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank,
753  *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank,
754  OpSize[0]);
755  break;
756  case TargetOpcode::G_LOAD:
757  // Loading in vector unit is slightly more expensive.
758  // This is actually only true for the LD1R and co instructions,
759  // but anyway for the fast mode this number does not matter and
760  // for the greedy mode the cost of the cross bank copy will
761  // offset this number.
762  // FIXME: Should be derived from the scheduling model.
763  if (OpRegBankIdx[0] != PMI_FirstGPR) {
764  Cost = 2;
765  break;
766  }
767 
768  if (cast<GLoad>(MI).isAtomic()) {
769  // Atomics always use GPR destinations. Don't refine any further.
770  OpRegBankIdx[0] = PMI_FirstGPR;
771  break;
772  }
773 
774  // Check if that load feeds fp instructions.
775  // In that case, we want the default mapping to be on FPR
776  // instead of blind map every scalar to GPR.
777  if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
778  [&](const MachineInstr &UseMI) {
779  // If we have at least one direct use in a FP instruction,
780  // assume this was a floating point load in the IR. If it was
781  // not, we would have had a bitcast before reaching that
782  // instruction.
783  //
784  // Int->FP conversion operations are also captured in
785  // onlyDefinesFP().
786  return onlyUsesFP(UseMI, MRI, TRI) ||
787  onlyDefinesFP(UseMI, MRI, TRI);
788  }))
789  OpRegBankIdx[0] = PMI_FirstFPR;
790  break;
791  case TargetOpcode::G_STORE:
792  // Check if that store is fed by fp instructions.
793  if (OpRegBankIdx[0] == PMI_FirstGPR) {
794  Register VReg = MI.getOperand(0).getReg();
795  if (!VReg)
796  break;
797  MachineInstr *DefMI = MRI.getVRegDef(VReg);
798  if (onlyDefinesFP(*DefMI, MRI, TRI))
799  OpRegBankIdx[0] = PMI_FirstFPR;
800  break;
801  }
802  break;
803  case TargetOpcode::G_SELECT: {
804  // If the destination is FPR, preserve that.
805  if (OpRegBankIdx[0] != PMI_FirstGPR)
806  break;
807 
808  // If we're taking in vectors, we have no choice but to put everything on
809  // FPRs, except for the condition. The condition must always be on a GPR.
810  LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
811  if (SrcTy.isVector()) {
813  break;
814  }
815 
816  // Try to minimize the number of copies. If we have more floating point
817  // constrained values than not, then we'll put everything on FPR. Otherwise,
818  // everything has to be on GPR.
819  unsigned NumFP = 0;
820 
821  // Check if the uses of the result always produce floating point values.
822  //
823  // For example:
824  //
825  // %z = G_SELECT %cond %x %y
826  // fpr = G_FOO %z ...
827  if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
828  [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); }))
829  ++NumFP;
830 
831  // Check if the defs of the source values always produce floating point
832  // values.
833  //
834  // For example:
835  //
836  // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
837  // %z = G_SELECT %cond %x %y
838  //
839  // Also check whether or not the sources have already been decided to be
840  // FPR. Keep track of this.
841  //
842  // This doesn't check the condition, since it's just whatever is in NZCV.
843  // This isn't passed explicitly in a register to fcsel/csel.
844  for (unsigned Idx = 2; Idx < 4; ++Idx) {
845  Register VReg = MI.getOperand(Idx).getReg();
846  MachineInstr *DefMI = MRI.getVRegDef(VReg);
847  if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank ||
848  onlyDefinesFP(*DefMI, MRI, TRI))
849  ++NumFP;
850  }
851 
852  // If we have more FP constraints than not, then move everything over to
853  // FPR.
854  if (NumFP >= 2)
856 
857  break;
858  }
859  case TargetOpcode::G_UNMERGE_VALUES: {
860  // If the first operand belongs to a FPR register bank, then make sure that
861  // we preserve that.
862  if (OpRegBankIdx[0] != PMI_FirstGPR)
863  break;
864 
865  LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
866  // UNMERGE into scalars from a vector should always use FPR.
867  // Likewise if any of the uses are FP instructions.
868  if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
869  any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
870  [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
871  // Set the register bank of every operand to FPR.
872  for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
873  Idx < NumOperands; ++Idx)
874  OpRegBankIdx[Idx] = PMI_FirstFPR;
875  }
876  break;
877  }
878  case TargetOpcode::G_EXTRACT_VECTOR_ELT:
879  // Destination and source need to be FPRs.
880  OpRegBankIdx[0] = PMI_FirstFPR;
881  OpRegBankIdx[1] = PMI_FirstFPR;
882 
883  // Index needs to be a GPR.
884  OpRegBankIdx[2] = PMI_FirstGPR;
885  break;
886  case TargetOpcode::G_INSERT_VECTOR_ELT:
887  OpRegBankIdx[0] = PMI_FirstFPR;
888  OpRegBankIdx[1] = PMI_FirstFPR;
889 
890  // The element may be either a GPR or FPR. Preserve that behaviour.
891  if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
892  OpRegBankIdx[2] = PMI_FirstFPR;
893  else
894  OpRegBankIdx[2] = PMI_FirstGPR;
895 
896  // Index needs to be a GPR.
897  OpRegBankIdx[3] = PMI_FirstGPR;
898  break;
899  case TargetOpcode::G_EXTRACT: {
900  // For s128 sources we have to use fpr unless we know otherwise.
901  auto Src = MI.getOperand(1).getReg();
902  LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
903  if (SrcTy.getSizeInBits() != 128)
904  break;
905  auto Idx = MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
906  ? PMI_FirstGPR
907  : PMI_FirstFPR;
908  OpRegBankIdx[0] = Idx;
909  OpRegBankIdx[1] = Idx;
910  break;
911  }
912  case TargetOpcode::G_BUILD_VECTOR: {
913  // If the first source operand belongs to a FPR register bank, then make
914  // sure that we preserve that.
915  if (OpRegBankIdx[1] != PMI_FirstGPR)
916  break;
917  Register VReg = MI.getOperand(1).getReg();
918  if (!VReg)
919  break;
920 
921  // Get the instruction that defined the source operand reg, and check if
922  // it's a floating point operation. Or, if it's a type like s16 which
923  // doesn't have a exact size gpr register class. The exception is if the
924  // build_vector has all constant operands, which may be better to leave as
925  // gpr without copies, so it can be matched in imported patterns.
926  MachineInstr *DefMI = MRI.getVRegDef(VReg);
927  unsigned DefOpc = DefMI->getOpcode();
928  const LLT SrcTy = MRI.getType(VReg);
929  if (all_of(MI.operands(), [&](const MachineOperand &Op) {
930  return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
931  TargetOpcode::G_CONSTANT;
932  }))
933  break;
935  SrcTy.getSizeInBits() < 32 ||
936  getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank) {
937  // Have a floating point op.
938  // Make sure every operand gets mapped to a FPR register class.
939  unsigned NumOperands = MI.getNumOperands();
940  for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
941  OpRegBankIdx[Idx] = PMI_FirstFPR;
942  }
943  break;
944  }
945  case TargetOpcode::G_VECREDUCE_FADD:
946  case TargetOpcode::G_VECREDUCE_FMUL:
947  case TargetOpcode::G_VECREDUCE_FMAX:
948  case TargetOpcode::G_VECREDUCE_FMIN:
949  case TargetOpcode::G_VECREDUCE_ADD:
950  case TargetOpcode::G_VECREDUCE_MUL:
951  case TargetOpcode::G_VECREDUCE_AND:
952  case TargetOpcode::G_VECREDUCE_OR:
953  case TargetOpcode::G_VECREDUCE_XOR:
954  case TargetOpcode::G_VECREDUCE_SMAX:
955  case TargetOpcode::G_VECREDUCE_SMIN:
956  case TargetOpcode::G_VECREDUCE_UMAX:
957  case TargetOpcode::G_VECREDUCE_UMIN:
958  // Reductions produce a scalar value from a vector, the scalar should be on
959  // FPR bank.
960  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
961  break;
962  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
963  case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
964  // These reductions also take a scalar accumulator input.
965  // Assign them FPR for now.
966  OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR, PMI_FirstFPR};
967  break;
968  case TargetOpcode::G_INTRINSIC: {
969  // Check if we know that the intrinsic has any constraints on its register
970  // banks. If it does, then update the mapping accordingly.
971  unsigned ID = MI.getIntrinsicID();
972  unsigned Idx = 0;
973  if (!isFPIntrinsic(ID))
974  break;
975  for (const auto &Op : MI.explicit_operands()) {
976  if (Op.isReg())
977  OpRegBankIdx[Idx] = PMI_FirstFPR;
978  ++Idx;
979  }
980  break;
981  }
982  case TargetOpcode::G_LROUND:
983  case TargetOpcode::G_LLROUND: {
984  // Source is always floating point and destination is always integer.
985  OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
986  break;
987  }
988  }
989 
990  // Finally construct the computed mapping.
991  SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
992  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
993  if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
994  LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
995  if (!Ty.isValid())
996  continue;
997  auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
998  if (!Mapping->isValid())
1000 
1001  OpdsMapping[Idx] = Mapping;
1002  }
1003  }
1004 
1006  getOperandsMapping(OpdsMapping), NumOperands);
1007 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
AArch64RegisterInfo.h
llvm::AArch64GenRegisterBankInfo::getFPExtMapping
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
CHECK_VALUEMAP_FPEXT
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:75
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:105
AArch64RegisterBankInfo.h
llvm::RegisterBankInfo::getInstrMappingImpl
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
Definition: RegisterBankInfo.cpp:159
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::RegisterBankInfo::verify
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
Definition: RegisterBankInfo.cpp:66
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
ErrorHandling.h
CHECK_VALUEMAP_CROSSREGCPY
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
RegisterBankInfo.h
llvm::RegisterBankInfo::applyDefaultMapping
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
Definition: RegisterBankInfo.cpp:435
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:551
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
GenericMachineInstrs.h
FPR
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
Definition: PPCISelLowering.cpp:3871
isPreISelGenericFloatingPointOpcode
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Definition: AArch64RegisterBankInfo.cpp:405
STLExtras.h
llvm::RegisterBankInfo::InstructionMapping::isValid
bool isValid() const
Check whether this object is valid.
Definition: RegisterBankInfo.h:253
llvm::AArch64GenRegisterBankInfo::PMI_GPR64
@ PMI_GPR64
Definition: AArch64RegisterBankInfo.h:36
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
MachineRegisterInfo.h
llvm::AArch64GenRegisterBankInfo::PMI_LastGPR
@ PMI_LastGPR
Definition: AArch64RegisterBankInfo.h:39
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1590
llvm::AArch64RegisterBankInfo::copyCost
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: AArch64RegisterBankInfo.cpp:215
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::AArch64GenRegisterBankInfo::PMI_FirstGPR
@ PMI_FirstGPR
Definition: AArch64RegisterBankInfo.h:38
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
InlinePriorityMode::Cost
@ Cost
llvm::AArch64GenRegisterBankInfo::PMI_FPR512
@ PMI_FPR512
Definition: AArch64RegisterBankInfo.h:34
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
Utils.h
llvm::AArch64GenRegisterBankInfo::PMI_FPR32
@ PMI_FPR32
Definition: AArch64RegisterBankInfo.h:30
llvm::AArch64GenRegisterBankInfo::Shift64Imm
@ Shift64Imm
Definition: AArch64RegisterBankInfo.h:61
TargetOpcodes.h
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::RegisterBank::getID
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
llvm::AArch64GenRegisterBankInfo::checkPartialMappingIdx
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
Definition: AArch64RegisterBankInfo.cpp:286
llvm::AArch64GenRegisterBankInfo::PMI_None
@ PMI_None
Definition: AArch64RegisterBankInfo.h:28
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::RegisterBankInfo::getInstrAlternativeMappings
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
Definition: RegisterBankInfo.cpp:430
llvm::RegisterBankInfo::getSizeInBits
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
Definition: RegisterBankInfo.cpp:493
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AArch64GenRegisterBankInfo::PartMappings
static RegisterBankInfo::PartialMapping PartMappings[]
Definition: AArch64RegisterBankInfo.h:45
CHECK_VALUEMAP
#define CHECK_VALUEMAP(RBName, Size)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::AArch64GenRegisterBankInfo::PartialMappingIdx
PartialMappingIdx
Definition: AArch64RegisterBankInfo.h:27
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:771
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::RegisterBankInfo::InstructionMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Definition: RegisterBankInfo.h:189
llvm::AArch64GenRegisterBankInfo::getValueMapping
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
llvm::AArch64GenRegisterBankInfo::PMI_FPR64
@ PMI_FPR64
Definition: AArch64RegisterBankInfo.h:31
llvm::AArch64GenRegisterBankInfo::PMI_GPR32
@ PMI_GPR32
Definition: AArch64RegisterBankInfo.h:35
llvm::RegisterBankInfo::DefaultMappingID
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
Definition: RegisterBankInfo.h:652
llvm::RegisterBankInfo::getOperandsMapping
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
Definition: RegisterBankInfo.cpp:329
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:664
llvm::RegisterBank::covers
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
Definition: RegisterBank.cpp:61
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RegisterBankInfo::getInstructionMapping
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Definition: RegisterBankInfo.h:525
llvm::AArch64GenRegisterBankInfo::PMI_GPR128
@ PMI_GPR128
Definition: AArch64RegisterBankInfo.h:37
isFPIntrinsic
static bool isFPIntrinsic(unsigned ID)
Definition: AArch64RegisterBankInfo.cpp:483
llvm::AArch64RegisterBankInfo::getRegBankFromRegClass
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Definition: AArch64RegisterBankInfo.cpp:237
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1597
CHECK_PARTIALMAP
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
llvm::AArch64GenRegisterBankInfo::PMI_FPR256
@ PMI_FPR256
Definition: AArch64RegisterBankInfo.h:33
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
TargetSubtargetInfo.h
llvm::AArch64RegisterBankInfo::getInstrMapping
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Definition: AArch64RegisterBankInfo.cpp:568
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:57
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AArch64GenRegisterBankInfo::getCopyMapping
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
llvm::AArch64GenRegisterBankInfo::PMI_FPR16
@ PMI_FPR16
Definition: AArch64RegisterBankInfo.h:29
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AArch64GenRegisterBankInfo::ValMappings
static RegisterBankInfo::ValueMapping ValMappings[]
Definition: AArch64RegisterBankInfo.h:46
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
llvm::AArch64GenRegisterBankInfo::PMI_FirstFPR
@ PMI_FirstFPR
Definition: AArch64RegisterBankInfo.h:40
CHECK_VALUEMAP_3OPS
#define CHECK_VALUEMAP_3OPS(RBName, Size)
llvm::RegisterBankInfo::getInvalidInstructionMapping
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
Definition: RegisterBankInfo.h:533
AArch64MCTargetDesc.h
llvm::RegisterBankInfo::copyCost
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Definition: RegisterBankInfo.h:613
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
RegisterBank.h
llvm::AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:106
llvm::AArch64GenRegisterBankInfo::PMI_FPR128
@ PMI_FPR128
Definition: AArch64RegisterBankInfo.h:32
MachineOperand.h
MachineFunction.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
TargetRegisterInfo.h
llvm::AArch64GenRegisterBankInfo::PMI_LastFPR
@ PMI_LastFPR
Definition: AArch64RegisterBankInfo.h:41
llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
Definition: AArch64RegisterBankInfo.cpp:44
llvm::LLT
Definition: LowLevelTypeImpl.h:39