31#include "llvm/IR/IntrinsicsAArch64.h"
37#define GET_TARGET_REGBANK_IMPL
38#include "AArch64GenRegisterBank.inc"
41#include "AArch64GenRegisterBankInfo.def"
49 static auto InitializeRegisterBankOnce = [&]() {
58 assert(&AArch64::GPRRegBank == &RBGPR &&
59 "The order in RegBanks is messed up");
63 assert(&AArch64::FPRRegBank == &RBFPR &&
64 "The order in RegBanks is messed up");
68 assert(&AArch64::CCRegBank == &RBCCR &&
69 "The order in RegBanks is messed up");
74 "Subclass not added?");
76 "GPRs should hold up to 128-bit");
81 "Subclass not added?");
83 "Subclass not added?");
85 "FPRs should hold up to 512-bit via QQQQ sequence");
90 "CCR should hold up to 32-bit");
96 "PartialMappingIdx's are incorrectly ordered");
100 "PartialMappingIdx's are incorrectly ordered");
103#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
106 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \
107 #Idx " is incorrectly initialized"); \
121#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
123 assert(checkValueMapImpl(PartialMappingIdx::PMI_##RBName##Size, \
124 PartialMappingIdx::PMI_First##RBName, Size, \
126 #RBName #Size " " #Offset " is incorrectly initialized"); \
129#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
143#define CHECK_VALUEMAP_3OPS(RBName, Size) \
145 CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
146 CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
147 CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
159#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
161 unsigned PartialMapDstIdx = PMI_##RBNameDst##Size - PMI_Min; \
162 unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
163 (void)PartialMapDstIdx; \
164 (void)PartialMapSrcIdx; \
165 const ValueMapping *Map = getCopyMapping( \
166 AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
168 assert(Map[0].BreakDown == \
169 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
170 Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
171 " Dst is incorrectly initialized"); \
172 assert(Map[1].BreakDown == \
173 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
174 Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
175 " Src is incorrectly initialized"); \
188#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
190 unsigned PartialMapDstIdx = PMI_FPR##DstSize - PMI_Min; \
191 unsigned PartialMapSrcIdx = PMI_FPR##SrcSize - PMI_Min; \
192 (void)PartialMapDstIdx; \
193 (void)PartialMapSrcIdx; \
194 const ValueMapping *Map = getFPExtMapping(DstSize, SrcSize); \
196 assert(Map[0].BreakDown == \
197 &AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
198 Map[0].NumBreakDowns == 1 && "FPR" #DstSize \
199 " Dst is incorrectly initialized"); \
200 assert(Map[1].BreakDown == \
201 &AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
202 Map[1].NumBreakDowns == 1 && "FPR" #SrcSize \
203 " Src is incorrectly initialized"); \
215 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
229 if (&
A == &AArch64::GPRRegBank && &
B == &AArch64::FPRRegBank)
232 if (&
A == &AArch64::FPRRegBank && &
B == &AArch64::GPRRegBank)
242 switch (RC.
getID()) {
243 case AArch64::FPR8RegClassID:
244 case AArch64::FPR16RegClassID:
245 case AArch64::FPR16_loRegClassID:
246 case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
247 case AArch64::FPR32RegClassID:
248 case AArch64::FPR64RegClassID:
249 case AArch64::FPR128RegClassID:
250 case AArch64::FPR64_loRegClassID:
251 case AArch64::FPR128_loRegClassID:
252 case AArch64::FPR128_0to7RegClassID:
253 case AArch64::DDRegClassID:
254 case AArch64::DDDRegClassID:
255 case AArch64::DDDDRegClassID:
256 case AArch64::QQRegClassID:
257 case AArch64::QQQRegClassID:
258 case AArch64::QQQQRegClassID:
260 case AArch64::GPR32commonRegClassID:
261 case AArch64::GPR32RegClassID:
262 case AArch64::GPR32spRegClassID:
263 case AArch64::GPR32sponlyRegClassID:
264 case AArch64::GPR32argRegClassID:
265 case AArch64::GPR32allRegClassID:
266 case AArch64::GPR64commonRegClassID:
267 case AArch64::GPR64RegClassID:
268 case AArch64::GPR64spRegClassID:
269 case AArch64::GPR64sponlyRegClassID:
270 case AArch64::GPR64argRegClassID:
271 case AArch64::GPR64allRegClassID:
272 case AArch64::GPR64noipRegClassID:
273 case AArch64::GPR64common_and_GPR64noipRegClassID:
274 case AArch64::GPR64noip_and_tcGPR64RegClassID:
275 case AArch64::tcGPR64RegClassID:
276 case AArch64::rtcGPR64RegClassID:
277 case AArch64::WSeqPairsClassRegClassID:
278 case AArch64::XSeqPairsClassRegClassID:
279 case AArch64::MatrixIndexGPR32_8_11RegClassID:
280 case AArch64::MatrixIndexGPR32_12_15RegClassID:
281 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID:
282 case AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID:
284 case AArch64::CCRRegClassID:
299 switch (
MI.getOpcode()) {
300 case TargetOpcode::G_OR: {
309 if (
MI.getNumOperands() != 3)
323 case TargetOpcode::G_BITCAST: {
330 if (
MI.getNumOperands() != 2)
345 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
352 copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank,
363 case TargetOpcode::G_LOAD: {
370 if (
MI.getNumOperands() != 2)
397void AArch64RegisterBankInfo::applyMappingImpl(
399 switch (OpdMapper.getMI().getOpcode()) {
400 case TargetOpcode::G_OR:
401 case TargetOpcode::G_BITCAST:
402 case TargetOpcode::G_LOAD:
404 assert((OpdMapper.getInstrMapping().getID() >= 1 &&
405 OpdMapper.getInstrMapping().getID() <= 4) &&
406 "Don't know how to handle that ID");
417 case TargetOpcode::G_FADD:
418 case TargetOpcode::G_FSUB:
419 case TargetOpcode::G_FMUL:
420 case TargetOpcode::G_FMA:
421 case TargetOpcode::G_FDIV:
422 case TargetOpcode::G_FCONSTANT:
423 case TargetOpcode::G_FPEXT:
424 case TargetOpcode::G_FPTRUNC:
425 case TargetOpcode::G_FCEIL:
426 case TargetOpcode::G_FFLOOR:
427 case TargetOpcode::G_FNEARBYINT:
428 case TargetOpcode::G_FNEG:
429 case TargetOpcode::G_FCOS:
430 case TargetOpcode::G_FSIN:
431 case TargetOpcode::G_FLOG10:
432 case TargetOpcode::G_FLOG:
433 case TargetOpcode::G_FLOG2:
434 case TargetOpcode::G_FSQRT:
435 case TargetOpcode::G_FABS:
436 case TargetOpcode::G_FEXP:
437 case TargetOpcode::G_FRINT:
438 case TargetOpcode::G_INTRINSIC_TRUNC:
439 case TargetOpcode::G_INTRINSIC_ROUND:
440 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
441 case TargetOpcode::G_FMAXNUM:
442 case TargetOpcode::G_FMINNUM:
443 case TargetOpcode::G_FMAXIMUM:
444 case TargetOpcode::G_FMINIMUM:
451AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
453 const unsigned Opc =
MI.getOpcode();
457 unsigned NumOperands =
MI.getNumOperands();
458 assert(NumOperands <= 3 &&
459 "This code is for instructions with 3 or less operands");
461 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
476 for (
unsigned Idx = 1;
Idx != NumOperands; ++
Idx) {
477 LLT OpTy =
MRI.getType(
MI.getOperand(
Idx).getReg());
482 "Operand has incompatible size");
485 assert(IsFPR == OpIsFPR &&
"Operand has incompatible type");
500 case Intrinsic::aarch64_neon_uaddlv:
501 case Intrinsic::aarch64_neon_uaddv:
502 case Intrinsic::aarch64_neon_saddv:
503 case Intrinsic::aarch64_neon_umaxv:
504 case Intrinsic::aarch64_neon_smaxv:
505 case Intrinsic::aarch64_neon_uminv:
506 case Intrinsic::aarch64_neon_sminv:
507 case Intrinsic::aarch64_neon_faddv:
508 case Intrinsic::aarch64_neon_fmaxv:
509 case Intrinsic::aarch64_neon_fminv:
510 case Intrinsic::aarch64_neon_fmaxnmv:
511 case Intrinsic::aarch64_neon_fminnmv:
513 case Intrinsic::aarch64_neon_saddlv: {
514 const LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
521bool AArch64RegisterBankInfo::hasFPConstraints(
const MachineInstr &
MI,
524 unsigned Depth)
const {
525 unsigned Op =
MI.getOpcode();
535 if (
Op != TargetOpcode::COPY && !
MI.isPHI() &&
541 if (RB == &AArch64::FPRRegBank)
543 if (RB == &AArch64::GPRRegBank)
550 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
555 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
562 unsigned Depth)
const {
563 switch (
MI.getOpcode()) {
564 case TargetOpcode::G_FPTOSI:
565 case TargetOpcode::G_FPTOUI:
566 case TargetOpcode::G_FCMP:
567 case TargetOpcode::G_LROUND:
568 case TargetOpcode::G_LLROUND:
576bool AArch64RegisterBankInfo::onlyDefinesFP(
const MachineInstr &
MI,
579 unsigned Depth)
const {
580 switch (
MI.getOpcode()) {
582 case TargetOpcode::G_SITOFP:
583 case TargetOpcode::G_UITOFP:
584 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
585 case TargetOpcode::G_INSERT_VECTOR_ELT:
586 case TargetOpcode::G_BUILD_VECTOR:
587 case TargetOpcode::G_BUILD_VECTOR_TRUNC:
589 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
591 case Intrinsic::aarch64_neon_ld1x2:
592 case Intrinsic::aarch64_neon_ld1x3:
593 case Intrinsic::aarch64_neon_ld1x4:
594 case Intrinsic::aarch64_neon_ld2:
595 case Intrinsic::aarch64_neon_ld2lane:
596 case Intrinsic::aarch64_neon_ld2r:
597 case Intrinsic::aarch64_neon_ld3:
598 case Intrinsic::aarch64_neon_ld3lane:
599 case Intrinsic::aarch64_neon_ld3r:
600 case Intrinsic::aarch64_neon_ld4:
601 case Intrinsic::aarch64_neon_ld4lane:
602 case Intrinsic::aarch64_neon_ld4r:
614bool AArch64RegisterBankInfo::isLoadFromFPType(
const MachineInstr &
MI)
const {
616 auto *
MemOp = cast<GMemOperation>(&
MI);
617 const Value *LdVal =
MemOp->getMMO().getValue();
621 Type *EltTy =
nullptr;
622 if (
const GlobalValue *GV = dyn_cast<GlobalValue>(LdVal)) {
623 EltTy = GV->getValueType();
627 for (
const auto *LdUser : LdVal->
users()) {
628 if (isa<LoadInst>(LdUser)) {
629 EltTy = LdUser->getType();
632 if (isa<StoreInst>(LdUser) && LdUser->getOperand(1) == LdVal) {
633 EltTy = LdUser->getOperand(0)->getType();
643 const unsigned Opc =
MI.getOpcode();
648 Opc == TargetOpcode::G_PHI) {
663 case TargetOpcode::G_ADD:
664 case TargetOpcode::G_SUB:
665 case TargetOpcode::G_PTR_ADD:
666 case TargetOpcode::G_MUL:
667 case TargetOpcode::G_SDIV:
668 case TargetOpcode::G_UDIV:
670 case TargetOpcode::G_AND:
671 case TargetOpcode::G_OR:
672 case TargetOpcode::G_XOR:
674 case TargetOpcode::G_FADD:
675 case TargetOpcode::G_FSUB:
676 case TargetOpcode::G_FMUL:
677 case TargetOpcode::G_FDIV:
678 case TargetOpcode::G_FMAXIMUM:
679 case TargetOpcode::G_FMINIMUM:
680 return getSameKindOfOperandsMapping(
MI);
681 case TargetOpcode::G_FPEXT: {
682 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
683 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
690 case TargetOpcode::G_SHL:
691 case TargetOpcode::G_LSHR:
692 case TargetOpcode::G_ASHR: {
693 LLT ShiftAmtTy =
MRI.getType(
MI.getOperand(2).getReg());
694 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
698 return getSameKindOfOperandsMapping(
MI);
700 case TargetOpcode::COPY: {
704 if ((DstReg.
isPhysical() || !
MRI.getType(DstReg).isValid()) ||
714 assert(DstRB && SrcRB &&
"Both RegBank were nullptr");
725 case TargetOpcode::G_BITCAST: {
726 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
727 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
732 DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
734 SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
739 Opc == TargetOpcode::G_BITCAST ? 2 : 1);
745 unsigned NumOperands =
MI.getNumOperands();
750 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
751 auto &MO =
MI.getOperand(
Idx);
752 if (!MO.isReg() || !MO.getReg())
755 LLT Ty =
MRI.getType(MO.getReg());
773 case AArch64::G_DUP: {
774 Register ScalarReg =
MI.getOperand(1).getReg();
775 LLT ScalarTy =
MRI.getType(ScalarReg);
776 auto ScalarDef =
MRI.getVRegDef(ScalarReg);
778 if (ScalarDef->getOpcode() == TargetOpcode::G_LOAD)
783 onlyDefinesFP(*ScalarDef,
MRI,
TRI)))
789 case TargetOpcode::G_TRUNC: {
790 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
795 case TargetOpcode::G_SITOFP:
796 case TargetOpcode::G_UITOFP: {
797 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
808 case TargetOpcode::G_FPTOSI:
809 case TargetOpcode::G_FPTOUI:
810 if (
MRI.getType(
MI.getOperand(0).getReg()).isVector())
814 case TargetOpcode::G_FCMP: {
819 OpRegBankIdx = {Idx0,
823 case TargetOpcode::G_BITCAST:
825 if (OpRegBankIdx[0] != OpRegBankIdx[1])
831 case TargetOpcode::G_LOAD: {
843 if (cast<GLoad>(
MI).isAtomic()) {
850 if (isLoadFromFPType(
MI)) {
858 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
867 return onlyUsesFP(UseMI, MRI, TRI) ||
868 onlyDefinesFP(UseMI, MRI, TRI);
873 case TargetOpcode::G_STORE:
885 case TargetOpcode::G_INDEXED_STORE:
896 case TargetOpcode::G_INDEXED_SEXTLOAD:
897 case TargetOpcode::G_INDEXED_ZEXTLOAD:
901 case TargetOpcode::G_INDEXED_LOAD: {
902 if (isLoadFromFPType(
MI))
906 case TargetOpcode::G_SELECT: {
913 LLT SrcTy =
MRI.getType(
MI.getOperand(2).getReg());
930 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
962 case TargetOpcode::G_UNMERGE_VALUES: {
968 LLT SrcTy =
MRI.getType(
MI.getOperand(
MI.getNumOperands()-1).getReg());
972 any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
975 for (
unsigned Idx = 0, NumOperands =
MI.getNumOperands();
981 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
989 case TargetOpcode::G_INSERT_VECTOR_ELT:
1002 case TargetOpcode::G_EXTRACT: {
1004 auto Src =
MI.getOperand(1).getReg();
1005 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
1008 auto Idx =
MRI.getRegClassOrNull(Src) == &AArch64::XSeqPairsClassRegClass
1011 OpRegBankIdx[0] =
Idx;
1012 OpRegBankIdx[1] =
Idx;
1015 case TargetOpcode::G_BUILD_VECTOR: {
1031 const LLT SrcTy =
MRI.getType(VReg);
1033 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
1034 TargetOpcode::G_CONSTANT;
1042 unsigned NumOperands =
MI.getNumOperands();
1043 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx)
1048 case TargetOpcode::G_VECREDUCE_FADD:
1049 case TargetOpcode::G_VECREDUCE_FMUL:
1050 case TargetOpcode::G_VECREDUCE_FMAX:
1051 case TargetOpcode::G_VECREDUCE_FMIN:
1052 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1053 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1054 case TargetOpcode::G_VECREDUCE_ADD:
1055 case TargetOpcode::G_VECREDUCE_MUL:
1056 case TargetOpcode::G_VECREDUCE_AND:
1057 case TargetOpcode::G_VECREDUCE_OR:
1058 case TargetOpcode::G_VECREDUCE_XOR:
1059 case TargetOpcode::G_VECREDUCE_SMAX:
1060 case TargetOpcode::G_VECREDUCE_SMIN:
1061 case TargetOpcode::G_VECREDUCE_UMAX:
1062 case TargetOpcode::G_VECREDUCE_UMIN:
1067 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1068 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
1073 case TargetOpcode::G_INTRINSIC:
1074 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1079 for (
const auto &
Op :
MI.defs()) {
1085 Idx +=
MI.getNumExplicitDefs();
1088 for (
const auto &
Op :
MI.explicit_uses()) {
1095 case TargetOpcode::G_LROUND:
1096 case TargetOpcode::G_LLROUND: {
1105 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
1106 if (
MI.getOperand(
Idx).isReg() &&
MI.getOperand(
Idx).getReg()) {
1107 LLT Ty =
MRI.getType(
MI.getOperand(
Idx).getReg());
1111 if (!Mapping->isValid())
1114 OpdsMapping[
Idx] = Mapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static unsigned getIntrinsicID(const SDNode *N)
#define CHECK_VALUEMAP(RBName, Size)
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define CHECK_VALUEMAP_3OPS(RBName, Size)
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize)
This file declares the targeting of the RegisterBankInfo class for AArch64.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx, unsigned Size)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx with a size of Size.
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias, ArrayRef< PartialMappingIdx > Order)
static const RegisterBankInfo::PartialMapping PartMappings[]
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size)
static const RegisterBankInfo::ValueMapping * getFPExtMapping(unsigned DstSize, unsigned SrcSize)
Get the instruction mapping for G_FPEXT.
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static const RegisterBankInfo::ValueMapping ValMappings[]
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
This class represents an Operation in the Expression.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
LLVM Value Representation.
iterator_range< user_iterator > users()
constexpr ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
The llvm::once_flag structure.