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AArch64TargetTransformInfo.h
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1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// AArch64 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 
19 #include "AArch64.h"
20 #include "AArch64Subtarget.h"
21 #include "AArch64TargetMachine.h"
22 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include <cstdint>
28 
29 namespace llvm {
30 
31 class APInt;
32 class Instruction;
33 class IntrinsicInst;
34 class Loop;
35 class SCEV;
36 class ScalarEvolution;
37 class Type;
38 class Value;
39 class VectorType;
40 
41 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
43  using TTI = TargetTransformInfo;
44 
45  friend BaseT;
46 
47  const AArch64Subtarget *ST;
48  const AArch64TargetLowering *TLI;
49 
50  const AArch64Subtarget *getST() const { return ST; }
51  const AArch64TargetLowering *getTLI() const { return TLI; }
52 
53  enum MemIntrinsicType {
54  VECTOR_LDST_TWO_ELEMENTS,
55  VECTOR_LDST_THREE_ELEMENTS,
56  VECTOR_LDST_FOUR_ELEMENTS
57  };
58 
59  bool isWideningInstruction(Type *Ty, unsigned Opcode,
61 
62 public:
63  explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
64  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
65  TLI(ST->getTargetLowering()) {}
66 
67  bool areInlineCompatible(const Function *Caller,
68  const Function *Callee) const;
69 
70  /// \name Scalar TTI Implementations
71  /// @{
72 
74  InstructionCost getIntImmCost(int64_t Val);
75  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
77  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
78  const APInt &Imm, Type *Ty,
80  Instruction *Inst = nullptr);
82  const APInt &Imm, Type *Ty,
84  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
85 
86  /// @}
87 
88  /// \name Vector TTI Implementations
89  /// @{
90 
91  bool enableInterleavedAccessVectorization() { return true; }
92 
93  unsigned getNumberOfRegisters(unsigned ClassID) const {
94  bool Vector = (ClassID == 1);
95  if (Vector) {
96  if (ST->hasNEON())
97  return 32;
98  return 0;
99  }
100  return 31;
101  }
102 
105 
107  IntrinsicInst &II) const;
108 
110  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
111  APInt &UndefElts2, APInt &UndefElts3,
112  std::function<void(Instruction *, unsigned, APInt, APInt &)>
113  SimplifyAndSetOp) const;
114 
116  switch (K) {
118  return TypeSize::getFixed(64);
120  if (ST->hasSVE())
121  return TypeSize::getFixed(
122  std::max(ST->getMinSVEVectorSizeInBits(), 128u));
123  return TypeSize::getFixed(ST->hasNEON() ? 128 : 0);
125  return TypeSize::getScalable(ST->hasSVE() ? 128 : 0);
126  }
127  llvm_unreachable("Unsupported register kind");
128  }
129 
130  unsigned getMinVectorRegisterBitWidth() const {
131  return ST->getMinVectorRegisterBitWidth();
132  }
133 
135  return ST->getVScaleForTuning();
136  }
137 
138  /// Try to return an estimate cost factor that can be used as a multiplier
139  /// when scalarizing an operation for a vector with ElementCount \p VF.
140  /// For scalable vectors this currently takes the most pessimistic view based
141  /// upon the maximum possible value for vscale.
142  unsigned getMaxNumElements(ElementCount VF) const {
143  if (!VF.isScalable())
144  return VF.getFixedValue();
145 
146  return VF.getKnownMinValue() * ST->getVScaleForTuning();
147  }
148 
149  unsigned getMaxInterleaveFactor(unsigned VF);
150 
151  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
152  Align Alignment, unsigned AddressSpace,
154 
155  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
156  const Value *Ptr, bool VariableMask,
157  Align Alignment,
159  const Instruction *I = nullptr);
160 
161  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
164  const Instruction *I = nullptr);
165 
166  InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
167  VectorType *VecTy, unsigned Index);
168 
170  const Instruction *I = nullptr);
171 
172  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
173  unsigned Index);
174 
176  bool IsUnsigned,
178 
180  VectorType *ValTy,
182 
183  InstructionCost getSpliceCost(VectorType *Tp, int Index);
184 
186  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
192  const Instruction *CxtI = nullptr);
193 
195  const SCEV *Ptr);
196 
197  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
198  CmpInst::Predicate VecPred,
200  const Instruction *I = nullptr);
201 
203  bool IsZeroCmp) const;
204  bool useNeonVector(const Type *Ty) const;
205 
206  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
207  MaybeAlign Alignment, unsigned AddressSpace,
209  const Instruction *I = nullptr);
210 
212 
216 
219 
221  Type *ExpectedType);
222 
224 
226  if (Ty->isPointerTy())
227  return true;
228 
229  if (Ty->isBFloatTy() && ST->hasBF16())
230  return true;
231 
232  if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy())
233  return true;
234 
235  if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
236  Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
237  return true;
238 
239  return false;
240  }
241 
242  bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
243  if (!ST->hasSVE())
244  return false;
245 
246  // For fixed vectors, avoid scalarization if using SVE for them.
247  if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors())
248  return false; // Fall back to scalarization of masked operations.
249 
251  }
252 
253  bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
254  return isLegalMaskedLoadStore(DataType, Alignment);
255  }
256 
257  bool isLegalMaskedStore(Type *DataType, Align Alignment) {
258  return isLegalMaskedLoadStore(DataType, Alignment);
259  }
260 
261  bool isLegalMaskedGatherScatter(Type *DataType) const {
262  if (!ST->hasSVE())
263  return false;
264 
265  // For fixed vectors, scalarize if not using SVE for them.
266  auto *DataTypeFVTy = dyn_cast<FixedVectorType>(DataType);
267  if (DataTypeFVTy && (!ST->useSVEForFixedLengthVectors() ||
268  DataTypeFVTy->getNumElements() < 2))
269  return false;
270 
272  }
273 
274  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
275  return isLegalMaskedGatherScatter(DataType);
276  }
277  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
278  return isLegalMaskedGatherScatter(DataType);
279  }
280 
281  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
282  // Return true if we can generate a `ld1r` splat load instruction.
283  if (!ST->hasNEON() || NumElements.isScalable())
284  return false;
285  switch (unsigned ElementBits = ElementTy->getScalarSizeInBits()) {
286  case 8:
287  case 16:
288  case 32:
289  case 64: {
290  // We accept bit-widths >= 64bits and elements {8,16,32,64} bits.
291  unsigned VectorBits = NumElements.getFixedValue() * ElementBits;
292  return VectorBits >= 64;
293  }
294  }
295  return false;
296  }
297 
298  bool isLegalNTStore(Type *DataType, Align Alignment) {
299  // NOTE: The logic below is mostly geared towards LV, which calls it with
300  // vectors with 2 elements. We might want to improve that, if other
301  // users show up.
302  // Nontemporal vector stores can be directly lowered to STNP, if the vector
303  // can be halved so that each half fits into a register. That's the case if
304  // the element type fits into a register and the number of elements is a
305  // power of 2 > 1.
306  if (auto *DataTypeVTy = dyn_cast<VectorType>(DataType)) {
307  unsigned NumElements =
308  cast<FixedVectorType>(DataTypeVTy)->getNumElements();
309  unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
310  return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
311  EltSize <= 128 && isPowerOf2_64(EltSize);
312  }
313  return BaseT::isLegalNTStore(DataType, Alignment);
314  }
315 
316  bool enableOrderedReductions() const { return true; }
317 
319  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
320  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
321  bool UseMaskForCond = false, bool UseMaskForGaps = false);
322 
323  bool
325  bool &AllowPromotionWithoutCommonHeader);
326 
327  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
328 
329  unsigned getGISelRematGlobalCost() const {
330  return 2;
331  }
332 
333  bool emitGetActiveLaneMask() const {
334  return ST->hasSVE();
335  }
336 
337  bool supportsScalableVectors() const { return ST->hasSVE(); }
338 
339  bool enableScalableVectorization() const { return ST->hasSVE(); }
340 
342  ElementCount VF) const;
343 
347 
349  ArrayRef<int> Mask, int Index,
350  VectorType *SubTp,
352  /// @}
353 };
354 
355 } // end namespace llvm
356 
357 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
llvm::AArch64TTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:166
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::AArch64TTIImpl::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
Definition: AArch64TargetTransformInfo.h:281
llvm::AArch64TTIImpl::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Definition: AArch64TargetTransformInfo.h:333
llvm::AArch64TTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AArch64TargetTransformInfo.cpp:2251
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::AArch64TTIImpl::isLegalMaskedGatherScatter
bool isLegalMaskedGatherScatter(Type *DataType) const
Definition: AArch64TargetTransformInfo.h:261
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
AArch64.h
llvm::AArch64TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: AArch64TargetTransformInfo.cpp:1789
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::AArch64TTIImpl::getIntImmCost
InstructionCost getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
Definition: AArch64TargetTransformInfo.cpp:57
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:218
llvm::ElementCount
Definition: TypeSize.h:390
llvm::AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: AArch64TargetTransformInfo.cpp:1304
llvm::AArch64TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: AArch64TargetTransformInfo.h:115
llvm::AArch64TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2098
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:594
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:309
llvm::AArch64TTIImpl::enableScalableVectorization
bool enableScalableVectorization() const
Definition: AArch64TargetTransformInfo.h:339
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:919
llvm::AArch64TTIImpl::supportsScalableVectors
bool supportsScalableVectors() const
Definition: AArch64TargetTransformInfo.h:337
llvm::AArch64TTIImpl::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: AArch64TargetTransformInfo.h:329
llvm::AArch64TTIImpl::AArch64TTIImpl
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
Definition: AArch64TargetTransformInfo.h:63
llvm::AArch64TTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: AArch64TargetTransformInfo.h:327
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:537
llvm::Optional
Definition: APInt.h:33
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::AArch64TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: AArch64TargetTransformInfo.h:93
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:376
VectorType
Definition: ItaniumDemangle.h:1065
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AArch64TargetTransformInfo.cpp:40
llvm::AArch64TTIImpl::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
Definition: AArch64TargetTransformInfo.cpp:1718
llvm::AArch64TTIImpl::getMaxNumElements
unsigned getMaxNumElements(ElementCount VF) const
Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation ...
Definition: AArch64TargetTransformInfo.h:142
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
AArch64TargetMachine.h
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:898
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:871
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1091
Intrinsics.h
llvm::AArch64TTIImpl::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
Definition: AArch64TargetTransformInfo.cpp:2181
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::AArch64TTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: AArch64TargetTransformInfo.cpp:97
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:23
llvm::AArch64TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:1402
llvm::AArch64TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2451
llvm::AArch64TTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64TargetTransformInfo.h:130
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:919
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::None
const NoneType None
Definition: None.h:24
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::AArch64TTIImpl::isLegalMaskedLoadStore
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:242
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::AArch64TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:227
llvm::AArch64TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2502
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::AArch64TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: AArch64TargetTransformInfo.cpp:2153
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::AArch64TTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2041
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:245
llvm::AArch64TTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: AArch64TargetTransformInfo.cpp:1233
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:41
llvm::AArch64TTIImpl::getArithmeticReductionCostSVE
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2476
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:430
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:898
llvm::AArch64TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AArch64TargetTransformInfo.cpp:1817
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::Type::isHalfTy
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:142
llvm::AArch64TTIImpl::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: AArch64TargetTransformInfo.cpp:2420
llvm::AArch64TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: AArch64TargetTransformInfo.h:274
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:296
llvm::AArch64TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AArch64TargetTransformInfo.cpp:2195
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:890
llvm::AArch64TTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: AArch64TargetTransformInfo.cpp:2601
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SystemZ::VectorBits
const unsigned VectorBits
Definition: SystemZ.h:154
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:773
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AArch64TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: AArch64TargetTransformInfo.h:91
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::LinearPolySize::getFixedValue
ScalarTy getFixedValue() const
Definition: TypeSize.h:312
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:868
llvm::AArch64TTIImpl::enableOrderedReductions
bool enableOrderedReductions() const
Definition: AArch64TargetTransformInfo.h:316
llvm::AArch64TTIImpl::getShuffleCost
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Definition: AArch64TargetTransformInfo.h:298
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Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:148
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Definition: TypeSize.h:286
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Definition: Type.h:151
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Definition: InstCombiner.h:45
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Definition: Type.h:145
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Definition: Alignment.h:340
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Definition: AArch64TargetTransformInfo.cpp:2065
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Definition: TargetTransformInfo.h:69
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Definition: AMDGPUMetadata.h:394
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Definition: AArch64Subtarget.h:38
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Definition: AArch64TargetTransformInfo.h:225
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Definition: AArch64TargetTransformInfo.h:253
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Definition: Value.h:74
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Definition: AArch64TargetTransformInfo.h:257
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Definition: AArch64TargetTransformInfo.h:134