LLVM  13.0.0git
AArch64TargetTransformInfo.h
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1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// AArch64 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 
19 #include "AArch64.h"
20 #include "AArch64Subtarget.h"
21 #include "AArch64TargetMachine.h"
22 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include <cstdint>
28 
29 namespace llvm {
30 
31 class APInt;
32 class Instruction;
33 class IntrinsicInst;
34 class Loop;
35 class SCEV;
36 class ScalarEvolution;
37 class Type;
38 class Value;
39 class VectorType;
40 
41 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
43  using TTI = TargetTransformInfo;
44 
45  friend BaseT;
46 
47  const AArch64Subtarget *ST;
48  const AArch64TargetLowering *TLI;
49 
50  const AArch64Subtarget *getST() const { return ST; }
51  const AArch64TargetLowering *getTLI() const { return TLI; }
52 
53  enum MemIntrinsicType {
54  VECTOR_LDST_TWO_ELEMENTS,
55  VECTOR_LDST_THREE_ELEMENTS,
56  VECTOR_LDST_FOUR_ELEMENTS
57  };
58 
59  bool isWideningInstruction(Type *Ty, unsigned Opcode,
61 
62 public:
63  explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
64  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
65  TLI(ST->getTargetLowering()) {}
66 
67  bool areInlineCompatible(const Function *Caller,
68  const Function *Callee) const;
69 
70  /// \name Scalar TTI Implementations
71  /// @{
72 
74  int getIntImmCost(int64_t Val);
75  int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
76  int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
78  Instruction *Inst = nullptr);
79  int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
81  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
82 
83  /// @}
84 
85  /// \name Vector TTI Implementations
86  /// @{
87 
88  bool enableInterleavedAccessVectorization() { return true; }
89 
90  unsigned getNumberOfRegisters(unsigned ClassID) const {
91  bool Vector = (ClassID == 1);
92  if (Vector) {
93  if (ST->hasNEON())
94  return 32;
95  return 0;
96  }
97  return 31;
98  }
99 
102 
104  switch (K) {
106  return TypeSize::getFixed(64);
108  if (ST->hasSVE())
109  return TypeSize::getFixed(
110  std::max(ST->getMinSVEVectorSizeInBits(), 128u));
111  return TypeSize::getFixed(ST->hasNEON() ? 128 : 0);
113  return TypeSize::getScalable(ST->hasSVE() ? 128 : 0);
114  }
115  llvm_unreachable("Unsupported register kind");
116  }
117 
119  return ST->getMinVectorRegisterBitWidth();
120  }
121 
123  if (ST->hasSVE())
125  return BaseT::getMaxVScale();
126  }
127 
128  unsigned getMaxInterleaveFactor(unsigned VF);
129 
130  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
131  const Value *Ptr, bool VariableMask,
132  Align Alignment,
134  const Instruction *I = nullptr);
135 
136  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
139  const Instruction *I = nullptr);
140 
141  InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
142  VectorType *VecTy, unsigned Index);
143 
145  const Instruction *I = nullptr);
146 
147  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
148  unsigned Index);
149 
151  bool IsPairwise, bool IsUnsigned,
153 
155  VectorType *ValTy,
156  bool IsPairwiseForm,
158 
160  unsigned Opcode, Type *Ty,
167  const Instruction *CxtI = nullptr);
168 
169  int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
170 
171  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
172  CmpInst::Predicate VecPred,
174  const Instruction *I = nullptr);
175 
177  bool IsZeroCmp) const;
178  bool useNeonVector(const Type *Ty) const;
179 
180  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src,
181  MaybeAlign Alignment, unsigned AddressSpace,
183  const Instruction *I = nullptr);
184 
186 
189 
192 
194  Type *ExpectedType);
195 
197 
198  bool isLegalElementTypeForSVE(Type *Ty) const {
199  if (Ty->isPointerTy())
200  return true;
201 
202  if (Ty->isBFloatTy() && ST->hasBF16())
203  return true;
204 
205  if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy())
206  return true;
207 
208  if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
209  Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
210  return true;
211 
212  return false;
213  }
214 
215  bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
216  if (isa<FixedVectorType>(DataType) || !ST->hasSVE())
217  return false;
218 
219  return isLegalElementTypeForSVE(DataType->getScalarType());
220  }
221 
222  bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
223  return isLegalMaskedLoadStore(DataType, Alignment);
224  }
225 
226  bool isLegalMaskedStore(Type *DataType, Align Alignment) {
227  return isLegalMaskedLoadStore(DataType, Alignment);
228  }
229 
230  bool isLegalMaskedGatherScatter(Type *DataType) const {
231  if (isa<FixedVectorType>(DataType) || !ST->hasSVE())
232  return false;
233 
234  return isLegalElementTypeForSVE(DataType->getScalarType());
235  }
236 
237  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
238  return isLegalMaskedGatherScatter(DataType);
239  }
240  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
241  return isLegalMaskedGatherScatter(DataType);
242  }
243 
244  bool isLegalNTStore(Type *DataType, Align Alignment) {
245  // NOTE: The logic below is mostly geared towards LV, which calls it with
246  // vectors with 2 elements. We might want to improve that, if other
247  // users show up.
248  // Nontemporal vector stores can be directly lowered to STNP, if the vector
249  // can be halved so that each half fits into a register. That's the case if
250  // the element type fits into a register and the number of elements is a
251  // power of 2 > 1.
252  if (auto *DataTypeVTy = dyn_cast<VectorType>(DataType)) {
253  unsigned NumElements =
254  cast<FixedVectorType>(DataTypeVTy)->getNumElements();
255  unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
256  return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
257  EltSize <= 128 && isPowerOf2_64(EltSize);
258  }
259  return BaseT::isLegalNTStore(DataType, Alignment);
260  }
261 
263  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
264  Align Alignment, unsigned AddressSpace,
266  bool UseMaskForCond = false, bool UseMaskForGaps = false);
267 
268  bool
270  bool &AllowPromotionWithoutCommonHeader);
271 
272  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
273 
274  unsigned getGISelRematGlobalCost() const {
275  return 2;
276  }
277 
278  bool supportsScalableVectors() const { return ST->hasSVE(); }
279 
281  ElementCount VF) const;
282 
284  unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
286 
288  ArrayRef<int> Mask, int Index,
289  VectorType *SubTp);
290  /// @}
291 };
292 
293 } // end namespace llvm
294 
295 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::AArch64TTIImpl::isLegalMaskedGatherScatter
bool isLegalMaskedGatherScatter(Type *DataType) const
Definition: AArch64TargetTransformInfo.h:230
llvm
Definition: AllocatorList.h:23
AArch64.h
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::AArch64TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: AArch64TargetTransformInfo.cpp:668
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:229
llvm::ElementCount
Definition: TypeSize.h:386
llvm::AArch64TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: AArch64TargetTransformInfo.h:103
llvm::AArch64TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:942
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:317
llvm::AArch64TTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: AArch64TargetTransformInfo.cpp:1091
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:924
llvm::AArch64TTIImpl::supportsScalableVectors
bool supportsScalableVectors() const
Definition: AArch64TargetTransformInfo.h:278
llvm::AArch64TTIImpl::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: AArch64TargetTransformInfo.h:274
llvm::AArch64TTIImpl::AArch64TTIImpl
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
Definition: AArch64TargetTransformInfo.h:63
llvm::AArch64TTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: AArch64TargetTransformInfo.h:272
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::Optional< unsigned >
llvm::AArch64TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: AArch64TargetTransformInfo.h:90
VectorType
Definition: ItaniumDemangle.h:901
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AArch64TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AArch64TargetTransformInfo.cpp:30
llvm::AArch64TTIImpl::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
Definition: AArch64TargetTransformInfo.cpp:597
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
AArch64TargetMachine.h
llvm::AArch64TTIImpl::getCostOfKeepingLiveOverCall
int getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
Definition: AArch64TargetTransformInfo.cpp:1021
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:903
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:845
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1079
Intrinsics.h
llvm::AArch64TTIImpl::getIntImmCostIntrin
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:155
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
llvm::AArch64TTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth()
Definition: AArch64TargetTransformInfo.h:118
llvm::Instruction
Definition: Instruction.h:45
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:25
llvm::AArch64TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:346
llvm::AArch64TTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: AArch64TargetTransformInfo.h:122
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:924
llvm::AArch64TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsPairwise, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:1251
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::AArch64TTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: AArch64TargetTransformInfo.cpp:1340
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::AArch64TTIImpl::isLegalMaskedLoadStore
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:215
llvm::AArch64TTIImpl::isLegalElementTypeForSVE
bool isLegalElementTypeForSVE(Type *Ty) const
Definition: AArch64TargetTransformInfo.h:198
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:116
llvm::AArch64TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:216
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:202
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:238
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:41
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::AArch64TTIImpl::getArithmeticReductionCostSVE
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, bool IsPairwiseForm, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:1277
llvm::AArch64::SVEBitsPerBlock
static constexpr unsigned SVEBitsPerBlock
Definition: AArch64BaseInfo.h:676
llvm::AArch64TTIImpl::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, ElementCount VF) const
Definition: AArch64TargetTransformInfo.cpp:1223
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:903
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::Type::isHalfTy
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:142
llvm::AArch64TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: AArch64TargetTransformInfo.h:237
llvm::BasicTTIImplBase< AArch64TTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:598
llvm::AArch64TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AArch64TargetTransformInfo.cpp:1035
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:895
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:750
llvm::AArch64TTIImpl::getAddressComputationCost
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
Definition: AArch64TargetTransformInfo.cpp:822
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::AArch64TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: AArch64TargetTransformInfo.h:88
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:759
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:896
llvm::AArch64TTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: AArch64TargetTransformInfo.cpp:207
llvm::AArch64TTIImpl::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:244
llvm::TargetTransformInfoImplBase::getIntImmCost
unsigned getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:352
llvm::AArch64TTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:840
llvm::Type::isFloatTy
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:148
llvm::AArch64TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AArch64TargetTransformInfo.cpp:693
llvm::AArch64TTIImpl::getIntImmCost
int getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
Definition: AArch64TargetTransformInfo.cpp:47
llvm::TypeSize
Definition: TypeSize.h:417
llvm::AArch64TTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
Definition: AArch64TargetTransformInfo.cpp:1151
Function.h
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::Type::isDoubleTy
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:151
llvm::AArch64TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:658
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:924
llvm::AArch64TTIImpl::getIntImmCostInst
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: AArch64TargetTransformInfo.cpp:87
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::AArch64TTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: AArch64TargetTransformInfo.h:240
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:66
AArch64Subtarget.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:924
llvm::Type::isBFloatTy
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
Definition: Type.h:145
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
TargetTransformInfo.h
llvm::AArch64TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: AArch64TargetTransformInfo.cpp:995
llvm::AArch64TTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:918
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:68
llvm::AArch64TTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AArch64TargetTransformInfo.cpp:1110
llvm::AArch64TTIImpl::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
Definition: AArch64TargetTransformInfo.cpp:1196
llvm::AArch64::SVEMaxBitsPerVector
static constexpr unsigned SVEMaxBitsPerVector
Definition: AArch64BaseInfo.h:677
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::AArch64TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)
Definition: AArch64TargetTransformInfo.cpp:1306
BasicTTIImpl.h
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:479
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
llvm::AArch64TTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:222
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::AArch64TTIImpl::useNeonVector
bool useNeonVector(const Type *Ty) const
Definition: AArch64TargetTransformInfo.cpp:938
llvm::AArch64TTIImpl::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
Definition: AArch64TargetTransformInfo.cpp:1115
llvm::AArch64TTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: AArch64TargetTransformInfo.cpp:901
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::AArch64TTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:226