LLVM  15.0.0git
Public Member Functions | List of all members
llvm::AArch64TTIImpl Class Reference

#include "Target/AArch64/AArch64TargetTransformInfo.h"

Inheritance diagram for llvm::AArch64TTIImpl:
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Collaboration diagram for llvm::AArch64TTIImpl:
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Public Member Functions

 AArch64TTIImpl (const AArch64TargetMachine *TM, const Function &F)
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
Scalar TTI Implementations
InstructionCost getIntImmCost (int64_t Val)
 Calculate the cost of materializing a 64-bit value. More...
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
 Calculate the cost of materializing the given constant. More...
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
 
InstructionCost getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
 
TTI::PopcntSupportKind getPopcntSupport (unsigned TyWidth)
 
Vector TTI Implementations
bool enableInterleavedAccessVectorization ()
 
unsigned getNumberOfRegisters (unsigned ClassID) const
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMinVectorRegisterBitWidth () const
 
Optional< unsigned > getVScaleForTuning () const
 
bool shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMaxNumElements (ElementCount VF) const
 Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF. More...
 
unsigned getMaxInterleaveFactor (unsigned VF)
 
bool prefersVectorizedAddressing () const
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)
 
InstructionCost getMinMaxReductionCost (VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
 
InstructionCost getArithmeticReductionCostSVE (unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
 
InstructionCost getSpliceCost (VectorType *Tp, int Index)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
InstructionCost getAddressComputationCost (Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
TTI::MemCmpExpansionOptions enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
 
bool useNeonVector (const Type *Ty) const
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys)
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
Value * getOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType)
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info)
 
bool isElementTypeLegalForScalableVector (Type *Ty) const
 
bool isLegalMaskedLoadStore (Type *DataType, Align Alignment)
 
bool isLegalMaskedLoad (Type *DataType, Align Alignment)
 
bool isLegalMaskedStore (Type *DataType, Align Alignment)
 
bool isLegalMaskedGatherScatter (Type *DataType) const
 
bool isLegalMaskedGather (Type *DataType, Align Alignment) const
 
bool isLegalMaskedScatter (Type *DataType, Align Alignment) const
 
bool isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
 
bool isLegalNTStore (Type *DataType, Align Alignment)
 
bool enableOrderedReductions () const
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
bool shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
 See if I should be considered for address type promotion. More...
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
unsigned getGISelRematGlobalCost () const
 
bool emitGetActiveLaneMask () const
 
bool supportsScalableVectors () const
 
bool enableScalableVectorization () const
 
bool isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
 
- Public Member Functions inherited from llvm::BasicTTIImplBase< AArch64TTIImpl >
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
 
bool hasBranchDivergence ()
 
bool useGPUDivergenceAnalysis ()
 
bool isSourceOfDivergence (const Value *V)
 
bool isAlwaysUniform (const Value *V)
 
unsigned getFlatAddressSpace ()
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLegalAddImmediate (int64_t imm)
 
bool isLegalICmpImmediate (int64_t imm)
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)
 
unsigned getStoreMinimumVF (unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isLSRCostLess (TTI::LSRCost C1, TTI::LSRCost C2)
 
bool isNumRegsMajorCostOfLSR ()
 
bool isProfitableLSRChainElement (Instruction *I)
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)
 
bool isTruncateFree (Type *Ty1, Type *Ty2)
 
bool isProfitableToHoist (Instruction *I)
 
bool useAA () const
 
bool isTypeLegal (Type *Ty)
 
unsigned getRegUsageForType (Type *Ty)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 
bool shouldBuildLookupTables ()
 
bool shouldBuildRelLookupTables () const
 
bool haveFastSqrt (Type *Ty)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty)
 
InstructionCost getFPOpCost (Type *Ty)
 
unsigned getInliningThresholdMultiplier ()
 
unsigned adjustInliningThreshold (const CallBase *CB)
 
int getInlinerVectorBonusPercent ()
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
 
bool preferPredicateOverEpilogue (Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI)
 
bool emitGetActiveLaneMask ()
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II)
 
Optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
 
InstructionCost getInstructionLatency (const Instruction *I)
 
virtual Optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
virtual Optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
virtual unsigned getCacheLineSize () const
 
virtual unsigned getPrefetchDistance () const
 
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
virtual unsigned getMaxPrefetchIterationsAhead () const
 
virtual bool enableWritePrefetching () const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
Optional< unsigned > getMaxVScale () const
 
Optional< unsigned > getVScaleForTuning () const
 
InstructionCost getScalarizationOverhead (VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract)
 Estimate the overhead of scalarizing an instruction. More...
 
InstructionCost getScalarizationOverhead (VectorType *InTy, bool Insert, bool Extract)
 Helper wrapper for the DemandedElts variant of getScalarizationOverhead. More...
 
InstructionCost getScalarizationOverhead (VectorType *RetTy, ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
 Estimate the overhead of scalarizing the inputs and outputs of an instruction, with return type RetTy and arguments Args of type Tys. More...
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
 Estimate the overhead of scalarizing an instructions unique non-constant operands. More...
 
unsigned getMaxInterleaveFactor (unsigned VF)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
TTI::ShuffleKind improveShuffleKindFromMask (TTI::ShuffleKind Kind, ArrayRef< int > Mask) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)
 
InstructionCost getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on arguments. More...
 
InstructionCost getTypeBasedIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on argument types. More...
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Compute a cost of the given call instruction. More...
 
unsigned getNumberOfParts (Type *Tp)
 
InstructionCost getAddressComputationCost (Type *Ty, ScalarEvolution *, const SCEV *)
 
InstructionCost getTreeReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate arithmetic and shuffle op costs for reduction intrinsics. More...
 
InstructionCost getOrderedReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate the cost of performing strict (in-order) reductions, which involves doing a sequence of floating point additions in lane order, starting with an initial value. More...
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
 Try to calculate op costs for min/max reduction operations. More...
 
InstructionCost getExtendedAddReductionCost (bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind)
 
InstructionCost getVectorSplitCost ()
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< AArch64TTIImpl >
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
InstructionCost getUserCost (const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
InstructionCost getInstructionLatency (const Instruction *I)
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)=default
 
 TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)
 
const DataLayout & getDataLayout () const
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
int getInlinerVectorBonusPercent () const
 
InstructionCost getMemcpyCost (const Instruction *I) const
 
BranchProbability getPredictableBranchThreshold () const
 
bool hasBranchDivergence () const
 
bool useGPUDivergenceAnalysis () const
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned, unsigned) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLoweredToCall (const Function *F) const
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
 
bool preferPredicateOverEpilogue (Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
 
bool emitGetActiveLaneMask () const
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
Optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
void getUnrollingPreferences (Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
 
void getPeelingPreferences (Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
 
bool isLegalAddImmediate (int64_t Imm) const
 
bool isLegalICmpImmediate (int64_t Imm) const
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
 
bool isLSRCostLess (const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
 
bool isNumRegsMajorCostOfLSR () const
 
bool isProfitableLSRChainElement (Instruction *I) const
 
bool canMacroFuseCmp () const
 
bool canSaveCmp (Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
 
TTI::AddressingModeKind getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
 
bool isLegalMaskedStore (Type *DataType, Align Alignment) const
 
bool isLegalMaskedLoad (Type *DataType, Align Alignment) const
 
bool isLegalNTStore (Type *DataType, Align Alignment) const
 
bool isLegalNTLoad (Type *DataType, Align Alignment) const
 
bool isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
 
bool isLegalMaskedScatter (Type *DataType, Align Alignment) const
 
bool isLegalMaskedGather (Type *DataType, Align Alignment) const
 
bool forceScalarizeMaskedGather (VectorType *DataType, Align Alignment) const
 
bool forceScalarizeMaskedScatter (VectorType *DataType, Align Alignment) const
 
bool isLegalMaskedCompressStore (Type *DataType) const
 
bool isLegalAltInstr (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
 
bool isLegalMaskedExpandLoad (Type *DataType) const
 
bool enableOrderedReductions () const
 
bool hasDivRemOp (Type *DataType, bool IsSigned) const
 
bool hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
 
bool prefersVectorizedAddressing () const
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
 
bool LSRWithInstrQueries () const
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const
 
bool isProfitableToHoist (Instruction *I) const
 
bool useAA () const
 
bool isTypeLegal (Type *Ty) const
 
unsigned getRegUsageForType (Type *Ty) const
 
bool shouldBuildLookupTables () const
 
bool shouldBuildLookupTablesForConstant (Constant *C) const
 
bool shouldBuildRelLookupTables () const
 
bool useColdCCForColdCall (Function &F) const
 
InstructionCost getScalarizationOverhead (VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
 
bool supportsEfficientVectorElementLoadStore () const
 
bool supportsTailCalls () const
 
bool enableAggressiveInterleaving (bool LoopHasReductions) const
 
TTI::MemCmpExpansionOptions enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
 
bool enableInterleavedAccessVectorization () const
 
bool enableMaskedInterleavedAccessVectorization () const
 
bool isFPVectorizationPotentiallyUnsafe () const
 
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
 
TTI::PopcntSupportKind getPopcntSupport (unsigned IntTyWidthInBit) const
 
bool haveFastSqrt (Type *Ty) const
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty) const
 
InstructionCost getFPOpCost (Type *Ty) const
 
InstructionCost getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
 
InstructionCost getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfRegisters (unsigned ClassID) const
 
unsigned getRegisterClassForType (bool Vector, Type *Ty=nullptr) const
 
const char * getRegisterClassName (unsigned ClassID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMinVectorRegisterBitWidth () const
 
Optional< unsigned > getMaxVScale () const
 
Optional< unsigned > getVScaleForTuning () const
 
bool shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const
 
ElementCount getMinimumVF (unsigned ElemWidth, bool IsScalable) const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
unsigned getStoreMinimumVF (unsigned VF, Type *, Type *) const
 
bool shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
 
unsigned getCacheLineSize () const
 
llvm::Optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
llvm::Optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
unsigned getPrefetchDistance () const
 
unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
unsigned getMaxPrefetchIterationsAhead () const
 
bool enableWritePrefetching () const
 
unsigned getMaxInterleaveFactor (unsigned VF) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None) const
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index) const
 
unsigned getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getVPMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
unsigned getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfParts (Type *Tp) const
 
InstructionCost getAddressComputationCost (Type *Tp, ScalarEvolution *, const SCEV *) const
 
InstructionCost getArithmeticReductionCost (unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
 
InstructionCost getMinMaxReductionCost (VectorType *, VectorType *, bool, TTI::TargetCostKind) const
 
InstructionCost getExtendedAddReductionCost (bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
unsigned getAtomicMemIntrinsicMaxElementSize () const
 
Value * getOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType) const
 
Type * getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize) const
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
bool areTypesABICompatible (const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeLoad (LoadInst *LI) const
 
bool isLegalToVectorizeStore (StoreInst *SI) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
 
bool isElementTypeLegalForScalableVector (Type *Ty) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
bool preferInLoopReduction (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
unsigned getGISelRematGlobalCost () const
 
bool supportsScalableVectors () const
 
bool enableScalableVectorization () const
 
bool hasActiveVectorLength (unsigned Opcode, Type *DataType, Align Alignment) const
 
TargetTransformInfo::VPLegalization getVPLegalizationStrategy (const VPIntrinsic &PI) const
 

Additional Inherited Members

- Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo TTI
 
- Protected Member Functions inherited from llvm::BasicTTIImplBase< AArch64TTIImpl >
 BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)
 
virtual ~BasicTTIImplBase ()=default
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< AArch64TTIImpl >
 TargetTransformInfoImplCRTPBase (const DataLayout &DL)
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const DataLayout &DL)
 
unsigned minRequiredElementSize (const Value *Val, bool &isSigned) const
 
bool isStridedAccess (const SCEV *Ptr) const
 
const SCEVConstant * getConstantStrideStep (ScalarEvolution *SE, const SCEV *Ptr) const
 
bool isConstantStridedAccessLessThan (ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
 
- Protected Attributes inherited from llvm::BasicTTIImplBase< AArch64TTIImpl >
const DataLayout & DL
 
- Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayout & DL
 

Detailed Description

Definition at line 41 of file AArch64TargetTransformInfo.h.

Constructor & Destructor Documentation

◆ AArch64TTIImpl()

llvm::AArch64TTIImpl::AArch64TTIImpl ( const AArch64TargetMachine *  TM,
const Function &  F 
)
inlineexplicit

Definition at line 63 of file AArch64TargetTransformInfo.h.

Member Function Documentation

◆ areInlineCompatible()

bool AArch64TTIImpl::areInlineCompatible ( const Function *  Caller,
const Function *  Callee 
) const

Definition at line 40 of file AArch64TargetTransformInfo.cpp.

References TM.

◆ emitGetActiveLaneMask()

bool llvm::AArch64TTIImpl::emitGetActiveLaneMask ( ) const
inline

Definition at line 337 of file AArch64TargetTransformInfo.h.

◆ enableInterleavedAccessVectorization()

bool llvm::AArch64TTIImpl::enableInterleavedAccessVectorization ( )
inline

Definition at line 91 of file AArch64TargetTransformInfo.h.

◆ enableMemCmpExpansion()

AArch64TTIImpl::TTI::MemCmpExpansionOptions AArch64TTIImpl::enableMemCmpExpansion ( bool  OptSize,
bool  IsZeroCmp 
) const

Definition at line 2066 of file AArch64TargetTransformInfo.cpp.

References Options, and llvm::ARM_MB::ST.

◆ enableOrderedReductions()

bool llvm::AArch64TTIImpl::enableOrderedReductions ( ) const
inline

Definition at line 320 of file AArch64TargetTransformInfo.h.

◆ enableScalableVectorization()

bool llvm::AArch64TTIImpl::enableScalableVectorization ( ) const
inline

Definition at line 343 of file AArch64TargetTransformInfo.h.

◆ getAddressComputationCost()

InstructionCost AArch64TTIImpl::getAddressComputationCost ( Type *  Ty,
ScalarEvolution *  SE,
const SCEV *  Ptr 
)

Definition at line 1979 of file AArch64TargetTransformInfo.cpp.

References llvm::Type::isVectorTy().

◆ getArithmeticInstrCost()

InstructionCost AArch64TTIImpl::getArithmeticInstrCost ( unsigned  Opcode,
Type *  Ty,
TTI::TargetCostKind  CostKind,
TTI::OperandValueKind  Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind  Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties  Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties  Opd2PropInfo = TTI::OP_None,
ArrayRef< const Value * >  Args = ArrayRef<const Value *>(),
const Instruction *  CxtI = nullptr 
)

Definition at line 1860 of file AArch64TargetTransformInfo.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::AND, llvm::AMDGPU::HSAMD::Kernel::Key::Args, CostKind, DL, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FSUB, llvm::Type::getScalarType(), llvm::Type::isFP128Ty(), llvm::Type::isVectorTy(), LLVM_FALLTHROUGH, llvm::AArch64CC::LT, Mul, llvm::ISD::MUL, llvm::ISD::MULHU, llvm::TargetTransformInfo::OK_UniformConstantValue, llvm::TargetTransformInfo::OP_None, llvm::TargetTransformInfo::OP_PowerOf2, llvm::ISD::OR, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::ISD::UDIV, llvm::MVT::v2i64, and llvm::ISD::XOR.

◆ getArithmeticReductionCost()

InstructionCost AArch64TTIImpl::getArithmeticReductionCost ( unsigned  Opcode,
VectorType *  Ty,
Optional< FastMathFlags >  FMF,
TTI::TargetCostKind  CostKind 
)

Definition at line 2549 of file AArch64TargetTransformInfo.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), CostKind, DL, llvm::InstructionCost::getInvalid(), llvm::AArch64CC::LT, llvm::ISD::OR, llvm::TargetTransformInfo::requiresOrderedReduction(), llvm::MVT::v16i8, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::XOR.

◆ getArithmeticReductionCostSVE()

InstructionCost AArch64TTIImpl::getArithmeticReductionCostSVE ( unsigned  Opcode,
VectorType *  ValTy,
TTI::TargetCostKind  CostKind 
)

Definition at line 2523 of file AArch64TargetTransformInfo.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), CostKind, DL, llvm::ISD::FADD, llvm::Type::getContext(), llvm::InstructionCost::getInvalid(), llvm::EVT::getTypeForEVT(), llvm::AArch64CC::LT, llvm::ISD::OR, and llvm::ISD::XOR.

◆ getCastInstrCost()

InstructionCost AArch64TTIImpl::getCastInstrCost ( unsigned  Opcode,
Type *  Dst,
Type *  Src,
TTI::CastContextHint  CCH,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 1445 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::ISD::BITCAST, CostKind, DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, I, llvm::EVT::isSimple(), llvm::MVT::nxv16i1, llvm::MVT::nxv16i8, llvm::MVT::nxv2f16, llvm::MVT::nxv2f32, llvm::MVT::nxv2f64, llvm::MVT::nxv2i1, llvm::MVT::nxv2i16, llvm::MVT::nxv2i32, llvm::MVT::nxv2i64, llvm::MVT::nxv2i8, llvm::MVT::nxv4f16, llvm::MVT::nxv4f32, llvm::MVT::nxv4f64, llvm::MVT::nxv4i1, llvm::MVT::nxv4i16, llvm::MVT::nxv4i32, llvm::MVT::nxv4i64, llvm::MVT::nxv4i8, llvm::MVT::nxv8f16, llvm::MVT::nxv8f32, llvm::MVT::nxv8f64, llvm::MVT::nxv8i1, llvm::MVT::nxv8i16, llvm::MVT::nxv8i32, llvm::MVT::nxv8i64, llvm::MVT::nxv8i8, Operands, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

◆ getCFInstrCost()

InstructionCost AArch64TTIImpl::getCFInstrCost ( unsigned  Opcode,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 1822 of file AArch64TargetTransformInfo.cpp.

References assert(), CostKind, and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getCmpSelInstrCost()

InstructionCost AArch64TTIImpl::getCmpSelInstrCost ( unsigned  Opcode,
Type *  ValTy,
Type *  CondTy,
CmpInst::Predicate  VecPred,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 1998 of file AArch64TargetTransformInfo.cpp.

References llvm::any_of(), llvm::CmpInst::BAD_ICMP_PREDICATE, CostKind, DL, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_UNE, I, llvm::CmpInst::isIntPredicate(), llvm::EVT::isSimple(), llvm::AArch64CC::LT, M, llvm::PatternMatch::m_Cmp(), llvm::PatternMatch::m_Select(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::match(), llvm::ISD::SELECT, llvm::ARM_MB::ST, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::MVT::v16i1, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i64, llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f16, llvm::MVT::v8i1, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, and llvm::MVT::v8i8.

◆ getCostOfKeepingLiveOverCall()

InstructionCost AArch64TTIImpl::getCostOfKeepingLiveOverCall ( ArrayRef< Type * >  Tys)

Definition at line 2228 of file AArch64TargetTransformInfo.cpp.

References Align, CostKind, I, llvm::SPII::Load, llvm::SPII::Store, and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getExtractWithExtendCost()

InstructionCost AArch64TTIImpl::getExtractWithExtendCost ( unsigned  Opcode,
Type *  Dst,
VectorType *  VecTy,
unsigned  Index 
)

Definition at line 1761 of file AArch64TargetTransformInfo.cpp.

References assert(), CostKind, DL, llvm::VectorType::getElementType(), llvm_unreachable, llvm::TargetTransformInfo::None, and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getGatherScatterOpCost()

InstructionCost AArch64TTIImpl::getGatherScatterOpCost ( unsigned  Opcode,
Type *  DataTy,
const Value *  Ptr,
bool  VariableMask,
Align  Alignment,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 2112 of file AArch64TargetTransformInfo.cpp.

References CostKind, DL, llvm::InstructionCost::getInvalid(), llvm::LinearPolySize< ElementCount >::getScalable(), getSVEGatherScatterOverhead(), I, and llvm::AArch64CC::LT.

◆ getGISelRematGlobalCost()

unsigned llvm::AArch64TTIImpl::getGISelRematGlobalCost ( ) const
inline

Definition at line 333 of file AArch64TargetTransformInfo.h.

◆ getInterleavedMemoryOpCost()

InstructionCost AArch64TTIImpl::getInterleavedMemoryOpCost ( unsigned  Opcode,
Type *  VecTy,
unsigned  Factor,
ArrayRef< unsigned >  Indices,
Align  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind,
bool  UseMaskForCond = false,
bool  UseMaskForGaps = false 
)

Definition at line 2200 of file AArch64TargetTransformInfo.cpp.

References assert(), CostKind, DL, llvm::FixedVectorType::get(), and llvm::Type::getScalarType().

◆ getIntImmCost() [1/2]

InstructionCost AArch64TTIImpl::getIntImmCost ( const APInt &  Imm,
Type *  Ty,
TTI::TargetCostKind  CostKind 
)

Calculate the cost of materializing the given constant.

Definition at line 78 of file AArch64TargetTransformInfo.cpp.

References llvm::APInt::ashr(), assert(), llvm::Type::getPrimitiveSizeInBits(), llvm::APInt::getSExtValue(), llvm::RISCVMatInt::Imm, llvm::Type::isIntegerTy(), and llvm::APInt::sextOrTrunc().

◆ getIntImmCost() [2/2]

InstructionCost AArch64TTIImpl::getIntImmCost ( int64_t  Val)

Calculate the cost of materializing a 64-bit value.

This helper method might only calculate a fraction of a larger immediate. Therefore it is valid to return a cost of ZERO.

Definition at line 63 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64_IMM::expandMOVImm(), Insn, and llvm::AArch64_AM::isLogicalImmediate().

Referenced by getIntImmCostInst(), and getIntImmCostIntrin().

◆ getIntImmCostInst()

InstructionCost AArch64TTIImpl::getIntImmCostInst ( unsigned  Opcode,
unsigned  Idx,
const APInt &  Imm,
Type *  Ty,
TTI::TargetCostKind  CostKind,
Instruction *  Inst = nullptr 
)

Definition at line 103 of file AArch64TargetTransformInfo.cpp.

References llvm::MCID::Add, assert(), llvm::MCID::Call, CostKind, getIntImmCost(), llvm::Type::getPrimitiveSizeInBits(), llvm::RISCVMatInt::Imm, llvm::Type::isIntegerTy(), llvm::SPII::Load, Mul, llvm::MipsISD::Ret, llvm::MCID::Select, llvm::SPII::Store, llvm::TargetTransformInfo::TCC_Basic, and llvm::TargetTransformInfo::TCC_Free.

◆ getIntImmCostIntrin()

InstructionCost AArch64TTIImpl::getIntImmCostIntrin ( Intrinsic::ID  IID,
unsigned  Idx,
const APInt &  Imm,
Type *  Ty,
TTI::TargetCostKind  CostKind 
)

Definition at line 172 of file AArch64TargetTransformInfo.cpp.

References assert(), CostKind, getIntImmCost(), llvm::Type::getPrimitiveSizeInBits(), llvm::RISCVMatInt::Imm, llvm::Type::isIntegerTy(), llvm::TargetTransformInfo::TCC_Basic, and llvm::TargetTransformInfo::TCC_Free.

◆ getIntrinsicInstrCost()

InstructionCost AArch64TTIImpl::getIntrinsicInstrCost ( const IntrinsicCostAttributes &  ICA,
TTI::TargetCostKind  CostKind 
)

Definition at line 233 of file AArch64TargetTransformInfo.cpp.

References llvm::abs(), llvm::MCID::Add, llvm::any_of(), CostKind, DL, llvm::IntrinsicCostAttributes::getID(), llvm::IntrinsicCostAttributes::getReturnType(), llvm::EVT::getTypeForEVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64CC::LT, M, llvm::APIntOps::smax(), llvm::APIntOps::smin(), llvm::APIntOps::umax(), llvm::APIntOps::umin(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i8.

◆ getMaskedMemoryOpCost()

InstructionCost AArch64TTIImpl::getMaskedMemoryOpCost ( unsigned  Opcode,
Type *  Src,
Align  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind 
)

Definition at line 2088 of file AArch64TargetTransformInfo.cpp.

References CostKind, DL, llvm::InstructionCost::getInvalid(), llvm::LinearPolySize< ElementCount >::getScalable(), and llvm::AArch64CC::LT.

◆ getMaxInterleaveFactor()

unsigned AArch64TTIImpl::getMaxInterleaveFactor ( unsigned  VF)

Definition at line 2242 of file AArch64TargetTransformInfo.cpp.

References llvm::ARM_MB::ST.

◆ getMaxNumElements()

unsigned llvm::AArch64TTIImpl::getMaxNumElements ( ElementCount  VF) const
inline

Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation for a vector with ElementCount VF.

For scalable vectors this currently takes the most pessimistic view based upon the maximum possible value for vscale.

Definition at line 144 of file AArch64TargetTransformInfo.h.

References llvm::LinearPolySize< LeafTy >::getFixedValue(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), and llvm::LinearPolySize< LeafTy >::isScalable().

◆ getMemoryOpCost()

InstructionCost AArch64TTIImpl::getMemoryOpCost ( unsigned  Opcode,
Type *  Src,
MaybeAlign  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 2145 of file AArch64TargetTransformInfo.cpp.

References CostKind, DL, llvm::InstructionCost::getInvalid(), llvm::LinearPolySize< ElementCount >::getScalable(), llvm::Type::getScalarSizeInBits(), llvm::AArch64CC::LT, llvm::MVT::Other, llvm::ARM_MB::ST, llvm::SPII::Store, llvm::TargetTransformInfo::TCK_CodeSize, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::TargetTransformInfo::TCK_SizeAndLatency, and llvm::MVT::v4i8.

◆ getMinMaxReductionCost()

InstructionCost AArch64TTIImpl::getMinMaxReductionCost ( VectorType *  Ty,
VectorType *  CondTy,
bool  IsUnsigned,
TTI::TargetCostKind  CostKind 
)

Definition at line 2498 of file AArch64TargetTransformInfo.cpp.

References assert(), Attrs, CostKind, DL, llvm::MVT::f16, llvm::Type::getContext(), llvm::EVT::getTypeForEVT(), llvm::Type::isFPOrFPVectorTy(), llvm::AArch64CC::LT, llvm::maxnum(), llvm::APIntOps::smin(), llvm::ARM_MB::ST, and llvm::APIntOps::umin().

◆ getMinVectorRegisterBitWidth()

unsigned llvm::AArch64TTIImpl::getMinVectorRegisterBitWidth ( ) const
inline

Definition at line 130 of file AArch64TargetTransformInfo.h.

◆ getNumberOfRegisters()

unsigned llvm::AArch64TTIImpl::getNumberOfRegisters ( unsigned  ClassID) const
inline

Definition at line 93 of file AArch64TargetTransformInfo.h.

References Vector.

◆ getOrCreateResultFromMemIntrinsic()

Value * AArch64TTIImpl::getOrCreateResultFromMemIntrinsic ( IntrinsicInst *  Inst,
Type *  ExpectedType 
)

Definition at line 2359 of file AArch64TargetTransformInfo.cpp.

References llvm::CallBase::arg_size(), Builder, llvm::numbers::e, llvm::UndefValue::get(), llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), llvm::Value::getType(), i, and llvm::ARM_MB::ST.

◆ getPeelingPreferences()

void AArch64TTIImpl::getPeelingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::PeelingPreferences &  PP 
)

Definition at line 2354 of file AArch64TargetTransformInfo.cpp.

◆ getPopcntSupport()

TargetTransformInfo::PopcntSupportKind AArch64TTIImpl::getPopcntSupport ( unsigned  TyWidth)

Definition at line 224 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::isPowerOf2_32(), llvm::TargetTransformInfo::PSK_FastHardware, and llvm::TargetTransformInfo::PSK_Software.

◆ getRegisterBitWidth()

TypeSize llvm::AArch64TTIImpl::getRegisterBitWidth ( TargetTransformInfo::RegisterKind  K) const
inline

Definition at line 115 of file AArch64TargetTransformInfo.h.

References llvm::LinearPolySize< TypeSize >::getFixed(), llvm::LinearPolySize< TypeSize >::getScalable(), llvm_unreachable, llvm::max(), llvm::TargetTransformInfo::RGK_FixedWidthVector, llvm::TargetTransformInfo::RGK_ScalableVector, and llvm::TargetTransformInfo::RGK_Scalar.

◆ getShuffleCost()

InstructionCost AArch64TTIImpl::getShuffleCost ( TTI::ShuffleKind  Kind,
VectorType *  Tp,
ArrayRef< int >  Mask,
int  Index,
VectorType *  SubTp,
ArrayRef< const Value * >  Args = None 
)

Definition at line 2697 of file AArch64TargetTransformInfo.cpp.

References llvm::all_of(), llvm::any_of(), llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), DL, E, llvm::enumerate(), llvm::VectorType::get(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), llvm::LinearPolySize< ElementCount >::getFixed(), getPerfectShuffleCost(), llvm::Type::getScalarSizeInBits(), llvm::Type::getScalarType(), llvm::AArch64CC::LT, llvm::BitmaskEnumDetail::Mask(), N, llvm::MVT::nxv16i1, llvm::MVT::nxv16i8, llvm::MVT::nxv2bf16, llvm::MVT::nxv2f16, llvm::MVT::nxv2f32, llvm::MVT::nxv2f64, llvm::MVT::nxv2i1, llvm::MVT::nxv2i64, llvm::MVT::nxv4bf16, llvm::MVT::nxv4f16, llvm::MVT::nxv4f32, llvm::MVT::nxv4i1, llvm::MVT::nxv4i32, llvm::MVT::nxv8bf16, llvm::MVT::nxv8f16, llvm::MVT::nxv8i1, llvm::MVT::nxv8i16, llvm::TargetTransformInfo::SK_Broadcast, llvm::TargetTransformInfo::SK_PermuteSingleSrc, llvm::TargetTransformInfo::SK_PermuteTwoSrc, llvm::TargetTransformInfo::SK_Reverse, llvm::TargetTransformInfo::SK_Select, llvm::TargetTransformInfo::SK_Transpose, llvm::Sched::Source, llvm::UndefMaskElem, llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4bf16, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8bf16, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::MVT::v8i8.

◆ getSpliceCost()

InstructionCost AArch64TTIImpl::getSpliceCost ( VectorType *  Tp,
int  Index 
)

Definition at line 2648 of file AArch64TargetTransformInfo.cpp.

References llvm::CmpInst::BAD_ICMP_PREDICATE, CostKind, DL, llvm::Type::getContext(), llvm::EVT::getTypeForEVT(), llvm::MVT::i1, llvm::AArch64CC::LT, llvm::TargetTransformInfo::None, llvm::MVT::nxv16i8, llvm::MVT::nxv2bf16, llvm::MVT::nxv2f16, llvm::MVT::nxv2f32, llvm::MVT::nxv2f64, llvm::MVT::nxv2i64, llvm::MVT::nxv4bf16, llvm::MVT::nxv4f16, llvm::MVT::nxv4f32, llvm::MVT::nxv4i32, llvm::MVT::nxv8bf16, llvm::MVT::nxv8f16, llvm::MVT::nxv8i16, llvm::MCID::Select, llvm::TargetTransformInfo::SK_Splice, and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getTgtMemIntrinsic()

bool AArch64TTIImpl::getTgtMemIntrinsic ( IntrinsicInst *  Inst,
MemIntrinsicInfo &  Info 
)

Definition at line 2395 of file AArch64TargetTransformInfo.cpp.

References llvm::CallBase::arg_size(), llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), and Info.

◆ getUnrollingPreferences()

void AArch64TTIImpl::getUnrollingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::UnrollingPreferences &  UP,
OptimizationRemarkEmitter *  ORE 
)

Definition at line 2298 of file AArch64TargetTransformInfo.cpp.

References BB, llvm::TargetTransformInfo::UnrollingPreferences::DefaultUnrollRuntimeCount, EnableFalkorHWPFUnrollFix, F, llvm::AArch64Subtarget::Falkor, llvm::LoopBase< BlockT, LoopT >::getBlocks(), getCalledFunction(), getFalkorUnrollingPreferences(), llvm::LoopBase< BlockT, LoopT >::getLoopDepth(), I, llvm::AArch64Subtarget::Others, llvm::TargetTransformInfo::UnrollingPreferences::Partial, llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold, llvm::TargetTransformInfo::UnrollingPreferences::PartialThreshold, llvm::TargetTransformInfo::UnrollingPreferences::Runtime, llvm::ARM_MB::ST, llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam, llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold, llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder, and llvm::TargetTransformInfo::UnrollingPreferences::UpperBound.

◆ getVectorInstrCost()

InstructionCost AArch64TTIImpl::getVectorInstrCost ( unsigned  Opcode,
Type *  Val,
unsigned  Index 
)

Definition at line 1832 of file AArch64TargetTransformInfo.cpp.

References assert(), DL, llvm::Type::isVectorTy(), llvm::AArch64CC::LT, and llvm::ARM_MB::ST.

◆ getVScaleForTuning()

Optional<unsigned> llvm::AArch64TTIImpl::getVScaleForTuning ( ) const
inline

Definition at line 134 of file AArch64TargetTransformInfo.h.

◆ instCombineIntrinsic()

Optional< Instruction * > AArch64TTIImpl::instCombineIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II 
) const

Definition at line 1274 of file AArch64TargetTransformInfo.cpp.

References DL, llvm::IntrinsicInst::getIntrinsicID(), instCombineConvertFromSVBool(), instCombineLD1GatherIndex(), instCombineMaxMinNM(), instCombineRDFFR(), instCombineST1ScatterIndex(), instCombineSVECmpNE(), instCombineSVECntElts(), instCombineSVEDup(), instCombineSVEDupX(), instCombineSVELast(), instCombineSVELD1(), instCombineSVEPTest(), instCombineSVESDIV(), instCombineSVESel(), instCombineSVESrshl(), instCombineSVEST1(), instCombineSVETBL(), instCombineSVETupleGet(), instCombineSVEUnpack(), instCombineSVEVectorBinOp(), instCombineSVEVectorFAdd(), instCombineSVEVectorMul(), instCombineSVEZip(), and llvm::None.

◆ isElementTypeLegalForScalableVector()

bool llvm::AArch64TTIImpl::isElementTypeLegalForScalableVector ( Type *  Ty) const
inline

Definition at line 229 of file AArch64TargetTransformInfo.h.

References llvm::Type::isBFloatTy(), llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), llvm::Type::isHalfTy(), llvm::Type::isIntegerTy(), and llvm::Type::isPointerTy().

Referenced by isLegalMaskedGatherScatter(), and isLegalMaskedLoadStore().

◆ isLegalBroadcastLoad()

bool llvm::AArch64TTIImpl::isLegalBroadcastLoad ( Type *  ElementTy,
ElementCount  NumElements 
) const
inline

Definition at line 285 of file AArch64TargetTransformInfo.h.

References llvm::LinearPolySize< LeafTy >::getFixedValue(), llvm::Type::getScalarSizeInBits(), llvm::LinearPolySize< LeafTy >::isScalable(), and llvm::SystemZ::VectorBits.

◆ isLegalMaskedGather()

bool llvm::AArch64TTIImpl::isLegalMaskedGather ( Type *  DataType,
Align  Alignment 
) const
inline

Definition at line 278 of file AArch64TargetTransformInfo.h.

References isLegalMaskedGatherScatter().

◆ isLegalMaskedGatherScatter()

bool llvm::AArch64TTIImpl::isLegalMaskedGatherScatter ( Type *  DataType) const
inline

Definition at line 265 of file AArch64TargetTransformInfo.h.

References llvm::Type::getScalarType(), and isElementTypeLegalForScalableVector().

Referenced by isLegalMaskedGather(), and isLegalMaskedScatter().

◆ isLegalMaskedLoad()

bool llvm::AArch64TTIImpl::isLegalMaskedLoad ( Type *  DataType,
Align  Alignment 
)
inline

Definition at line 257 of file AArch64TargetTransformInfo.h.

References isLegalMaskedLoadStore().

◆ isLegalMaskedLoadStore()

bool llvm::AArch64TTIImpl::isLegalMaskedLoadStore ( Type *  DataType,
Align  Alignment 
)
inline

Definition at line 246 of file AArch64TargetTransformInfo.h.

References llvm::Type::getScalarType(), and isElementTypeLegalForScalableVector().

Referenced by isLegalMaskedLoad(), and isLegalMaskedStore().

◆ isLegalMaskedScatter()

bool llvm::AArch64TTIImpl::isLegalMaskedScatter ( Type *  DataType,
Align  Alignment 
) const
inline

Definition at line 281 of file AArch64TargetTransformInfo.h.

References isLegalMaskedGatherScatter().

◆ isLegalMaskedStore()

bool llvm::AArch64TTIImpl::isLegalMaskedStore ( Type *  DataType,
Align  Alignment 
)
inline

Definition at line 261 of file AArch64TargetTransformInfo.h.

References isLegalMaskedLoadStore().

◆ isLegalNTStore()

bool llvm::AArch64TTIImpl::isLegalNTStore ( Type *  DataType,
Align  Alignment 
)
inline

Definition at line 302 of file AArch64TargetTransformInfo.h.

References llvm::TargetTransformInfoImplBase::isLegalNTStore(), and llvm::isPowerOf2_64().

◆ isLegalToVectorizeReduction()

bool AArch64TTIImpl::isLegalToVectorizeReduction ( const RecurrenceDescriptor &  RdxDesc,
ElementCount  VF 
) const

Definition at line 2467 of file AArch64TargetTransformInfo.cpp.

References llvm::Add, llvm::And, llvm::FAdd, llvm::FMax, llvm::FMin, llvm::FMulAdd, llvm::RecurrenceDescriptor::getRecurrenceKind(), llvm::RecurrenceDescriptor::getRecurrenceType(), llvm::Type::isBFloatTy(), llvm::LinearPolySize< LeafTy >::isScalable(), llvm::Or, llvm::SelectFCmp, llvm::SelectICmp, llvm::SMax, llvm::SMin, llvm::UMax, llvm::UMin, and llvm::Xor.

◆ prefersVectorizedAddressing()

bool AArch64TTIImpl::prefersVectorizedAddressing ( ) const

Definition at line 2083 of file AArch64TargetTransformInfo.cpp.

References llvm::ARM_MB::ST.

◆ shouldConsiderAddressTypePromotion()

bool AArch64TTIImpl::shouldConsiderAddressTypePromotion ( const Instruction &  I,
bool &  AllowPromotionWithoutCommonHeader 
)

See if I should be considered for address type promotion.

We check if I is a sext with right type and used in memory accesses. If it used in a "complex" getelementptr, we allow it to be promoted without finding other sext instructions that sign extended the same initial value. A getelementptr is considered as "complex" if it has more than 2 operands.

Definition at line 2440 of file AArch64TargetTransformInfo.cpp.

References llvm::Type::getInt64Ty(), and I.

◆ shouldExpandReduction()

bool llvm::AArch64TTIImpl::shouldExpandReduction ( const IntrinsicInst *  II) const
inline

Definition at line 331 of file AArch64TargetTransformInfo.h.

◆ shouldMaximizeVectorBandwidth()

bool AArch64TTIImpl::shouldMaximizeVectorBandwidth ( TargetTransformInfo::RegisterKind  K) const

Definition at line 54 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::TargetTransformInfo::RGK_FixedWidthVector, and llvm::TargetTransformInfo::RGK_Scalar.

◆ simplifyDemandedVectorEltsIntrinsic()

Optional< Value * > AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II,
APInt  DemandedElts,
APInt &  UndefElts,
APInt &  UndefElts2,
APInt &  UndefElts3,
std::function< void(Instruction *, unsigned, APInt, APInt &)>  SimplifyAndSetOp 
) const

Definition at line 1347 of file AArch64TargetTransformInfo.cpp.

References llvm::IntrinsicInst::getIntrinsicID(), and llvm::None.

◆ supportsScalableVectors()

bool llvm::AArch64TTIImpl::supportsScalableVectors ( ) const
inline

Definition at line 341 of file AArch64TargetTransformInfo.h.

◆ useNeonVector()

bool AArch64TTIImpl::useNeonVector ( const Type *  Ty) const

Definition at line 2141 of file AArch64TargetTransformInfo.cpp.

References llvm::ARM_MB::ST.

The documentation for this class was generated from the following files:
Generated on Thu Jun 30 2022 07:23:32 for LLVM by   doxygen 1.8.17