LLVM 19.0.0git
ARMLegalizerInfo.cpp
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1//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "ARMLegalizerInfo.h"
14#include "ARMCallLowering.h"
15#include "ARMSubtarget.h"
23#include "llvm/IR/Type.h"
24
25using namespace llvm;
26using namespace LegalizeActions;
27
28static bool AEABI(const ARMSubtarget &ST) {
29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
30}
31
33 using namespace TargetOpcode;
34
35 const LLT p0 = LLT::pointer(0, 32);
36
37 const LLT s1 = LLT::scalar(1);
38 const LLT s8 = LLT::scalar(8);
39 const LLT s16 = LLT::scalar(16);
40 const LLT s32 = LLT::scalar(32);
41 const LLT s64 = LLT::scalar(64);
42
43 auto &LegacyInfo = getLegacyLegalizerInfo();
44 if (ST.isThumb1Only()) {
45 // Thumb1 is not supported yet.
46 LegacyInfo.computeTables();
47 verify(*ST.getInstrInfo());
48 return;
49 }
50
51 getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
52 .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16});
53
54 getActionDefinitionsBuilder(G_SEXT_INREG).lower();
55
56 getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR})
57 .legalFor({s32})
58 .clampScalar(0, s32, s32);
59
60 if (ST.hasNEON())
61 getActionDefinitionsBuilder({G_ADD, G_SUB})
62 .legalFor({s32, s64})
63 .minScalar(0, s32);
64 else
65 getActionDefinitionsBuilder({G_ADD, G_SUB})
66 .legalFor({s32})
67 .minScalar(0, s32);
68
69 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
70 .legalFor({{s32, s32}})
71 .minScalar(0, s32)
72 .clampScalar(1, s32, s32);
73
74 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
75 (ST.isThumb() && ST.hasDivideInThumbMode());
76 if (HasHWDivide)
77 getActionDefinitionsBuilder({G_SDIV, G_UDIV})
78 .legalFor({s32})
79 .clampScalar(0, s32, s32);
80 else
81 getActionDefinitionsBuilder({G_SDIV, G_UDIV})
82 .libcallFor({s32})
83 .clampScalar(0, s32, s32);
84
85 auto &REMBuilder =
86 getActionDefinitionsBuilder({G_SREM, G_UREM}).minScalar(0, s32);
87 if (HasHWDivide)
88 REMBuilder.lowerFor({s32});
89 else if (AEABI(ST))
90 REMBuilder.customFor({s32});
91 else
92 REMBuilder.libcallFor({s32});
93
95 .legalFor({{p0, s32}})
96 .minScalar(1, s32);
98 .legalFor({{s32, p0}})
99 .minScalar(0, s32);
100
102 .legalFor({s32, p0})
103 .clampScalar(0, s32, s32);
104
106 .legalForCartesianProduct({s1}, {s32, p0})
107 .minScalar(1, s32);
108
110 .legalForCartesianProduct({s32, p0}, {s1})
111 .minScalar(0, s32);
112
113 // We're keeping these builders around because we'll want to add support for
114 // floating point to them.
115 auto &LoadStoreBuilder = getActionDefinitionsBuilder({G_LOAD, G_STORE})
116 .legalForTypesWithMemDesc({{s8, p0, s8, 8},
117 {s16, p0, s16, 8},
118 {s32, p0, s32, 8},
119 {p0, p0, p0, 8}})
120 .unsupportedIfMemSizeNotPow2();
121
122 getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
123 getActionDefinitionsBuilder(G_GLOBAL_VALUE).legalFor({p0});
124
125 auto &PhiBuilder =
127 .legalFor({s32, p0})
128 .minScalar(0, s32);
129
131 .legalFor({{p0, s32}})
132 .minScalar(1, s32);
133
135
136 if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
138 {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
139 .legalFor({s32, s64});
140
141 LoadStoreBuilder
142 .legalForTypesWithMemDesc({{s64, p0, s64, 32}})
143 .maxScalar(0, s32);
144 PhiBuilder.legalFor({s64});
145
147 {s32, s64});
148
149 getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}});
150 getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}});
151
152 getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}});
153 getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}});
154
155 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
156 .legalForCartesianProduct({s32}, {s32, s64});
157 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
158 .legalForCartesianProduct({s32, s64}, {s32});
159
160 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV}).legalFor({s32});
162 } else {
163 getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
164 .libcallFor({s32, s64});
165
166 LoadStoreBuilder.maxScalar(0, s32);
167
168 getActionDefinitionsBuilder(G_FNEG).lowerFor({s32, s64});
169
170 getActionDefinitionsBuilder(G_FCONSTANT).customFor({s32, s64});
171
173 {s32, s64});
174
175 if (AEABI(ST))
176 setFCmpLibcallsAEABI();
177 else
178 setFCmpLibcallsGNU();
179
180 getActionDefinitionsBuilder(G_FPEXT).libcallFor({{s64, s32}});
181 getActionDefinitionsBuilder(G_FPTRUNC).libcallFor({{s32, s64}});
182
183 getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
184 .libcallForCartesianProduct({s32}, {s32, s64});
185 getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
186 .libcallForCartesianProduct({s32, s64}, {s32});
187
188 getActionDefinitionsBuilder({G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
189 .libcall();
190 }
191
192 // Just expand whatever loads and stores are left.
193 LoadStoreBuilder.lower();
194
195 if (!ST.useSoftFloat() && ST.hasVFP4Base())
196 getActionDefinitionsBuilder(G_FMA).legalFor({s32, s64});
197 else
198 getActionDefinitionsBuilder(G_FMA).libcallFor({s32, s64});
199
200 getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
201
202 if (ST.hasV5TOps()) {
204 .legalFor({s32, s32})
205 .clampScalar(1, s32, s32)
206 .clampScalar(0, s32, s32);
207 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
208 .lowerFor({s32, s32})
209 .clampScalar(1, s32, s32)
210 .clampScalar(0, s32, s32);
211 } else {
212 getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
213 .libcallFor({s32, s32})
214 .clampScalar(1, s32, s32)
215 .clampScalar(0, s32, s32);
217 .lowerFor({s32, s32})
218 .clampScalar(1, s32, s32)
219 .clampScalar(0, s32, s32);
220 }
221
222 LegacyInfo.computeTables();
223 verify(*ST.getInstrInfo());
224}
225
226void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
227 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
228 // default-initialized.
229 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
230 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
231 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
232 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
233 {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
234 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
235 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
236 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
237 {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
238 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
239 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
240 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}};
241 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
242 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
243 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
244 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
245 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
246 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
247 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
248 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
249 {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
250 {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
251 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
252 {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
253 {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
254
255 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
256 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
257 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
258 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
259 {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
260 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
261 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
262 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
263 {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
264 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
265 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
266 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}};
267 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
268 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
269 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
270 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
271 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
272 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
273 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
274 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
275 {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
276 {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
277 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
278 {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
279 {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
280}
281
282void ARMLegalizerInfo::setFCmpLibcallsGNU() {
283 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
284 // default-initialized.
285 FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
286 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
287 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
288 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
289 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
290 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
291 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F32, CmpInst::ICMP_EQ}};
292 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
293 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
294 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
295 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
296 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
297 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
298 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
299 {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
300 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
301 {RTLIB::UO_F32, CmpInst::ICMP_NE}};
302
303 FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
304 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
305 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
306 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
307 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
308 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
309 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::UO_F64, CmpInst::ICMP_EQ}};
310 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
311 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
312 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
313 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
314 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
315 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
316 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
317 {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
318 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
319 {RTLIB::UO_F64, CmpInst::ICMP_NE}};
320}
321
323ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
324 unsigned Size) const {
325 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
326 if (Size == 32)
327 return FCmp32Libcalls[Predicate];
328 if (Size == 64)
329 return FCmp64Libcalls[Predicate];
330 llvm_unreachable("Unsupported size for FCmp predicate");
331}
332
334 LostDebugLocObserver &LocObserver) const {
335 using namespace TargetOpcode;
336
337 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
338 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
339 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
340
341 switch (MI.getOpcode()) {
342 default:
343 return false;
344 case G_SREM:
345 case G_UREM: {
346 Register OriginalResult = MI.getOperand(0).getReg();
347 auto Size = MRI.getType(OriginalResult).getSizeInBits();
348 if (Size != 32)
349 return false;
350
351 auto Libcall =
352 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
353
354 // Our divmod libcalls return a struct containing the quotient and the
355 // remainder. Create a new, unused register for the quotient and use the
356 // destination of the original instruction for the remainder.
357 Type *ArgTy = Type::getInt32Ty(Ctx);
358 StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
359 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
360 OriginalResult};
361 auto Status = createLibcall(MIRBuilder, Libcall, {RetRegs, RetTy, 0},
362 {{MI.getOperand(1).getReg(), ArgTy, 0},
363 {MI.getOperand(2).getReg(), ArgTy, 0}},
364 LocObserver, &MI);
366 return false;
367 break;
368 }
369 case G_FCMP: {
370 assert(MRI.getType(MI.getOperand(2).getReg()) ==
371 MRI.getType(MI.getOperand(3).getReg()) &&
372 "Mismatched operands for G_FCMP");
373 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
374
375 auto OriginalResult = MI.getOperand(0).getReg();
376 auto Predicate =
377 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
378 auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
379
380 if (Libcalls.empty()) {
381 assert((Predicate == CmpInst::FCMP_TRUE ||
382 Predicate == CmpInst::FCMP_FALSE) &&
383 "Predicate needs libcalls, but none specified");
384 MIRBuilder.buildConstant(OriginalResult,
385 Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
386 MI.eraseFromParent();
387 return true;
388 }
389
390 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
391 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
392 auto *RetTy = Type::getInt32Ty(Ctx);
393
395 for (auto Libcall : Libcalls) {
396 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
397 auto Status = createLibcall(MIRBuilder, Libcall.LibcallID,
398 {LibcallResult, RetTy, 0},
399 {{MI.getOperand(2).getReg(), ArgTy, 0},
400 {MI.getOperand(3).getReg(), ArgTy, 0}},
401 LocObserver, &MI);
402
404 return false;
405
406 auto ProcessedResult =
407 Libcalls.size() == 1
408 ? OriginalResult
409 : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
410
411 // We have a result, but we need to transform it into a proper 1-bit 0 or
412 // 1, taking into account the different peculiarities of the values
413 // returned by the comparison functions.
414 CmpInst::Predicate ResultPred = Libcall.Predicate;
415 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
416 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
417 // to keep the types consistent.
418 MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
419 } else {
420 // We need to compare against 0.
421 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
422 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0);
423 MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
424 }
425 Results.push_back(ProcessedResult);
426 }
427
428 if (Results.size() != 1) {
429 assert(Results.size() == 2 && "Unexpected number of results");
430 MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
431 }
432 break;
433 }
434 case G_FCONSTANT: {
435 // Convert to integer constants, while preserving the binary representation.
436 auto AsInteger =
437 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
438 MIRBuilder.buildConstant(MI.getOperand(0),
439 *ConstantInt::get(Ctx, AsInteger));
440 break;
441 }
442 }
443
444 MI.eraseFromParent();
445 return true;
446}
unsigned const MachineRegisterInfo * MRI
This file describes how to lower LLVM calls to machine code calls.
static bool AEABI(const ARMSubtarget &ST)
This file declares the targeting of the Machinelegalizer class for ARM.
Function Alias Analysis Results
return RetTy
uint64_t Size
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
ppc ctr loops verify
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ARMLegalizerInfo(const ARMSubtarget &ST)
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:966
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:969
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:983
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:995
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:996
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:972
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:981
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:970
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:971
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:993
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:980
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:974
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:977
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:978
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:973
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:975
@ ICMP_EQ
equal
Definition: InstrTypes.h:987
@ ICMP_NE
not equal
Definition: InstrTypes.h:988
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:994
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:982
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:979
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:968
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:976
bool isFPPredicate() const
Definition: InstrTypes.h:1095
bool isIntPredicate() const
Definition: InstrTypes.h:1096
size_t size() const
Definition: Function.h:804
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:356
void resize(typename StorageT::size_type s)
Definition: IndexedMap.h:61
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:57
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & libcallFor(std::initializer_list< LLT > Types)
LegalizeRuleSet & maxScalar(unsigned TypeIdx, const LLT Ty)
Ensure the scalar is at most as wide as Ty.
LegalizeRuleSet & customForCartesianProduct(std::initializer_list< LLT > Types)
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & lowerFor(std::initializer_list< LLT > Types)
The instruction is lowered when type index 0 is any type in the given list.
LegalizeRuleSet & clampScalar(unsigned TypeIdx, const LLT MinTy, const LLT MaxTy)
Limit the range of scalar sizes to MinTy and MaxTy.
LegalizeRuleSet & alwaysLegal()
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalForTypesWithMemDesc(std::initializer_list< LegalityPredicates::TypePairAndMemDesc > TypesAndMemDesc)
The instruction is legal when type indexes 0 and 1 along with the memory size and minimum alignment i...
LegalizeRuleSet & customFor(std::initializer_list< LLT > Types)
@ Legalized
Instruction has been legalized and the MachineFunction changed.
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Class to represent struct types.
Definition: DerivedTypes.h:216
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:373
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static Type * getDoubleTy(LLVMContext &C)
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Libcall
The operation should be implemented as a call to some kind of runtime support library.
Definition: LegalizerInfo.h:83
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
LegalizerHelper::LegalizeResult createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, const CallLowering::ArgInfo &Result, ArrayRef< CallLowering::ArgInfo > Args, CallingConv::ID CC, LostDebugLocObserver &LocObserver, MachineInstr *MI=nullptr)
Helper function that creates a libcall to the given Name using the given calling convention CC.