14 #ifndef LLVM_CODEGEN_GLOBALISEL_LEGALIZATIONARTIFACTCOMBINER_H
15 #define LLVM_CODEGEN_GLOBALISEL_LEGALIZATIONARTIFACTCOMBINER_H
30 #define DEBUG_TYPE "legalizer"
38 static bool isArtifactCast(
unsigned Opc) {
40 case TargetOpcode::G_TRUNC:
41 case TargetOpcode::G_SEXT:
42 case TargetOpcode::G_ZEXT:
43 case TargetOpcode::G_ANYEXT:
60 assert(
MI.getOpcode() == TargetOpcode::G_ANYEXT);
64 Register SrcReg = lookThroughCopyInstrs(
MI.getOperand(1).getReg());
70 if (
MRI.getType(DstReg) ==
MRI.getType(TruncSrc))
74 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
75 UpdatedDefs.push_back(DstReg);
76 markInstAndDefDead(
MI, *
MRI.getVRegDef(SrcReg), DeadInsts);
88 UpdatedDefs.push_back(DstReg);
89 markInstAndDefDead(
MI, *ExtMI, DeadInsts);
94 auto *SrcMI =
MRI.getVRegDef(SrcReg);
95 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
96 const LLT DstTy =
MRI.getType(DstReg);
97 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
98 auto &CstVal = SrcMI->getOperand(1);
100 DstReg, CstVal.getCImm()->getValue().sext(DstTy.
getSizeInBits()));
101 UpdatedDefs.push_back(DstReg);
102 markInstAndDefDead(
MI, *SrcMI, DeadInsts);
114 assert(
MI.getOpcode() == TargetOpcode::G_ZEXT);
118 Register SrcReg = lookThroughCopyInstrs(
MI.getOperand(1).getReg());
126 LLT DstTy =
MRI.getType(DstReg);
127 if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
128 isConstantUnsupported(DstTy))
131 LLT SrcTy =
MRI.getType(SrcReg);
135 if (SextSrc && (DstTy !=
MRI.getType(SextSrc)))
136 SextSrc =
Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0);
137 if (TruncSrc && (DstTy !=
MRI.getType(TruncSrc)))
138 TruncSrc =
Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
139 Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc,
Mask);
140 markInstAndDefDead(
MI, *
MRI.getVRegDef(SrcReg), DeadInsts);
149 MI.getOperand(1).setReg(ZextSrc);
151 UpdatedDefs.push_back(DstReg);
152 markDefDead(
MI, *
MRI.getVRegDef(SrcReg), DeadInsts);
157 auto *SrcMI =
MRI.getVRegDef(SrcReg);
158 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
159 const LLT DstTy =
MRI.getType(DstReg);
160 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
161 auto &CstVal = SrcMI->getOperand(1);
163 DstReg, CstVal.getCImm()->getValue().zext(DstTy.
getSizeInBits()));
164 UpdatedDefs.push_back(DstReg);
165 markInstAndDefDead(
MI, *SrcMI, DeadInsts);
176 assert(
MI.getOpcode() == TargetOpcode::G_SEXT);
180 Register SrcReg = lookThroughCopyInstrs(
MI.getOperand(1).getReg());
185 LLT DstTy =
MRI.getType(DstReg);
186 if (isInstUnsupported({TargetOpcode::G_SEXT_INREG, {DstTy}}))
189 LLT SrcTy =
MRI.getType(SrcReg);
190 uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
191 if (DstTy !=
MRI.getType(TruncSrc))
192 TruncSrc =
Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
193 Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits);
194 markInstAndDefDead(
MI, *
MRI.getVRegDef(SrcReg), DeadInsts);
207 UpdatedDefs.push_back(DstReg);
208 markInstAndDefDead(
MI, *
MRI.getVRegDef(SrcReg), DeadInsts);
213 auto *SrcMI =
MRI.getVRegDef(SrcReg);
214 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
215 const LLT DstTy =
MRI.getType(DstReg);
216 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
217 auto &CstVal = SrcMI->getOperand(1);
219 DstReg, CstVal.getCImm()->getValue().sext(DstTy.
getSizeInBits()));
220 UpdatedDefs.push_back(DstReg);
221 markInstAndDefDead(
MI, *SrcMI, DeadInsts);
234 assert(
MI.getOpcode() == TargetOpcode::G_TRUNC);
238 Register SrcReg = lookThroughCopyInstrs(
MI.getOperand(1).getReg());
241 auto *SrcMI =
MRI.getVRegDef(SrcReg);
242 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
243 const LLT DstTy =
MRI.getType(DstReg);
244 if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
245 auto &CstVal = SrcMI->getOperand(1);
247 DstReg, CstVal.getCImm()->getValue().trunc(DstTy.
getSizeInBits()));
248 UpdatedDefs.push_back(DstReg);
249 markInstAndDefDead(
MI, *SrcMI, DeadInsts);
256 if (
auto *SrcMerge = dyn_cast<GMerge>(SrcMI)) {
257 const Register MergeSrcReg = SrcMerge->getSourceReg(0);
258 const LLT MergeSrcTy =
MRI.getType(MergeSrcReg);
259 const LLT DstTy =
MRI.getType(DstReg);
267 if (DstSize < MergeSrcSize) {
270 if (isInstUnsupported({TargetOpcode::G_TRUNC, {DstTy, MergeSrcTy}}))
273 LLVM_DEBUG(
dbgs() <<
"Combining G_TRUNC(G_MERGE_VALUES) to G_TRUNC: "
276 Builder.buildTrunc(DstReg, MergeSrcReg);
277 UpdatedDefs.push_back(DstReg);
278 }
else if (DstSize == MergeSrcSize) {
281 dbgs() <<
"Replacing G_TRUNC(G_MERGE_VALUES) with merge input: "
285 }
else if (DstSize % MergeSrcSize == 0) {
288 if (isInstUnsupported(
289 {TargetOpcode::G_MERGE_VALUES, {DstTy, MergeSrcTy}}))
293 dbgs() <<
"Combining G_TRUNC(G_MERGE_VALUES) to G_MERGE_VALUES: "
296 const unsigned NumSrcs = DstSize / MergeSrcSize;
297 assert(NumSrcs < SrcMI->getNumOperands() - 1 &&
298 "trunc(merge) should require less inputs than merge");
300 for (
unsigned i = 0;
i < NumSrcs; ++
i)
301 SrcRegs[
i] = SrcMerge->getSourceReg(
i);
303 Builder.buildMerge(DstReg, SrcRegs);
304 UpdatedDefs.push_back(DstReg);
310 markInstAndDefDead(
MI, *SrcMerge, DeadInsts);
322 Builder.buildTrunc(DstReg, TruncSrc);
323 UpdatedDefs.push_back(DstReg);
324 markInstAndDefDead(
MI, *
MRI.getVRegDef(TruncSrc), DeadInsts);
335 unsigned Opcode =
MI.getOpcode();
336 assert(Opcode == TargetOpcode::G_ANYEXT || Opcode == TargetOpcode::G_ZEXT ||
337 Opcode == TargetOpcode::G_SEXT);
340 MI.getOperand(1).getReg(),
MRI)) {
343 LLT DstTy =
MRI.getType(DstReg);
345 if (Opcode == TargetOpcode::G_ANYEXT) {
347 if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
350 Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, {DstReg}, {});
351 UpdatedDefs.push_back(DstReg);
355 if (isConstantUnsupported(DstTy))
358 Builder.buildConstant(DstReg, 0);
359 UpdatedDefs.push_back(DstReg);
362 markInstAndDefDead(
MI, *
DefMI, DeadInsts);
372 assert(
MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
374 const unsigned CastOpc = CastMI.
getOpcode();
376 if (!isArtifactCast(CastOpc))
379 const unsigned NumDefs =
MI.getNumOperands() - 1;
382 const LLT CastSrcTy =
MRI.getType(CastSrcReg);
383 const LLT DestTy =
MRI.getType(
MI.getOperand(0).getReg());
384 const LLT SrcTy =
MRI.getType(
MI.getOperand(NumDefs).getReg());
389 if (CastOpc == TargetOpcode::G_TRUNC) {
400 unsigned UnmergeNumElts =
405 if (isInstUnsupported(
406 {TargetOpcode::G_UNMERGE_VALUES, {UnmergeTy, CastSrcTy}}))
410 auto NewUnmerge =
Builder.buildUnmerge(UnmergeTy, CastSrcReg);
412 for (
unsigned I = 0;
I != NumDefs; ++
I) {
414 UpdatedDefs.push_back(DefReg);
415 Builder.buildTrunc(DefReg, NewUnmerge.getReg(
I));
418 markInstAndDefDead(
MI, CastMI, DeadInsts);
430 if (CastSrcSize % DestSize != 0)
434 if (isInstUnsupported(
435 {TargetOpcode::G_UNMERGE_VALUES, {DestTy, CastSrcTy}}))
440 const unsigned NewNumDefs = CastSrcSize / DestSize;
442 for (
unsigned Idx = 0; Idx < NewNumDefs; ++Idx) {
444 DstRegs[Idx] =
MI.getOperand(Idx).getReg();
446 DstRegs[Idx] =
MRI.createGenericVirtualRegister(DestTy);
451 Builder.buildUnmerge(DstRegs, CastSrcReg);
452 UpdatedDefs.
append(DstRegs.begin(), DstRegs.begin() + NewNumDefs);
453 markInstAndDefDead(
MI, CastMI, DeadInsts);
468 case TargetOpcode::G_BUILD_VECTOR:
469 case TargetOpcode::G_MERGE_VALUES:
496 case TargetOpcode::G_CONCAT_VECTORS: {
507 if (ConvertOp == TargetOpcode::G_TRUNC)
522 Builder.buildCopy(DstReg, SrcReg);
523 UpdatedDefs.push_back(DstReg);
528 for (
auto &
UseMI :
MRI.use_instructions(DstReg)) {
529 UseMIs.push_back(&
UseMI);
533 MRI.replaceRegWith(DstReg, SrcReg);
534 UpdatedDefs.push_back(SrcReg);
536 for (
auto *
UseMI : UseMIs)
544 if (
Def.getReg() == SearchDef)
575 unsigned SrcSize =
MRI.getType(Src1Reg).getSizeInBits();
578 unsigned StartSrcIdx = (StartBit / SrcSize) + 1;
580 unsigned InRegOffset = StartBit % SrcSize;
584 if (InRegOffset + Size > SrcSize)
588 if (InRegOffset == 0 && Size == SrcSize) {
589 CurrentBest = SrcReg;
590 return findValueFromDefImpl(SrcReg, 0, Size);
593 return findValueFromDefImpl(SrcReg, InRegOffset, Size);
607 unsigned SrcSize =
MRI.getType(Src1Reg).getSizeInBits();
610 unsigned StartSrcIdx = (StartBit / SrcSize) + 1;
612 unsigned InRegOffset = StartBit % SrcSize;
614 if (InRegOffset != 0)
621 if (Size > SrcSize) {
622 if (Size % SrcSize > 0)
625 unsigned NumSrcsUsed = Size / SrcSize;
630 LLT SrcTy =
MRI.getType(Src1Reg);
635 LI.
getAction({TargetOpcode::G_BUILD_VECTOR, {NewBVTy, SrcTy}});
640 for (
unsigned SrcIdx = StartSrcIdx; SrcIdx < StartSrcIdx + NumSrcsUsed;
642 NewSrcs.push_back(BV.
getReg(SrcIdx));
647 return BV.
getReg(StartSrcIdx);
657 assert(
MI.getOpcode() == TargetOpcode::G_INSERT);
660 Register ContainerSrcReg =
MI.getOperand(1).getReg();
661 Register InsertedReg =
MI.getOperand(2).getReg();
662 LLT InsertedRegTy =
MRI.getType(InsertedReg);
663 unsigned InsertOffset =
MI.getOperand(3).getImm();
701 unsigned InsertedEndBit = InsertOffset + InsertedRegTy.
getSizeInBits();
702 unsigned EndBit = StartBit + Size;
703 unsigned NewStartBit;
705 if (EndBit <= InsertOffset || InsertedEndBit <= StartBit) {
706 SrcRegToUse = ContainerSrcReg;
707 NewStartBit = StartBit;
708 return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
710 if (InsertOffset <= StartBit && EndBit <= InsertedEndBit) {
711 SrcRegToUse = InsertedReg;
712 NewStartBit = StartBit - InsertOffset;
713 if (NewStartBit == 0 &&
714 Size ==
MRI.getType(SrcRegToUse).getSizeInBits())
715 CurrentBest = SrcRegToUse;
716 return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
731 switch (
Def->getOpcode()) {
732 case TargetOpcode::G_CONCAT_VECTORS:
733 return findValueFromConcat(cast<GConcatVectors>(*
Def), StartBit, Size);
734 case TargetOpcode::G_UNMERGE_VALUES: {
735 unsigned DefStartBit = 0;
736 unsigned DefSize =
MRI.getType(DefReg).getSizeInBits();
737 for (
const auto &MO :
Def->defs()) {
738 if (MO.getReg() == DefReg)
740 DefStartBit += DefSize;
742 Register SrcReg =
Def->getOperand(
Def->getNumOperands() - 1).getReg();
744 findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
750 if (StartBit == 0 && Size == DefSize)
754 case TargetOpcode::G_BUILD_VECTOR:
755 return findValueFromBuildVector(cast<GBuildVector>(*
Def), StartBit,
757 case TargetOpcode::G_INSERT:
758 return findValueFromInsert(*
Def, StartBit, Size);
776 Register FoundReg = findValueFromDefImpl(DefReg, StartBit, Size);
777 return FoundReg != DefReg ? FoundReg :
Register();
785 unsigned NumDefs =
MI.getNumDefs();
786 LLT DestTy =
MRI.getType(
MI.getReg(0));
789 for (
unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
791 if (
MRI.use_nodbg_empty(DefReg)) {
792 DeadDefs[DefIdx] =
true;
798 if (
MRI.getType(FoundVal) != DestTy)
805 MI.getOperand(DefIdx).setReg(DefReg);
807 DeadDefs[DefIdx] =
true;
809 return DeadDefs.
all();
817 unsigned NumDefs =
MI.getNumDefs();
823 LLT OpTy =
MRI.getType(SrcReg);
824 LLT DestTy =
MRI.getType(
MI.getReg(0));
831 markInstAndDefDead(
MI, *SrcDef, DeadInsts, SrcDefIdx);
835 if (
auto *SrcUnmerge = dyn_cast<GUnmerge>(SrcDef)) {
841 Register SrcUnmergeSrc = SrcUnmerge->getSourceReg();
842 LLT SrcUnmergeSrcTy =
MRI.getType(SrcUnmergeSrc);
848 {TargetOpcode::G_UNMERGE_VALUES, {OpTy, SrcUnmergeSrcTy}});
849 switch (ActionStep.
Action) {
862 auto NewUnmerge =
Builder.buildUnmerge(DestTy, SrcUnmergeSrc);
867 for (
unsigned I = 0;
I != NumDefs; ++
I) {
873 markInstAndDefDead(
MI, *SrcUnmerge, DeadInsts, SrcDefIdx);
878 unsigned ConvertOp = 0;
882 if (isArtifactCast(
SrcOp)) {
888 ConvertOp, OpTy, DestTy)) {
896 if (NumMergeRegs < NumDefs) {
897 if (NumDefs % NumMergeRegs != 0)
908 const unsigned NewNumDefs = NumDefs / NumMergeRegs;
909 for (
unsigned Idx = 0; Idx < NumMergeRegs; ++Idx) {
911 for (
unsigned j = 0, DefIdx = Idx * NewNumDefs;
j < NewNumDefs;
913 DstRegs.push_back(
MI.getReg(DefIdx));
921 LLT MergeEltTy = MergeSrcTy.
divide(NewNumDefs);
938 for (
unsigned k = 0; k < NewNumDefs; ++k)
939 TmpRegs[k] =
MRI.createGenericVirtualRegister(MergeEltTy);
943 for (
unsigned k = 0; k < NewNumDefs; ++k)
944 Builder.buildInstr(ConvertOp, {DstRegs[k]}, {TmpRegs[k]});
948 UpdatedDefs.
append(DstRegs.begin(), DstRegs.end());
951 }
else if (NumMergeRegs > NumDefs) {
952 if (ConvertOp != 0 || NumMergeRegs % NumDefs != 0)
963 const unsigned NumRegs = NumMergeRegs / NumDefs;
964 for (
unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
966 for (
unsigned j = 0, Idx = NumRegs * DefIdx + 1;
j < NumRegs;
971 Builder.buildMerge(DefReg, Regs);
972 UpdatedDefs.push_back(DefReg);
978 if (!ConvertOp && DestTy != MergeSrcTy)
979 ConvertOp = TargetOpcode::G_BITCAST;
984 for (
unsigned Idx = 0; Idx < NumDefs; ++Idx) {
985 Register DefReg =
MI.getOperand(Idx).getReg();
988 if (!
MRI.use_empty(DefReg)) {
989 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc});
990 UpdatedDefs.push_back(DefReg);
994 markInstAndDefDead(
MI, *MergeI, DeadInsts);
998 assert(DestTy == MergeSrcTy &&
999 "Bitcast and the other kinds of conversions should "
1000 "have happened earlier");
1003 for (
unsigned Idx = 0; Idx < NumDefs; ++Idx) {
1004 Register DstReg =
MI.getOperand(Idx).getReg();
1011 markInstAndDefDead(
MI, *MergeI, DeadInsts);
1018 assert(
MI.getOpcode() == TargetOpcode::G_EXTRACT);
1032 Register SrcReg = lookThroughCopyInstrs(
MI.getOperand(1).getReg());
1034 if (!MergeI || !isa<GMergeLikeOp>(MergeI))
1038 LLT DstTy =
MRI.getType(DstReg);
1039 LLT SrcTy =
MRI.getType(SrcReg);
1043 unsigned Offset =
MI.getOperand(2).getImm();
1045 unsigned MergeSrcSize = SrcTy.
getSizeInBits() / NumMergeSrcs;
1046 unsigned MergeSrcIdx = Offset / MergeSrcSize;
1049 unsigned EndMergeSrcIdx = (Offset + ExtractDstSize - 1) / MergeSrcSize;
1052 if (MergeSrcIdx != EndMergeSrcIdx)
1058 Offset - MergeSrcIdx * MergeSrcSize);
1059 UpdatedDefs.push_back(DstReg);
1060 markInstAndDefDead(
MI, *MergeI, DeadInsts);
1074 if (!DeadInsts.empty())
1075 deleteMarkedDeadInsts(DeadInsts, WrapperObserver);
1082 bool Changed =
false;
1083 switch (
MI.getOpcode()) {
1086 case TargetOpcode::G_ANYEXT:
1089 case TargetOpcode::G_ZEXT:
1092 case TargetOpcode::G_SEXT:
1095 case TargetOpcode::G_UNMERGE_VALUES:
1097 UpdatedDefs, WrapperObserver);
1099 case TargetOpcode::G_MERGE_VALUES:
1100 case TargetOpcode::G_BUILD_VECTOR:
1101 case TargetOpcode::G_CONCAT_VECTORS:
1105 if (U.getOpcode() == TargetOpcode::G_UNMERGE_VALUES ||
1106 U.getOpcode() == TargetOpcode::G_TRUNC) {
1107 UpdatedDefs.push_back(
MI.getOperand(0).getReg());
1112 case TargetOpcode::G_EXTRACT:
1115 case TargetOpcode::G_TRUNC:
1122 UpdatedDefs.push_back(
MI.getOperand(0).getReg());
1130 while (!UpdatedDefs.empty()) {
1134 switch (
Use.getOpcode()) {
1136 case TargetOpcode::G_ANYEXT:
1137 case TargetOpcode::G_ZEXT:
1138 case TargetOpcode::G_SEXT:
1139 case TargetOpcode::G_UNMERGE_VALUES:
1140 case TargetOpcode::G_EXTRACT:
1141 case TargetOpcode::G_TRUNC:
1145 case TargetOpcode::COPY: {
1147 if (Copy.isVirtual())
1148 UpdatedDefs.push_back(Copy);
1164 switch (
MI.getOpcode()) {
1165 case TargetOpcode::COPY:
1166 case TargetOpcode::G_TRUNC:
1167 case TargetOpcode::G_ZEXT:
1168 case TargetOpcode::G_ANYEXT:
1169 case TargetOpcode::G_SEXT:
1170 case TargetOpcode::G_EXTRACT:
1171 return MI.getOperand(1).getReg();
1172 case TargetOpcode::G_UNMERGE_VALUES:
1173 return MI.getOperand(
MI.getNumOperands() - 1).getReg();
1184 void markDefDead(MachineInstr &
MI, MachineInstr &
DefMI,
1185 SmallVectorImpl<MachineInstr *> &DeadInsts,
1186 unsigned DefIdx = 0) {
1196 MachineInstr *PrevMI = &
MI;
1197 while (PrevMI != &
DefMI) {
1198 Register PrevRegSrc = getArtifactSrcReg(*PrevMI);
1200 MachineInstr *TmpDef =
MRI.getVRegDef(PrevRegSrc);
1201 if (
MRI.hasOneUse(PrevRegSrc)) {
1202 if (TmpDef != &
DefMI) {
1203 assert((TmpDef->getOpcode() == TargetOpcode::COPY ||
1204 isArtifactCast(TmpDef->getOpcode())) &&
1205 "Expecting copy or artifact cast here");
1207 DeadInsts.push_back(TmpDef);
1214 if (PrevMI == &
DefMI) {
1217 for (MachineOperand &
Def :
DefMI.defs()) {
1219 if (!
MRI.use_empty(
Def.getReg())) {
1224 if (!
MRI.hasOneUse(
DefMI.getOperand(DefIdx).getReg()))
1232 DeadInsts.push_back(&
DefMI);
1241 void markInstAndDefDead(MachineInstr &
MI, MachineInstr &
DefMI,
1242 SmallVectorImpl<MachineInstr *> &DeadInsts,
1243 unsigned DefIdx = 0) {
1244 DeadInsts.push_back(&
MI);
1245 markDefDead(
MI,
DefMI, DeadInsts, DefIdx);
1254 void deleteMarkedDeadInsts(SmallVectorImpl<MachineInstr *> &DeadInsts,
1255 GISelObserverWrapper &WrapperObserver) {
1256 for (
auto *DeadMI : DeadInsts) {
1258 WrapperObserver.erasingInstr(*DeadMI);
1259 DeadMI->eraseFromParent();
1266 bool isInstUnsupported(
const LegalityQuery &Query)
const {
1267 using namespace LegalizeActions;
1272 bool isInstLegal(
const LegalityQuery &Query)
const {
1276 bool isConstantUnsupported(LLT Ty)
const {
1278 return isInstUnsupported({TargetOpcode::G_CONSTANT, {Ty}});
1280 LLT EltTy = Ty.getElementType();
1281 return isInstUnsupported({TargetOpcode::G_CONSTANT, {EltTy}}) ||
1282 isInstUnsupported({TargetOpcode::G_BUILD_VECTOR, {Ty, EltTy}});
1292 if (
MRI.getType(TmpReg).isValid())
1303 #endif // LLVM_CODEGEN_GLOBALISEL_LEGALIZATIONARTIFACTCOMBINER_H