LLVM  14.0.0git
M68kInstrInfo.h
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1 //===-- M68kInstrInfo.h - M68k Instruction Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the M68k implementation of the TargetInstrInfo class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
15 #define LLVM_LIB_TARGET_M68K_M68KINSTRINFO_H
16 
17 #include "M68k.h"
18 #include "M68kRegisterInfo.h"
19 
21 
24 
25 #define GET_INSTRINFO_HEADER
26 #include "M68kGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class M68kSubtarget;
31 
32 namespace M68k {
33 // These MUST be kept in sync with codes definitions in M68kInstrInfo.td
34 enum CondCode {
35  COND_T = 0, // True
36  COND_F = 1, // False
37  COND_HI = 2, // High
38  COND_LS = 3, // Less or Same
39  COND_CC = 4, // Carry Clear
40  COND_CS = 5, // Carry Set
41  COND_NE = 6, // Not Equal
42  COND_EQ = 7, // Equal
43  COND_VC = 8, // Overflow Clear
44  COND_VS = 9, // Overflow Set
45  COND_PL = 10, // Plus
46  COND_MI = 11, // Minus
47  COND_GE = 12, // Greater or Equal
48  COND_LT = 13, // Less Than
49  COND_GT = 14, // Greater Than
50  COND_LE = 15, // Less or Equal
53 };
54 
55 // FIXME would be nice tablegen to generate these predicates and converters
56 // mb tag based
57 
59  switch (CC) {
60  default:
61  llvm_unreachable("Illegal condition code!");
62  case M68k::COND_T:
63  return M68k::COND_F;
64  case M68k::COND_F:
65  return M68k::COND_T;
66  case M68k::COND_HI:
67  return M68k::COND_LS;
68  case M68k::COND_LS:
69  return M68k::COND_HI;
70  case M68k::COND_CC:
71  return M68k::COND_CS;
72  case M68k::COND_CS:
73  return M68k::COND_CC;
74  case M68k::COND_NE:
75  return M68k::COND_EQ;
76  case M68k::COND_EQ:
77  return M68k::COND_NE;
78  case M68k::COND_VC:
79  return M68k::COND_VS;
80  case M68k::COND_VS:
81  return M68k::COND_VC;
82  case M68k::COND_PL:
83  return M68k::COND_MI;
84  case M68k::COND_MI:
85  return M68k::COND_PL;
86  case M68k::COND_GE:
87  return M68k::COND_LT;
88  case M68k::COND_LT:
89  return M68k::COND_GE;
90  case M68k::COND_GT:
91  return M68k::COND_LE;
92  case M68k::COND_LE:
93  return M68k::COND_GT;
94  }
95 }
96 
97 static inline unsigned GetCondBranchFromCond(M68k::CondCode CC) {
98  switch (CC) {
99  default:
100  llvm_unreachable("Illegal condition code!");
101  case M68k::COND_EQ:
102  return M68k::Beq8;
103  case M68k::COND_NE:
104  return M68k::Bne8;
105  case M68k::COND_LT:
106  return M68k::Blt8;
107  case M68k::COND_LE:
108  return M68k::Ble8;
109  case M68k::COND_GT:
110  return M68k::Bgt8;
111  case M68k::COND_GE:
112  return M68k::Bge8;
113  case M68k::COND_CS:
114  return M68k::Bcs8;
115  case M68k::COND_LS:
116  return M68k::Bls8;
117  case M68k::COND_HI:
118  return M68k::Bhi8;
119  case M68k::COND_CC:
120  return M68k::Bcc8;
121  case M68k::COND_MI:
122  return M68k::Bmi8;
123  case M68k::COND_PL:
124  return M68k::Bpl8;
125  case M68k::COND_VS:
126  return M68k::Bvs8;
127  case M68k::COND_VC:
128  return M68k::Bvc8;
129  }
130 }
131 
132 static inline M68k::CondCode GetCondFromBranchOpc(unsigned Opcode) {
133  switch (Opcode) {
134  default:
135  return M68k::COND_INVALID;
136  case M68k::Beq8:
137  return M68k::COND_EQ;
138  case M68k::Bne8:
139  return M68k::COND_NE;
140  case M68k::Blt8:
141  return M68k::COND_LT;
142  case M68k::Ble8:
143  return M68k::COND_LE;
144  case M68k::Bgt8:
145  return M68k::COND_GT;
146  case M68k::Bge8:
147  return M68k::COND_GE;
148  case M68k::Bcs8:
149  return M68k::COND_CS;
150  case M68k::Bls8:
151  return M68k::COND_LS;
152  case M68k::Bhi8:
153  return M68k::COND_HI;
154  case M68k::Bcc8:
155  return M68k::COND_CC;
156  case M68k::Bmi8:
157  return M68k::COND_MI;
158  case M68k::Bpl8:
159  return M68k::COND_PL;
160  case M68k::Bvs8:
161  return M68k::COND_VS;
162  case M68k::Bvc8:
163  return M68k::COND_VC;
164  }
165 }
166 
167 static inline unsigned IsCMP(unsigned Op) {
168  switch (Op) {
169  default:
170  return false;
171  case M68k::CMP8dd:
172  case M68k::CMP8df:
173  case M68k::CMP8di:
174  case M68k::CMP8dj:
175  case M68k::CMP8dp:
176  case M68k::CMP16dr:
177  case M68k::CMP16df:
178  case M68k::CMP16di:
179  case M68k::CMP16dj:
180  case M68k::CMP16dp:
181  return true;
182  }
183 }
184 
185 static inline bool IsSETCC(unsigned SETCC) {
186  switch (SETCC) {
187  default:
188  return false;
189  case M68k::SETd8eq:
190  case M68k::SETd8ne:
191  case M68k::SETd8lt:
192  case M68k::SETd8ge:
193  case M68k::SETd8le:
194  case M68k::SETd8gt:
195  case M68k::SETd8cs:
196  case M68k::SETd8cc:
197  case M68k::SETd8ls:
198  case M68k::SETd8hi:
199  case M68k::SETd8pl:
200  case M68k::SETd8mi:
201  case M68k::SETd8vc:
202  case M68k::SETd8vs:
203  case M68k::SETj8eq:
204  case M68k::SETj8ne:
205  case M68k::SETj8lt:
206  case M68k::SETj8ge:
207  case M68k::SETj8le:
208  case M68k::SETj8gt:
209  case M68k::SETj8cs:
210  case M68k::SETj8cc:
211  case M68k::SETj8ls:
212  case M68k::SETj8hi:
213  case M68k::SETj8pl:
214  case M68k::SETj8mi:
215  case M68k::SETj8vc:
216  case M68k::SETj8vs:
217  case M68k::SETp8eq:
218  case M68k::SETp8ne:
219  case M68k::SETp8lt:
220  case M68k::SETp8ge:
221  case M68k::SETp8le:
222  case M68k::SETp8gt:
223  case M68k::SETp8cs:
224  case M68k::SETp8cc:
225  case M68k::SETp8ls:
226  case M68k::SETp8hi:
227  case M68k::SETp8pl:
228  case M68k::SETp8mi:
229  case M68k::SETp8vc:
230  case M68k::SETp8vs:
231  return true;
232  }
233 }
234 
235 } // namespace M68k
236 
238  virtual void anchor();
239 
240 protected:
243 
244 public:
245  explicit M68kInstrInfo(const M68kSubtarget &STI);
246 
247  static const M68kInstrInfo *create(M68kSubtarget &STI);
248 
249  /// TargetInstrInfo is a superset of MRegister info. As such, whenever a
250  /// client has an instance of instruction info, it should always be able to
251  /// get register info as well (through this method).
252  const M68kRegisterInfo &getRegisterInfo() const { return RI; };
253 
255  MachineBasicBlock *&FBB,
257  bool AllowModify) const override;
258 
260  MachineBasicBlock *&FBB,
262  bool AllowModify) const;
263 
265  int *BytesRemoved = nullptr) const override;
266 
269  const DebugLoc &DL,
270  int *BytesAdded = nullptr) const override;
271 
273  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
274  bool KillSrc) const override;
275 
276  bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
277  unsigned &Size, unsigned &Offset,
278  const MachineFunction &MF) const override;
279 
282  bool IsKill, int FrameIndex,
283  const TargetRegisterClass *RC,
284  const TargetRegisterInfo *TRI) const override;
285 
288  int FrameIndex, const TargetRegisterClass *RC,
289  const TargetRegisterInfo *TRI) const override;
290 
291  bool expandPostRAPseudo(MachineInstr &MI) const override;
292 
293  bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override;
294 
295  /// Add appropriate SExt nodes
297  DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
298 
299  /// Add appropriate ZExt nodes
301  DebugLoc DL, unsigned Reg, MVT From, MVT To) const;
302 
303  /// Move across register classes without extension
304  bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const;
305 
306  /// Move from register and extend
307  bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst,
308  MVT MVTSrc) const;
309 
310  /// Move from memory and extend
311  bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned,
312  const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
313 
314  /// Push/Pop to/from stack
315  bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
316  bool IsPush) const;
317 
318  /// Moves to/from CCR
319  bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const;
320 
321  /// Expand all MOVEM pseudos into real MOVEMs
322  bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
323  bool IsRM) const;
324 
325  /// Return a virtual register initialized with the the global base register
326  /// value. Output instructions required to initialize the register in the
327  /// function entry block, if necessary.
328  unsigned getGlobalBaseReg(MachineFunction *MF) const;
329 
330  std::pair<unsigned, unsigned>
331  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
332 
335 };
336 
337 } // namespace llvm
338 
339 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::M68kInstrInfo::Subtarget
const M68kSubtarget & Subtarget
Definition: M68kInstrInfo.h:241
llvm::M68k::CondCode
CondCode
Definition: M68kInstrInfo.h:34
llvm::M68kInstrInfo::AddZExt
void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate ZExt nodes.
Definition: M68kInstrInfo.cpp:329
llvm::M68kInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: M68kInstrInfo.cpp:279
llvm::M68k::COND_PL
@ COND_PL
Definition: M68kInstrInfo.h:45
llvm::M68kInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: M68kInstrInfo.cpp:755
llvm::M68k::COND_GT
@ COND_GT
Definition: M68kInstrInfo.h:49
llvm::M68kInstrInfo::ExpandMOVX_RR
bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const
Move across register classes without extension.
Definition: M68kInstrInfo.cpp:348
llvm::M68k::COND_NE
@ COND_NE
Definition: M68kInstrInfo.h:41
llvm::M68kInstrInfo::ExpandMOVEM
bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsRM) const
Expand all MOVEM pseudos into real MOVEMs.
Definition: M68kInstrInfo.cpp:505
llvm::M68kInstrInfo::ExpandMOVSZX_RR
bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst, MVT MVTSrc) const
Move from register and extend.
Definition: M68kInstrInfo.cpp:386
llvm::M68kRegisterInfo
Definition: M68kRegisterInfo.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::M68kInstrInfo::ExpandMOVSZX_RM
bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned, const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const
Move from memory and extend.
Definition: M68kInstrInfo.cpp:435
TargetInstrInfo.h
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::M68kInstrInfo::RI
const M68kRegisterInfo RI
Definition: M68kInstrInfo.h:242
llvm::M68k::COND_VS
@ COND_VS
Definition: M68kInstrInfo.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
M68k.h
llvm::M68k::COND_GE
@ COND_GE
Definition: M68kInstrInfo.h:47
llvm::M68kInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: M68kInstrInfo.cpp:811
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
M68kGenInstrInfo
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::M68k::LAST_VALID_COND
@ LAST_VALID_COND
Definition: M68kInstrInfo.h:51
llvm::M68k::COND_F
@ COND_F
Definition: M68kInstrInfo.h:36
llvm::M68kInstrInfo::isPCRelRegisterOperandLegal
bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override
Definition: M68kInstrInfo.cpp:601
llvm::M68k::COND_T
@ COND_T
Definition: M68kInstrInfo.h:35
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::M68k::GetCondFromBranchOpc
static M68k::CondCode GetCondFromBranchOpc(unsigned Opcode)
Definition: M68kInstrInfo.h:132
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::M68kInstrInfo::create
static const M68kInstrInfo * create(M68kSubtarget &STI)
llvm::M68kInstrInfo::ExpandPUSH_POP
bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsPush) const
Push/Pop to/from stack.
Definition: M68kInstrInfo.cpp:472
llvm::M68k::COND_HI
@ COND_HI
Definition: M68kInstrInfo.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::M68kInstrInfo::getStackSlotRange
bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override
Definition: M68kInstrInfo.cpp:745
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::M68k::GetCondBranchFromCond
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
Definition: M68kInstrInfo.h:97
llvm::M68k::COND_INVALID
@ COND_INVALID
Definition: M68kInstrInfo.h:52
llvm::M68k::COND_LT
@ COND_LT
Definition: M68kInstrInfo.h:48
llvm::M68k::COND_CC
@ COND_CC
Definition: M68kInstrInfo.h:39
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::M68k::COND_VC
@ COND_VC
Definition: M68kInstrInfo.h:43
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::M68kInstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
Return a virtual register initialized with the the global base register value.
Definition: M68kInstrInfo.cpp:789
llvm::M68kInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: M68kInstrInfo.cpp:640
llvm::M68kInstrInfo::AnalyzeBranchImpl
bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: M68kInstrInfo.cpp:82
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::M68kInstrInfo
Definition: M68kInstrInfo.h:237
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::M68k::COND_LS
@ COND_LS
Definition: M68kInstrInfo.h:38
llvm::M68kInstrInfo::ExpandCCR
bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const
Moves to/from CCR.
Definition: M68kInstrInfo.cpp:488
llvm::M68kInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: M68kInstrInfo.cpp:771
llvm::M68k::IsSETCC
static bool IsSETCC(unsigned SETCC)
Definition: M68kInstrInfo.h:185
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::M68kInstrInfo::M68kInstrInfo
M68kInstrInfo(const M68kSubtarget &STI)
Definition: M68kInstrInfo.cpp:42
llvm::M68kInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: M68kInstrInfo.cpp:248
llvm::M68k::COND_MI
@ COND_MI
Definition: M68kInstrInfo.h:46
llvm::M68kInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: M68kInstrInfo.cpp:256
MachineInstrBuilder.h
llvm::M68kInstrInfo::getRegisterInfo
const M68kRegisterInfo & getRegisterInfo() const
TargetInstrInfo is a superset of MRegister info.
Definition: M68kInstrInfo.h:252
llvm::M68k::COND_EQ
@ COND_EQ
Definition: M68kInstrInfo.h:42
M68kBaseInfo.h
M68kRegisterInfo.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::M68kInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: M68kInstrInfo.cpp:816
llvm::M68kInstrInfo::AddSExt
void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate SExt nodes.
Definition: M68kInstrInfo.cpp:312
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::M68kInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: M68kInstrInfo.cpp:574
llvm::M68k::COND_CS
@ COND_CS
Definition: M68kInstrInfo.h:40
llvm::M68k::COND_LE
@ COND_LE
Definition: M68kInstrInfo.h:50
llvm::M68k::IsCMP
static unsigned IsCMP(unsigned Op)
Definition: M68kInstrInfo.h:167
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::M68k::GetOppositeBranchCondition
static M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC)
Definition: M68kInstrInfo.h:58