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26 #define DEBUG_TYPE "ppc-call-lowering"
38 "Return value without a vreg");
57 const auto &
DL =
F.getParent()->getDataLayout();
58 auto &TLI = *getTLI<PPCTargetLowering>();
63 for (
const auto &
Arg :
F.args()) {
64 if (
DL.getTypeStoreSize(
Arg.getType()).isZero())
74 TLI.ccAssignFnForCall(
F.getCallingConv(),
false,
F.isVarArg());
78 MIRBuilder,
F.getCallingConv(),
82 void PPCIncomingValueHandler::assignValueToReg(
Register ValVReg,
85 markPhysRegUsed(PhysReg);
86 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
89 void PPCIncomingValueHandler::assignValueToAddress(
Register ValVReg,
105 Register PPCIncomingValueHandler::getStackAddress(
uint64_t Size, int64_t Offset,
109 const bool IsImmutable = !Flags.
isByVal();
110 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
121 void FormalArgHandler::markPhysRegUsed(
unsigned PhysReg) {
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
bool empty() const
empty - Check if the array is empty.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineFunction & getMF()
Getter for the function we currently build.
Analysis containing CSE Info
Register getReg(unsigned Idx) const
Get the register for the operand index.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Helper class to build MachineInstr.
This class contains a discriminated union of information about pointers in memory operands,...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
PPCCallLowering(const PPCTargetLowering &TLI)
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
MachineIRBuilder & MIRBuilder
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
size_t size() const
size - Get the array size.
Align max(MaybeAlign Lhs, Align Rhs)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
LLVM Value Representation.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const