LLVM  16.0.0git
PPCCallLowering.cpp
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1 //===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCCallLowering.h"
16 #include "PPCCallingConv.h"
17 #include "PPCISelLowering.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
25 #include "llvm/Support/Debug.h"
26 
27 #define DEBUG_TYPE "ppc-call-lowering"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
34  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
36  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
37 
38  void assignValueToReg(Register ValVReg, Register PhysReg,
39  CCValAssign VA) override;
40  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
41  MachinePointerInfo &MPO, CCValAssign &VA) override;
42  Register getStackAddress(uint64_t Size, int64_t Offset,
43  MachinePointerInfo &MPO,
44  ISD::ArgFlagsTy Flags) override;
45 
47 };
48 } // namespace
49 
50 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
51  CCValAssign VA) {
52  MIB.addUse(PhysReg, RegState::Implicit);
53  Register ExtReg = extendRegister(ValVReg, VA);
54  MIRBuilder.buildCopy(PhysReg, ExtReg);
55 }
56 
57 void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
58  LLT MemTy,
59  MachinePointerInfo &MPO,
60  CCValAssign &VA) {
61  llvm_unreachable("unimplemented");
62 }
63 
64 Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset,
65  MachinePointerInfo &MPO,
66  ISD::ArgFlagsTy Flags) {
67  llvm_unreachable("unimplemented");
68 }
69 
71  : CallLowering(&TLI) {}
72 
74  const Value *Val, ArrayRef<Register> VRegs,
76  Register SwiftErrorVReg) const {
77  auto MIB = MIRBuilder.buildInstrNoInsert(PPC::BLR8);
78  bool Success = true;
79  MachineFunction &MF = MIRBuilder.getMF();
80  const Function &F = MF.getFunction();
82  auto &DL = F.getParent()->getDataLayout();
83  if (!VRegs.empty()) {
84  // Setup the information about the return value.
85  ArgInfo OrigArg{VRegs, Val->getType(), 0};
87 
88  // Split the return value into consecutive registers if needed.
89  SmallVector<ArgInfo, 8> SplitArgs;
90  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
91 
92  // Use the calling convention callback to determine type and location of
93  // return value.
94  OutgoingValueAssigner ArgAssigner(RetCC_PPC);
95 
96  // Handler to move the return value into the correct location.
97  OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
98 
99  // Iterate over all return values, and move them to the assigned location.
100  Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
101  MIRBuilder, F.getCallingConv(),
102  F.isVarArg());
103  }
104  MIRBuilder.insertInstr(MIB);
105  return Success;
106 }
107 
109  CallLoweringInfo &Info) const {
110  return false;
111 }
112 
114  const Function &F,
116  FunctionLoweringInfo &FLI) const {
117  MachineFunction &MF = MIRBuilder.getMF();
119  const auto &DL = F.getParent()->getDataLayout();
120  auto &TLI = *getTLI<PPCTargetLowering>();
121 
122  // Loop over each arg, set flags and split to single value types
123  SmallVector<ArgInfo, 8> SplitArgs;
124  unsigned I = 0;
125  for (const auto &Arg : F.args()) {
126  if (DL.getTypeStoreSize(Arg.getType()).isZero())
127  continue;
128 
129  ArgInfo OrigArg{VRegs[I], Arg, I};
131  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
132  ++I;
133  }
134 
135  CCAssignFn *AssignFn =
136  TLI.ccAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
137  IncomingValueAssigner ArgAssigner(AssignFn);
138  FormalArgHandler ArgHandler(MIRBuilder, MRI);
139  return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
140  MIRBuilder, F.getCallingConv(),
141  F.isVarArg());
142 }
143 
144 void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
145  Register PhysReg,
146  CCValAssign VA) {
147  markPhysRegUsed(PhysReg);
148  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
149 }
150 
151 void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
152  Register Addr, LLT MemTy,
153  MachinePointerInfo &MPO,
154  CCValAssign &VA) {
155  // define a lambda expression to load value
156  auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
157  LLT MemTy, const DstOp &Res, Register Addr) {
159  auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
160  inferAlignFromPtrInfo(MF, MPO));
161  return MIRBuilder.buildLoad(Res, Addr, *MMO);
162  };
163 
164  BuildLoad(MIRBuilder, MPO, MemTy, ValVReg, Addr);
165 }
166 
167 Register PPCIncomingValueHandler::getStackAddress(uint64_t Size, int64_t Offset,
168  MachinePointerInfo &MPO,
169  ISD::ArgFlagsTy Flags) {
170  auto &MFI = MIRBuilder.getMF().getFrameInfo();
171  const bool IsImmutable = !Flags.isByVal();
172  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
174 
175  // Build Frame Index based on whether the machine is 32-bit or 64-bit
178  MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
179  StackUsed = std::max(StackUsed, Size + Offset);
180  return AddrReg.getReg(0);
181 }
182 
183 void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) {
184  MIRBuilder.getMRI()->addLiveIn(PhysReg);
185  MIRBuilder.getMBB().addLiveIn(PhysReg);
186 }
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PPCCallLowering.h
CallLowering.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:289
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::PPCCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: PPCCallLowering.cpp:108
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:333
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:250
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:39
MachineIRBuilder.h
llvm::PPCIncomingValueHandler::StackUsed
uint64_t StackUsed
Definition: PPCCallLowering.h:45
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
F
#define F(x, y, z)
Definition: MD5.cpp:55
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
PPCSubtarget.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::codeview::EncodedFramePtrReg::FramePtr
@ FramePtr
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:903
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::FormalArgHandler
Definition: M68kCallLowering.h:66
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:223
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:271
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:435
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
TargetCallingConv.h
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:712
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:562
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:296
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::PPCTargetLowering
Definition: PPCISelLowering.h:749
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RetCC_PPC
bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCCallLowering::PPCCallLowering
PPCCallLowering(const PPCTargetLowering &TLI)
Definition: PPCCallLowering.cpp:70
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::PPCCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: PPCCallLowering.cpp:73
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:145
PPCCallingConv.h
llvm::PPCCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: PPCCallLowering.cpp:113
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
CallingConvLower.h
MachineFrameInfo.h
Success
#define Success
Definition: AArch64Disassembler.cpp:295
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:217
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:230
PPCISelLowering.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::DstOp
Definition: MachineIRBuilder.h:67
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::omp::RTLDependInfoFields::Flags
@ Flags
llvm::CallLowering
Definition: CallLowering.h:44
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:437
PPCTargetMachine.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:192