LLVM 18.0.0git
PPCCallLowering.cpp
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1//===-- PPCCallLowering.h - Call lowering for GlobalISel -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12///
13//===----------------------------------------------------------------------===//
14
15#include "PPCCallLowering.h"
16#include "PPCCallingConv.h"
17#include "PPCISelLowering.h"
18#include "PPCSubtarget.h"
19#include "PPCTargetMachine.h"
25#include "llvm/Support/Debug.h"
26
27#define DEBUG_TYPE "ppc-call-lowering"
28
29using namespace llvm;
30
31namespace {
32
33struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
34 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
36 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
37
38 void assignValueToReg(Register ValVReg, Register PhysReg,
39 const CCValAssign &VA) override;
40 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
41 const MachinePointerInfo &MPO,
42 const CCValAssign &VA) override;
45 ISD::ArgFlagsTy Flags) override;
46
48};
49} // namespace
50
51void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
52 const CCValAssign &VA) {
53 MIB.addUse(PhysReg, RegState::Implicit);
54 Register ExtReg = extendRegister(ValVReg, VA);
55 MIRBuilder.buildCopy(PhysReg, ExtReg);
56}
57
58void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
59 LLT MemTy,
60 const MachinePointerInfo &MPO,
61 const CCValAssign &VA) {
62 llvm_unreachable("unimplemented");
63}
64
65Register OutgoingArgHandler::getStackAddress(uint64_t Size, int64_t Offset,
67 ISD::ArgFlagsTy Flags) {
68 llvm_unreachable("unimplemented");
69}
70
72 : CallLowering(&TLI) {}
73
75 const Value *Val, ArrayRef<Register> VRegs,
77 Register SwiftErrorVReg) const {
78 auto MIB = MIRBuilder.buildInstrNoInsert(PPC::BLR8);
79 bool Success = true;
80 MachineFunction &MF = MIRBuilder.getMF();
81 const Function &F = MF.getFunction();
83 auto &DL = F.getParent()->getDataLayout();
84 if (!VRegs.empty()) {
85 // Setup the information about the return value.
86 ArgInfo OrigArg{VRegs, Val->getType(), 0};
88
89 // Split the return value into consecutive registers if needed.
91 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
92
93 // Use the calling convention callback to determine type and location of
94 // return value.
96
97 // Handler to move the return value into the correct location.
98 OutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
99
100 // Iterate over all return values, and move them to the assigned location.
101 Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
102 MIRBuilder, F.getCallingConv(),
103 F.isVarArg());
104 }
105 MIRBuilder.insertInstr(MIB);
106 return Success;
107}
108
110 CallLoweringInfo &Info) const {
111 return false;
112}
113
115 const Function &F,
117 FunctionLoweringInfo &FLI) const {
118 MachineFunction &MF = MIRBuilder.getMF();
120 const auto &DL = F.getParent()->getDataLayout();
121 auto &TLI = *getTLI<PPCTargetLowering>();
122
123 // Loop over each arg, set flags and split to single value types
124 SmallVector<ArgInfo, 8> SplitArgs;
125 unsigned I = 0;
126 for (const auto &Arg : F.args()) {
127 if (DL.getTypeStoreSize(Arg.getType()).isZero())
128 continue;
129
130 ArgInfo OrigArg{VRegs[I], Arg, I};
132 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
133 ++I;
134 }
135
136 CCAssignFn *AssignFn =
137 TLI.ccAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
138 IncomingValueAssigner ArgAssigner(AssignFn);
139 FormalArgHandler ArgHandler(MIRBuilder, MRI);
140 return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
141 MIRBuilder, F.getCallingConv(),
142 F.isVarArg());
143}
144
145void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
146 Register PhysReg,
147 const CCValAssign &VA) {
148 markPhysRegUsed(PhysReg);
149 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
150}
151
152void PPCIncomingValueHandler::assignValueToAddress(
153 Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
154 const CCValAssign &VA) {
155 // define a lambda expression to load value
156 auto BuildLoad = [](MachineIRBuilder &MIRBuilder,
157 const MachinePointerInfo &MPO, LLT MemTy,
158 const DstOp &Res, Register Addr) {
160 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
161 inferAlignFromPtrInfo(MF, MPO));
162 return MIRBuilder.buildLoad(Res, Addr, *MMO);
163 };
164
165 BuildLoad(MIRBuilder, MPO, MemTy, ValVReg, Addr);
166}
167
168Register PPCIncomingValueHandler::getStackAddress(uint64_t Size, int64_t Offset,
170 ISD::ArgFlagsTy Flags) {
171 auto &MFI = MIRBuilder.getMF().getFrameInfo();
172 const bool IsImmutable = !Flags.isByVal();
173 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
175
176 // Build Frame Index based on whether the machine is 32-bit or 64-bit
180 StackUsed = std::max(StackUsed, Size + Offset);
181 return AddrReg.getReg(0);
182}
183
184void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) {
185 MIRBuilder.getMRI()->addLiveIn(PhysReg);
186 MIRBuilder.getMBB().addLiveIn(PhysReg);
187}
unsigned const MachineRegisterInfo * MRI
#define Success
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file describes how to lower LLVM calls to machine code calls.
uint64_t Addr
uint64_t Size
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
This file describes how to lower LLVM calls to machine code calls.
static const unsigned FramePtr
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
CCValAssign - Represent assignment of one arg/retval to a location.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:410
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:49
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
@ MOLoad
The memory access reads data.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
PPCCallLowering(const PPCTargetLowering &TLI)
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:716
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:336
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA)=0
The specified value has been assigned to a stack location.
virtual void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.