LLVM  15.0.0git
CallLowering.cpp
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1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements some simple delegations needed for call lowering.
11 ///
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/LLVMContext.h"
25 #include "llvm/IR/Module.h"
27 
28 #define DEBUG_TYPE "call-lowering"
29 
30 using namespace llvm;
31 
32 void CallLowering::anchor() {}
33 
34 /// Helper function which updates \p Flags when \p AttrFn returns true.
35 static void
37  const std::function<bool(Attribute::AttrKind)> &AttrFn) {
38  if (AttrFn(Attribute::SExt))
39  Flags.setSExt();
40  if (AttrFn(Attribute::ZExt))
41  Flags.setZExt();
42  if (AttrFn(Attribute::InReg))
43  Flags.setInReg();
44  if (AttrFn(Attribute::StructRet))
45  Flags.setSRet();
46  if (AttrFn(Attribute::Nest))
47  Flags.setNest();
48  if (AttrFn(Attribute::ByVal))
49  Flags.setByVal();
50  if (AttrFn(Attribute::Preallocated))
51  Flags.setPreallocated();
52  if (AttrFn(Attribute::InAlloca))
53  Flags.setInAlloca();
54  if (AttrFn(Attribute::Returned))
55  Flags.setReturned();
56  if (AttrFn(Attribute::SwiftSelf))
57  Flags.setSwiftSelf();
58  if (AttrFn(Attribute::SwiftAsync))
59  Flags.setSwiftAsync();
60  if (AttrFn(Attribute::SwiftError))
61  Flags.setSwiftError();
62 }
63 
65  unsigned ArgIdx) const {
66  ISD::ArgFlagsTy Flags;
67  addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
68  return Call.paramHasAttr(ArgIdx, Attr);
69  });
70  return Flags;
71 }
72 
74  const AttributeList &Attrs,
75  unsigned OpIdx) const {
76  addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
77  return Attrs.hasAttributeAtIndex(OpIdx, Attr);
78  });
79 }
80 
82  ArrayRef<Register> ResRegs,
84  Register SwiftErrorVReg,
85  std::function<unsigned()> GetCalleeReg) const {
87  const DataLayout &DL = MIRBuilder.getDataLayout();
88  MachineFunction &MF = MIRBuilder.getMF();
90  bool CanBeTailCalled = CB.isTailCall() &&
91  isInTailCallPosition(CB, MF.getTarget()) &&
92  (MF.getFunction()
93  .getFnAttribute("disable-tail-calls")
94  .getValueAsString() != "true");
95 
96  CallingConv::ID CallConv = CB.getCallingConv();
97  Type *RetTy = CB.getType();
98  bool IsVarArg = CB.getFunctionType()->isVarArg();
99 
100  SmallVector<BaseArgInfo, 4> SplitArgs;
101  getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
102  Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
103 
104  if (!Info.CanLowerReturn) {
105  // Callee requires sret demotion.
106  insertSRetOutgoingArgument(MIRBuilder, CB, Info);
107 
108  // The sret demotion isn't compatible with tail-calls, since the sret
109  // argument points into the caller's stack frame.
110  CanBeTailCalled = false;
111  }
112 
113 
114  // First step is to marshall all the function's parameters into the correct
115  // physregs and memory locations. Gather the sequence of argument types that
116  // we'll pass to the assigner function.
117  unsigned i = 0;
118  unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
119  for (auto &Arg : CB.args()) {
120  ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i),
121  i < NumFixedArgs};
122  setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB);
123 
124  // If we have an explicit sret argument that is an Instruction, (i.e., it
125  // might point to function-local memory), we can't meaningfully tail-call.
126  if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
127  CanBeTailCalled = false;
128 
129  Info.OrigArgs.push_back(OrigArg);
130  ++i;
131  }
132 
133  // Try looking through a bitcast from one function type to another.
134  // Commonly happens with calls to objc_msgSend().
135  const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
136  if (const Function *F = dyn_cast<Function>(CalleeV))
137  Info.Callee = MachineOperand::CreateGA(F, 0);
138  else
139  Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
140 
141  Register ReturnHintAlignReg;
142  Align ReturnHintAlign;
143 
144  Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, ISD::ArgFlagsTy{}};
145 
146  if (!Info.OrigRet.Ty->isVoidTy()) {
148 
149  if (MaybeAlign Alignment = CB.getRetAlign()) {
150  if (*Alignment > Align(1)) {
151  ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
152  Info.OrigRet.Regs[0] = ReturnHintAlignReg;
153  ReturnHintAlign = *Alignment;
154  }
155  }
156  }
157 
158  Info.CB = &CB;
159  Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
160  Info.CallConv = CallConv;
161  Info.SwiftErrorVReg = SwiftErrorVReg;
162  Info.IsMustTailCall = CB.isMustTailCall();
163  Info.IsTailCall = CanBeTailCalled;
164  Info.IsVarArg = IsVarArg;
165  if (!lowerCall(MIRBuilder, Info))
166  return false;
167 
168  if (ReturnHintAlignReg && !Info.IsTailCall) {
169  MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg,
170  ReturnHintAlign);
171  }
172 
173  return true;
174 }
175 
176 template <typename FuncInfoTy>
178  const DataLayout &DL,
179  const FuncInfoTy &FuncInfo) const {
180  auto &Flags = Arg.Flags[0];
181  const AttributeList &Attrs = FuncInfo.getAttributes();
182  addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
183 
184  PointerType *PtrTy = dyn_cast<PointerType>(Arg.Ty->getScalarType());
185  if (PtrTy) {
186  Flags.setPointer();
188  }
189 
190  Align MemAlign = DL.getABITypeAlign(Arg.Ty);
191  if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
193  unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
194 
195  Type *ElementTy = FuncInfo.getParamByValType(ParamIdx);
196  if (!ElementTy)
197  ElementTy = FuncInfo.getParamInAllocaType(ParamIdx);
198  if (!ElementTy)
199  ElementTy = FuncInfo.getParamPreallocatedType(ParamIdx);
200  assert(ElementTy && "Must have byval, inalloca or preallocated type");
201  Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
202 
203  // For ByVal, alignment should be passed from FE. BE will guess if
204  // this info is not there but there are cases it cannot get right.
205  if (auto ParamAlign = FuncInfo.getParamStackAlign(ParamIdx))
206  MemAlign = *ParamAlign;
207  else if ((ParamAlign = FuncInfo.getParamAlign(ParamIdx)))
208  MemAlign = *ParamAlign;
209  else
210  MemAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
211  } else if (OpIdx >= AttributeList::FirstArgIndex) {
212  if (auto ParamAlign =
213  FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
214  MemAlign = *ParamAlign;
215  }
216  Flags.setMemAlign(MemAlign);
217  Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
218 
219  // Don't try to use the returned attribute if the argument is marked as
220  // swiftself, since it won't be passed in x0.
221  if (Flags.isSwiftSelf())
222  Flags.setReturned(false);
223 }
224 
225 template void
226 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
227  const DataLayout &DL,
228  const Function &FuncInfo) const;
229 
230 template void
231 CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
232  const DataLayout &DL,
233  const CallBase &FuncInfo) const;
234 
236  SmallVectorImpl<ArgInfo> &SplitArgs,
237  const DataLayout &DL,
238  CallingConv::ID CallConv,
240  LLVMContext &Ctx = OrigArg.Ty->getContext();
241 
242  SmallVector<EVT, 4> SplitVTs;
243  ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, Offsets, 0);
244 
245  if (SplitVTs.size() == 0)
246  return;
247 
248  if (SplitVTs.size() == 1) {
249  // No splitting to do, but we want to replace the original type (e.g. [1 x
250  // double] -> double).
251  SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
252  OrigArg.OrigArgIndex, OrigArg.Flags[0],
253  OrigArg.IsFixed, OrigArg.OrigValue);
254  return;
255  }
256 
257  // Create one ArgInfo for each virtual register in the original ArgInfo.
258  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
259 
260  bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
261  OrigArg.Ty, CallConv, false, DL);
262  for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
263  Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
264  SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,
265  OrigArg.Flags[0], OrigArg.IsFixed);
266  if (NeedsRegBlock)
267  SplitArgs.back().Flags[0].setInConsecutiveRegs();
268  }
269 
270  SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
271 }
272 
273 /// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
274 static MachineInstrBuilder
276  ArrayRef<Register> SrcRegs) {
277  MachineRegisterInfo &MRI = *B.getMRI();
278  LLT LLTy = MRI.getType(DstRegs[0]);
279  LLT PartLLT = MRI.getType(SrcRegs[0]);
280 
281  // Deal with v3s16 split into v2s16
282  LLT LCMTy = getCoverTy(LLTy, PartLLT);
283  if (LCMTy == LLTy) {
284  // Common case where no padding is needed.
285  assert(DstRegs.size() == 1);
286  return B.buildConcatVectors(DstRegs[0], SrcRegs);
287  }
288 
289  // We need to create an unmerge to the result registers, which may require
290  // widening the original value.
291  Register UnmergeSrcReg;
292  if (LCMTy != PartLLT) {
293  assert(DstRegs.size() == 1);
294  return B.buildDeleteTrailingVectorElements(DstRegs[0],
295  B.buildMerge(LCMTy, SrcRegs));
296  } else {
297  // We don't need to widen anything if we're extracting a scalar which was
298  // promoted to a vector e.g. s8 -> v4s8 -> s8
299  assert(SrcRegs.size() == 1);
300  UnmergeSrcReg = SrcRegs[0];
301  }
302 
303  int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
304 
305  SmallVector<Register, 8> PadDstRegs(NumDst);
306  std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
307 
308  // Create the excess dead defs for the unmerge.
309  for (int I = DstRegs.size(); I != NumDst; ++I)
310  PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
311 
312  if (PadDstRegs.size() == 1)
313  return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
314  return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
315 }
316 
317 /// Create a sequence of instructions to combine pieces split into register
318 /// typed values to the original IR value. \p OrigRegs contains the destination
319 /// value registers of type \p LLTy, and \p Regs contains the legalized pieces
320 /// with type \p PartLLT. This is used for incoming values (physregs to vregs).
322  ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
323  const ISD::ArgFlagsTy Flags) {
324  MachineRegisterInfo &MRI = *B.getMRI();
325 
326  if (PartLLT == LLTy) {
327  // We should have avoided introducing a new virtual register, and just
328  // directly assigned here.
329  assert(OrigRegs[0] == Regs[0]);
330  return;
331  }
332 
333  if (PartLLT.getSizeInBits() == LLTy.getSizeInBits() && OrigRegs.size() == 1 &&
334  Regs.size() == 1) {
335  B.buildBitcast(OrigRegs[0], Regs[0]);
336  return;
337  }
338 
339  // A vector PartLLT needs extending to LLTy's element size.
340  // E.g. <2 x s64> = G_SEXT <2 x s32>.
341  if (PartLLT.isVector() == LLTy.isVector() &&
342  PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
343  (!PartLLT.isVector() ||
344  PartLLT.getNumElements() == LLTy.getNumElements()) &&
345  OrigRegs.size() == 1 && Regs.size() == 1) {
346  Register SrcReg = Regs[0];
347 
348  LLT LocTy = MRI.getType(SrcReg);
349 
350  if (Flags.isSExt()) {
351  SrcReg = B.buildAssertSExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
352  .getReg(0);
353  } else if (Flags.isZExt()) {
354  SrcReg = B.buildAssertZExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
355  .getReg(0);
356  }
357 
358  // Sometimes pointers are passed zero extended.
359  LLT OrigTy = MRI.getType(OrigRegs[0]);
360  if (OrigTy.isPointer()) {
361  LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits());
362  B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg));
363  return;
364  }
365 
366  B.buildTrunc(OrigRegs[0], SrcReg);
367  return;
368  }
369 
370  if (!LLTy.isVector() && !PartLLT.isVector()) {
371  assert(OrigRegs.size() == 1);
372  LLT OrigTy = MRI.getType(OrigRegs[0]);
373 
374  unsigned SrcSize = PartLLT.getSizeInBits().getFixedSize() * Regs.size();
375  if (SrcSize == OrigTy.getSizeInBits())
376  B.buildMerge(OrigRegs[0], Regs);
377  else {
378  auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
379  B.buildTrunc(OrigRegs[0], Widened);
380  }
381 
382  return;
383  }
384 
385  if (PartLLT.isVector()) {
386  assert(OrigRegs.size() == 1);
387  SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
388 
389  // If PartLLT is a mismatched vector in both number of elements and element
390  // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
391  // have the same elt type, i.e. v4s32.
392  if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
393  PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
394  Regs.size() == 1) {
395  LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
396  .changeElementCount(PartLLT.getElementCount() * 2);
397  CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
398  PartLLT = NewTy;
399  }
400 
401  if (LLTy.getScalarType() == PartLLT.getElementType()) {
402  mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
403  } else {
404  unsigned I = 0;
405  LLT GCDTy = getGCDType(LLTy, PartLLT);
406 
407  // We are both splitting a vector, and bitcasting its element types. Cast
408  // the source pieces into the appropriate number of pieces with the result
409  // element type.
410  for (Register SrcReg : CastRegs)
411  CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0);
412  mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
413  }
414 
415  return;
416  }
417 
418  assert(LLTy.isVector() && !PartLLT.isVector());
419 
420  LLT DstEltTy = LLTy.getElementType();
421 
422  // Pointer information was discarded. We'll need to coerce some register types
423  // to avoid violating type constraints.
424  LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
425 
426  assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
427 
428  if (DstEltTy == PartLLT) {
429  // Vector was trivially scalarized.
430 
431  if (RealDstEltTy.isPointer()) {
432  for (Register Reg : Regs)
433  MRI.setType(Reg, RealDstEltTy);
434  }
435 
436  B.buildBuildVector(OrigRegs[0], Regs);
437  } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
438  // Deal with vector with 64-bit elements decomposed to 32-bit
439  // registers. Need to create intermediate 64-bit elements.
440  SmallVector<Register, 8> EltMerges;
441  int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
442 
443  assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
444 
445  for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
446  auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));
447  // Fix the type in case this is really a vector of pointers.
448  MRI.setType(Merge.getReg(0), RealDstEltTy);
449  EltMerges.push_back(Merge.getReg(0));
450  Regs = Regs.drop_front(PartsPerElt);
451  }
452 
453  B.buildBuildVector(OrigRegs[0], EltMerges);
454  } else {
455  // Vector was split, and elements promoted to a wider type.
456  // FIXME: Should handle floating point promotions.
457  LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
458  auto BV = B.buildBuildVector(BVType, Regs);
459  B.buildTrunc(OrigRegs[0], BV);
460  }
461 }
462 
463 /// Create a sequence of instructions to expand the value in \p SrcReg (of type
464 /// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
465 /// contain the type of scalar value extension if necessary.
466 ///
467 /// This is used for outgoing values (vregs to physregs)
469  Register SrcReg, LLT SrcTy, LLT PartTy,
470  unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
471  // We could just insert a regular copy, but this is unreachable at the moment.
472  assert(SrcTy != PartTy && "identical part types shouldn't reach here");
473 
474  const unsigned PartSize = PartTy.getSizeInBits();
475 
476  if (PartTy.isVector() == SrcTy.isVector() &&
477  PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
478  assert(DstRegs.size() == 1);
479  B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
480  return;
481  }
482 
483  if (SrcTy.isVector() && !PartTy.isVector() &&
484  PartSize > SrcTy.getElementType().getSizeInBits()) {
485  // Vector was scalarized, and the elements extended.
486  auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
487  for (int i = 0, e = DstRegs.size(); i != e; ++i)
488  B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
489  return;
490  }
491 
492  LLT GCDTy = getGCDType(SrcTy, PartTy);
493  if (GCDTy == PartTy) {
494  // If this already evenly divisible, we can create a simple unmerge.
495  B.buildUnmerge(DstRegs, SrcReg);
496  return;
497  }
498 
499  MachineRegisterInfo &MRI = *B.getMRI();
500  LLT DstTy = MRI.getType(DstRegs[0]);
501  LLT LCMTy = getCoverTy(SrcTy, PartTy);
502 
503  const unsigned DstSize = DstTy.getSizeInBits();
504  const unsigned SrcSize = SrcTy.getSizeInBits();
505  unsigned CoveringSize = LCMTy.getSizeInBits();
506 
507  Register UnmergeSrc = SrcReg;
508 
509  if (!LCMTy.isVector() && CoveringSize != SrcSize) {
510  // For scalars, it's common to be able to use a simple extension.
511  if (SrcTy.isScalar() && DstTy.isScalar()) {
512  CoveringSize = alignTo(SrcSize, DstSize);
513  LLT CoverTy = LLT::scalar(CoveringSize);
514  UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
515  } else {
516  // Widen to the common type.
517  // FIXME: This should respect the extend type
518  Register Undef = B.buildUndef(SrcTy).getReg(0);
519  SmallVector<Register, 8> MergeParts(1, SrcReg);
520  for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
521  MergeParts.push_back(Undef);
522  UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
523  }
524  }
525 
526  if (LCMTy.isVector() && CoveringSize != SrcSize)
527  UnmergeSrc = B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
528 
529  B.buildUnmerge(DstRegs, UnmergeSrc);
530 }
531 
533  ValueHandler &Handler, ValueAssigner &Assigner,
535  CallingConv::ID CallConv, bool IsVarArg,
536  ArrayRef<Register> ThisReturnRegs) const {
537  MachineFunction &MF = MIRBuilder.getMF();
538  const Function &F = MF.getFunction();
540 
541  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
542  if (!determineAssignments(Assigner, Args, CCInfo))
543  return false;
544 
545  return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
546  ThisReturnRegs);
547 }
548 
549 static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags) {
550  if (Flags.isSExt())
551  return TargetOpcode::G_SEXT;
552  if (Flags.isZExt())
553  return TargetOpcode::G_ZEXT;
554  return TargetOpcode::G_ANYEXT;
555 }
556 
559  CCState &CCInfo) const {
560  LLVMContext &Ctx = CCInfo.getContext();
561  const CallingConv::ID CallConv = CCInfo.getCallingConv();
562 
563  unsigned NumArgs = Args.size();
564  for (unsigned i = 0; i != NumArgs; ++i) {
565  EVT CurVT = EVT::getEVT(Args[i].Ty);
566 
567  MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT);
568 
569  // If we need to split the type over multiple regs, check it's a scenario
570  // we currently support.
571  unsigned NumParts =
572  TLI->getNumRegistersForCallingConv(Ctx, CallConv, CurVT);
573 
574  if (NumParts == 1) {
575  // Try to use the register type if we couldn't assign the VT.
576  if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
577  Args[i].Flags[0], CCInfo))
578  return false;
579  continue;
580  }
581 
582  // For incoming arguments (physregs to vregs), we could have values in
583  // physregs (or memlocs) which we want to extract and copy to vregs.
584  // During this, we might have to deal with the LLT being split across
585  // multiple regs, so we have to record this information for later.
586  //
587  // If we have outgoing args, then we have the opposite case. We have a
588  // vreg with an LLT which we want to assign to a physical location, and
589  // we might have to record that the value has to be split later.
590 
591  // We're handling an incoming arg which is split over multiple regs.
592  // E.g. passing an s128 on AArch64.
593  ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
594  Args[i].Flags.clear();
595 
596  for (unsigned Part = 0; Part < NumParts; ++Part) {
597  ISD::ArgFlagsTy Flags = OrigFlags;
598  if (Part == 0) {
599  Flags.setSplit();
600  } else {
601  Flags.setOrigAlign(Align(1));
602  if (Part == NumParts - 1)
603  Flags.setSplitEnd();
604  }
605 
606  Args[i].Flags.push_back(Flags);
607  if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
608  Args[i].Flags[Part], CCInfo)) {
609  // Still couldn't assign this smaller part type for some reason.
610  return false;
611  }
612  }
613  }
614 
615  return true;
616 }
617 
620  CCState &CCInfo,
622  MachineIRBuilder &MIRBuilder,
623  ArrayRef<Register> ThisReturnRegs) const {
624  MachineFunction &MF = MIRBuilder.getMF();
626  const Function &F = MF.getFunction();
627  const DataLayout &DL = F.getParent()->getDataLayout();
628 
629  const unsigned NumArgs = Args.size();
630 
631  // Stores thunks for outgoing register assignments. This is used so we delay
632  // generating register copies until mem loc assignments are done. We do this
633  // so that if the target is using the delayed stack protector feature, we can
634  // find the split point of the block accurately. E.g. if we have:
635  // G_STORE %val, %memloc
636  // $x0 = COPY %foo
637  // $x1 = COPY %bar
638  // CALL func
639  // ... then the split point for the block will correctly be at, and including,
640  // the copy to $x0. If instead the G_STORE instruction immediately precedes
641  // the CALL, then we'd prematurely choose the CALL as the split point, thus
642  // generating a split block with a CALL that uses undefined physregs.
643  SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
644 
645  for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
646  assert(j < ArgLocs.size() && "Skipped too many arg locs");
647  CCValAssign &VA = ArgLocs[j];
648  assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
649 
650  if (VA.needsCustom()) {
651  std::function<void()> Thunk;
652  unsigned NumArgRegs = Handler.assignCustomValue(
653  Args[i], makeArrayRef(ArgLocs).slice(j), &Thunk);
654  if (Thunk)
655  DelayedOutgoingRegAssignments.emplace_back(Thunk);
656  if (!NumArgRegs)
657  return false;
658  j += NumArgRegs;
659  continue;
660  }
661 
662  const MVT ValVT = VA.getValVT();
663  const MVT LocVT = VA.getLocVT();
664 
665  const LLT LocTy(LocVT);
666  const LLT ValTy(ValVT);
667  const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
668  const EVT OrigVT = EVT::getEVT(Args[i].Ty);
669  const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
670 
671  // Expected to be multiple regs for a single incoming arg.
672  // There should be Regs.size() ArgLocs per argument.
673  // This should be the same as getNumRegistersForCallingConv
674  const unsigned NumParts = Args[i].Flags.size();
675 
676  // Now split the registers into the assigned types.
677  Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
678 
679  if (NumParts != 1 || NewLLT != OrigTy) {
680  // If we can't directly assign the register, we need one or more
681  // intermediate values.
682  Args[i].Regs.resize(NumParts);
683 
684  // For each split register, create and assign a vreg that will store
685  // the incoming component of the larger value. These will later be
686  // merged to form the final vreg.
687  for (unsigned Part = 0; Part < NumParts; ++Part)
688  Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
689  }
690 
691  assert((j + (NumParts - 1)) < ArgLocs.size() &&
692  "Too many regs for number of args");
693 
694  // Coerce into outgoing value types before register assignment.
695  if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy) {
696  assert(Args[i].OrigRegs.size() == 1);
697  buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
698  ValTy, extendOpFromFlags(Args[i].Flags[0]));
699  }
700 
701  bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
702  for (unsigned Part = 0; Part < NumParts; ++Part) {
703  Register ArgReg = Args[i].Regs[Part];
704  // There should be Regs.size() ArgLocs per argument.
705  unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
706  CCValAssign &VA = ArgLocs[j + Idx];
707  const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
708 
709  if (VA.isMemLoc() && !Flags.isByVal()) {
710  // Individual pieces may have been spilled to the stack and others
711  // passed in registers.
712 
713  // TODO: The memory size may be larger than the value we need to
714  // store. We may need to adjust the offset for big endian targets.
715  LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags);
716 
717  MachinePointerInfo MPO;
718  Register StackAddr = Handler.getStackAddress(
719  MemTy.getSizeInBytes(), VA.getLocMemOffset(), MPO, Flags);
720 
721  Handler.assignValueToAddress(Args[i], Part, StackAddr, MemTy, MPO, VA);
722  continue;
723  }
724 
725  if (VA.isMemLoc() && Flags.isByVal()) {
726  assert(Args[i].Regs.size() == 1 &&
727  "didn't expect split byval pointer");
728 
729  if (Handler.isIncomingArgumentHandler()) {
730  // We just need to copy the frame index value to the pointer.
731  MachinePointerInfo MPO;
732  Register StackAddr = Handler.getStackAddress(
733  Flags.getByValSize(), VA.getLocMemOffset(), MPO, Flags);
734  MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
735  } else {
736  // For outgoing byval arguments, insert the implicit copy byval
737  // implies, such that writes in the callee do not modify the caller's
738  // value.
739  uint64_t MemSize = Flags.getByValSize();
740  int64_t Offset = VA.getLocMemOffset();
741 
742  MachinePointerInfo DstMPO;
743  Register StackAddr =
744  Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
745 
746  MachinePointerInfo SrcMPO(Args[i].OrigValue);
747  if (!Args[i].OrigValue) {
748  // We still need to accurately track the stack address space if we
749  // don't know the underlying value.
750  const LLT PtrTy = MRI.getType(StackAddr);
751  SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
752  }
753 
754  Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
755  inferAlignFromPtrInfo(MF, DstMPO));
756 
757  Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
758  inferAlignFromPtrInfo(MF, SrcMPO));
759 
760  Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
761  DstMPO, DstAlign, SrcMPO, SrcAlign,
762  MemSize, VA);
763  }
764  continue;
765  }
766 
767  assert(!VA.needsCustom() && "custom loc should have been handled already");
768 
769  if (i == 0 && !ThisReturnRegs.empty() &&
770  Handler.isIncomingArgumentHandler() &&
772  Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA);
773  continue;
774  }
775 
776  if (Handler.isIncomingArgumentHandler())
777  Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
778  else {
779  DelayedOutgoingRegAssignments.emplace_back([=, &Handler]() {
780  Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
781  });
782  }
783  }
784 
785  // Now that all pieces have been assigned, re-pack the register typed values
786  // into the original value typed registers.
787  if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT) {
788  // Merge the split registers into the expected larger result vregs of
789  // the original call.
790  buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
791  LocTy, Args[i].Flags[0]);
792  }
793 
794  j += NumParts - 1;
795  }
796  for (auto &Fn : DelayedOutgoingRegAssignments)
797  Fn();
798 
799  return true;
800 }
801 
803  ArrayRef<Register> VRegs, Register DemoteReg,
804  int FI) const {
805  MachineFunction &MF = MIRBuilder.getMF();
807  const DataLayout &DL = MF.getDataLayout();
808 
809  SmallVector<EVT, 4> SplitVTs;
811  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
812 
813  assert(VRegs.size() == SplitVTs.size());
814 
815  unsigned NumValues = SplitVTs.size();
816  Align BaseAlign = DL.getPrefTypeAlign(RetTy);
817  Type *RetPtrTy = RetTy->getPointerTo(DL.getAllocaAddrSpace());
818  LLT OffsetLLTy = getLLTForType(*DL.getIntPtrType(RetPtrTy), DL);
819 
821 
822  for (unsigned I = 0; I < NumValues; ++I) {
823  Register Addr;
824  MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
825  auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
826  MRI.getType(VRegs[I]),
827  commonAlignment(BaseAlign, Offsets[I]));
828  MIRBuilder.buildLoad(VRegs[I], Addr, *MMO);
829  }
830 }
831 
833  ArrayRef<Register> VRegs,
834  Register DemoteReg) const {
835  MachineFunction &MF = MIRBuilder.getMF();
837  const DataLayout &DL = MF.getDataLayout();
838 
839  SmallVector<EVT, 4> SplitVTs;
841  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
842 
843  assert(VRegs.size() == SplitVTs.size());
844 
845  unsigned NumValues = SplitVTs.size();
846  Align BaseAlign = DL.getPrefTypeAlign(RetTy);
847  unsigned AS = DL.getAllocaAddrSpace();
848  LLT OffsetLLTy =
849  getLLTForType(*DL.getIntPtrType(RetTy->getPointerTo(AS)), DL);
850 
851  MachinePointerInfo PtrInfo(AS);
852 
853  for (unsigned I = 0; I < NumValues; ++I) {
854  Register Addr;
855  MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
856  auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
857  MRI.getType(VRegs[I]),
858  commonAlignment(BaseAlign, Offsets[I]));
859  MIRBuilder.buildStore(VRegs[I], Addr, *MMO);
860  }
861 }
862 
864  const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
865  MachineRegisterInfo &MRI, const DataLayout &DL) const {
866  unsigned AS = DL.getAllocaAddrSpace();
867  DemoteReg = MRI.createGenericVirtualRegister(
868  LLT::pointer(AS, DL.getPointerSizeInBits(AS)));
869 
870  Type *PtrTy = PointerType::get(F.getReturnType(), AS);
871 
872  SmallVector<EVT, 1> ValueVTs;
873  ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs);
874 
875  // NOTE: Assume that a pointer won't get split into more than one VT.
876  assert(ValueVTs.size() == 1);
877 
878  ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()),
881  DemoteArg.Flags[0].setSRet();
882  SplitArgs.insert(SplitArgs.begin(), DemoteArg);
883 }
884 
886  const CallBase &CB,
887  CallLoweringInfo &Info) const {
888  const DataLayout &DL = MIRBuilder.getDataLayout();
889  Type *RetTy = CB.getType();
890  unsigned AS = DL.getAllocaAddrSpace();
891  LLT FramePtrTy = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
892 
893  int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
894  DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false);
895 
896  Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0);
897  ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS),
899  setArgFlags(DemoteArg, AttributeList::ReturnIndex, DL, CB);
900  DemoteArg.Flags[0].setSRet();
901 
902  Info.OrigArgs.insert(Info.OrigArgs.begin(), DemoteArg);
903  Info.DemoteStackIndex = FI;
904  Info.DemoteRegister = DemoteReg;
905 }
906 
909  CCAssignFn *Fn) const {
910  for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
911  MVT VT = MVT::getVT(Outs[I].Ty);
912  if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo))
913  return false;
914  }
915  return true;
916 }
917 
921  const DataLayout &DL) const {
922  LLVMContext &Context = RetTy->getContext();
924 
925  SmallVector<EVT, 4> SplitVTs;
926  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs);
928 
929  for (EVT VT : SplitVTs) {
930  unsigned NumParts =
931  TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
932  MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
933  Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
934 
935  for (unsigned I = 0; I < NumParts; ++I) {
936  Outs.emplace_back(PartTy, Flags);
937  }
938  }
939 }
940 
942  const auto &F = MF.getFunction();
943  Type *ReturnType = F.getReturnType();
944  CallingConv::ID CallConv = F.getCallingConv();
945 
946  SmallVector<BaseArgInfo, 4> SplitArgs;
947  getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
948  MF.getDataLayout());
949  return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
950 }
951 
953  const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
954  const SmallVectorImpl<CCValAssign> &OutLocs,
955  const SmallVectorImpl<ArgInfo> &OutArgs) const {
956  for (unsigned i = 0; i < OutLocs.size(); ++i) {
957  auto &ArgLoc = OutLocs[i];
958  // If it's not a register, it's fine.
959  if (!ArgLoc.isRegLoc())
960  continue;
961 
962  MCRegister PhysReg = ArgLoc.getLocReg();
963 
964  // Only look at callee-saved registers.
965  if (MachineOperand::clobbersPhysReg(CallerPreservedMask, PhysReg))
966  continue;
967 
968  LLVM_DEBUG(
969  dbgs()
970  << "... Call has an argument passed in a callee-saved register.\n");
971 
972  // Check if it was copied from.
973  const ArgInfo &OutInfo = OutArgs[i];
974 
975  if (OutInfo.Regs.size() > 1) {
976  LLVM_DEBUG(
977  dbgs() << "... Cannot handle arguments in multiple registers.\n");
978  return false;
979  }
980 
981  // Check if we copy the register, walking through copies from virtual
982  // registers. Note that getDefIgnoringCopies does not ignore copies from
983  // physical registers.
984  MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
985  if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
986  LLVM_DEBUG(
987  dbgs()
988  << "... Parameter was not copied into a VReg, cannot tail call.\n");
989  return false;
990  }
991 
992  // Got a copy. Verify that it's the same as the register we want.
993  Register CopyRHS = RegDef->getOperand(1).getReg();
994  if (CopyRHS != PhysReg) {
995  LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
996  "VReg, cannot tail call.\n");
997  return false;
998  }
999  }
1000 
1001  return true;
1002 }
1003 
1005  MachineFunction &MF,
1006  SmallVectorImpl<ArgInfo> &InArgs,
1007  ValueAssigner &CalleeAssigner,
1008  ValueAssigner &CallerAssigner) const {
1009  const Function &F = MF.getFunction();
1010  CallingConv::ID CalleeCC = Info.CallConv;
1011  CallingConv::ID CallerCC = F.getCallingConv();
1012 
1013  if (CallerCC == CalleeCC)
1014  return true;
1015 
1017  CCState CCInfo1(CalleeCC, Info.IsVarArg, MF, ArgLocs1, F.getContext());
1018  if (!determineAssignments(CalleeAssigner, InArgs, CCInfo1))
1019  return false;
1020 
1022  CCState CCInfo2(CallerCC, F.isVarArg(), MF, ArgLocs2, F.getContext());
1023  if (!determineAssignments(CallerAssigner, InArgs, CCInfo2))
1024  return false;
1025 
1026  // We need the argument locations to match up exactly. If there's more in
1027  // one than the other, then we are done.
1028  if (ArgLocs1.size() != ArgLocs2.size())
1029  return false;
1030 
1031  // Make sure that each location is passed in exactly the same way.
1032  for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
1033  const CCValAssign &Loc1 = ArgLocs1[i];
1034  const CCValAssign &Loc2 = ArgLocs2[i];
1035 
1036  // We need both of them to be the same. So if one is a register and one
1037  // isn't, we're done.
1038  if (Loc1.isRegLoc() != Loc2.isRegLoc())
1039  return false;
1040 
1041  if (Loc1.isRegLoc()) {
1042  // If they don't have the same register location, we're done.
1043  if (Loc1.getLocReg() != Loc2.getLocReg())
1044  return false;
1045 
1046  // They matched, so we can move to the next ArgLoc.
1047  continue;
1048  }
1049 
1050  // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
1051  if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
1052  return false;
1053  }
1054 
1055  return true;
1056 }
1057 
1059  const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const {
1060  const MVT ValVT = VA.getValVT();
1061  if (ValVT != MVT::iPTR) {
1062  LLT ValTy(ValVT);
1063 
1064  // We lost the pointeriness going through CCValAssign, so try to restore it
1065  // based on the flags.
1066  if (Flags.isPointer()) {
1067  LLT PtrTy = LLT::pointer(Flags.getPointerAddrSpace(),
1068  ValTy.getScalarSizeInBits());
1069  if (ValVT.isVector())
1070  return LLT::vector(ValTy.getElementCount(), PtrTy);
1071  return PtrTy;
1072  }
1073 
1074  return ValTy;
1075  }
1076 
1077  unsigned AddrSpace = Flags.getPointerAddrSpace();
1078  return LLT::pointer(AddrSpace, DL.getPointerSize(AddrSpace));
1079 }
1080 
1082  const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
1083  const MachinePointerInfo &DstPtrInfo, Align DstAlign,
1084  const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
1085  CCValAssign &VA) const {
1086  MachineFunction &MF = MIRBuilder.getMF();
1088  SrcPtrInfo,
1090  SrcAlign);
1091 
1093  DstPtrInfo,
1095  MemSize, DstAlign);
1096 
1097  const LLT PtrTy = MRI.getType(DstPtr);
1098  const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
1099 
1100  auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
1101  MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1102 }
1103 
1105  CCValAssign &VA,
1106  unsigned MaxSizeBits) {
1107  LLT LocTy{VA.getLocVT()};
1108  LLT ValTy{VA.getValVT()};
1109 
1110  if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1111  return ValReg;
1112 
1113  if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1114  if (MaxSizeBits <= ValTy.getSizeInBits())
1115  return ValReg;
1116  LocTy = LLT::scalar(MaxSizeBits);
1117  }
1118 
1119  const LLT ValRegTy = MRI.getType(ValReg);
1120  if (ValRegTy.isPointer()) {
1121  // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1122  // we have to cast to do the extension.
1123  LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits());
1124  ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0);
1125  }
1126 
1127  switch (VA.getLocInfo()) {
1128  default: break;
1129  case CCValAssign::Full:
1130  case CCValAssign::BCvt:
1131  // FIXME: bitconverting between vector types may or may not be a
1132  // nop in big-endian situations.
1133  return ValReg;
1134  case CCValAssign::AExt: {
1135  auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1136  return MIB.getReg(0);
1137  }
1138  case CCValAssign::SExt: {
1139  Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1140  MIRBuilder.buildSExt(NewReg, ValReg);
1141  return NewReg;
1142  }
1143  case CCValAssign::ZExt: {
1144  Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1145  MIRBuilder.buildZExt(NewReg, ValReg);
1146  return NewReg;
1147  }
1148  }
1149  llvm_unreachable("unable to extend register");
1150 }
1151 
1152 void CallLowering::ValueAssigner::anchor() {}
1153 
1155  Register SrcReg,
1156  LLT NarrowTy) {
1157  switch (VA.getLocInfo()) {
1158  case CCValAssign::LocInfo::ZExt: {
1159  return MIRBuilder
1160  .buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1161  NarrowTy.getScalarSizeInBits())
1162  .getReg(0);
1163  }
1164  case CCValAssign::LocInfo::SExt: {
1165  return MIRBuilder
1166  .buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1167  NarrowTy.getScalarSizeInBits())
1168  .getReg(0);
1169  break;
1170  }
1171  default:
1172  return SrcReg;
1173  }
1174 }
1175 
1176 /// Check if we can use a basic COPY instruction between the two types.
1177 ///
1178 /// We're currently building on top of the infrastructure using MVT, which loses
1179 /// pointer information in the CCValAssign. We accept copies from physical
1180 /// registers that have been reported as integers if it's to an equivalent sized
1181 /// pointer LLT.
1182 static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
1183  if (SrcTy == DstTy)
1184  return true;
1185 
1186  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1187  return false;
1188 
1189  SrcTy = SrcTy.getScalarType();
1190  DstTy = DstTy.getScalarType();
1191 
1192  return (SrcTy.isPointer() && DstTy.isScalar()) ||
1193  (DstTy.isScalar() && SrcTy.isPointer());
1194 }
1195 
1197  Register PhysReg,
1198  CCValAssign VA) {
1199  const MVT LocVT = VA.getLocVT();
1200  const LLT LocTy(LocVT);
1201  const LLT RegTy = MRI.getType(ValVReg);
1202 
1203  if (isCopyCompatibleType(RegTy, LocTy)) {
1204  MIRBuilder.buildCopy(ValVReg, PhysReg);
1205  return;
1206  }
1207 
1208  auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
1209  auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
1210  MIRBuilder.buildTrunc(ValVReg, Hint);
1211 }
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
i
i
Definition: README.txt:29
llvm::ISD::ArgFlagsTy::isInAlloca
bool isInAlloca() const
Definition: TargetCallingConv.h:91
llvm::CallLowering::ValueAssigner
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:158
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:459
Merge
R600 Clause Merge
Definition: R600ClauseMergePass.cpp:70
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::ISD::ArgFlagsTy::setSwiftSelf
void setSwiftSelf()
Definition: TargetCallingConv.h:98
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
llvm::ISD::ArgFlagsTy::setNest
void setNest()
Definition: TargetCallingConv.h:119
CallLowering.h
llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition: TargetLowering.h:4279
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
buildCopyToRegs
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
Definition: CallLowering.cpp:468
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:430
llvm::Function
Definition: Function.h:60
llvm::CallLowering::IncomingValueHandler::assignValueToReg
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
Provides a default implementation for argument handling.
Definition: CallLowering.cpp:1196
llvm::PointerType::get
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Definition: Type.cpp:727
llvm::ISD::ArgFlagsTy::setMemAlign
void setMemAlign(Align A)
Definition: TargetCallingConv.h:148
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::CallLowering::ValueHandler::extendRegister
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
Definition: CallLowering.cpp:1104
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::CallLowering::ValueHandler
Definition: CallLowering.h:226
llvm::CallLowering::insertSRetOutgoingArgument
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
Definition: CallLowering.cpp:885
llvm::ISD::ArgFlagsTy::setPointer
void setPointer()
Definition: TargetCallingConv.h:142
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:167
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Module.h
llvm::AttributeList
Definition: Attributes.h:408
llvm::CallBase::getAttributes
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1474
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1254
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:141
extendOpFromFlags
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
Definition: CallLowering.cpp:549
llvm::CallBase::isMustTailCall
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: Instructions.cpp:298
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:235
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::LLT::changeElementCount
LLT changeElementCount(ElementCount EC) const
Return a vector or scalar with the same element type and the new element count.
Definition: LowLevelTypeImpl.h:189
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:56
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
MachineIRBuilder.h
buildCopyFromRegs
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT, const ISD::ArgFlagsTy Flags)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
Definition: CallLowering.cpp:321
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:283
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::FunctionType::isVarArg
bool isVarArg() const
Definition: DerivedTypes.h:123
llvm::ISD::ArgFlagsTy::isSwiftSelf
bool isSwiftSelf() const
Definition: TargetCallingConv.h:97
MachineRegisterInfo.h
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:20
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:949
llvm::CallLowering::getTLI
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
Definition: CallLowering.h:337
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:1004
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
TargetMachine.h
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:452
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:888
llvm::ISD::ArgFlagsTy::setReturned
void setReturned(bool V=true)
Definition: TargetCallingConv.h:122
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:180
llvm::CallLowering::checkReturnTypeForCallConv
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
Definition: CallLowering.cpp:941
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::CallLowering::ValueHandler::assignValueToReg
virtual void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MachineIRBuilder::buildPtrToInt
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Definition: MachineIRBuilder.h:658
mergeVectorRegsToResultRegs
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
Definition: CallLowering.cpp:275
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::CallLowering::ValueHandler::getStackValueStoreType
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
Definition: CallLowering.cpp:1058
Utils.h
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:279
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:651
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:557
llvm::CallLowering::ValueHandler::assignCustomValue
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:292
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:255
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallBase::getCallingConv
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1455
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:305
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:279
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:314
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::CallLowering::isTypeIsValidForThisReturn
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: CallLowering.h:587
llvm::CallLowering::ArgInfo::NoArgIndex
static const unsigned NoArgIndex
Sentinel value for implicit machine-level input arguments.
Definition: CallLowering.h:79
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:411
llvm::ISD::ArgFlagsTy::setSplit
void setSplit()
Definition: TargetCallingConv.h:133
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1580
llvm::CallBase::isTailCall
bool isTailCall() const
Tests if this call site is marked as a tail call.
Definition: Instructions.cpp:305
llvm::ArrayRef::drop_front
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:203
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::CallBase::getRetAlign
MaybeAlign getRetAlign() const
Extract the alignment of the return value.
Definition: InstrTypes.h:1733
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:907
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:695
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:561
I
#define I(x, y, z)
Definition: MD5.cpp:58
Analysis.h
llvm::Attribute::AttrKind
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
Definition: Attributes.h:71
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:934
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:632
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(Align A)
Definition: TargetCallingConv.h:164
llvm::TargetLoweringBase::hasBigEndianPartOrdering
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
Definition: TargetLowering.h:1613
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:257
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::ISD::ArgFlagsTy::setSwiftError
void setSwiftError()
Definition: TargetCallingConv.h:104
llvm::ISD::ArgFlagsTy::getPointerAddrSpace
unsigned getPointerAddrSpace() const
Definition: TargetCallingConv.h:187
isCopyCompatibleType
static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy)
Check if we can use a basic COPY instruction between the two types.
Definition: CallLowering.cpp:1182
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.h:858
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::ISD::ArgFlagsTy::setByVal
void setByVal()
Definition: TargetCallingConv.h:86
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
llvm::CallLowering::addArgFlagsFromAttributes
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
Definition: CallLowering.cpp:73
llvm::MachineFunction
Definition: MachineFunction.h:241
addFlagsUsingAttrFn
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
Definition: CallLowering.cpp:36
llvm::ISD::ArgFlagsTy::setByValSize
void setByValSize(unsigned S)
Definition: TargetCallingConv.h:173
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:140
llvm::CallLowering::ValueHandler::copyArgumentMemory
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
Definition: CallLowering.cpp:1081
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:859
DataLayout.h
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::CallLowering::ValueHandler::getStackAddress
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
llvm::ISD::ArgFlagsTy::setInAlloca
void setInAlloca()
Definition: TargetCallingConv.h:92
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MachineIRBuilder::buildAssertAlign
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
Definition: MachineIRBuilder.h:874
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:802
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:278
llvm::ISD::ArgFlagsTy::setSplitEnd
void setSplitEnd()
Definition: TargetCallingConv.h:136
uint32_t
llvm::ISD::ArgFlagsTy::isPreallocated
bool isPreallocated() const
Definition: TargetCallingConv.h:94
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::ArgFlagsTy::setPointerAddrSpace
void setPointerAddrSpace(unsigned AS)
Definition: TargetCallingConv.h:188
llvm::MVT::iPTR
@ iPTR
Definition: MachineValueType.h:312
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LLT::changeElementType
LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
Definition: LowLevelTypeImpl.h:173
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:442
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:191
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:682
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
NumFixedArgs
static unsigned NumFixedArgs
Definition: LanaiISelLowering.cpp:364
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:135
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:863
llvm::CallLowering::getAttributesForArgIdx
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
Definition: CallLowering.cpp:64
j
return j(j<< 16)
llvm::CallLowering::canLowerReturn
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: CallLowering.h:487
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:832
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:774
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1901
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::ArrayRef::take_front
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:227
MachineFrameInfo.h
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:162
llvm::CallLowering::handleAssignments
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=None) const
Use Handler to insert code to handle the argument/return values represented by Args.
Definition: CallLowering.cpp:618
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
llvm::ISD::ArgFlagsTy::isPointer
bool isPointer() const
Definition: TargetCallingConv.h:141
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:50
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:774
llvm::CallLowering::IncomingValueHandler::buildExtensionHint
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
Definition: CallLowering.cpp:1154
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1389
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:170
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:447
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.h:866
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:143
llvm::ISD::ArgFlagsTy::setSRet
void setSRet()
Definition: TargetCallingConv.h:83
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1572
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:529
llvm::isInTailCallPosition
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:522
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::CallLowering::getReturnInfo
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
Definition: CallLowering.cpp:918
MachineOperand.h
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::CallLowering::BaseArgInfo::IsFixed
bool IsFixed
Definition: CallLowering.h:52
llvm::ISD::ArgFlagsTy::setPreallocated
void setPreallocated()
Definition: TargetCallingConv.h:95
llvm::CallLowering::ArgInfo::OrigValue
const Value * OrigValue
Optionally track the original IR value for the argument.
Definition: CallLowering.h:73
LLVMContext.h
llvm::CallLowering::ValueAssigner::assignArg
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:182
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:415
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1301
llvm::CallLowering::ArgInfo::OrigArgIndex
unsigned OrigArgIndex
Index original Function's argument.
Definition: CallLowering.h:76
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:952
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:101
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::ISD::ArgFlagsTy::setSwiftAsync
void setSwiftAsync()
Definition: TargetCallingConv.h:101
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:413
llvm::CallLowering::ValueHandler::isIncomingArgumentHandler
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
Definition: CallLowering.h:240
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::CCValAssign::needsCustom
bool needsCustom() const
Definition: CallingConvLower.h:146
llvm::CallBase::args
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1332
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:532
llvm::CallLowering::ValueHandler::assignValueToAddress
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA)=0
The specified value has been assigned to a stack location.
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:927
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:792
llvm::CallLowering::BaseArgInfo::Flags
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::lowerCall
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:547
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:177