28#define DEBUG_TYPE "call-lowering"
32void CallLowering::anchor() {}
38 if (AttrFn(Attribute::SExt))
40 if (AttrFn(Attribute::ZExt))
42 if (AttrFn(Attribute::InReg))
44 if (AttrFn(Attribute::StructRet))
46 if (AttrFn(Attribute::Nest))
48 if (AttrFn(Attribute::ByVal))
50 if (AttrFn(Attribute::Preallocated))
51 Flags.setPreallocated();
52 if (AttrFn(Attribute::InAlloca))
54 if (AttrFn(Attribute::Returned))
56 if (AttrFn(Attribute::SwiftSelf))
58 if (AttrFn(Attribute::SwiftAsync))
59 Flags.setSwiftAsync();
60 if (AttrFn(Attribute::SwiftError))
61 Flags.setSwiftError();
65 unsigned ArgIdx)
const {
68 return Call.paramHasAttr(ArgIdx, Attr);
77 return Call.hasRetAttr(Attr);
84 unsigned OpIdx)
const {
86 return Attrs.hasAttributeAtIndex(OpIdx, Attr);
94 std::function<
unsigned()> GetCalleeReg)
const {
113 if (!
Info.CanLowerReturn) {
119 CanBeTailCalled =
false;
128 for (
const auto &
Arg : CB.
args()) {
135 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&
Arg))
136 CanBeTailCalled =
false;
138 Info.OrigArgs.push_back(OrigArg);
145 if (
const Function *
F = dyn_cast<Function>(CalleeV))
151 Align ReturnHintAlign;
155 if (!
Info.OrigRet.Ty->isVoidTy()) {
159 if (*Alignment >
Align(1)) {
160 ReturnHintAlignReg =
MRI.cloneVirtualRegister(ResRegs[0]);
161 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
162 ReturnHintAlign = *Alignment;
169 Info.CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
170 assert(
Info.CFIType->getType()->isIntegerTy(32) &&
"Invalid CFI type");
175 Info.CallConv = CallConv;
176 Info.SwiftErrorVReg = SwiftErrorVReg;
178 Info.IsTailCall = CanBeTailCalled;
179 Info.IsVarArg = IsVarArg;
183 if (ReturnHintAlignReg && !
Info.IsTailCall) {
191template <
typename FuncInfoTy>
199 PointerType *PtrTy = dyn_cast<PointerType>(
Arg.Ty->getScalarType());
212 ElementTy =
FuncInfo.getParamInAllocaType(ParamIdx);
214 ElementTy =
FuncInfo.getParamPreallocatedType(ParamIdx);
215 assert(ElementTy &&
"Must have byval, inalloca or preallocated type");
216 Flags.setByValSize(
DL.getTypeAllocSize(ElementTy));
220 if (
auto ParamAlign =
FuncInfo.getParamStackAlign(ParamIdx))
221 MemAlign = *ParamAlign;
222 else if ((ParamAlign =
FuncInfo.getParamAlign(ParamIdx)))
223 MemAlign = *ParamAlign;
225 MemAlign =
Align(
getTLI()->getByValTypeAlignment(ElementTy,
DL));
227 if (
auto ParamAlign =
229 MemAlign = *ParamAlign;
231 Flags.setMemAlign(MemAlign);
232 Flags.setOrigAlign(
DL.getABITypeAlign(
Arg.Ty));
236 if (
Flags.isSwiftSelf())
237 Flags.setReturned(
false);
260 if (SplitVTs.
size() == 0)
263 if (SplitVTs.
size() == 1) {
273 assert(OrigArg.
Regs.size() == SplitVTs.
size() &&
"Regs / types mismatch");
276 OrigArg.
Ty, CallConv,
false,
DL);
277 for (
unsigned i = 0, e = SplitVTs.
size(); i < e; ++i) {
278 Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
282 SplitArgs.
back().Flags[0].setInConsecutiveRegs();
285 SplitArgs.
back().Flags[0].setInConsecutiveRegsLast();
293 LLT LLTy =
MRI.getType(DstRegs[0]);
294 LLT PartLLT =
MRI.getType(SrcRegs[0]);
301 return B.buildConcatVectors(DstRegs[0], SrcRegs);
307 if (LCMTy != PartLLT) {
309 return B.buildDeleteTrailingVectorElements(
310 DstRegs[0],
B.buildMergeLikeInstr(LCMTy, SrcRegs));
315 UnmergeSrcReg = SrcRegs[0];
321 std::copy(DstRegs.
begin(), DstRegs.
end(), PadDstRegs.
begin());
324 for (
int I = DstRegs.
size();
I != NumDst; ++
I)
325 PadDstRegs[
I] =
MRI.createGenericVirtualRegister(LLTy);
327 if (PadDstRegs.
size() == 1)
328 return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
329 return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
341 if (PartLLT == LLTy) {
344 assert(OrigRegs[0] == Regs[0]);
350 B.buildBitcast(OrigRegs[0], Regs[0]);
360 OrigRegs.
size() == 1 && Regs.
size() == 1) {
363 LLT LocTy =
MRI.getType(SrcReg);
365 if (
Flags.isSExt()) {
368 }
else if (
Flags.isZExt()) {
374 LLT OrigTy =
MRI.getType(OrigRegs[0]);
377 B.buildIntToPtr(OrigRegs[0],
B.buildTrunc(IntPtrTy, SrcReg));
381 B.buildTrunc(OrigRegs[0], SrcReg);
387 LLT OrigTy =
MRI.getType(OrigRegs[0]);
391 B.buildMergeValues(OrigRegs[0], Regs);
393 auto Widened =
B.buildMergeLikeInstr(
LLT::scalar(SrcSize), Regs);
394 B.buildTrunc(OrigRegs[0], Widened);
412 CastRegs[0] =
B.buildBitcast(NewTy, Regs[0]).getReg(0);
426 CastRegs[
I++] =
B.buildBitcast(GCDTy, SrcReg).getReg(0);
439 LLT RealDstEltTy =
MRI.getType(OrigRegs[0]).getElementType();
443 if (DstEltTy == PartLLT) {
448 MRI.setType(Reg, RealDstEltTy);
451 B.buildBuildVector(OrigRegs[0], Regs);
462 B.buildMergeLikeInstr(RealDstEltTy, Regs.
take_front(PartsPerElt));
464 MRI.setType(
Merge.getReg(0), RealDstEltTy);
469 B.buildBuildVector(OrigRegs[0], EltMerges);
474 auto BV =
B.buildBuildVector(BVType, Regs);
475 B.buildTrunc(OrigRegs[0], BV);
486 unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
488 assert(SrcTy != PartTy &&
"identical part types shouldn't reach here");
495 B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
503 for (
int i = 0, e = DstRegs.
size(); i != e; ++i)
504 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
513 B.buildPadVectorWithUndefElements(DstReg, SrcReg);
518 if (GCDTy == PartTy) {
520 B.buildUnmerge(DstRegs, SrcReg);
525 LLT DstTy =
MRI.getType(DstRegs[0]);
528 if (PartTy.
isVector() && LCMTy == PartTy) {
530 B.buildPadVectorWithUndefElements(DstRegs[0], SrcReg);
540 if (!LCMTy.
isVector() && CoveringSize != SrcSize) {
543 CoveringSize =
alignTo(SrcSize, DstSize);
545 UnmergeSrc =
B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).
getReg(0);
549 Register Undef =
B.buildUndef(SrcTy).getReg(0);
551 for (
unsigned Size = SrcSize;
Size != CoveringSize;
Size += SrcSize)
553 UnmergeSrc =
B.buildMergeLikeInstr(LCMTy, MergeParts).getReg(0);
557 if (LCMTy.
isVector() && CoveringSize != SrcSize)
558 UnmergeSrc =
B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
560 B.buildUnmerge(DstRegs, UnmergeSrc);
572 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
F.getContext());
582 return TargetOpcode::G_SEXT;
584 return TargetOpcode::G_ZEXT;
585 return TargetOpcode::G_ANYEXT;
594 unsigned NumArgs = Args.size();
595 for (
unsigned i = 0; i != NumArgs; ++i) {
608 Args[i].Flags[0], CCInfo))
625 Args[i].Flags.clear();
627 for (
unsigned Part = 0; Part < NumParts; ++Part) {
633 if (Part == NumParts - 1)
637 Args[i].Flags.push_back(
Flags);
639 Args[i].Flags[Part], CCInfo)) {
660 const unsigned NumArgs = Args.size();
674 SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
676 for (
unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
677 assert(j < ArgLocs.
size() &&
"Skipped too many arg locs");
679 assert(VA.
getValNo() == i &&
"Location doesn't correspond to current arg");
682 std::function<void()> Thunk;
684 Args[i],
ArrayRef(ArgLocs).slice(j), &Thunk);
686 DelayedOutgoingRegAssignments.emplace_back(Thunk);
696 const LLT LocTy(LocVT);
697 const LLT ValTy(ValVT);
705 const unsigned NumParts = Args[i].Flags.size();
708 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
710 if (NumParts != 1 || NewLLT != OrigTy) {
713 Args[i].Regs.resize(NumParts);
718 for (
unsigned Part = 0; Part < NumParts; ++Part)
719 Args[i].Regs[Part] =
MRI.createGenericVirtualRegister(NewLLT);
722 assert((j + (NumParts - 1)) < ArgLocs.
size() &&
723 "Too many regs for number of args");
727 assert(Args[i].OrigRegs.size() == 1);
733 for (
unsigned Part = 0; Part < NumParts; ++Part) {
734 Register ArgReg = Args[i].Regs[Part];
736 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
757 assert(Args[i].Regs.size() == 1 &&
758 "didn't expect split byval pointer");
765 MIRBuilder.
buildCopy(Args[i].Regs[0], StackAddr);
778 if (!Args[i].OrigValue) {
781 const LLT PtrTy =
MRI.getType(StackAddr);
785 Align DstAlign = std::max(
Flags.getNonZeroByValAlign(),
788 Align SrcAlign = std::max(
Flags.getNonZeroByValAlign(),
792 DstMPO, DstAlign, SrcMPO, SrcAlign,
800 if (i == 0 && !ThisReturnRegs.
empty() &&
810 DelayedOutgoingRegAssignments.emplace_back([=, &Handler]() {
822 LocTy, Args[i].
Flags[0]);
827 for (
auto &Fn : DelayedOutgoingRegAssignments)
846 unsigned NumValues = SplitVTs.
size();
848 Type *RetPtrTy =
RetTy->getPointerTo(
DL.getAllocaAddrSpace());
853 for (
unsigned I = 0;
I < NumValues; ++
I) {
857 MRI.getType(VRegs[
I]),
876 unsigned NumValues = SplitVTs.
size();
878 unsigned AS =
DL.getAllocaAddrSpace();
883 for (
unsigned I = 0;
I < NumValues; ++
I) {
887 MRI.getType(VRegs[
I]),
896 unsigned AS =
DL.getAllocaAddrSpace();
897 DemoteReg =
MRI.createGenericVirtualRegister(
911 DemoteArg.
Flags[0].setSRet();
920 unsigned AS =
DL.getAllocaAddrSpace();
930 DemoteArg.
Flags[0].setSRet();
932 Info.OrigArgs.insert(
Info.OrigArgs.begin(), DemoteArg);
933 Info.DemoteStackIndex = FI;
934 Info.DemoteRegister = DemoteReg;
940 for (
unsigned I = 0,
E = Outs.
size();
I <
E; ++
I) {
959 for (
EVT VT : SplitVTs) {
965 for (
unsigned I = 0;
I < NumParts; ++
I) {
973 Type *ReturnType =
F.getReturnType();
986 for (
unsigned i = 0; i < OutLocs.
size(); ++i) {
987 const auto &ArgLoc = OutLocs[i];
989 if (!ArgLoc.isRegLoc())
1000 <<
"... Call has an argument passed in a callee-saved register.\n");
1003 const ArgInfo &OutInfo = OutArgs[i];
1005 if (OutInfo.
Regs.size() > 1) {
1007 dbgs() <<
"... Cannot handle arguments in multiple registers.\n");
1015 if (!RegDef || RegDef->
getOpcode() != TargetOpcode::COPY) {
1018 <<
"... Parameter was not copied into a VReg, cannot tail call.\n");
1024 if (CopyRHS != PhysReg) {
1025 LLVM_DEBUG(
dbgs() <<
"... Callee-saved register was not copied into "
1026 "VReg, cannot tail call.\n");
1043 if (CallerCC == CalleeCC)
1047 CCState CCInfo1(CalleeCC,
Info.IsVarArg, MF, ArgLocs1,
F.getContext());
1052 CCState CCInfo2(CallerCC,
F.isVarArg(), MF, ArgLocs2,
F.getContext());
1058 if (ArgLocs1.
size() != ArgLocs2.
size())
1062 for (
unsigned i = 0, e = ArgLocs1.
size(); i < e; ++i) {
1091 if (ValVT != MVT::iPTR) {
1096 if (
Flags.isPointer()) {
1107 unsigned AddrSpace =
Flags.getPointerAddrSpace();
1127 const LLT PtrTy =
MRI.getType(DstPtr);
1131 MIRBuilder.
buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1136 unsigned MaxSizeBits) {
1140 if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1143 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1144 if (MaxSizeBits <= ValTy.getSizeInBits())
1149 const LLT ValRegTy =
MRI.getType(ValReg);
1169 Register NewReg =
MRI.createGenericVirtualRegister(LocTy);
1174 Register NewReg =
MRI.createGenericVirtualRegister(LocTy);
1182void CallLowering::ValueAssigner::anchor() {}
1230 const LLT LocTy(LocVT);
1231 const LLT RegTy =
MRI.getType(ValVReg);
1238 auto Copy = MIRBuilder.
buildCopy(LocTy, PhysReg);
1239 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT, const ISD::ArgFlagsTy Flags)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy)
Check if we can use a basic COPY instruction between the two types.
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
This file describes how to lower LLVM calls to machine code calls.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static unsigned NumFixedArgs
This file declares the MachineIRBuilder class.
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::FuncInfo FuncInfo
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
const T & front() const
front - Get the first element.
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
StringRef getValueAsString() const
Return the attribute's value as a string.
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
CCState - This class holds information needed while lowering arguments and return values.
CallingConv::ID getCallingConv() const
LLVMContext & getContext() const
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
unsigned getValNo() const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
MaybeAlign getRetAlign() const
Extract the alignment of the return value.
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
CallingConv::ID getCallingConv() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
Value * getCalledOperand() const
FunctionType * getFunctionType() const
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
AttributeList getAttributes() const
Return the parameter attributes for this call.
bool isTailCall() const
Tests if this call site is marked as a tail call.
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
ISD::ArgFlagsTy getAttributesForReturn(const CallBase &Call) const
A parsed version of the target data layout string in and methods for querying it.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr LLT changeElementCount(ElementCount EC) const
Return a vector or scalar with the same element type and the new element count.
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
This is an important class for using LLVM in a threaded context.
Wrapper class representing physical registers. Should be passed by value.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Class to represent pointers.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
iterator insert(iterator I, T &&Elt)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
constexpr ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< TypeSize > *Offsets, TypeSize StartingOffset)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
This struct is a compact representation of a valid (non-zero power of two) alignment.
const Value * OrigValue
Optionally track the original IR value for the argument.
SmallVector< Register, 4 > Regs
unsigned OrigArgIndex
Index original Function's argument.
static const unsigned NoArgIndex
Sentinel value for implicit machine-level input arguments.
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
Provides a default implementation for argument handling.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA)=0
The specified value has been assigned to a stack location.
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
virtual void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.