LLVM  13.0.0git
CallLowering.cpp
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1 //===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements some simple delegations needed for call lowering.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/IR/Instructions.h"
23 #include "llvm/IR/LLVMContext.h"
24 #include "llvm/IR/Module.h"
26 
27 #define DEBUG_TYPE "call-lowering"
28 
29 using namespace llvm;
30 
31 void CallLowering::anchor() {}
32 
33 /// Helper function which updates \p Flags when \p AttrFn returns true.
34 static void
36  const std::function<bool(Attribute::AttrKind)> &AttrFn) {
37  if (AttrFn(Attribute::SExt))
38  Flags.setSExt();
39  if (AttrFn(Attribute::ZExt))
40  Flags.setZExt();
41  if (AttrFn(Attribute::InReg))
42  Flags.setInReg();
43  if (AttrFn(Attribute::StructRet))
44  Flags.setSRet();
45  if (AttrFn(Attribute::Nest))
46  Flags.setNest();
47  if (AttrFn(Attribute::ByVal))
48  Flags.setByVal();
49  if (AttrFn(Attribute::Preallocated))
50  Flags.setPreallocated();
51  if (AttrFn(Attribute::InAlloca))
52  Flags.setInAlloca();
53  if (AttrFn(Attribute::Returned))
54  Flags.setReturned();
55  if (AttrFn(Attribute::SwiftSelf))
56  Flags.setSwiftSelf();
57  if (AttrFn(Attribute::SwiftError))
58  Flags.setSwiftError();
59 }
60 
62  unsigned ArgIdx) const {
63  ISD::ArgFlagsTy Flags;
64  addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
65  return Call.paramHasAttr(ArgIdx, Attr);
66  });
67  return Flags;
68 }
69 
71  const AttributeList &Attrs,
72  unsigned OpIdx) const {
73  addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
74  return Attrs.hasAttribute(OpIdx, Attr);
75  });
76 }
77 
79  ArrayRef<Register> ResRegs,
81  Register SwiftErrorVReg,
82  std::function<unsigned()> GetCalleeReg) const {
84  const DataLayout &DL = MIRBuilder.getDataLayout();
85  MachineFunction &MF = MIRBuilder.getMF();
86  bool CanBeTailCalled = CB.isTailCall() &&
87  isInTailCallPosition(CB, MF.getTarget()) &&
88  (MF.getFunction()
89  .getFnAttribute("disable-tail-calls")
90  .getValueAsString() != "true");
91 
92  CallingConv::ID CallConv = CB.getCallingConv();
93  Type *RetTy = CB.getType();
94  bool IsVarArg = CB.getFunctionType()->isVarArg();
95 
97  getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
98  Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
99 
100  if (!Info.CanLowerReturn) {
101  // Callee requires sret demotion.
102  insertSRetOutgoingArgument(MIRBuilder, CB, Info);
103 
104  // The sret demotion isn't compatible with tail-calls, since the sret
105  // argument points into the caller's stack frame.
106  CanBeTailCalled = false;
107  }
108 
109  // First step is to marshall all the function's parameters into the correct
110  // physregs and memory locations. Gather the sequence of argument types that
111  // we'll pass to the assigner function.
112  unsigned i = 0;
113  unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
114  for (auto &Arg : CB.args()) {
115  ArgInfo OrigArg{ArgRegs[i], *Arg.get(), getAttributesForArgIdx(CB, i),
116  i < NumFixedArgs};
117  setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB);
118 
119  // If we have an explicit sret argument that is an Instruction, (i.e., it
120  // might point to function-local memory), we can't meaningfully tail-call.
121  if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
122  CanBeTailCalled = false;
123 
124  Info.OrigArgs.push_back(OrigArg);
125  ++i;
126  }
127 
128  // Try looking through a bitcast from one function type to another.
129  // Commonly happens with calls to objc_msgSend().
130  const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
131  if (const Function *F = dyn_cast<Function>(CalleeV))
132  Info.Callee = MachineOperand::CreateGA(F, 0);
133  else
134  Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
135 
136  Info.OrigRet = ArgInfo{ResRegs, RetTy, ISD::ArgFlagsTy{}};
137  if (!Info.OrigRet.Ty->isVoidTy())
139 
140  Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
141  Info.CallConv = CallConv;
142  Info.SwiftErrorVReg = SwiftErrorVReg;
143  Info.IsMustTailCall = CB.isMustTailCall();
144  Info.IsTailCall = CanBeTailCalled;
145  Info.IsVarArg = IsVarArg;
146  return lowerCall(MIRBuilder, Info);
147 }
148 
149 template <typename FuncInfoTy>
151  const DataLayout &DL,
152  const FuncInfoTy &FuncInfo) const {
153  auto &Flags = Arg.Flags[0];
154  const AttributeList &Attrs = FuncInfo.getAttributes();
155  addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
156 
157  if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
158  Type *ElementTy = cast<PointerType>(Arg.Ty)->getElementType();
159 
160  auto Ty = Attrs.getAttribute(OpIdx, Attribute::ByVal).getValueAsType();
161  Flags.setByValSize(DL.getTypeAllocSize(Ty ? Ty : ElementTy));
162 
163  // For ByVal, alignment should be passed from FE. BE will guess if
164  // this info is not there but there are cases it cannot get right.
165  Align FrameAlign;
166  if (auto ParamAlign = FuncInfo.getParamAlign(OpIdx - 1))
167  FrameAlign = *ParamAlign;
168  else
169  FrameAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
170  Flags.setByValAlign(FrameAlign);
171  }
172  Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
173 
174  // Don't try to use the returned attribute if the argument is marked as
175  // swiftself, since it won't be passed in x0.
176  if (Flags.isSwiftSelf())
177  Flags.setReturned(false);
178 }
179 
180 template void
181 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
182  const DataLayout &DL,
183  const Function &FuncInfo) const;
184 
185 template void
186 CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
187  const DataLayout &DL,
188  const CallBase &FuncInfo) const;
189 
191  SmallVectorImpl<ArgInfo> &SplitArgs,
192  const DataLayout &DL,
193  CallingConv::ID CallConv) const {
194  LLVMContext &Ctx = OrigArg.Ty->getContext();
195 
196  SmallVector<EVT, 4> SplitVTs;
198  ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
199 
200  if (SplitVTs.size() == 0)
201  return;
202 
203  if (SplitVTs.size() == 1) {
204  // No splitting to do, but we want to replace the original type (e.g. [1 x
205  // double] -> double).
206  SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
207  OrigArg.Flags[0], OrigArg.IsFixed,
208  OrigArg.OrigValue);
209  return;
210  }
211 
212  // Create one ArgInfo for each virtual register in the original ArgInfo.
213  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
214 
215  bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
216  OrigArg.Ty, CallConv, false);
217  for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
218  Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
219  SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
220  OrigArg.IsFixed);
221  if (NeedsRegBlock)
222  SplitArgs.back().Flags[0].setInConsecutiveRegs();
223  }
224 
225  SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
226 }
227 
229  Type *PackedTy,
230  MachineIRBuilder &MIRBuilder) const {
231  assert(DstRegs.size() > 1 && "Nothing to unpack");
232 
233  const DataLayout &DL = MIRBuilder.getDataLayout();
234 
235  SmallVector<LLT, 8> LLTs;
237  computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
238  assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
239 
240  for (unsigned i = 0; i < DstRegs.size(); ++i)
241  MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
242 }
243 
244 /// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
245 static MachineInstrBuilder
247  ArrayRef<Register> SrcRegs) {
248  MachineRegisterInfo &MRI = *B.getMRI();
249  LLT LLTy = MRI.getType(DstRegs[0]);
250  LLT PartLLT = MRI.getType(SrcRegs[0]);
251 
252  // Deal with v3s16 split into v2s16
253  LLT LCMTy = getLCMType(LLTy, PartLLT);
254  if (LCMTy == LLTy) {
255  // Common case where no padding is needed.
256  assert(DstRegs.size() == 1);
257  return B.buildConcatVectors(DstRegs[0], SrcRegs);
258  }
259 
260  // We need to create an unmerge to the result registers, which may require
261  // widening the original value.
262  Register UnmergeSrcReg;
263  if (LCMTy != PartLLT) {
264  // e.g. A <3 x s16> value was split to <2 x s16>
265  // %register_value0:_(<2 x s16>)
266  // %register_value1:_(<2 x s16>)
267  // %undef:_(<2 x s16>) = G_IMPLICIT_DEF
268  // %concat:_<6 x s16>) = G_CONCAT_VECTORS %reg_value0, %reg_value1, %undef
269  // %dst_reg:_(<3 x s16>), %dead:_(<3 x s16>) = G_UNMERGE_VALUES %concat
270  const int NumWide = LCMTy.getSizeInBits() / PartLLT.getSizeInBits();
271  Register Undef = B.buildUndef(PartLLT).getReg(0);
272 
273  // Build vector of undefs.
274  SmallVector<Register, 8> WidenedSrcs(NumWide, Undef);
275 
276  // Replace the first sources with the real registers.
277  std::copy(SrcRegs.begin(), SrcRegs.end(), WidenedSrcs.begin());
278  UnmergeSrcReg = B.buildConcatVectors(LCMTy, WidenedSrcs).getReg(0);
279  } else {
280  // We don't need to widen anything if we're extracting a scalar which was
281  // promoted to a vector e.g. s8 -> v4s8 -> s8
282  assert(SrcRegs.size() == 1);
283  UnmergeSrcReg = SrcRegs[0];
284  }
285 
286  int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
287 
288  SmallVector<Register, 8> PadDstRegs(NumDst);
289  std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
290 
291  // Create the excess dead defs for the unmerge.
292  for (int I = DstRegs.size(); I != NumDst; ++I)
293  PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
294 
295  return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
296 }
297 
298 /// Create a sequence of instructions to combine pieces split into register
299 /// typed values to the original IR value. \p OrigRegs contains the destination
300 /// value registers of type \p LLTy, and \p Regs contains the legalized pieces
301 /// with type \p PartLLT. This is used for incoming values (physregs to vregs).
303  ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) {
304  MachineRegisterInfo &MRI = *B.getMRI();
305 
306  // We could just insert a regular copy, but this is unreachable at the moment.
307  assert(LLTy != PartLLT && "identical part types shouldn't reach here");
308 
309  if (PartLLT.isVector() == LLTy.isVector() &&
310  PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits()) {
311  assert(OrigRegs.size() == 1 && Regs.size() == 1);
312  B.buildTrunc(OrigRegs[0], Regs[0]);
313  return;
314  }
315 
316  if (!LLTy.isVector() && !PartLLT.isVector()) {
317  assert(OrigRegs.size() == 1);
318  LLT OrigTy = MRI.getType(OrigRegs[0]);
319 
320  unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size();
321  if (SrcSize == OrigTy.getSizeInBits())
322  B.buildMerge(OrigRegs[0], Regs);
323  else {
324  auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs);
325  B.buildTrunc(OrigRegs[0], Widened);
326  }
327 
328  return;
329  }
330 
331  if (PartLLT.isVector()) {
332  assert(OrigRegs.size() == 1 &&
333  LLTy.getScalarType() == PartLLT.getElementType());
334  mergeVectorRegsToResultRegs(B, OrigRegs, Regs);
335  return;
336  }
337 
338  assert(LLTy.isVector() && !PartLLT.isVector());
339 
340  LLT DstEltTy = LLTy.getElementType();
341 
342  // Pointer information was discarded. We'll need to coerce some register types
343  // to avoid violating type constraints.
344  LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
345 
346  assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
347 
348  if (DstEltTy == PartLLT) {
349  // Vector was trivially scalarized.
350 
351  if (RealDstEltTy.isPointer()) {
352  for (Register Reg : Regs)
353  MRI.setType(Reg, RealDstEltTy);
354  }
355 
356  B.buildBuildVector(OrigRegs[0], Regs);
357  } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
358  // Deal with vector with 64-bit elements decomposed to 32-bit
359  // registers. Need to create intermediate 64-bit elements.
360  SmallVector<Register, 8> EltMerges;
361  int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
362 
363  assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
364 
365  for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
366  auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt));
367  // Fix the type in case this is really a vector of pointers.
368  MRI.setType(Merge.getReg(0), RealDstEltTy);
369  EltMerges.push_back(Merge.getReg(0));
370  Regs = Regs.drop_front(PartsPerElt);
371  }
372 
373  B.buildBuildVector(OrigRegs[0], EltMerges);
374  } else {
375  // Vector was split, and elements promoted to a wider type.
376  // FIXME: Should handle floating point promotions.
377  LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);
378  auto BV = B.buildBuildVector(BVType, Regs);
379  B.buildTrunc(OrigRegs[0], BV);
380  }
381 }
382 
383 /// Create a sequence of instructions to expand the value in \p SrcReg (of type
384 /// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
385 /// contain the type of scalar value extension if necessary.
386 ///
387 /// This is used for outgoing values (vregs to physregs)
389  Register SrcReg, LLT SrcTy, LLT PartTy,
390  unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
391  // We could just insert a regular copy, but this is unreachable at the moment.
392  assert(SrcTy != PartTy && "identical part types shouldn't reach here");
393 
394  const unsigned PartSize = PartTy.getSizeInBits();
395 
396  if (PartTy.isVector() == SrcTy.isVector() &&
397  PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
398  assert(DstRegs.size() == 1);
399  B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
400  return;
401  }
402 
403  if (SrcTy.isVector() && !PartTy.isVector() &&
404  PartSize > SrcTy.getElementType().getSizeInBits()) {
405  // Vector was scalarized, and the elements extended.
406  auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
407  for (int i = 0, e = DstRegs.size(); i != e; ++i)
408  B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
409  return;
410  }
411 
412  LLT GCDTy = getGCDType(SrcTy, PartTy);
413  if (GCDTy == PartTy) {
414  // If this already evenly divisible, we can create a simple unmerge.
415  B.buildUnmerge(DstRegs, SrcReg);
416  return;
417  }
418 
419  MachineRegisterInfo &MRI = *B.getMRI();
420  LLT DstTy = MRI.getType(DstRegs[0]);
421  LLT LCMTy = getLCMType(SrcTy, PartTy);
422 
423  const unsigned LCMSize = LCMTy.getSizeInBits();
424  const unsigned DstSize = DstTy.getSizeInBits();
425  const unsigned SrcSize = SrcTy.getSizeInBits();
426 
427  Register UnmergeSrc = SrcReg;
428  if (LCMSize != SrcSize) {
429  // Widen to the common type.
430  Register Undef = B.buildUndef(SrcTy).getReg(0);
431  SmallVector<Register, 8> MergeParts(1, SrcReg);
432  for (unsigned Size = SrcSize; Size != LCMSize; Size += SrcSize)
433  MergeParts.push_back(Undef);
434 
435  UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0);
436  }
437 
438  // Unmerge to the original registers and pad with dead defs.
439  SmallVector<Register, 8> UnmergeResults(DstRegs.begin(), DstRegs.end());
440  for (unsigned Size = DstSize * DstRegs.size(); Size != LCMSize;
441  Size += DstSize) {
442  UnmergeResults.push_back(MRI.createGenericVirtualRegister(DstTy));
443  }
444 
445  B.buildUnmerge(UnmergeResults, UnmergeSrc);
446 }
447 
450  ValueHandler &Handler,
451  CallingConv::ID CallConv, bool IsVarArg,
452  Register ThisReturnReg) const {
453  MachineFunction &MF = MIRBuilder.getMF();
454  const Function &F = MF.getFunction();
456 
457  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
458  return handleAssignments(CCInfo, ArgLocs, MIRBuilder, Args, Handler,
459  ThisReturnReg);
460 }
461 
462 static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags) {
463  if (Flags.isSExt())
464  return TargetOpcode::G_SEXT;
465  if (Flags.isZExt())
466  return TargetOpcode::G_ZEXT;
467  return TargetOpcode::G_ANYEXT;
468 }
469 
472  MachineIRBuilder &MIRBuilder,
474  ValueHandler &Handler,
475  Register ThisReturnReg) const {
476  MachineFunction &MF = MIRBuilder.getMF();
478  const Function &F = MF.getFunction();
479  const DataLayout &DL = F.getParent()->getDataLayout();
480 
481  unsigned NumArgs = Args.size();
482  for (unsigned i = 0; i != NumArgs; ++i) {
483  EVT CurVT = EVT::getEVT(Args[i].Ty);
484  if (CurVT.isSimple() &&
485  !Handler.assignArg(i, CurVT.getSimpleVT(), CurVT.getSimpleVT(),
486  CCValAssign::Full, Args[i], Args[i].Flags[0],
487  CCInfo))
488  continue;
489 
490  MVT NewVT = TLI->getRegisterTypeForCallingConv(
491  F.getContext(), CCInfo.getCallingConv(), EVT(CurVT));
492 
493  // If we need to split the type over multiple regs, check it's a scenario
494  // we currently support.
495  unsigned NumParts = TLI->getNumRegistersForCallingConv(
496  F.getContext(), CCInfo.getCallingConv(), CurVT);
497 
498  if (NumParts == 1) {
499  // Try to use the register type if we couldn't assign the VT.
500  if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
501  Args[i].Flags[0], CCInfo))
502  return false;
503 
504  // If we couldn't directly assign this part, some casting may be
505  // necessary. Create the new register, but defer inserting the conversion
506  // instructions.
507  assert(Args[i].OrigRegs.empty());
508  Args[i].OrigRegs.push_back(Args[i].Regs[0]);
509  assert(Args[i].Regs.size() == 1);
510 
511  const LLT VATy(NewVT);
512  Args[i].Regs[0] = MRI.createGenericVirtualRegister(VATy);
513  continue;
514  }
515 
516  const LLT NewLLT(NewVT);
517 
518  // For incoming arguments (physregs to vregs), we could have values in
519  // physregs (or memlocs) which we want to extract and copy to vregs.
520  // During this, we might have to deal with the LLT being split across
521  // multiple regs, so we have to record this information for later.
522  //
523  // If we have outgoing args, then we have the opposite case. We have a
524  // vreg with an LLT which we want to assign to a physical location, and
525  // we might have to record that the value has to be split later.
526  if (Handler.isIncomingArgumentHandler()) {
527  // We're handling an incoming arg which is split over multiple regs.
528  // E.g. passing an s128 on AArch64.
529  ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
530  Args[i].OrigRegs.push_back(Args[i].Regs[0]);
531  Args[i].Regs.clear();
532  Args[i].Flags.clear();
533  // For each split register, create and assign a vreg that will store
534  // the incoming component of the larger value. These will later be
535  // merged to form the final vreg.
536  for (unsigned Part = 0; Part < NumParts; ++Part) {
538  ISD::ArgFlagsTy Flags = OrigFlags;
539  if (Part == 0) {
540  Flags.setSplit();
541  } else {
542  Flags.setOrigAlign(Align(1));
543  if (Part == NumParts - 1)
544  Flags.setSplitEnd();
545  }
546  Args[i].Regs.push_back(Reg);
547  Args[i].Flags.push_back(Flags);
548  if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full, Args[i],
549  Args[i].Flags[Part], CCInfo)) {
550  // Still couldn't assign this smaller part type for some reason.
551  return false;
552  }
553  }
554  } else {
555  assert(Args[i].Regs.size() == 1);
556 
557  // This type is passed via multiple registers in the calling convention.
558  // We need to extract the individual parts.
559  assert(Args[i].OrigRegs.empty());
560  Args[i].OrigRegs.push_back(Args[i].Regs[0]);
561 
562  ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
563  // We're going to replace the regs and flags with the split ones.
564  Args[i].Regs.clear();
565  Args[i].Flags.clear();
566  for (unsigned PartIdx = 0; PartIdx < NumParts; ++PartIdx) {
567  ISD::ArgFlagsTy Flags = OrigFlags;
568  if (PartIdx == 0) {
569  Flags.setSplit();
570  } else {
571  Flags.setOrigAlign(Align(1));
572  if (PartIdx == NumParts - 1)
573  Flags.setSplitEnd();
574  }
575 
576  // TODO: Also check if there is a valid extension that preserves the
577  // bits. However currently this call lowering doesn't support non-exact
578  // split parts, so that can't be tested.
579  if (OrigFlags.isReturned() &&
580  (NumParts * NewVT.getSizeInBits() != CurVT.getSizeInBits())) {
581  Flags.setReturned(false);
582  }
583 
584  Register NewReg = MRI.createGenericVirtualRegister(NewLLT);
585 
586  Args[i].Regs.push_back(NewReg);
587  Args[i].Flags.push_back(Flags);
588  if (Handler.assignArg(i, NewVT, NewVT, CCValAssign::Full,
589  Args[i], Args[i].Flags[PartIdx], CCInfo))
590  return false;
591  }
592  }
593  }
594 
595  for (unsigned i = 0, e = Args.size(), j = 0; i != e; ++i, ++j) {
596  assert(j < ArgLocs.size() && "Skipped too many arg locs");
597 
598  CCValAssign &VA = ArgLocs[j];
599  assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
600 
601  if (VA.needsCustom()) {
602  unsigned NumArgRegs =
603  Handler.assignCustomValue(Args[i], makeArrayRef(ArgLocs).slice(j));
604  if (!NumArgRegs)
605  return false;
606  j += NumArgRegs;
607  continue;
608  }
609 
610  EVT VAVT = VA.getValVT();
611  const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
612  const LLT VATy(VAVT.getSimpleVT());
613 
614  // Expected to be multiple regs for a single incoming arg.
615  // There should be Regs.size() ArgLocs per argument.
616  unsigned NumArgRegs = Args[i].Regs.size();
617  assert((j + (NumArgRegs - 1)) < ArgLocs.size() &&
618  "Too many regs for number of args");
619 
620  // Coerce into outgoing value types before register assignment.
621  if (!Handler.isIncomingArgumentHandler() && OrigTy != VATy) {
622  assert(Args[i].OrigRegs.size() == 1);
623  buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
624  VATy, extendOpFromFlags(Args[i].Flags[0]));
625  }
626 
627  for (unsigned Part = 0; Part < NumArgRegs; ++Part) {
628  Register ArgReg = Args[i].Regs[Part];
629  // There should be Regs.size() ArgLocs per argument.
630  VA = ArgLocs[j + Part];
631  const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
632 
633  if (VA.isMemLoc() && !Flags.isByVal()) {
634  // Individual pieces may have been spilled to the stack and others
635  // passed in registers.
636 
637  // FIXME: Use correct address space for pointer size
638  EVT LocVT = VA.getValVT();
639  unsigned MemSize = LocVT == MVT::iPTR ? DL.getPointerSize()
640  : LocVT.getStoreSize();
641  unsigned Offset = VA.getLocMemOffset();
642  MachinePointerInfo MPO;
643  Register StackAddr =
644  Handler.getStackAddress(MemSize, Offset, MPO, Flags);
645  Handler.assignValueToAddress(Args[i], Part, StackAddr, MemSize, MPO,
646  VA);
647  continue;
648  }
649 
650  if (VA.isMemLoc() && Flags.isByVal()) {
651  assert(Args[i].Regs.size() == 1 &&
652  "didn't expect split byval pointer");
653 
654  if (Handler.isIncomingArgumentHandler()) {
655  // We just need to copy the frame index value to the pointer.
656  MachinePointerInfo MPO;
657  Register StackAddr = Handler.getStackAddress(
658  Flags.getByValSize(), VA.getLocMemOffset(), MPO, Flags);
659  MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
660  } else {
661  // For outgoing byval arguments, insert the implicit copy byval
662  // implies, such that writes in the callee do not modify the caller's
663  // value.
664  uint64_t MemSize = Flags.getByValSize();
665  int64_t Offset = VA.getLocMemOffset();
666 
667  MachinePointerInfo DstMPO;
668  Register StackAddr =
669  Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
670 
671  MachinePointerInfo SrcMPO(Args[i].OrigValue);
672  if (!Args[i].OrigValue) {
673  // We still need to accurately track the stack address space if we
674  // don't know the underlying value.
675  const LLT PtrTy = MRI.getType(StackAddr);
676  SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
677  }
678 
679  Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
680  inferAlignFromPtrInfo(MF, DstMPO));
681 
682  Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
683  inferAlignFromPtrInfo(MF, SrcMPO));
684 
685  Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
686  DstMPO, DstAlign, SrcMPO, SrcAlign,
687  MemSize, VA);
688  }
689  continue;
690  }
691 
692  assert(!VA.needsCustom() && "custom loc should have been handled already");
693 
694  if (i == 0 && ThisReturnReg.isValid() &&
695  Handler.isIncomingArgumentHandler() &&
697  Handler.assignValueToReg(Args[i].Regs[i], ThisReturnReg, VA);
698  continue;
699  }
700 
701  Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
702  }
703 
704  // Now that all pieces have been assigned, re-pack the register typed values
705  // into the original value typed registers.
706  if (Handler.isIncomingArgumentHandler() && OrigTy != VATy) {
707  // Merge the split registers into the expected larger result vregs of
708  // the original call.
709  buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
710  VATy);
711  }
712 
713  j += NumArgRegs - 1;
714  }
715 
716  return true;
717 }
718 
720  ArrayRef<Register> VRegs, Register DemoteReg,
721  int FI) const {
722  MachineFunction &MF = MIRBuilder.getMF();
724  const DataLayout &DL = MF.getDataLayout();
725 
726  SmallVector<EVT, 4> SplitVTs;
728  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
729 
730  assert(VRegs.size() == SplitVTs.size());
731 
732  unsigned NumValues = SplitVTs.size();
733  Align BaseAlign = DL.getPrefTypeAlign(RetTy);
734  Type *RetPtrTy = RetTy->getPointerTo(DL.getAllocaAddrSpace());
735  LLT OffsetLLTy = getLLTForType(*DL.getIntPtrType(RetPtrTy), DL);
736 
738 
739  for (unsigned I = 0; I < NumValues; ++I) {
740  Register Addr;
741  MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
742  auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
743  MRI.getType(VRegs[I]).getSizeInBytes(),
744  commonAlignment(BaseAlign, Offsets[I]));
745  MIRBuilder.buildLoad(VRegs[I], Addr, *MMO);
746  }
747 }
748 
750  ArrayRef<Register> VRegs,
751  Register DemoteReg) const {
752  MachineFunction &MF = MIRBuilder.getMF();
754  const DataLayout &DL = MF.getDataLayout();
755 
756  SmallVector<EVT, 4> SplitVTs;
758  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
759 
760  assert(VRegs.size() == SplitVTs.size());
761 
762  unsigned NumValues = SplitVTs.size();
763  Align BaseAlign = DL.getPrefTypeAlign(RetTy);
764  unsigned AS = DL.getAllocaAddrSpace();
765  LLT OffsetLLTy =
766  getLLTForType(*DL.getIntPtrType(RetTy->getPointerTo(AS)), DL);
767 
768  MachinePointerInfo PtrInfo(AS);
769 
770  for (unsigned I = 0; I < NumValues; ++I) {
771  Register Addr;
772  MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
773  auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
774  MRI.getType(VRegs[I]).getSizeInBytes(),
775  commonAlignment(BaseAlign, Offsets[I]));
776  MIRBuilder.buildStore(VRegs[I], Addr, *MMO);
777  }
778 }
779 
781  const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
782  MachineRegisterInfo &MRI, const DataLayout &DL) const {
783  unsigned AS = DL.getAllocaAddrSpace();
784  DemoteReg = MRI.createGenericVirtualRegister(
785  LLT::pointer(AS, DL.getPointerSizeInBits(AS)));
786 
787  Type *PtrTy = PointerType::get(F.getReturnType(), AS);
788 
789  SmallVector<EVT, 1> ValueVTs;
790  ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs);
791 
792  // NOTE: Assume that a pointer won't get split into more than one VT.
793  assert(ValueVTs.size() == 1);
794 
795  ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()));
797  DemoteArg.Flags[0].setSRet();
798  SplitArgs.insert(SplitArgs.begin(), DemoteArg);
799 }
800 
802  const CallBase &CB,
803  CallLoweringInfo &Info) const {
804  const DataLayout &DL = MIRBuilder.getDataLayout();
805  Type *RetTy = CB.getType();
806  unsigned AS = DL.getAllocaAddrSpace();
807  LLT FramePtrTy = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
808 
809  int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
810  DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false);
811 
812  Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0);
813  ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS));
814  setArgFlags(DemoteArg, AttributeList::ReturnIndex, DL, CB);
815  DemoteArg.Flags[0].setSRet();
816 
817  Info.OrigArgs.insert(Info.OrigArgs.begin(), DemoteArg);
818  Info.DemoteStackIndex = FI;
819  Info.DemoteRegister = DemoteReg;
820 }
821 
824  CCAssignFn *Fn) const {
825  for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
826  MVT VT = MVT::getVT(Outs[I].Ty);
827  if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo))
828  return false;
829  }
830  return true;
831 }
832 
836  const DataLayout &DL) const {
837  LLVMContext &Context = RetTy->getContext();
839 
840  SmallVector<EVT, 4> SplitVTs;
841  ComputeValueVTs(*TLI, DL, RetTy, SplitVTs);
843 
844  for (EVT VT : SplitVTs) {
845  unsigned NumParts =
846  TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
847  MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
848  Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
849 
850  for (unsigned I = 0; I < NumParts; ++I) {
851  Outs.emplace_back(PartTy, Flags);
852  }
853  }
854 }
855 
857  const auto &F = MF.getFunction();
858  Type *ReturnType = F.getReturnType();
859  CallingConv::ID CallConv = F.getCallingConv();
860 
861  SmallVector<BaseArgInfo, 4> SplitArgs;
862  getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
863  MF.getDataLayout());
864  return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
865 }
866 
869  CCAssignFn &AssignFnFixed,
870  CCAssignFn &AssignFnVarArg) const {
871  for (unsigned i = 0, e = Args.size(); i < e; ++i) {
872  MVT VT = MVT::getVT(Args[i].Ty);
873  CCAssignFn &Fn = Args[i].IsFixed ? AssignFnFixed : AssignFnVarArg;
874  if (Fn(i, VT, VT, CCValAssign::Full, Args[i].Flags[0], CCState)) {
875  // Bail out on anything we can't handle.
876  LLVM_DEBUG(dbgs() << "Cannot analyze " << EVT(VT).getEVTString()
877  << " (arg number = " << i << "\n");
878  return false;
879  }
880  }
881  return true;
882 }
883 
885  const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
886  const SmallVectorImpl<CCValAssign> &OutLocs,
887  const SmallVectorImpl<ArgInfo> &OutArgs) const {
888  for (unsigned i = 0; i < OutLocs.size(); ++i) {
889  auto &ArgLoc = OutLocs[i];
890  // If it's not a register, it's fine.
891  if (!ArgLoc.isRegLoc())
892  continue;
893 
894  MCRegister PhysReg = ArgLoc.getLocReg();
895 
896  // Only look at callee-saved registers.
897  if (MachineOperand::clobbersPhysReg(CallerPreservedMask, PhysReg))
898  continue;
899 
900  LLVM_DEBUG(
901  dbgs()
902  << "... Call has an argument passed in a callee-saved register.\n");
903 
904  // Check if it was copied from.
905  const ArgInfo &OutInfo = OutArgs[i];
906 
907  if (OutInfo.Regs.size() > 1) {
908  LLVM_DEBUG(
909  dbgs() << "... Cannot handle arguments in multiple registers.\n");
910  return false;
911  }
912 
913  // Check if we copy the register, walking through copies from virtual
914  // registers. Note that getDefIgnoringCopies does not ignore copies from
915  // physical registers.
916  MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
917  if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
918  LLVM_DEBUG(
919  dbgs()
920  << "... Parameter was not copied into a VReg, cannot tail call.\n");
921  return false;
922  }
923 
924  // Got a copy. Verify that it's the same as the register we want.
925  Register CopyRHS = RegDef->getOperand(1).getReg();
926  if (CopyRHS != PhysReg) {
927  LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
928  "VReg, cannot tail call.\n");
929  return false;
930  }
931  }
932 
933  return true;
934 }
935 
937  MachineFunction &MF,
938  SmallVectorImpl<ArgInfo> &InArgs,
939  CCAssignFn &CalleeAssignFnFixed,
940  CCAssignFn &CalleeAssignFnVarArg,
941  CCAssignFn &CallerAssignFnFixed,
942  CCAssignFn &CallerAssignFnVarArg) const {
943  const Function &F = MF.getFunction();
944  CallingConv::ID CalleeCC = Info.CallConv;
945  CallingConv::ID CallerCC = F.getCallingConv();
946 
947  if (CallerCC == CalleeCC)
948  return true;
949 
951  CCState CCInfo1(CalleeCC, false, MF, ArgLocs1, F.getContext());
952  if (!analyzeArgInfo(CCInfo1, InArgs, CalleeAssignFnFixed,
953  CalleeAssignFnVarArg))
954  return false;
955 
957  CCState CCInfo2(CallerCC, false, MF, ArgLocs2, F.getContext());
958  if (!analyzeArgInfo(CCInfo2, InArgs, CallerAssignFnFixed,
959  CalleeAssignFnVarArg))
960  return false;
961 
962  // We need the argument locations to match up exactly. If there's more in
963  // one than the other, then we are done.
964  if (ArgLocs1.size() != ArgLocs2.size())
965  return false;
966 
967  // Make sure that each location is passed in exactly the same way.
968  for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
969  const CCValAssign &Loc1 = ArgLocs1[i];
970  const CCValAssign &Loc2 = ArgLocs2[i];
971 
972  // We need both of them to be the same. So if one is a register and one
973  // isn't, we're done.
974  if (Loc1.isRegLoc() != Loc2.isRegLoc())
975  return false;
976 
977  if (Loc1.isRegLoc()) {
978  // If they don't have the same register location, we're done.
979  if (Loc1.getLocReg() != Loc2.getLocReg())
980  return false;
981 
982  // They matched, so we can move to the next ArgLoc.
983  continue;
984  }
985 
986  // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
987  if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
988  return false;
989  }
990 
991  return true;
992 }
993 
995  const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
996  const MachinePointerInfo &DstPtrInfo, Align DstAlign,
997  const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
998  CCValAssign &VA) const {
1001  SrcPtrInfo,
1003  SrcAlign);
1004 
1006  DstPtrInfo,
1008  MemSize, DstAlign);
1009 
1010  const LLT PtrTy = MRI.getType(DstPtr);
1011  const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
1012 
1013  auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
1014  MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1015 }
1016 
1018  CCValAssign &VA,
1019  unsigned MaxSizeBits) {
1020  LLT LocTy{VA.getLocVT()};
1021  LLT ValTy = MRI.getType(ValReg);
1022  if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1023  return ValReg;
1024 
1025  if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1026  if (MaxSizeBits <= ValTy.getSizeInBits())
1027  return ValReg;
1028  LocTy = LLT::scalar(MaxSizeBits);
1029  }
1030 
1031  switch (VA.getLocInfo()) {
1032  default: break;
1033  case CCValAssign::Full:
1034  case CCValAssign::BCvt:
1035  // FIXME: bitconverting between vector types may or may not be a
1036  // nop in big-endian situations.
1037  return ValReg;
1038  case CCValAssign::AExt: {
1039  auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1040  return MIB.getReg(0);
1041  }
1042  case CCValAssign::SExt: {
1043  Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1044  MIRBuilder.buildSExt(NewReg, ValReg);
1045  return NewReg;
1046  }
1047  case CCValAssign::ZExt: {
1048  Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1049  MIRBuilder.buildZExt(NewReg, ValReg);
1050  return NewReg;
1051  }
1052  }
1053  llvm_unreachable("unable to extend register");
1054 }
1055 
1056 void CallLowering::ValueHandler::anchor() {}
1057 
1059  Register SrcReg,
1060  LLT NarrowTy) {
1061  switch (VA.getLocInfo()) {
1062  case CCValAssign::LocInfo::ZExt: {
1063  return MIRBuilder
1064  .buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1065  NarrowTy.getScalarSizeInBits())
1066  .getReg(0);
1067  }
1068  case CCValAssign::LocInfo::SExt: {
1069  return MIRBuilder
1070  .buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1071  NarrowTy.getScalarSizeInBits())
1072  .getReg(0);
1073  break;
1074  }
1075  default:
1076  return SrcReg;
1077  }
1078 }
1079 
1081  Register PhysReg,
1082  CCValAssign &VA) {
1083  const LLT LocTy(VA.getLocVT());
1084  const LLT ValTy = MRI.getType(ValVReg);
1085 
1086  if (ValTy.getSizeInBits() == LocTy.getSizeInBits()) {
1087  MIRBuilder.buildCopy(ValVReg, PhysReg);
1088  return;
1089  }
1090 
1091  auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
1092  auto Hint = buildExtensionHint(VA, Copy.getReg(0), ValTy);
1093  MIRBuilder.buildTrunc(ValVReg, Hint);
1094 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
i
i
Definition: README.txt:29
llvm::ISD::ArgFlagsTy::isInAlloca
bool isInAlloca() const
Definition: TargetCallingConv.h:94
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::ISD::ArgFlagsTy::isReturned
bool isReturned() const
Definition: TargetCallingConv.h:121
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:396
Merge
R600 Clause Merge
Definition: R600ClauseMergePass.cpp:69
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:788
llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
Definition: TargetLowering.h:3986
llvm::ISD::ArgFlagsTy::setSwiftSelf
void setSwiftSelf()
Definition: TargetCallingConv.h:101
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:163
llvm::ISD::ArgFlagsTy::setNest
void setNest()
Definition: TargetCallingConv.h:119
CallLowering.h
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
buildCopyToRegs
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
Definition: CallLowering.cpp:388
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Function
Definition: Function.h:61
llvm::PointerType::get
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Definition: Type.cpp:693
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::CallLowering::ValueHandler::extendRegister
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
Definition: CallLowering.cpp:1017
llvm::CallLowering::ValueHandler
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:145
llvm::CallLowering::insertSRetOutgoingArgument
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
Definition: CallLowering.cpp:801
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:121
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:76
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::CallLowering::ValueHandler::assignValueToReg
virtual void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Module.h
llvm::AttributeList
Definition: Attributes.h:375
llvm::CallBase::getAttributes
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1472
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1244
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
extendOpFromFlags
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
Definition: CallLowering.cpp:462
llvm::CallBase::isMustTailCall
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: Instructions.cpp:294
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::CallLowering::ValueHandler::assignCustomValue
virtual unsigned assignCustomValue(const ArgInfo &Arg, ArrayRef< CCValAssign > VAs)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:195
buildCopyFromRegs
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
Definition: CallLowering.cpp:302
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
MachineIRBuilder.h
llvm::CallLowering::ValueHandler::getStackAddress
virtual Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:255
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::FunctionType::isVarArg
bool isVarArg() const
Definition: DerivedTypes.h:122
llvm::ISD::ArgFlagsTy::isSwiftSelf
bool isSwiftSelf() const
Definition: TargetCallingConv.h:100
MachineRegisterInfo.h
llvm::CallLowering::ValueHandler::assignArg
virtual bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Definition: CallLowering.h:215
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:21
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
TargetLowering.h
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:796
llvm::EVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:355
llvm::CallLowering::getTLI
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
Definition: CallLowering.h:252
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::CallLowering::analyzeArgInfo
bool analyzeArgInfo(CCState &CCState, SmallVectorImpl< ArgInfo > &Args, CCAssignFn &AssignFnFixed, CCAssignFn &AssignFnVarArg) const
Analyze passed or returned values from a call, supplied in ArgInfo, incorporating info about the pass...
Definition: CallLowering.cpp:867
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
TargetMachine.h
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:426
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:840
llvm::ISD::ArgFlagsTy::setReturned
void setReturned(bool V=true)
Definition: TargetCallingConv.h:122
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:182
llvm::CallLowering::checkReturnTypeForCallConv
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
Definition: CallLowering.cpp:856
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:88
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::CallLowering::ValueHandler::assignValueToAddress
virtual void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, MachinePointerInfo &MPO, CCValAssign &VA)=0
The specified value has been assigned to a stack location.
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
mergeVectorRegsToResultRegs
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
Definition: CallLowering.cpp:246
llvm::LLT::getSizeInBytes
unsigned getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:117
llvm::CallLowering::handleAssignments
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke Handler::assignArg on each of the given Args and then use Handler to move them to the assigned...
Definition: CallLowering.cpp:448
Utils.h
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:280
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::LLT::vector
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:58
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:83
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallBase::getCallingConv
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1453
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:297
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:95
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:277
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:80
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:239
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:178
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:751
llvm::CallLowering::isTypeIsValidForThisReturn
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: CallLowering.h:493
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:378
llvm::ISD::ArgFlagsTy::setSplit
void setSplit()
Definition: TargetCallingConv.h:133
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:614
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1498
llvm::CallBase::isTailCall
bool isTailCall() const
Tests if this call site is marked as a tail call.
Definition: Instructions.cpp:301
llvm::ArrayRef::drop_front
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:202
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.cpp:243
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:822
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.cpp:249
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:600
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:529
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
llvm::Attribute::AttrKind
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
Definition: Attributes.h:71
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:96
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:100
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(Align A)
Definition: TargetCallingConv.h:172
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:259
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:94
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:815
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::ISD::ArgFlagsTy::setSwiftError
void setSwiftError()
Definition: TargetCallingConv.h:104
llvm::Function::hasAttribute
bool hasAttribute(unsigned i, Attribute::AttrKind Kind) const
check if an attributes is in the list of attributes.
Definition: Function.h:434
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::ISD::ArgFlagsTy::setByVal
void setByVal()
Definition: TargetCallingConv.h:89
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
llvm::CallLowering::addArgFlagsFromAttributes
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
Definition: CallLowering.cpp:70
llvm::MachineFunction
Definition: MachineFunction.h:227
addFlagsUsingAttrFn
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
Definition: CallLowering.cpp:35
llvm::ISD::ArgFlagsTy::setByValSize
void setByValSize(unsigned S)
Definition: TargetCallingConv.h:181
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:142
llvm::CallLowering::ValueHandler::copyArgumentMemory
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
Definition: CallLowering.cpp:994
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:847
DataLayout.h
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::ISD::ArgFlagsTy::setInAlloca
void setInAlloca()
Definition: TargetCallingConv.h:95
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:719
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::ISD::ArgFlagsTy::setSplitEnd
void setSplitEnd()
Definition: TargetCallingConv.h:136
uint32_t
llvm::ISD::ArgFlagsTy::isPreallocated
bool isPreallocated() const
Definition: TargetCallingConv.h:97
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:518
llvm::ISD::ArgFlagsTy::setByValAlign
void setByValAlign(Align A)
Definition: TargetCallingConv.h:154
llvm::MVT::iPTR
@ iPTR
Definition: MachineValueType.h:295
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:416
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:193
llvm::Value::stripPointerCasts
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:636
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
NumFixedArgs
static unsigned NumFixedArgs
Definition: LanaiISelLowering.cpp:368
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:780
llvm::CallLowering::unpackRegs
void unpackRegs(ArrayRef< Register > DstRegs, Register SrcReg, Type *PackedTy, MachineIRBuilder &MIRBuilder) const
Generate instructions for unpacking SrcReg into the DstRegs corresponding to the aggregate type Packe...
Definition: CallLowering.cpp:228
llvm::CallLowering::getAttributesForArgIdx
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
Definition: CallLowering.cpp:61
llvm::computeValueLLTs
void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
computeValueLLTs - Given an LLVM IR type, compute a sequence of LLTs that represent all the individua...
Definition: Analysis.cpp:132
j
return j(j<< 16)
llvm::CallLowering::canLowerReturn
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: CallLowering.h:397
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:146
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:749
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:221
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:177
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:737
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1840
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:222
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::ArrayRef::take_front
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:226
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:355
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
llvm::CallLowering::IncomingValueHandler::assignValueToReg
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign &VA) override
Provides a default implementation for argument handling.
Definition: CallLowering.cpp:1080
llvm::Attribute::getValueAsType
Type * getValueAsType() const
Return the attribute's value as a Type.
Definition: Attributes.cpp:304
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:79
llvm::CallLowering::ArgInfo::Regs
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:62
llvm::CallLowering::BaseArgInfo::Ty
Type * Ty
Definition: CallLowering.h:49
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:715
llvm::CallLowering::IncomingValueHandler::buildExtensionHint
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
Definition: CallLowering.cpp:1058
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:221
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1389
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, CCAssignFn &CalleeAssignFnFixed, CCAssignFn &CalleeAssignFnVarArg, CCAssignFn &CallerAssignFnFixed, CCAssignFn &CallerAssignFnVarArg) const
Definition: CallLowering.cpp:936
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:190
Instructions.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::MachineRegisterInfo::cloneVirtualRegister
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Definition: MachineRegisterInfo.cpp:172
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:149
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:421
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::ISD::ArgFlagsTy::setSRet
void setSRet()
Definition: TargetCallingConv.h:86
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1490
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:497
llvm::isInTailCallPosition
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:501
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::Function::getAttribute
Attribute getAttribute(unsigned i, Attribute::AttrKind Kind) const
gets the attribute from the list of attributes.
Definition: Function.h:449
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallLowering::getReturnInfo
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
Definition: CallLowering.cpp:833
MachineOperand.h
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1164
llvm::CallLowering::BaseArgInfo::IsFixed
bool IsFixed
Definition: CallLowering.h:51
llvm::ISD::ArgFlagsTy::setPreallocated
void setPreallocated()
Definition: TargetCallingConv.h:98
llvm::CallLowering::ArgInfo::OrigValue
const Value * OrigValue
Optionally track the original IR value for the argument.
Definition: CallLowering.h:72
LLVMContext.h
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:388
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:188
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1224
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:884
copy
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local copy
Definition: README.txt:124
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:380
llvm::CallLowering::ValueHandler::isIncomingArgumentHandler
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
Definition: CallLowering.h:155
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::CCValAssign::needsCustom
bool needsCustom() const
Definition: CallingConvLower.h:148
llvm::CallBase::args
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1322
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:77
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:773
llvm::CallLowering::BaseArgInfo::Flags
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:50
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::lowerCall
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:457
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:150