29#define DEBUG_TYPE "ppc-vsx-copy"
53 return IsRegInClass(
Reg, &PPC::VSRCRegClass,
MRI);
57 return IsRegInClass(
Reg, &PPC::VRRCRegClass,
MRI);
61 return IsRegInClass(
Reg, &PPC::F8RCRegClass,
MRI);
65 return IsRegInClass(
Reg, &PPC::VSFRCRegClass,
MRI);
69 return IsRegInClass(
Reg, &PPC::VSSRCRegClass,
MRI);
91 "Unknown source for a VSX copy");
93 Register NewVReg =
MRI.createVirtualRegister(SrcRC);
95 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
103 }
else if (!IsVSReg(DstMO.
getReg(),
MRI) &&
111 "Unknown destination for a VSX copy");
114 Register NewVReg =
MRI.createVirtualRegister(DstRC);
122 }
else if (IsRegInClass(DstMO.
getReg(), &PPC::WACC_HIRCRegClass,
MRI) &&
123 IsRegInClass(SrcMO.
getReg(), &PPC::WACCRCRegClass,
MRI)) {
135 if (!IsRegInClass(OrigSrc.
getReg(), &PPC::DMRRCRegClass,
MRI))
138 if (OrigSrc.
getSubReg() != PPC::sub_wacc_hi)
147 if (
MRI.use_nodbg_empty(
DefMI->getOperand(0).getReg()))
148 DefMI->eraseFromParent();
181char PPCVSXWACCCopy::
ID = 0;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const HexagonInstrInfo * TII
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const PPCInstrInfo * getInstrInfo() const override
Wrapper class representing virtual and physical registers.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createPPCVSXWACCCopyPass()