LLVM 24.0.0git
RISCVExpandPseudoPreEmit.cpp
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1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains one of the four passes that expand pseudo instructions
10// into target instructions. This pass is run very late, but before atomic
11// instructions are expanded.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVExpandPseudoBase.h"
17#include "RISCVInstrInfo.h"
18#include "RISCVSubtarget.h"
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22
23using namespace llvm;
24
25#define RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME \
26 "RISC-V Pseudo Instruction Expansion - Pre-Emit"
27
28namespace {
29
30class RISCVExpandPseudoPreEmitImpl final : public RISCVExpandPseudoImplBase {
31 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
32 MachineBasicBlock::iterator &NextMBBI) const override;
33
34 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
35 MachineBasicBlock::iterator &NextMBBI) const;
36
37 bool expandCCOpToCMov(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MBBI) const;
39
40 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator MBBI,
42 unsigned Opcode) const;
43
44 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MBBI) const;
46
47 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
48 MachineBasicBlock::iterator MBBI) const;
49
50 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI) const;
52
53 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI) const;
55
56 bool
57 expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI) const;
59
60 bool expandPseudoClearFPR64(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI) const;
62};
63
64class RISCVExpandPseudoPreEmitLegacy : public MachineFunctionPass {
65public:
66 static char ID;
67
68 RISCVExpandPseudoPreEmitLegacy() : MachineFunctionPass(ID) {}
69
70 bool runOnMachineFunction(MachineFunction &MF) override {
71 return RISCVExpandPseudoPreEmitImpl().run(MF);
72 }
73
74 StringRef getPassName() const override {
75 return RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME;
76 }
77};
78
79} // anonymous namespace
80
81bool RISCVExpandPseudoPreEmitImpl::expandMI(
82 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
83 MachineBasicBlock::iterator &NextMBBI) const {
84 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
85 // expanded instructions for each pseudo is correct in the Size field of the
86 // tablegen definition for the pseudo.
87 switch (MBBI->getOpcode()) {
88 case RISCV::PseudoMV_FPR16INX:
89 return expandMV_FPR16INX(MBB, MBBI);
90 case RISCV::PseudoMV_FPR32INX:
91 return expandMV_FPR32INX(MBB, MBBI);
92 case RISCV::PseudoRV32ZdinxSD:
93 return expandRV32ZdinxStore(MBB, MBBI);
94 case RISCV::PseudoRV32ZdinxLD:
95 return expandRV32ZdinxLoad(MBB, MBBI);
96 case RISCV::PseudoCCMOVGPRNoX0:
97 case RISCV::PseudoCCMOVGPR:
98 case RISCV::PseudoCCADD:
99 case RISCV::PseudoCCSUB:
100 case RISCV::PseudoCCAND:
101 case RISCV::PseudoCCOR:
102 case RISCV::PseudoCCXOR:
103 case RISCV::PseudoCCMAX:
104 case RISCV::PseudoCCMAXU:
105 case RISCV::PseudoCCMIN:
106 case RISCV::PseudoCCMINU:
107 case RISCV::PseudoCCMUL:
108 case RISCV::PseudoCCLUI:
109 case RISCV::PseudoCCQC_E_LB:
110 case RISCV::PseudoCCQC_E_LH:
111 case RISCV::PseudoCCQC_E_LW:
112 case RISCV::PseudoCCQC_E_LHU:
113 case RISCV::PseudoCCQC_E_LBU:
114 case RISCV::PseudoCCLB:
115 case RISCV::PseudoCCLH:
116 case RISCV::PseudoCCLW:
117 case RISCV::PseudoCCLHU:
118 case RISCV::PseudoCCLBU:
119 case RISCV::PseudoCCLWU:
120 case RISCV::PseudoCCLD:
121 case RISCV::PseudoCCQC_LI:
122 case RISCV::PseudoCCQC_E_LI:
123 case RISCV::PseudoCCADDW:
124 case RISCV::PseudoCCSUBW:
125 case RISCV::PseudoCCSLL:
126 case RISCV::PseudoCCSRL:
127 case RISCV::PseudoCCSRA:
128 case RISCV::PseudoCCADDI:
129 case RISCV::PseudoCCSLLI:
130 case RISCV::PseudoCCSRLI:
131 case RISCV::PseudoCCSRAI:
132 case RISCV::PseudoCCANDI:
133 case RISCV::PseudoCCORI:
134 case RISCV::PseudoCCXORI:
135 case RISCV::PseudoCCSLLW:
136 case RISCV::PseudoCCSRLW:
137 case RISCV::PseudoCCSRAW:
138 case RISCV::PseudoCCADDIW:
139 case RISCV::PseudoCCSLLIW:
140 case RISCV::PseudoCCSRLIW:
141 case RISCV::PseudoCCSRAIW:
142 case RISCV::PseudoCCANDN:
143 case RISCV::PseudoCCORN:
144 case RISCV::PseudoCCXNOR:
145 case RISCV::PseudoCCNDS_BFOS:
146 case RISCV::PseudoCCNDS_BFOZ:
147 return expandCCOp(MBB, MBBI, NextMBBI);
148 case RISCV::PseudoVMCLR_M_B1:
149 case RISCV::PseudoVMCLR_M_B2:
150 case RISCV::PseudoVMCLR_M_B4:
151 case RISCV::PseudoVMCLR_M_B8:
152 case RISCV::PseudoVMCLR_M_B16:
153 case RISCV::PseudoVMCLR_M_B32:
154 case RISCV::PseudoVMCLR_M_B64:
155 // vmclr.m vd => vmxor.mm vd, vd, vd
156 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
157 case RISCV::PseudoVMSET_M_B1:
158 case RISCV::PseudoVMSET_M_B2:
159 case RISCV::PseudoVMSET_M_B4:
160 case RISCV::PseudoVMSET_M_B8:
161 case RISCV::PseudoVMSET_M_B16:
162 case RISCV::PseudoVMSET_M_B32:
163 case RISCV::PseudoVMSET_M_B64:
164 // vmset.m vd => vmxnor.mm vd, vd, vd
165 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
166 case RISCV::PseudoReadVLENBViaVSETVLIX0:
167 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
168 case RISCV::PseudoClearFPR64:
169 return expandPseudoClearFPR64(MBB, MBBI);
170 }
171
172 return false;
173}
174
175bool RISCVExpandPseudoPreEmitImpl::expandCCOp(
176 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
177 MachineBasicBlock::iterator &NextMBBI) const {
178 // First try expanding to a Conditional Move rather than a branch+mv
179 if (expandCCOpToCMov(MBB, MBBI))
180 return true;
181
182 MachineFunction *MF = MBB.getParent();
183 MachineInstr &MI = *MBBI;
184 DebugLoc DL = MI.getDebugLoc();
185
186 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
187 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
188
189 MF->insert(++MBB.getIterator(), TrueBB);
190 MF->insert(++TrueBB->getIterator(), MergeBB);
191
192 // We want to copy the "true" value only when the branch is executed.
193 // The SDNodeXform is responsible for the inversion.
194 unsigned BranchOpCode =
195 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
196
197 // Insert branch instruction.
198 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
199 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
200 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
201 .addMBB(MergeBB);
202
203 Register DestReg = MI.getOperand(0).getReg();
204 assert(MI.getOperand(1).getReg() == DestReg);
205
206 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
207 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
208 // Add MV.
209 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
210 .add(MI.getOperand(2))
211 .addImm(0);
212 } else {
213 unsigned NewOpc;
214 // clang-format off
215 switch (MI.getOpcode()) {
216 default:
217 llvm_unreachable("Unexpected opcode!");
218 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
219 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
220 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
221 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
222 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
223 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
224 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
225 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
226 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
227 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
228 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
229 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
230 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
231 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
232 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
233 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
234 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
235 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
236 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
237 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
238 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
239 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
240 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
241 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
242 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
243 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
244 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
245 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
246 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
247 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
248 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
249 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
250 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
251 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
252 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
253 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
254 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
255 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
256 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
257 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
258 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
259 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
260 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
261 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
262 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
263 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
264 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
265 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
266 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
267 }
268 // clang-format on
269
270 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
271 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
272 .add(MI.getOperand(2))
273 .add(MI.getOperand(3))
274 .add(MI.getOperand(4));
275 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
276 NewOpc == RISCV::QC_E_LI) {
277 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
278 } else {
279 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
280 .add(MI.getOperand(2))
281 .add(MI.getOperand(3));
282 }
283 }
284
285 TrueBB->addSuccessor(MergeBB);
286
287 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
288 MergeBB->transferSuccessors(&MBB);
289
290 MBB.addSuccessor(TrueBB);
291 MBB.addSuccessor(MergeBB);
292
293 NextMBBI = MBB.end();
294 MI.eraseFromParent();
295
296 // Make sure live-ins are correctly attached to this new basic block.
297 LivePhysRegs LiveRegs;
298 computeAndAddLiveIns(LiveRegs, *TrueBB);
299 computeAndAddLiveIns(LiveRegs, *MergeBB);
300
301 return true;
302}
303
304bool RISCVExpandPseudoPreEmitImpl::expandCCOpToCMov(
305 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
306 MachineInstr &MI = *MBBI;
307 DebugLoc DL = MI.getDebugLoc();
308
309 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
310 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
311 return false;
312
313 if (!STI->hasVendorXqcicm())
314 return false;
315
316 MachineOperand &LHS = MI.getOperand(MI.getNumExplicitOperands() - 2);
317 MachineOperand &RHS = MI.getOperand(MI.getNumExplicitOperands() - 1);
318
319 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
320 if (LHS.getReg() == RISCV::X0 || MI.getOperand(1).getReg() == RISCV::X0 ||
321 MI.getOperand(2).getReg() == RISCV::X0)
322 return false;
323
324 // Use branch opcode to select appropriate Xqcicm instruction
325 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
326 std::optional<unsigned> CMovRegOpcode;
327 bool IsSigned = true;
328 unsigned CMovImmOpcode;
329 switch (BCC) {
330 default:
331 return false; // Unhandled branch opcodes
332 case RISCV::BNE:
333 CMovRegOpcode = RISCV::QC_MVEQ;
334 CMovImmOpcode = RISCV::QC_MVEQI;
335 break;
336 case RISCV::BEQ:
337 CMovRegOpcode = RISCV::QC_MVNE;
338 CMovImmOpcode = RISCV::QC_MVNEI;
339 break;
340 case RISCV::BGE:
341 CMovRegOpcode = RISCV::QC_MVLT;
342 CMovImmOpcode = RISCV::QC_MVLTI;
343 break;
344 case RISCV::BLT:
345 CMovRegOpcode = RISCV::QC_MVGE;
346 CMovImmOpcode = RISCV::QC_MVGEI;
347 break;
348 case RISCV::BGEU:
349 CMovRegOpcode = RISCV::QC_MVLTU;
350 CMovImmOpcode = RISCV::QC_MVLTUI;
351 break;
352 case RISCV::BLTU:
353 CMovRegOpcode = RISCV::QC_MVGEU;
354 CMovImmOpcode = RISCV::QC_MVGEUI;
355 break;
356 case RISCV::QC_BEQI:
357 CMovImmOpcode = RISCV::QC_MVNEI;
358 break;
359 case RISCV::QC_BNEI:
360 CMovImmOpcode = RISCV::QC_MVEQI;
361 break;
362 case RISCV::QC_BLTI:
363 CMovImmOpcode = RISCV::QC_MVGEI;
364 break;
365 case RISCV::QC_BGEI:
366 CMovImmOpcode = RISCV::QC_MVLTI;
367 break;
368 case RISCV::QC_BLTUI:
369 CMovImmOpcode = RISCV::QC_MVGEUI;
370 IsSigned = false;
371 break;
372 case RISCV::QC_BGEUI:
373 CMovImmOpcode = RISCV::QC_MVLTUI;
374 IsSigned = false;
375 break;
376 }
377
378 if (RHS.isImm()) {
379 if ((!isInt<5>(RHS.getImm()) || !IsSigned) &&
380 (!isUInt<5>(RHS.getImm()) || IsSigned))
381 return false;
382
383 // $dst = PseudoCCMOVGPR $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
384 // $dst = PseudoCCMOVGPRNoX0 $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
385 // =>
386 // $dst = QC_MVccI $falsev (=$dst), $lhs, $rhs_imm, $truev
387 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
388 .addDef(MI.getOperand(0).getReg())
389 .addReg(MI.getOperand(1).getReg())
390 .addReg(LHS.getReg())
391 .add(RHS)
392 .addReg(MI.getOperand(2).getReg());
393
394 MI.eraseFromParent();
395 return true;
396 }
397
398 if (RHS.getReg() == RISCV::X0) {
399 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, X0
400 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, X0
401 // =>
402 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
403 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
404 .addDef(MI.getOperand(0).getReg())
405 .addReg(MI.getOperand(1).getReg())
406 .addReg(LHS.getReg())
407 .addImm(0)
408 .addReg(MI.getOperand(2).getReg());
409
410 MI.eraseFromParent();
411 return true;
412 }
413
414 if (!CMovRegOpcode)
415 return false;
416
417 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, $rhs
418 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, $rhs
419 // =>
420 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
421 BuildMI(MBB, MBBI, DL, TII->get(*CMovRegOpcode))
422 .addDef(MI.getOperand(0).getReg())
423 .addReg(MI.getOperand(1).getReg())
424 .addReg(LHS.getReg())
425 .addReg(RHS.getReg())
426 .addReg(MI.getOperand(2).getReg());
427 MI.eraseFromParent();
428 return true;
429}
430
431bool RISCVExpandPseudoPreEmitImpl::expandVMSET_VMCLR(
432 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
433 unsigned Opcode) const {
434 DebugLoc DL = MBBI->getDebugLoc();
435 Register DstReg = MBBI->getOperand(0).getReg();
436 const MCInstrDesc &Desc = TII->get(Opcode);
437 BuildMI(MBB, MBBI, DL, Desc, DstReg)
438 .addReg(DstReg, RegState::Undef)
439 .addReg(DstReg, RegState::Undef);
440 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
441 return true;
442}
443
444bool RISCVExpandPseudoPreEmitImpl::expandMV_FPR16INX(
445 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
446 DebugLoc DL = MBBI->getDebugLoc();
447 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
448 Register DstReg = TRI->getMatchingSuperReg(
449 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
450 Register SrcReg = TRI->getMatchingSuperReg(
451 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
452
453 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
454 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
455 .addImm(0);
456
457 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
458 return true;
459}
460
461bool RISCVExpandPseudoPreEmitImpl::expandMV_FPR32INX(
462 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
463 DebugLoc DL = MBBI->getDebugLoc();
464 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
465 Register DstReg = TRI->getMatchingSuperReg(
466 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
467 Register SrcReg = TRI->getMatchingSuperReg(
468 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
469
470 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
471 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
472 .addImm(0);
473
474 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
475 return true;
476}
477
478// This function expands the PseudoRV32ZdinxSD for storing a double-precision
479// floating-point value into memory by generating an equivalent instruction
480// sequence for RV32.
481bool RISCVExpandPseudoPreEmitImpl::expandRV32ZdinxStore(
482 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
483 DebugLoc DL = MBBI->getDebugLoc();
484 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
485 Register Lo =
486 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
487 Register Hi =
488 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
489 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
490 Hi = RISCV::X0;
491
492 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
493 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
494 .addReg(MBBI->getOperand(1).getReg())
495 .add(MBBI->getOperand(2));
496
497 MachineInstrBuilder MIBHi;
498 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
499 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
500 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
501 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
502 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
503 .add(MBBI->getOperand(1))
504 .add(MBBI->getOperand(2));
505 } else {
506 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
507 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
508 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
509 .add(MBBI->getOperand(1))
510 .addImm(MBBI->getOperand(2).getImm() + 4);
511 }
512
513 MachineFunction *MF = MBB.getParent();
514 SmallVector<MachineMemOperand *> NewLoMMOs;
515 SmallVector<MachineMemOperand *> NewHiMMOs;
516 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
517 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
518 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
519 }
520 MIBLo.setMemRefs(NewLoMMOs);
521 MIBHi.setMemRefs(NewHiMMOs);
522
523 MBBI->eraseFromParent();
524 return true;
525}
526
527// This function expands PseudoRV32ZdinxLoad for loading a double-precision
528// floating-point value from memory into an equivalent instruction sequence for
529// RV32.
530bool RISCVExpandPseudoPreEmitImpl::expandRV32ZdinxLoad(
531 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
532 DebugLoc DL = MBBI->getDebugLoc();
533 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
534 Register Lo =
535 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
536 Register Hi =
537 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
538 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
539
540 MachineInstrBuilder MIBLo, MIBHi;
541
542 // If the register of operand 1 is equal to the Lo register, then swap the
543 // order of loading the Lo and Hi statements.
544 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
545 // Order: Lo, Hi
546 if (!IsOp1EqualToLo) {
547 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
548 .addReg(MBBI->getOperand(1).getReg())
549 .add(MBBI->getOperand(2));
550 }
551
552 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
553 auto Offset = MBBI->getOperand(2).getOffset();
554 assert(Offset % 8 == 0);
555 MBBI->getOperand(2).setOffset(Offset + 4);
556 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
557 .addReg(MBBI->getOperand(1).getReg())
558 .add(MBBI->getOperand(2));
559 MBBI->getOperand(2).setOffset(Offset);
560 } else {
561 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
562 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
563 .addReg(MBBI->getOperand(1).getReg())
564 .addImm(MBBI->getOperand(2).getImm() + 4);
565 }
566
567 // Order: Hi, Lo
568 if (IsOp1EqualToLo) {
569 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
570 .addReg(MBBI->getOperand(1).getReg())
571 .add(MBBI->getOperand(2));
572 }
573
574 MachineFunction *MF = MBB.getParent();
575 SmallVector<MachineMemOperand *> NewLoMMOs;
576 SmallVector<MachineMemOperand *> NewHiMMOs;
577 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
578 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
579 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
580 }
581 MIBLo.setMemRefs(NewLoMMOs);
582 MIBHi.setMemRefs(NewHiMMOs);
583
584 MBBI->eraseFromParent();
585 return true;
586}
587
588bool RISCVExpandPseudoPreEmitImpl::expandPseudoReadVLENBViaVSETVLIX0(
589 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
590 DebugLoc DL = MBBI->getDebugLoc();
591 Register Dst = MBBI->getOperand(0).getReg();
592 unsigned Mul = MBBI->getOperand(1).getImm();
593 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
594 unsigned VTypeImm = RISCVVType::encodeVTYPE(
595 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
596
597 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
598 .addReg(Dst, RegState::Define)
599 .addReg(RISCV::X0, RegState::Kill)
600 .addImm(VTypeImm);
601
602 MBBI->eraseFromParent();
603 return true;
604}
605
606bool RISCVExpandPseudoPreEmitImpl::expandPseudoClearFPR64(
607 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
608 const DebugLoc &DL = MBBI->getDebugLoc();
609 Register Dst = MBBI->getOperand(0).getReg();
610
611 if (STI->is64Bit()) {
612 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FMV_D_X), Dst).addReg(RISCV::X0);
613 } else {
614 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FCVT_D_W), Dst)
615 .addReg(RISCV::X0)
616 .addImm(RISCVFPRndMode::RNE);
617 }
618
619 MBBI->eraseFromParent();
620 return true;
621}
622
623char RISCVExpandPseudoPreEmitLegacy::ID = 0;
624
625INITIALIZE_PASS(RISCVExpandPseudoPreEmitLegacy, "riscv-expand-pseudo-pre-emit",
626 RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME, false, false)
627
628FunctionPass *llvm::createRISCVExpandPseudoPreEmitLegacyPass() {
629 return new RISCVExpandPseudoPreEmitLegacy();
630}
631
632PreservedAnalyses
633RISCVExpandPseudoPreEmitPass::run(MachineFunction &MF,
634 MachineFunctionAnalysisManager &MFAM) {
635 bool Changed = RISCVExpandPseudoPreEmitImpl().run(MF);
636 if (!Changed)
637 return PreservedAnalyses::all();
638 return getMachineFunctionPassPreservedAnalyses();
639}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:866
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2131
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME
#define RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME
Definition RISCVExpandPseudoPreEmit.cpp:25
RHS
Value * RHS
Definition X86PartialReduction.cpp:83
LHS
Value * LHS
Definition X86PartialReduction.cpp:82
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:77
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:950
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition MachineBasicBlock.h:255
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:828
llvm::MachineBasicBlock::eraseFromParent
LLVM_ABI void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition MachineBasicBlock.cpp:1527
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition MachineBasicBlock.h:325
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1162
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:343
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, LLT MemTy, Align BaseAlignment, const MMOMetadata &Metadata=MMOMetadata(), SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:580
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:544
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1027
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::PreservedAnalyses::all
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
llvm::RISCVExpandPseudoPreEmitPass::run
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Definition RISCVExpandPseudoPreEmit.cpp:633
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:423
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
Changed
Changed
Definition ObjCARCOpts.cpp:2366
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:186
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm::dwarf_linker::DebugSectionKind::DebugLoc
@ DebugLoc
Definition DWARFLinkerBase.h:35
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:578
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:166
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::MachineFunctionAnalysisManager
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
Definition MachineFunctionAnalysisManager.h:24
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:26
llvm::getMachineFunctionPassPreservedAnalyses
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
Definition MachinePassManager.cpp:162
llvm::createRISCVExpandPseudoPreEmitLegacyPass
FunctionPass * createRISCVExpandPseudoPreEmitLegacyPass()
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition SmallVector.h:1162
llvm::computeAndAddLiveIns
LLVM_ABI void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
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