25#define DEBUG_TYPE "riscv-merge-base-offset"
26#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
52 MachineFunctionProperties::Property::IsSSA);
66char RISCVMergeBaseOffsetOpt::ID = 0;
88 if (
Hi.getOpcode() != RISCV::LUI &&
Hi.getOpcode() != RISCV::AUIPC)
92 unsigned ExpectedFlags =
101 Register HiDestReg =
Hi.getOperand(0).getReg();
102 if (!
MRI->hasOneUse(HiDestReg))
105 Lo = &*
MRI->use_instr_begin(HiDestReg);
106 if (
Lo->getOpcode() != RISCV::ADDI)
110 if (
Hi.getOpcode() == RISCV::LUI) {
116 assert(
Hi.getOpcode() == RISCV::AUIPC);
128 }
else if (HiOp1.
isCPI()) {
144 if (
Hi.getOpcode() != RISCV::AUIPC)
147 MRI->constrainRegClass(
Lo.getOperand(0).getReg(),
148 MRI->getRegClass(
Tail.getOperand(0).getReg()));
149 MRI->replaceRegWith(
Tail.getOperand(0).getReg(),
Lo.getOperand(0).getReg());
150 Tail.eraseFromParent();
152 <<
" " <<
Hi <<
" " <<
Lo;);
179 assert((TailAdd.
getOpcode() == RISCV::ADD) &&
"Expected ADD instruction!");
185 if (!
MRI->hasOneUse(Reg))
189 if (OffsetTail.
getOpcode() == RISCV::ADDI ||
190 OffsetTail.
getOpcode() == RISCV::ADDIW) {
196 int64_t OffLo = AddiImmOp.
getImm();
200 if (OffsetLui.
getOpcode() != RISCV::LUI ||
204 int64_t
Offset = SignExtend64<32>(LuiImmOp.
getImm() << 12);
207 if (!
ST->is64Bit() || OffsetTail.
getOpcode() == RISCV::ADDIW)
213 <<
" " << OffsetLui);
218 }
else if (OffsetTail.
getOpcode() == RISCV::LUI) {
246 TailShXAdd.
getOpcode() == RISCV::SH2ADD ||
247 TailShXAdd.
getOpcode() == RISCV::SH3ADD) &&
248 "Expected SHXADD instruction!");
257 if (!
MRI->hasOneUse(Rs1))
261 if (OffsetTail.
getOpcode() != RISCV::ADDI)
274 case RISCV::SH1ADD: ShAmt = 1;
break;
275 case RISCV::SH2ADD: ShAmt = 2;
break;
276 case RISCV::SH3ADD: ShAmt = 3;
break;
287bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(
MachineInstr &
Hi,
294 if (!
MRI->hasOneUse(DestReg))
299 switch (
Tail.getOpcode()) {
301 LLVM_DEBUG(
dbgs() <<
"Don't know how to get offset from this instr:"
310 if (
MRI->hasOneUse(TailDestReg)) {
312 if (TailTail.
getOpcode() == RISCV::ADDI) {
316 Tail.eraseFromParent();
334 return foldLargeOffset(
Hi,
Lo,
Tail, DestReg);
341 return foldShiftedOffset(
Hi,
Lo,
Tail, DestReg);
363 std::optional<int64_t> CommonOffset;
365 switch (
UseMI.getOpcode()) {
386 if (
UseMI.getOperand(1).isFI())
392 "Expected base address use");
395 if (CommonOffset &&
Offset != CommonOffset)
406 int64_t NewOffset =
Hi.getOperand(1).getOffset() + *CommonOffset;
409 NewOffset = SignExtend64<32>(NewOffset);
411 if (!isInt<32>(NewOffset))
414 Hi.getOperand(1).setOffset(NewOffset);
416 if (
Hi.getOpcode() != RISCV::AUIPC)
422 UseMI.removeOperand(2);
423 UseMI.addOperand(ImmOp);
426 UseMI.getOperand(1).setReg(
Hi.getOperand(0).getReg());
429 Lo.eraseFromParent();
433bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(
MachineFunction &Fn) {
439 bool MadeChange =
false;
445 if (!detectFoldable(
Hi,
Lo))
447 MadeChange |= detectAndFoldOffset(
Hi, *
Lo);
448 MadeChange |= foldIntoMemoryOps(
Hi, *
Lo);
457 return new RISCVMergeBaseOffsetOpt();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
#define RISCV_MERGE_BASE_OFFSET_NAME
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const BlockAddress * getBlockAddress() const
void setOffset(int64_t Offset)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.