LLVM 19.0.0git
RISCVMergeBaseOffset.cpp
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1//===----- RISCVMergeBaseOffset.cpp - Optimise address calculations ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Merge the offset of address calculation into the offset field
10// of instructions in a global address lowering sequence.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCV.h"
15#include "RISCVTargetMachine.h"
17#include "llvm/CodeGen/Passes.h"
19#include "llvm/Support/Debug.h"
21#include <optional>
22using namespace llvm;
23
24#define DEBUG_TYPE "riscv-merge-base-offset"
25#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
26namespace {
27
28class RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
29 const RISCVSubtarget *ST = nullptr;
31
32public:
33 static char ID;
34 bool runOnMachineFunction(MachineFunction &Fn) override;
35 bool detectFoldable(MachineInstr &Hi, MachineInstr *&Lo);
36
37 bool detectAndFoldOffset(MachineInstr &Hi, MachineInstr &Lo);
38 void foldOffset(MachineInstr &Hi, MachineInstr &Lo, MachineInstr &Tail,
39 int64_t Offset);
40 bool foldLargeOffset(MachineInstr &Hi, MachineInstr &Lo,
41 MachineInstr &TailAdd, Register GSReg);
42 bool foldShiftedOffset(MachineInstr &Hi, MachineInstr &Lo,
43 MachineInstr &TailShXAdd, Register GSReg);
44
45 bool foldIntoMemoryOps(MachineInstr &Hi, MachineInstr &Lo);
46
47 RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
48
51 MachineFunctionProperties::Property::IsSSA);
52 }
53
54 void getAnalysisUsage(AnalysisUsage &AU) const override {
55 AU.setPreservesCFG();
57 }
58
59 StringRef getPassName() const override {
61 }
62};
63} // end anonymous namespace
64
65char RISCVMergeBaseOffsetOpt::ID = 0;
66INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, DEBUG_TYPE,
67 RISCV_MERGE_BASE_OFFSET_NAME, false, false)
68
69// Detect either of the patterns:
70//
71// 1. (medlow pattern):
72// lui vreg1, %hi(s)
73// addi vreg2, vreg1, %lo(s)
74//
75// 2. (medany pattern):
76// .Lpcrel_hi1:
77// auipc vreg1, %pcrel_hi(s)
78// addi vreg2, vreg1, %pcrel_lo(.Lpcrel_hi1)
79//
80// The pattern is only accepted if:
81// 1) The first instruction has only one use, which is the ADDI.
82// 2) The address operands have the appropriate type, reflecting the
83// lowering of a global address or constant pool using medlow or medany.
84// 3) The offset value in the Global Address or Constant Pool is 0.
85bool RISCVMergeBaseOffsetOpt::detectFoldable(MachineInstr &Hi,
86 MachineInstr *&Lo) {
87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC &&
88 Hi.getOpcode() != RISCV::PseudoMovAddr)
89 return false;
90
91 const MachineOperand &HiOp1 = Hi.getOperand(1);
92 unsigned ExpectedFlags =
93 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI;
94 if (HiOp1.getTargetFlags() != ExpectedFlags)
95 return false;
96
97 if (!(HiOp1.isGlobal() || HiOp1.isCPI() || HiOp1.isBlockAddress()) ||
98 HiOp1.getOffset() != 0)
99 return false;
100
101 if (Hi.getOpcode() == RISCV::PseudoMovAddr) {
102 // Most of the code should handle it correctly without modification by
103 // setting Lo and Hi both point to PseudoMovAddr
104 Lo = &Hi;
105 } else {
106 Register HiDestReg = Hi.getOperand(0).getReg();
107 if (!MRI->hasOneUse(HiDestReg))
108 return false;
109
110 Lo = &*MRI->use_instr_begin(HiDestReg);
111 if (Lo->getOpcode() != RISCV::ADDI)
112 return false;
113 }
114
115 const MachineOperand &LoOp2 = Lo->getOperand(2);
116 if (Hi.getOpcode() == RISCV::LUI || Hi.getOpcode() == RISCV::PseudoMovAddr) {
117 if (LoOp2.getTargetFlags() != RISCVII::MO_LO ||
118 !(LoOp2.isGlobal() || LoOp2.isCPI() || LoOp2.isBlockAddress()) ||
119 LoOp2.getOffset() != 0)
120 return false;
121 } else {
122 assert(Hi.getOpcode() == RISCV::AUIPC);
123 if (LoOp2.getTargetFlags() != RISCVII::MO_PCREL_LO ||
125 return false;
126 }
127
128 if (HiOp1.isGlobal()) {
129 LLVM_DEBUG(dbgs() << " Found lowered global address: "
130 << *HiOp1.getGlobal() << "\n");
131 } else if (HiOp1.isBlockAddress()) {
132 LLVM_DEBUG(dbgs() << " Found lowered basic address: "
133 << *HiOp1.getBlockAddress() << "\n");
134 } else if (HiOp1.isCPI()) {
135 LLVM_DEBUG(dbgs() << " Found lowered constant pool: " << HiOp1.getIndex()
136 << "\n");
137 }
138
139 return true;
140}
141
142// Update the offset in Hi and Lo instructions.
143// Delete the tail instruction and update all the uses to use the
144// output from Lo.
145void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &Hi, MachineInstr &Lo,
146 MachineInstr &Tail, int64_t Offset) {
147 assert(isInt<32>(Offset) && "Unexpected offset");
148 // Put the offset back in Hi and the Lo
149 Hi.getOperand(1).setOffset(Offset);
150 if (Hi.getOpcode() != RISCV::AUIPC)
151 Lo.getOperand(2).setOffset(Offset);
152 // Delete the tail instruction.
153 MRI->constrainRegClass(Lo.getOperand(0).getReg(),
154 MRI->getRegClass(Tail.getOperand(0).getReg()));
155 MRI->replaceRegWith(Tail.getOperand(0).getReg(), Lo.getOperand(0).getReg());
156 Tail.eraseFromParent();
157 LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n"
158 << " " << Hi << " " << Lo;);
159}
160
161// Detect patterns for large offsets that are passed into an ADD instruction.
162// If the pattern is found, updates the offset in Hi and Lo instructions
163// and deletes TailAdd and the instructions that produced the offset.
164//
165// Base address lowering is of the form:
166// Hi: lui vreg1, %hi(s)
167// Lo: addi vreg2, vreg1, %lo(s)
168// / \
169// / \
170// / \
171// / The large offset can be of two forms: \
172// 1) Offset that has non zero bits in lower 2) Offset that has non zero
173// 12 bits and upper 20 bits bits in upper 20 bits only
174// OffseLUI: lui vreg3, 4
175// OffsetTail: addi voff, vreg3, 188 OffsetTail: lui voff, 128
176// \ /
177// \ /
178// \ /
179// \ /
180// TailAdd: add vreg4, vreg2, voff
181bool RISCVMergeBaseOffsetOpt::foldLargeOffset(MachineInstr &Hi,
183 MachineInstr &TailAdd,
184 Register GAReg) {
185 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
186 Register Rs = TailAdd.getOperand(1).getReg();
187 Register Rt = TailAdd.getOperand(2).getReg();
188 Register Reg = Rs == GAReg ? Rt : Rs;
189
190 // Can't fold if the register has more than one use.
191 if (!Reg.isVirtual() || !MRI->hasOneUse(Reg))
192 return false;
193 // This can point to an ADDI(W) or a LUI:
194 MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
195 if (OffsetTail.getOpcode() == RISCV::ADDI ||
196 OffsetTail.getOpcode() == RISCV::ADDIW) {
197 // The offset value has non zero bits in both %hi and %lo parts.
198 // Detect an ADDI that feeds from a LUI instruction.
199 MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
200 if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
201 return false;
202 Register AddiReg = OffsetTail.getOperand(1).getReg();
203 int64_t OffLo = AddiImmOp.getImm();
204
205 // Handle rs1 of ADDI is X0.
206 if (AddiReg == RISCV::X0) {
207 LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail);
208 foldOffset(Hi, Lo, TailAdd, OffLo);
209 OffsetTail.eraseFromParent();
210 return true;
211 }
212
213 MachineInstr &OffsetLui = *MRI->getVRegDef(AddiReg);
214 MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
215 if (OffsetLui.getOpcode() != RISCV::LUI ||
216 LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
217 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
218 return false;
219 int64_t Offset = SignExtend64<32>(LuiImmOp.getImm() << 12);
220 Offset += OffLo;
221 // RV32 ignores the upper 32 bits. ADDIW sign extends the result.
222 if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW)
223 Offset = SignExtend64<32>(Offset);
224 // We can only fold simm32 offsets.
225 if (!isInt<32>(Offset))
226 return false;
227 LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail
228 << " " << OffsetLui);
229 foldOffset(Hi, Lo, TailAdd, Offset);
230 OffsetTail.eraseFromParent();
231 OffsetLui.eraseFromParent();
232 return true;
233 } else if (OffsetTail.getOpcode() == RISCV::LUI) {
234 // The offset value has all zero bits in the lower 12 bits. Only LUI
235 // exists.
236 LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail);
237 int64_t Offset = SignExtend64<32>(OffsetTail.getOperand(1).getImm() << 12);
238 foldOffset(Hi, Lo, TailAdd, Offset);
239 OffsetTail.eraseFromParent();
240 return true;
241 }
242 return false;
243}
244
245// Detect patterns for offsets that are passed into a SHXADD instruction.
246// The offset has 1, 2, or 3 trailing zeros and fits in simm13, simm14, simm15.
247// The constant is created with addi voff, x0, C, and shXadd is used to
248// fill insert the trailing zeros and do the addition.
249// If the pattern is found, updates the offset in Hi and Lo instructions
250// and deletes TailShXAdd and the instructions that produced the offset.
251//
252// Hi: lui vreg1, %hi(s)
253// Lo: addi vreg2, vreg1, %lo(s)
254// OffsetTail: addi voff, x0, C
255// TailAdd: shXadd vreg4, voff, vreg2
256bool RISCVMergeBaseOffsetOpt::foldShiftedOffset(MachineInstr &Hi,
258 MachineInstr &TailShXAdd,
259 Register GAReg) {
260 assert((TailShXAdd.getOpcode() == RISCV::SH1ADD ||
261 TailShXAdd.getOpcode() == RISCV::SH2ADD ||
262 TailShXAdd.getOpcode() == RISCV::SH3ADD) &&
263 "Expected SHXADD instruction!");
264
265 if (GAReg != TailShXAdd.getOperand(2).getReg())
266 return false;
267
268 // The first source is the shifted operand.
269 Register Rs1 = TailShXAdd.getOperand(1).getReg();
270
271 // Can't fold if the register has more than one use.
272 if (!Rs1.isVirtual() || !MRI->hasOneUse(Rs1))
273 return false;
274 // This can point to an ADDI X0, C.
275 MachineInstr &OffsetTail = *MRI->getVRegDef(Rs1);
276 if (OffsetTail.getOpcode() != RISCV::ADDI)
277 return false;
278 if (!OffsetTail.getOperand(1).isReg() ||
279 OffsetTail.getOperand(1).getReg() != RISCV::X0 ||
280 !OffsetTail.getOperand(2).isImm())
281 return false;
282
283 int64_t Offset = OffsetTail.getOperand(2).getImm();
284 assert(isInt<12>(Offset) && "Unexpected offset");
285
286 unsigned ShAmt;
287 switch (TailShXAdd.getOpcode()) {
288 default: llvm_unreachable("Unexpected opcode");
289 case RISCV::SH1ADD: ShAmt = 1; break;
290 case RISCV::SH2ADD: ShAmt = 2; break;
291 case RISCV::SH3ADD: ShAmt = 3; break;
292 }
293
294 Offset = (uint64_t)Offset << ShAmt;
295
296 LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail);
297 foldOffset(Hi, Lo, TailShXAdd, Offset);
298 OffsetTail.eraseFromParent();
299 return true;
300}
301
302bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &Hi,
303 MachineInstr &Lo) {
304 Register DestReg = Lo.getOperand(0).getReg();
305
306 // Look for arithmetic instructions we can get an offset from.
307 // We might be able to remove the arithmetic instructions by folding the
308 // offset into the LUI+ADDI.
309 if (!MRI->hasOneUse(DestReg))
310 return false;
311
312 // Lo has only one use.
313 MachineInstr &Tail = *MRI->use_instr_begin(DestReg);
314 switch (Tail.getOpcode()) {
315 default:
316 LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
317 << Tail);
318 break;
319 case RISCV::ADDI: {
320 // Offset is simply an immediate operand.
321 int64_t Offset = Tail.getOperand(2).getImm();
322
323 // We might have two ADDIs in a row.
324 Register TailDestReg = Tail.getOperand(0).getReg();
325 if (MRI->hasOneUse(TailDestReg)) {
326 MachineInstr &TailTail = *MRI->use_instr_begin(TailDestReg);
327 if (TailTail.getOpcode() == RISCV::ADDI) {
328 Offset += TailTail.getOperand(2).getImm();
329 LLVM_DEBUG(dbgs() << " Offset Instrs: " << Tail << TailTail);
330 foldOffset(Hi, Lo, TailTail, Offset);
331 Tail.eraseFromParent();
332 return true;
333 }
334 }
335
336 LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail);
337 foldOffset(Hi, Lo, Tail, Offset);
338 return true;
339 }
340 case RISCV::ADD:
341 // The offset is too large to fit in the immediate field of ADDI.
342 // This can be in two forms:
343 // 1) LUI hi_Offset followed by:
344 // ADDI lo_offset
345 // This happens in case the offset has non zero bits in
346 // both hi 20 and lo 12 bits.
347 // 2) LUI (offset20)
348 // This happens in case the lower 12 bits of the offset are zeros.
349 return foldLargeOffset(Hi, Lo, Tail, DestReg);
350 case RISCV::SH1ADD:
351 case RISCV::SH2ADD:
352 case RISCV::SH3ADD:
353 // The offset is too large to fit in the immediate field of ADDI.
354 // It may be encoded as (SH2ADD (ADDI X0, C), DestReg) or
355 // (SH3ADD (ADDI X0, C), DestReg).
356 return foldShiftedOffset(Hi, Lo, Tail, DestReg);
357 }
358
359 return false;
360}
361
362bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
363 MachineInstr &Lo) {
364 Register DestReg = Lo.getOperand(0).getReg();
365
366 // If all the uses are memory ops with the same offset, we can transform:
367 //
368 // 1. (medlow pattern):
369 // Hi: lui vreg1, %hi(foo) ---> lui vreg1, %hi(foo+8)
370 // Lo: addi vreg2, vreg1, %lo(foo) ---> lw vreg3, lo(foo+8)(vreg1)
371 // Tail: lw vreg3, 8(vreg2)
372 //
373 // 2. (medany pattern):
374 // Hi: 1:auipc vreg1, %pcrel_hi(s) ---> auipc vreg1, %pcrel_hi(foo+8)
375 // Lo: addi vreg2, vreg1, %pcrel_lo(1b) ---> lw vreg3, %pcrel_lo(1b)(vreg1)
376 // Tail: lw vreg3, 8(vreg2)
377
378 std::optional<int64_t> CommonOffset;
380 InlineAsmMemoryOpIndexesMap;
381 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) {
382 switch (UseMI.getOpcode()) {
383 default:
384 LLVM_DEBUG(dbgs() << "Not a load or store instruction: " << UseMI);
385 return false;
386 case RISCV::LB:
387 case RISCV::LH:
388 case RISCV::LW:
389 case RISCV::LBU:
390 case RISCV::LHU:
391 case RISCV::LWU:
392 case RISCV::LD:
393 case RISCV::FLH:
394 case RISCV::FLW:
395 case RISCV::FLD:
396 case RISCV::SB:
397 case RISCV::SH:
398 case RISCV::SW:
399 case RISCV::SD:
400 case RISCV::FSH:
401 case RISCV::FSW:
402 case RISCV::FSD: {
403 if (UseMI.getOperand(1).isFI())
404 return false;
405 // Register defined by Lo should not be the value register.
406 if (DestReg == UseMI.getOperand(0).getReg())
407 return false;
408 assert(DestReg == UseMI.getOperand(1).getReg() &&
409 "Expected base address use");
410 // All load/store instructions must use the same offset.
411 int64_t Offset = UseMI.getOperand(2).getImm();
412 if (CommonOffset && Offset != CommonOffset)
413 return false;
414 CommonOffset = Offset;
415 break;
416 }
417 case RISCV::INLINEASM:
418 case RISCV::INLINEASM_BR: {
419 SmallVector<unsigned> InlineAsmMemoryOpIndexes;
420 unsigned NumOps = 0;
421 for (unsigned I = InlineAsm::MIOp_FirstOperand;
422 I < UseMI.getNumOperands(); I += 1 + NumOps) {
423 const MachineOperand &FlagsMO = UseMI.getOperand(I);
424 // Should be an imm.
425 if (!FlagsMO.isImm())
426 continue;
427
428 const InlineAsm::Flag Flags(FlagsMO.getImm());
429 NumOps = Flags.getNumOperandRegisters();
430
431 // Memory constraints have two operands.
432 if (NumOps != 2 || !Flags.isMemKind())
433 continue;
434
435 // We can't do this for constraint A because AMO instructions don't have
436 // an immediate offset field.
437 if (Flags.getMemoryConstraintID() == InlineAsm::ConstraintCode::A)
438 return false;
439
440 const MachineOperand &AddrMO = UseMI.getOperand(I + 1);
441 if (!AddrMO.isReg() || AddrMO.getReg() != DestReg)
442 continue;
443
444 const MachineOperand &OffsetMO = UseMI.getOperand(I + 2);
445 if (!OffsetMO.isImm())
446 continue;
447
448 // All inline asm memory operands must use the same offset.
449 int64_t Offset = OffsetMO.getImm();
450 if (CommonOffset && Offset != CommonOffset)
451 return false;
452 CommonOffset = Offset;
453 InlineAsmMemoryOpIndexes.push_back(I + 1);
454 }
455 InlineAsmMemoryOpIndexesMap.insert(
456 std::make_pair(&UseMI, InlineAsmMemoryOpIndexes));
457 break;
458 }
459 }
460 }
461
462 // We found a common offset.
463 // Update the offsets in global address lowering.
464 // We may have already folded some arithmetic so we need to add to any
465 // existing offset.
466 int64_t NewOffset = Hi.getOperand(1).getOffset() + *CommonOffset;
467 // RV32 ignores the upper 32 bits.
468 if (!ST->is64Bit())
469 NewOffset = SignExtend64<32>(NewOffset);
470 // We can only fold simm32 offsets.
471 if (!isInt<32>(NewOffset))
472 return false;
473
474 Hi.getOperand(1).setOffset(NewOffset);
475 MachineOperand &ImmOp = Lo.getOperand(2);
476 // Expand PseudoMovAddr into LUI
477 if (Hi.getOpcode() == RISCV::PseudoMovAddr) {
478 auto *TII = ST->getInstrInfo();
479 Hi.setDesc(TII->get(RISCV::LUI));
480 Hi.removeOperand(2);
481 }
482
483 if (Hi.getOpcode() != RISCV::AUIPC)
484 ImmOp.setOffset(NewOffset);
485
486 // Update the immediate in the load/store instructions to add the offset.
487 for (MachineInstr &UseMI :
488 llvm::make_early_inc_range(MRI->use_instructions(DestReg))) {
489 if (UseMI.getOpcode() == RISCV::INLINEASM ||
490 UseMI.getOpcode() == RISCV::INLINEASM_BR) {
491 auto &InlineAsmMemoryOpIndexes = InlineAsmMemoryOpIndexesMap[&UseMI];
492 for (unsigned I : InlineAsmMemoryOpIndexes) {
493 MachineOperand &MO = UseMI.getOperand(I + 1);
494 switch (ImmOp.getType()) {
496 MO.ChangeToGA(ImmOp.getGlobal(), ImmOp.getOffset(),
497 ImmOp.getTargetFlags());
498 break;
500 MO.ChangeToMCSymbol(ImmOp.getMCSymbol(), ImmOp.getTargetFlags());
501 MO.setOffset(ImmOp.getOffset());
502 break;
504 MO.ChangeToBA(ImmOp.getBlockAddress(), ImmOp.getOffset(),
505 ImmOp.getTargetFlags());
506 break;
507 default:
508 report_fatal_error("unsupported machine operand type");
509 break;
510 }
511 }
512 } else {
513 UseMI.removeOperand(2);
514 UseMI.addOperand(ImmOp);
515 }
516 }
517
518 // Prevent Lo (originally PseudoMovAddr, which is also pointed by Hi) from
519 // being erased
520 if (&Lo == &Hi)
521 return true;
522
523 MRI->replaceRegWith(Lo.getOperand(0).getReg(), Hi.getOperand(0).getReg());
524 Lo.eraseFromParent();
525 return true;
526}
527
528bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
529 if (skipFunction(Fn.getFunction()))
530 return false;
531
533
534 bool MadeChange = false;
535 MRI = &Fn.getRegInfo();
536 for (MachineBasicBlock &MBB : Fn) {
537 LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
538 for (MachineInstr &Hi : MBB) {
539 MachineInstr *Lo = nullptr;
540 if (!detectFoldable(Hi, Lo))
541 continue;
542 MadeChange |= detectAndFoldOffset(Hi, *Lo);
543 MadeChange |= foldIntoMemoryOps(Hi, *Lo);
544 }
545 }
546
547 return MadeChange;
548}
549
550/// Returns an instance of the Merge Base Offset Optimization pass.
552 return new RISCVMergeBaseOffsetOpt();
553}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
#define I(x, y, z)
Definition: MD5.cpp:58
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
#define RISCV_MERGE_BASE_OFFSET_NAME
#define DEBUG_TYPE
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
support::ulittle16_t & Lo
Definition: aarch32.cpp:206
support::ulittle16_t & Hi
Definition: aarch32.cpp:205
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:566
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:576
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
void ChangeToBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
ChangeToBA - Replace this operand with a new block address operand.
const BlockAddress * getBlockAddress() const
void setOffset(int64_t Offset)
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167