LLVM 19.0.0git
VEFrameLowering.cpp
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1//===-- VEFrameLowering.cpp - VE Frame Information ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the VE implementation of TargetFrameLowering class.
10//
11// On VE, stack frames are structured as follows:
12//
13// The stack grows downward.
14//
15// All of the individual frame areas on the frame below are optional, i.e. it's
16// possible to create a function so that the particular area isn't present
17// in the frame.
18//
19// At function entry, the "frame" looks as follows:
20//
21// | | Higher address
22// |----------------------------------------------|
23// | Parameter area for this function |
24// |----------------------------------------------|
25// | Register save area (RSA) for this function |
26// |----------------------------------------------|
27// | Return address for this function |
28// |----------------------------------------------|
29// | Frame pointer for this function |
30// |----------------------------------------------| <- sp
31// | | Lower address
32//
33// VE doesn't use on demand stack allocation, so user code generated by LLVM
34// needs to call VEOS to allocate stack frame. VE's ABI want to reduce the
35// number of VEOS calls, so ABI requires to allocate not only RSA (in general
36// CSR, callee saved register) area but also call frame at the prologue of
37// caller function.
38//
39// After the prologue has run, the frame has the following general structure.
40// Note that technically the last frame area (VLAs) doesn't get created until
41// in the main function body, after the prologue is run. However, it's depicted
42// here for completeness.
43//
44// | | Higher address
45// |----------------------------------------------|
46// | Parameter area for this function |
47// |----------------------------------------------|
48// | Register save area (RSA) for this function |
49// |----------------------------------------------|
50// | Return address for this function |
51// |----------------------------------------------|
52// | Frame pointer for this function |
53// |----------------------------------------------| <- fp(=old sp)
54// |.empty.space.to.make.part.below.aligned.in....|
55// |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is
56// |.alignment....................................| unknown at compile time)
57// |----------------------------------------------|
58// | Local variables of fixed size including spill|
59// | slots |
60// |----------------------------------------------| <- bp(not defined by ABI,
61// |.variable-sized.local.variables.(VLAs)........| LLVM chooses SX17)
62// |..............................................| (size of this area is
63// |..............................................| unknown at compile time)
64// |----------------------------------------------| <- stack top (returned by
65// | Parameter area for callee | alloca)
66// |----------------------------------------------|
67// | Register save area (RSA) for callee |
68// |----------------------------------------------|
69// | Return address for callee |
70// |----------------------------------------------|
71// | Frame pointer for callee |
72// |----------------------------------------------| <- sp
73// | | Lower address
74//
75// To access the data in a frame, at-compile time, a constant offset must be
76// computable from one of the pointers (fp, bp, sp) to access it. The size
77// of the areas with a dotted background cannot be computed at compile-time
78// if they are present, making it required to have all three of fp, bp and
79// sp to be set up to be able to access all contents in the frame areas,
80// assuming all of the frame areas are non-empty.
81//
82// For most functions, some of the frame areas are empty. For those functions,
83// it may not be necessary to set up fp or bp:
84// * A base pointer is definitely needed when there are both VLAs and local
85// variables with more-than-default alignment requirements.
86// * A frame pointer is definitely needed when there are local variables with
87// more-than-default alignment requirements.
88//
89// In addition, VE ABI defines RSA frame, return address, and frame pointer
90// as follows:
91//
92// |----------------------------------------------| <- sp+176
93// | %s18...%s33 |
94// |----------------------------------------------| <- sp+48
95// | Linkage area register (%s17) |
96// |----------------------------------------------| <- sp+40
97// | Procedure linkage table register (%plt=%s16) |
98// |----------------------------------------------| <- sp+32
99// | Global offset table register (%got=%s15) |
100// |----------------------------------------------| <- sp+24
101// | Thread pointer register (%tp=%s14) |
102// |----------------------------------------------| <- sp+16
103// | Return address |
104// |----------------------------------------------| <- sp+8
105// | Frame pointer |
106// |----------------------------------------------| <- sp+0
107//
108// NOTE: This description is based on VE ABI and description in
109// AArch64FrameLowering.cpp. Thanks a lot.
110//===----------------------------------------------------------------------===//
111
112#include "VEFrameLowering.h"
113#include "VEInstrInfo.h"
115#include "VESubtarget.h"
122#include "llvm/IR/DataLayout.h"
123#include "llvm/IR/Function.h"
127
128using namespace llvm;
129
131 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0,
132 Align(16)),
133 STI(ST) {}
134
138 uint64_t NumBytes,
139 bool RequireFPUpdate) const {
141 DebugLoc DL;
142 const VEInstrInfo &TII = *STI.getInstrInfo();
143
144 // Insert following codes here as prologue
145 //
146 // st %fp, 0(, %sp) iff !isLeafProc
147 // st %lr, 8(, %sp) iff !isLeafProc
148 // st %got, 24(, %sp) iff hasGOT
149 // st %plt, 32(, %sp) iff hasGOT
150 // st %s17, 40(, %sp) iff hasBP
151 if (!FuncInfo->isLeafProc()) {
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
153 .addReg(VE::SX11)
154 .addImm(0)
155 .addImm(0)
156 .addReg(VE::SX9);
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
158 .addReg(VE::SX11)
159 .addImm(0)
160 .addImm(8)
161 .addReg(VE::SX10);
162 }
163 if (hasGOT(MF)) {
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
165 .addReg(VE::SX11)
166 .addImm(0)
167 .addImm(24)
168 .addReg(VE::SX15);
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
170 .addReg(VE::SX11)
171 .addImm(0)
172 .addImm(32)
173 .addReg(VE::SX16);
174 }
175 if (hasBP(MF))
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
177 .addReg(VE::SX11)
178 .addImm(0)
179 .addImm(40)
180 .addReg(VE::SX17);
181}
182
186 uint64_t NumBytes,
187 bool RequireFPUpdate) const {
189 DebugLoc DL;
190 const VEInstrInfo &TII = *STI.getInstrInfo();
191
192 // Insert following codes here as epilogue
193 //
194 // ld %s17, 40(, %sp) iff hasBP
195 // ld %plt, 32(, %sp) iff hasGOT
196 // ld %got, 24(, %sp) iff hasGOT
197 // ld %lr, 8(, %sp) iff !isLeafProc
198 // ld %fp, 0(, %sp) iff !isLeafProc
199 if (hasBP(MF))
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17)
201 .addReg(VE::SX11)
202 .addImm(0)
203 .addImm(40);
204 if (hasGOT(MF)) {
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16)
206 .addReg(VE::SX11)
207 .addImm(0)
208 .addImm(32);
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15)
210 .addReg(VE::SX11)
211 .addImm(0)
212 .addImm(24);
213 }
214 if (!FuncInfo->isLeafProc()) {
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10)
216 .addReg(VE::SX11)
217 .addImm(0)
218 .addImm(8);
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9)
220 .addReg(VE::SX11)
221 .addImm(0)
222 .addImm(0);
223 }
224}
225
226void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,
229 int64_t NumBytes,
230 MaybeAlign MaybeAlign) const {
231 DebugLoc DL;
232 const VEInstrInfo &TII = *STI.getInstrInfo();
233
234 if (NumBytes == 0) {
235 // Nothing to do here.
236 } else if (isInt<7>(NumBytes)) {
237 // adds.l %s11, NumBytes@lo, %s11
238 BuildMI(MBB, MBBI, DL, TII.get(VE::ADDSLri), VE::SX11)
239 .addReg(VE::SX11)
240 .addImm(NumBytes);
241 } else if (isInt<32>(NumBytes)) {
242 // lea %s11, NumBytes@lo(, %s11)
243 BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11)
244 .addReg(VE::SX11)
245 .addImm(0)
246 .addImm(Lo_32(NumBytes));
247 } else {
248 // Emit following codes. This clobbers SX13 which we always know is
249 // available here.
250 // lea %s13, NumBytes@lo
251 // and %s13, %s13, (32)0
252 // lea.sl %sp, NumBytes@hi(%s13, %sp)
253 BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)
254 .addImm(0)
255 .addImm(0)
256 .addImm(Lo_32(NumBytes));
257 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)
258 .addReg(VE::SX13)
259 .addImm(M0(32));
260 BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)
261 .addReg(VE::SX11)
262 .addReg(VE::SX13)
263 .addImm(Hi_32(NumBytes));
264 }
265
266 if (MaybeAlign) {
267 // and %sp, %sp, Align-1
268 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11)
269 .addReg(VE::SX11)
271 }
272}
273
274void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
276 DebugLoc DL;
277 const VEInstrInfo &TII = *STI.getInstrInfo();
278
279 // Emit following codes. It is not possible to insert multiple
280 // BasicBlocks in PEI pass, so we emit two pseudo instructions here.
281 //
282 // EXTEND_STACK // pseudo instrcution
283 // EXTEND_STACK_GUARD // pseudo instrcution
284 //
285 // EXTEND_STACK pseudo will be converted by ExpandPostRA pass into
286 // following instructions with multiple basic blocks later.
287 //
288 // thisBB:
289 // brge.l.t %sp, %sl, sinkBB
290 // syscallBB:
291 // ld %s61, 0x18(, %tp) // load param area
292 // or %s62, 0, %s0 // spill the value of %s0
293 // lea %s63, 0x13b // syscall # of grow
294 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0
295 // shm.l %sl, 0x8(%s61) // store old limit at addr:8
296 // shm.l %sp, 0x10(%s61) // store new limit at addr:16
297 // monc // call monitor
298 // or %s0, 0, %s62 // restore the value of %s0
299 // sinkBB:
300 //
301 // EXTEND_STACK_GUARD pseudo will be simply eliminated by ExpandPostRA
302 // pass. This pseudo is required to be at the next of EXTEND_STACK
303 // pseudo in order to protect iteration loop in ExpandPostRA.
304 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK));
305 BuildMI(MBB, MBBI, DL, TII.get(VE::EXTEND_STACK_GUARD));
306}
307
309 MachineBasicBlock &MBB) const {
311 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
312 MachineFrameInfo &MFI = MF.getFrameInfo();
313 const VEInstrInfo &TII = *STI.getInstrInfo();
314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo();
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF);
317
318 // Debug location must be unknown since the first debug location is used
319 // to determine the end of the prologue.
320 DebugLoc DL;
321
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF))
323 report_fatal_error("Function \"" + Twine(MF.getName()) +
324 "\" required "
325 "stack re-alignment, but LLVM couldn't handle it "
326 "(probably because it has a dynamic alloca).");
327
328 // Get the number of bytes to allocate from the FrameInfo.
329 // This number of bytes is already aligned to ABI stack alignment.
330 uint64_t NumBytes = MFI.getStackSize();
331
332 // Adjust stack size if this function is not a leaf function since the
333 // VE ABI requires a reserved area at the top of stack as described in
334 // VEFrameLowering.cpp.
335 if (!FuncInfo->isLeafProc()) {
336 // NOTE: The number is aligned to ABI stack alignment after adjustment.
337 NumBytes = STI.getAdjustedFrameSize(NumBytes);
338 }
339
340 // Finally, ensure that the size is sufficiently aligned for the
341 // data on the stack.
342 NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
343
344 // Update stack size with corrected value.
345 MFI.setStackSize(NumBytes);
346
347 // Emit Prologue instructions to save multiple registers.
348 emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);
349
350 // Emit instructions to save SP in FP as follows if this is not a leaf
351 // function:
352 // or %fp, 0, %sp
353 if (!FuncInfo->isLeafProc())
354 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX9)
355 .addReg(VE::SX11)
356 .addImm(0);
357
358 // Emit stack adjust instructions
359 MaybeAlign RuntimeAlign =
360 NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : std::nullopt;
361 assert((RuntimeAlign == std::nullopt || !FuncInfo->isLeafProc()) &&
362 "SP has to be saved in order to align variable sized stack object!");
363 emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);
364
365 if (hasBP(MF)) {
366 // Copy SP to BP.
367 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX17)
368 .addReg(VE::SX11)
369 .addImm(0);
370 }
371
372 // Emit stack extend instructions
373 if (NumBytes != 0)
374 emitSPExtend(MF, MBB, MBBI);
375}
376
380 if (!hasReservedCallFrame(MF)) {
381 MachineInstr &MI = *I;
382 int64_t Size = MI.getOperand(0).getImm();
383 if (MI.getOpcode() == VE::ADJCALLSTACKDOWN)
384 Size = -Size;
385
386 if (Size)
387 emitSPAdjustment(MF, MBB, I, Size);
388 }
389 return MBB.erase(I);
390}
391
393 MachineBasicBlock &MBB) const {
395 DebugLoc DL;
397 MachineFrameInfo &MFI = MF.getFrameInfo();
398 const VEInstrInfo &TII = *STI.getInstrInfo();
399
400 uint64_t NumBytes = MFI.getStackSize();
401
402 // Emit instructions to retrieve original SP.
403 if (!FuncInfo->isLeafProc()) {
404 // If SP is saved in FP, retrieve it as follows:
405 // or %sp, 0, %fp iff !isLeafProc
406 BuildMI(MBB, MBBI, DL, TII.get(VE::ORri), VE::SX11)
407 .addReg(VE::SX9)
408 .addImm(0);
409 } else {
410 // Emit stack adjust instructions.
411 emitSPAdjustment(MF, MBB, MBBI, NumBytes, std::nullopt);
412 }
413
414 // Emit Epilogue instructions to restore multiple registers.
415 emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);
416}
417
418// hasFP - Return true if the specified function should have a dedicated frame
419// pointer register. This is true if the function has variable sized allocas
420// or if frame pointer elimination is disabled.
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
423
424 const MachineFrameInfo &MFI = MF.getFrameInfo();
425 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
428}
429
431 const MachineFrameInfo &MFI = MF.getFrameInfo();
433
434 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
435}
436
439
440 // If a global base register is assigned (!= 0), GOT is used.
441 return FuncInfo->getGlobalBaseReg() != 0;
442}
443
445 int FI,
446 Register &FrameReg) const {
447 const MachineFrameInfo &MFI = MF.getFrameInfo();
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo();
449 bool isFixed = MFI.isFixedObjectIndex(FI);
450
451 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);
452
453 if (!hasFP(MF)) {
454 // If FP is not used, frame indexies are based on a %sp regiter.
455 FrameReg = VE::SX11; // %sp
456 return StackOffset::getFixed(FrameOffset +
458 }
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) {
460 // If data on stack require realignemnt, frame indexies are based on a %sp
461 // or %s17 (bp) register. If there is a variable sized object, bp is used.
462 if (hasBP(MF))
463 FrameReg = VE::SX17; // %bp
464 else
465 FrameReg = VE::SX11; // %sp
466 return StackOffset::getFixed(FrameOffset +
468 }
469 // Use %fp by default.
470 FrameReg = RegInfo->getFrameRegister(MF);
471 return StackOffset::getFixed(FrameOffset);
472}
473
474bool VEFrameLowering::isLeafProc(MachineFunction &MF) const {
475
477 MachineFrameInfo &MFI = MF.getFrameInfo();
478
479 return !MFI.hasCalls() // No calls
480 && !MRI.isPhysRegUsed(VE::SX18) // Registers within limits
481 // (s18 is first CSR)
482 && !MRI.isPhysRegUsed(VE::SX11) // %sp un-used
483 && !hasFP(MF); // Don't need %fp
484}
485
487 BitVector &SavedRegs,
488 RegScavenger *RS) const {
490
491 // Functions having BP need to emit prologue and epilogue to allocate local
492 // buffer on the stack even if the function is a leaf function.
493 if (isLeafProc(MF) && !hasBP(MF)) {
495 FuncInfo->setLeafProc(true);
496 }
497}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A debug info location.
Definition: DebugLoc.h:33
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
void emitEpilogueInsns(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, uint64_t NumBytes, bool RequireFPUpdate) const
bool hasBP(const MachineFunction &MF) const
const VESubtarget & STI
void emitPrologueInsns(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, uint64_t NumBytes, bool RequireFPUpdate) const
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
VEFrameLowering(const VESubtarget &ST)
bool hasGOT(const MachineFunction &MF) const
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
uint64_t getAdjustedFrameSize(uint64_t FrameSize) const
Given a actual stack size as determined by FrameInfo, this function returns adjusted framesize which ...
Definition: VESubtarget.cpp:50
const VEInstrInfo * getInstrInfo() const override
Definition: VESubtarget.h:51
const VERegisterInfo * getRegisterInfo() const override
Definition: VESubtarget.h:55
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:330
unsigned M1(unsigned Val)
Definition: VE.h:376
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition: MathExtras.h:138
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:159
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition: MathExtras.h:143
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned M0(unsigned Val)
Definition: VE.h:375
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:141
Register getFrameRegister(const MachineFunction &MF) const override