50void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
53 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
56void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
67 int64_t
Imm =
Op.getImm();
68 if (isInt<16>(Imm) || isUInt<16>(Imm))
69 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
71 printU32ImmOperand(
MI, OpNo, STI, O);
74void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
79void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
84void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
89void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
92 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
95void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
97 if (
MI->getOperand(OpNo).getImm()) {
102void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
115 printU16ImmDecOperand(
MI, OpNo, O);
119void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
134 printU16ImmDecOperand(
MI, OpNo, O);
138void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
141 if (
MI->getOperand(OpNo).getImm()) {
143 printU8ImmDecOperand(
MI, OpNo, O);
147void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
150 if (
MI->getOperand(OpNo).getImm()) {
152 printU8ImmDecOperand(
MI, OpNo, O);
156void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
159 printU32ImmOperand(
MI, OpNo, STI, O);
162void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
168void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
172 printSMEMOffset(
MI, OpNo, STI, O);
175void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
178 printU32ImmOperand(
MI, OpNo, STI, O);
181void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
183 auto Imm =
MI->getOperand(OpNo).getImm();
189 printTH(
MI, TH, Scope, O);
190 printScope(Scope, O);
206 O <<
" /* unexpected cache policy bit */";
209void AMDGPUInstPrinter::printTH(
const MCInst *
MI, int64_t TH, int64_t Scope,
215 const unsigned Opcode =
MI->getOpcode();
243 O << (IsStore ?
"TH_STORE_" :
"TH_LOAD_");
253 : (IsStore ?
"RT_WB" :
"LU"));
274void AMDGPUInstPrinter::printScope(int64_t Scope,
raw_ostream &O) {
292void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
294 if (
MI->getOperand(OpNo).getImm()) {
296 printU16ImmOperand(
MI, OpNo, STI, O);
300void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
302 unsigned Dim =
MI->getOperand(OpNo).getImm();
303 O <<
" dim:SQ_RSRC_IMG_";
312void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
315 printNamedBit(
MI, OpNo, O,
"a16");
317 printNamedBit(
MI, OpNo, O,
"r128");
320void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
325void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
334 unsigned Val =
MI->getOperand(OpNo).getImm();
336 if (Val == UFMT_DEFAULT)
341 O <<
" format:" << Val;
344 if (Val == DFMT_NFMT_DEFAULT)
351 if (Dfmt != DFMT_DEFAULT) {
353 if (Nfmt != NFMT_DEFAULT) {
357 if (Nfmt != NFMT_DEFAULT) {
362 O <<
" format:" << Val;
373 case AMDGPU::PRIVATE_RSRC_REG:
385void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
387 auto Opcode =
MI->getOpcode();
405 printRegularOperand(
MI, OpNo, STI, O);
411 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
412 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
413 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
414 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
415 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
416 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
417 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
418 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
419 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
420 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
421 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
422 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
423 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
424 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
425 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
426 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
427 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
428 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
429 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
430 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
431 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
432 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
433 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
434 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
435 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
436 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
437 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
438 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
439 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
440 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
441 printDefaultVccOperand(
false, STI, O);
446void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
453 printRegularOperand(
MI, OpNo, STI, O);
456void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
459 int32_t SImm =
static_cast<int32_t
>(
Imm);
465 if (printImmediateFloat32(Imm, STI, O))
468 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
475 else if (Imm == 0xBC00)
477 else if (Imm == 0x3800)
479 else if (Imm == 0xB800)
481 else if (Imm == 0x4000)
483 else if (Imm == 0xC000)
485 else if (Imm == 0x4400)
487 else if (Imm == 0xC400)
489 else if (Imm == 0x3118 && STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
501 else if (Imm == 0xBF80)
503 else if (Imm == 0x3F00)
505 else if (Imm == 0xBF00)
507 else if (Imm == 0x4000)
509 else if (Imm == 0xC000)
511 else if (Imm == 0x4080)
513 else if (Imm == 0xC080)
515 else if (Imm == 0x3E22 && STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
523void AMDGPUInstPrinter::printImmediateBF16(
uint32_t Imm,
526 int16_t SImm =
static_cast<int16_t
>(
Imm);
535 O << formatHex(static_cast<uint64_t>(Imm));
538void AMDGPUInstPrinter::printImmediateF16(
uint32_t Imm,
541 int16_t SImm =
static_cast<int16_t
>(
Imm);
555void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm, uint8_t OpType,
558 int32_t SImm =
static_cast<int32_t
>(
Imm);
568 if (printImmediateFloat32(Imm, STI, O))
574 if (isUInt<16>(Imm) &&
581 if (isUInt<16>(Imm) &&
589 O << formatHex(static_cast<uint64_t>(Imm));
592bool AMDGPUInstPrinter::printImmediateFloat32(
uint32_t Imm,
595 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
597 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
599 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
601 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
603 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
605 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
607 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
609 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
611 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
613 else if (Imm == 0x3e22f983 &&
614 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
622void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
625 int32_t SImm =
static_cast<int32_t
>(
Imm);
631 if (printImmediateFloat32(Imm, STI, O))
634 O << formatHex(static_cast<uint64_t>(Imm));
637void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
640 int64_t SImm =
static_cast<int64_t
>(
Imm);
641 if (SImm >= -16 && SImm <= 64) {
646 if (Imm == llvm::bit_cast<uint64_t>(0.0))
648 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
650 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
652 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
654 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
656 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
658 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
660 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
662 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
664 else if (Imm == 0x3fc45f306dc9c882 &&
665 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
666 O <<
"0.15915494309189532";
669 O << formatHex(static_cast<uint64_t>(
Hi_32(Imm)));
671 assert(isUInt<32>(Imm) || isInt<32>(Imm));
675 O << formatHex(static_cast<uint64_t>(Imm));
679void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
682 unsigned Imm =
MI->getOperand(OpNo).getImm();
687 switch (
MI->getOpcode()) {
688 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
689 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
690 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
691 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
692 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
693 << ((Imm >> 2) & 1) <<
']';
698 O <<
" blgp:" <<
Imm;
701void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
704 unsigned Imm =
MI->getOperand(OpNo).getImm();
708 O <<
" cbsz:" <<
Imm;
711void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
714 unsigned Imm =
MI->getOperand(OpNo).getImm();
718 O <<
" abid:" <<
Imm;
721void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
734void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
738 printU4ImmDecOperand(
MI, OpNo, O);
741void AMDGPUInstPrinter::printWaitVAVDst(
const MCInst *
MI,
unsigned OpNo,
744 O <<
" wait_va_vdst:";
745 printU4ImmDecOperand(
MI, OpNo, O);
748void AMDGPUInstPrinter::printWaitVMVSrc(
const MCInst *
MI,
unsigned OpNo,
751 O <<
" wait_vm_vsrc:";
752 printU4ImmDecOperand(
MI, OpNo, O);
755void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
759 printU4ImmDecOperand(
MI, OpNo, O);
763 unsigned OpNo)
const {
767 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
768 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
772void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
775 unsigned Opc =
MI->getOpcode();
784 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
785 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
786 printDefaultVccOperand(
true, STI, O);
788 printRegularOperand(
MI, OpNo, STI, O);
792void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
797 if (OpNo >=
MI->getNumOperands()) {
798 O <<
"/*Missing OP" << OpNo <<
"*/";
809 int RCID =
Desc.operands()[OpNo].RegClass;
815 <<
"\' register class*/";
818 }
else if (
Op.isImm()) {
819 const uint8_t OpTy =
Desc.operands()[OpNo].OperandType;
834 printImmediate32(
Op.getImm(), STI, O);
838 printImmediate64(
Op.getImm(), STI, O,
false);
843 printImmediate64(
Op.getImm(), STI, O,
true);
848 printImmediateInt16(
Op.getImm(), STI, O);
854 printImmediateF16(
Op.getImm(), STI, O);
860 printImmediateBF16(
Op.getImm(), STI, O);
871 printImmediateV216(
Op.getImm(), OpTy, STI, O);
880 printImmediate32(
Op.getImm(), STI, O);
881 O <<
"/*Invalid immediate*/";
888 }
else if (
Op.isDFPImm()) {
889 double Value = bit_cast<double>(
Op.getDFPImm());
895 int RCID =
Desc.operands()[OpNo].RegClass;
898 printImmediate32(llvm::bit_cast<uint32_t>((
float)
Value), STI, O);
899 else if (RCBits == 64)
900 printImmediate64(llvm::bit_cast<uint64_t>(
Value), STI, O,
true);
904 }
else if (
Op.isExpr()) {
912 switch (
MI->getOpcode()) {
915 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
916 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
917 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
918 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
919 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
920 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
921 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
922 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
923 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
924 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
925 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
926 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
927 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
928 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
929 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
930 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
931 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
932 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
933 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
934 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
935 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
936 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
937 case AMDGPU::V_CNDMASK_B32_e32_gfx12:
938 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
939 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
940 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
941 case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
942 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
943 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
944 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
945 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
946 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
947 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
948 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
950 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
951 case AMDGPU::V_CNDMASK_B32_e32_vi:
953 AMDGPU::OpName::src1))
954 printDefaultVccOperand(OpNo == 0, STI, O);
962 if ((
int)OpNo == SOffsetIdx)
963 printSymbolicFormat(
MI, STI, O);
967void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
972 if (needsImpliedVcc(
Desc, OpNo))
973 printDefaultVccOperand(
true, STI, O);
975 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
980 bool NegMnemo =
false;
983 if (OpNo + 1 <
MI->getNumOperands() &&
986 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
997 printRegularOperand(
MI, OpNo + 1, STI, O);
1006 switch (
MI->getOpcode()) {
1010 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
1011 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
1012 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
1013 if ((
int)OpNo + 1 ==
1015 printDefaultVccOperand(OpNo == 0, STI, O);
1020void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
1025 if (needsImpliedVcc(
Desc, OpNo))
1026 printDefaultVccOperand(
true, STI, O);
1028 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
1031 printRegularOperand(
MI, OpNo + 1, STI, O);
1036 switch (
MI->getOpcode()) {
1039 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
1040 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
1041 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
1043 AMDGPU::OpName::src1))
1044 printDefaultVccOperand(OpNo == 0, STI, O);
1049void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
1055 unsigned Imm =
MI->getOperand(OpNo).getImm();
1057 for (
size_t i = 1; i < 8; ++i) {
1058 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
1063void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
1066 using namespace AMDGPU::DPP;
1068 unsigned Imm =
MI->getOperand(OpNo).getImm();
1072 O <<
" /* DP ALU dpp only supports row_newbcast */";
1075 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
1081 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
1082 (Imm <= DppCtrl::ROW_SHL_LAST)) {
1084 printU4ImmDecOperand(
MI, OpNo, O);
1085 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
1086 (Imm <= DppCtrl::ROW_SHR_LAST)) {
1088 printU4ImmDecOperand(
MI, OpNo, O);
1089 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
1090 (Imm <= DppCtrl::ROW_ROR_LAST)) {
1092 printU4ImmDecOperand(
MI, OpNo, O);
1093 }
else if (Imm == DppCtrl::WAVE_SHL1) {
1095 O <<
"/* wave_shl is not supported starting from GFX10 */";
1099 }
else if (Imm == DppCtrl::WAVE_ROL1) {
1101 O <<
"/* wave_rol is not supported starting from GFX10 */";
1105 }
else if (Imm == DppCtrl::WAVE_SHR1) {
1107 O <<
"/* wave_shr is not supported starting from GFX10 */";
1111 }
else if (Imm == DppCtrl::WAVE_ROR1) {
1113 O <<
"/* wave_ror is not supported starting from GFX10 */";
1117 }
else if (Imm == DppCtrl::ROW_MIRROR) {
1119 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1120 O <<
"row_half_mirror";
1121 }
else if (Imm == DppCtrl::BCAST15) {
1123 O <<
"/* row_bcast is not supported starting from GFX10 */";
1126 O <<
"row_bcast:15";
1127 }
else if (Imm == DppCtrl::BCAST31) {
1129 O <<
"/* row_bcast is not supported starting from GFX10 */";
1132 O <<
"row_bcast:31";
1133 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1134 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1136 O <<
"row_newbcast:";
1140 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
1141 "than GFX90A/GFX10 */";
1144 printU4ImmDecOperand(
MI, OpNo, O);
1145 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1146 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1148 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
1152 printU4ImmDecOperand(
MI, OpNo, O);
1154 O <<
"/* Invalid dpp_ctrl value */";
1158void AMDGPUInstPrinter::printDppRowMask(
const MCInst *
MI,
unsigned OpNo,
1162 printU4ImmOperand(
MI, OpNo, STI, O);
1165void AMDGPUInstPrinter::printDppBankMask(
const MCInst *
MI,
unsigned OpNo,
1169 printU4ImmOperand(
MI, OpNo, STI, O);
1172void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
1175 unsigned Imm =
MI->getOperand(OpNo).getImm();
1177 O <<
" bound_ctrl:1";
1181void AMDGPUInstPrinter::printDppFI(
const MCInst *
MI,
unsigned OpNo,
1184 unsigned Imm =
MI->getOperand(OpNo).getImm();
1185 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1190void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
1194 unsigned Imm =
MI->getOperand(OpNo).getImm();
1196 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
1197 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
1198 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
1199 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
1200 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
1201 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
1202 case SdwaSel::DWORD:
O <<
"DWORD";
break;
1207void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
1211 printSDWASel(
MI, OpNo, O);
1214void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
1218 printSDWASel(
MI, OpNo, O);
1221void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
1225 printSDWASel(
MI, OpNo, O);
1228void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
1234 unsigned Imm =
MI->getOperand(OpNo).getImm();
1236 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
1237 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
1238 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1243void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1246 unsigned Opc =
MI->getOpcode();
1248 unsigned En =
MI->getOperand(EnIdx).getImm();
1253 if (
MI->getOperand(ComprIdx).getImm())
1254 OpNo = OpNo -
N +
N / 2;
1262void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1265 printExpSrcN(
MI, OpNo, STI, O, 0);
1268void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1271 printExpSrcN(
MI, OpNo, STI, O, 1);
1274void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1277 printExpSrcN(
MI, OpNo, STI, O, 2);
1280void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1283 printExpSrcN(
MI, OpNo, STI, O, 3);
1286void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1292 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1297 O <<
' ' << TgtName;
1301 O <<
" invalid_target_" <<
Id;
1306 bool IsPacked,
bool HasDstSel) {
1309 for (
int I = 0;
I < NumOps; ++
I) {
1310 if (!!(Ops[
I] &
Mod) != DefaultValue)
1320void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1324 unsigned Opc =
MI->getOpcode();
1328 std::pair<int, int> MOps[] = {
1329 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
1330 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
1331 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
1334 for (
auto [SrcMod, Src] : MOps) {
1340 (ModIdx != -1) ?
MI->getOperand(ModIdx).getImm() : DefaultValue;
1350 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
1351 AMDGPU::OpName::src2_modifiers}) {
1354 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1356 Ops[NumOps++] = DefaultValue;
1360 const bool HasDstSel =
1372 for (
int I = 0;
I < NumOps; ++
I) {
1376 O << !!(Ops[
I] &
Mod);
1386void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1389 unsigned Opc =
MI->getOpcode();
1393 unsigned Mod =
MI->getOperand(SrcMod).getImm();
1396 if (Index0 || Index1)
1397 O <<
" op_sel:[" << Index0 <<
',' << Index1 <<
']';
1406 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1413void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1419void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1425void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1431void AMDGPUInstPrinter::printIndexKey8bit(
const MCInst *
MI,
unsigned OpNo,
1434 auto Imm =
MI->getOperand(OpNo).getImm() & 0x7;
1438 O <<
" index_key:" <<
Imm;
1441void AMDGPUInstPrinter::printIndexKey16bit(
const MCInst *
MI,
unsigned OpNo,
1444 auto Imm =
MI->getOperand(OpNo).getImm() & 0x7;
1448 O <<
" index_key:" <<
Imm;
1451void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1454 unsigned Imm =
MI->getOperand(OpNum).getImm();
1466 O <<
"invalid_param_" <<
Imm;
1470void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1473 unsigned Attr =
MI->getOperand(OpNum).getImm();
1474 O <<
"attr" << Attr;
1477void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1480 unsigned Chan =
MI->getOperand(OpNum).getImm();
1481 O <<
'.' <<
"xyzw"[Chan & 0x3];
1484void AMDGPUInstPrinter::printGPRIdxMode(
const MCInst *
MI,
unsigned OpNo,
1488 unsigned Val =
MI->getOperand(OpNo).getImm();
1490 if ((Val & ~ENABLE_MASK) != 0) {
1491 O << formatHex(static_cast<uint64_t>(Val));
1494 bool NeedComma =
false;
1495 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1496 if (Val & (1 << ModeId)) {
1507void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1510 printRegularOperand(
MI, OpNo, STI, O);
1512 printRegularOperand(
MI, OpNo + 1, STI, O);
1520 if (
Op.getImm() == 1) {
1531 if (
Op.getImm() == 1)
1538 int Imm =
MI->getOperand(OpNo).getImm();
1552 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1557 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1559 StringRef MsgName = getMsgName(MsgId, STI);
1561 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1562 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1563 O <<
"sendmsg(" << MsgName;
1564 if (msgRequiresOp(MsgId, STI)) {
1565 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1566 if (msgSupportsStream(MsgId, OpId, STI)) {
1571 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1572 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1584 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1585 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1589 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1616 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1623 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1625 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1626 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1633 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1635 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1636 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1637 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1639 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1641 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1646 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1649 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1656 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1657 if (GroupSize > 1 &&
1659 OrMask < GroupSize &&
1662 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1670 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1677 printU16ImmDecOperand(
MI, OpNo, O);
1686 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1687 unsigned Vmcnt, Expcnt, Lgkmcnt;
1693 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1695 bool NeedSpace =
false;
1697 if (!IsDefaultVmcnt || PrintAll) {
1698 O <<
"vmcnt(" << Vmcnt <<
')';
1702 if (!IsDefaultExpcnt || PrintAll) {
1705 O <<
"expcnt(" << Expcnt <<
')';
1709 if (!IsDefaultLgkmcnt || PrintAll) {
1712 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1721 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1723 bool HasNonDefaultVal =
false;
1724 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1729 bool NeedSpace =
false;
1730 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1731 if (!IsDefault || !HasNonDefaultVal) {
1734 O <<
Name <<
'(' << Val <<
')';
1746 const char *BadInstId =
"/* invalid instid value */";
1747 static const std::array<const char *, 12> InstIds = {
1748 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1749 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1750 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1751 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1753 const char *BadInstSkip =
"/* invalid instskip value */";
1754 static const std::array<const char *, 6> InstSkips = {
1755 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1757 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1758 const char *Prefix =
"";
1760 unsigned Value = SImm16 & 0xF;
1762 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1763 O << Prefix <<
"instid0(" <<
Name <<
')';
1767 Value = (SImm16 >> 4) & 7;
1770 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1771 O << Prefix <<
"instskip(" <<
Name <<
')';
1775 Value = (SImm16 >> 7) & 0xF;
1777 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1778 O << Prefix <<
"instid1(" <<
Name <<
')';
1789 unsigned Val =
MI->getOperand(OpNo).getImm();
1790 auto [
Id,
Offset, Width] = HwregEncoding::decode(Val);
1794 if (!HwRegName.
empty()) {
1799 if (Width != HwregSize::Default ||
Offset != HwregOffset::Default)
1800 O <<
", " <<
Offset <<
", " << Width;
1807 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1815void AMDGPUInstPrinter::printByteSel(
const MCInst *
MI,
unsigned OpNo,
1818 uint8_t Imm =
MI->getOperand(OpNo).getImm();
1825#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
bool mayStore() const
Return true if this instruction could possibly modify memory.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isVOPCAsmOnly(unsigned Opc)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_BF16
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_IMM_BF16_DEFERRED
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_AC_BF16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.
Description of the encoding of one expression Op.