28 "amdgpu-keep-16-bit-reg-suffixes",
29 cl::desc(
"Keep .l and .h suffixes in asm for debugging purposes"),
57void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
60 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
63void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
68 int64_t Imm =
MI->getOperand(OpNo).getImm();
69 if (isInt<16>(Imm) || isUInt<16>(Imm))
70 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
72 printU32ImmOperand(
MI, OpNo, STI, O);
75void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
80void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
85void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
90void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
93 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
96void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
98 if (
MI->getOperand(OpNo).getImm()) {
103void AMDGPUInstPrinter::printOffen(
const MCInst *
MI,
unsigned OpNo,
105 printNamedBit(
MI, OpNo, O,
"offen");
108void AMDGPUInstPrinter::printIdxen(
const MCInst *
MI,
unsigned OpNo,
110 printNamedBit(
MI, OpNo, O,
"idxen");
113void AMDGPUInstPrinter::printAddr64(
const MCInst *
MI,
unsigned OpNo,
115 printNamedBit(
MI, OpNo, O,
"addr64");
118void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
124 printU16ImmDecOperand(
MI, OpNo, O);
128void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
136 bool IsFlatSeg = !(Desc.
TSFlags &
140 printU16ImmDecOperand(
MI, OpNo, O);
146void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
149 if (
MI->getOperand(OpNo).getImm()) {
151 printU8ImmDecOperand(
MI, OpNo, O);
155void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
158 if (
MI->getOperand(OpNo).getImm()) {
160 printU8ImmDecOperand(
MI, OpNo, O);
164void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
167 printU32ImmOperand(
MI, OpNo, STI, O);
170void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
176void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
180 printSMEMOffset(
MI, OpNo, STI, O);
183void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
186 printU32ImmOperand(
MI, OpNo, STI, O);
189void AMDGPUInstPrinter::printGDS(
const MCInst *
MI,
unsigned OpNo,
191 printNamedBit(
MI, OpNo, O,
"gds");
194void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
196 auto Imm =
MI->getOperand(OpNo).getImm();
208 O <<
" /* unexpected cache policy bit */";
211void AMDGPUInstPrinter::printSWZ(
const MCInst *
MI,
unsigned OpNo,
215void AMDGPUInstPrinter::printTFE(
const MCInst *
MI,
unsigned OpNo,
217 printNamedBit(
MI, OpNo, O,
"tfe");
220void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
222 if (
MI->getOperand(OpNo).getImm()) {
224 printU16ImmOperand(
MI, OpNo, STI, O);
228void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
230 unsigned Dim =
MI->getOperand(OpNo).getImm();
231 O <<
" dim:SQ_RSRC_IMG_";
240void AMDGPUInstPrinter::printUNorm(
const MCInst *
MI,
unsigned OpNo,
242 printNamedBit(
MI, OpNo, O,
"unorm");
245void AMDGPUInstPrinter::printDA(
const MCInst *
MI,
unsigned OpNo,
247 printNamedBit(
MI, OpNo, O,
"da");
250void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
253 printNamedBit(
MI, OpNo, O,
"a16");
255 printNamedBit(
MI, OpNo, O,
"r128");
258void AMDGPUInstPrinter::printA16(
const MCInst *
MI,
unsigned OpNo,
260 printNamedBit(
MI, OpNo, O,
"a16");
263void AMDGPUInstPrinter::printLWE(
const MCInst *
MI,
unsigned OpNo,
265 printNamedBit(
MI, OpNo, O,
"lwe");
268void AMDGPUInstPrinter::printD16(
const MCInst *
MI,
unsigned OpNo,
270 printNamedBit(
MI, OpNo, O,
"d16");
273void AMDGPUInstPrinter::printExpCompr(
const MCInst *
MI,
unsigned OpNo,
276 printNamedBit(
MI, OpNo, O,
"compr");
279void AMDGPUInstPrinter::printExpVM(
const MCInst *
MI,
unsigned OpNo,
282 printNamedBit(
MI, OpNo, O,
"vm");
285void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
290void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
299 unsigned Val =
MI->getOperand(OpNo).getImm();
301 if (Val == UFMT_DEFAULT)
306 O <<
" format:" << Val;
309 if (Val == DFMT_NFMT_DEFAULT)
316 if (Dfmt != DFMT_DEFAULT) {
318 if (Nfmt != NFMT_DEFAULT) {
322 if (Nfmt != NFMT_DEFAULT) {
327 O <<
" format:" << Val;
338 case AMDGPU::PRIVATE_RSRC_REG:
349 if (!
RegName.consume_back(
".l"))
355void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
357 auto Opcode =
MI->getOpcode();
375 printRegularOperand(
MI, OpNo, STI, O);
381 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
382 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
383 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
384 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
385 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
386 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
387 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
388 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
389 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
390 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
391 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
392 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
393 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
394 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
395 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
396 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
397 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
398 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
399 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
400 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
401 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
402 printDefaultVccOperand(
false, STI, O);
407void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
414 printRegularOperand(
MI, OpNo, STI, O);
417void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
420 int16_t SImm =
static_cast<int16_t
>(
Imm);
429void AMDGPUInstPrinter::printImmediate16(
uint32_t Imm,
432 int16_t SImm =
static_cast<int16_t
>(
Imm);
440 else if (Imm == 0xBC00)
442 else if (Imm == 0x3800)
444 else if (Imm == 0xB800)
446 else if (Imm == 0x4000)
448 else if (Imm == 0xC000)
450 else if (Imm == 0x4400)
452 else if (Imm == 0xC400)
454 else if (Imm == 0x3118 &&
455 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm)) {
463void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm,
467 printImmediate16(Lo16, STI, O);
470void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
473 int32_t SImm =
static_cast<int32_t
>(
Imm);
474 if (SImm >= -16 && SImm <= 64) {
479 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
481 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
483 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
485 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
487 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
489 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
491 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
493 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
495 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
497 else if (Imm == 0x3e22f983 &&
498 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
501 O << formatHex(static_cast<uint64_t>(Imm));
504void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
507 int64_t SImm =
static_cast<int64_t
>(
Imm);
508 if (SImm >= -16 && SImm <= 64) {
513 if (Imm == llvm::bit_cast<uint64_t>(0.0))
515 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
517 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
519 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
521 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
523 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
525 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
527 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
529 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
531 else if (Imm == 0x3fc45f306dc9c882 &&
532 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
533 O <<
"0.15915494309189532";
535 assert(isUInt<32>(Imm) || isInt<32>(Imm));
539 O << formatHex(static_cast<uint64_t>(Imm));
543void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
546 unsigned Imm =
MI->getOperand(OpNo).getImm();
551 switch (
MI->getOpcode()) {
552 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
553 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
554 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
555 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
556 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
557 << ((Imm >> 2) & 1) <<
']';
562 O <<
" blgp:" <<
Imm;
565void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
568 unsigned Imm =
MI->getOperand(OpNo).getImm();
572 O <<
" cbsz:" <<
Imm;
575void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
578 unsigned Imm =
MI->getOperand(OpNo).getImm();
582 O <<
" abid:" <<
Imm;
585void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
598void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
601 uint8_t
Imm =
MI->getOperand(OpNo).getImm();
604 printU4ImmDecOperand(
MI, OpNo, O);
608void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
611 uint8_t
Imm =
MI->getOperand(OpNo).getImm();
614 printU4ImmDecOperand(
MI, OpNo, O);
618bool AMDGPUInstPrinter::needsImpliedVcc(
const MCInstrDesc &Desc,
619 unsigned OpNo)
const {
627void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
630 unsigned Opc =
MI->getOpcode();
641 printDefaultVccOperand(
true, STI, O);
643 printRegularOperand(
MI, OpNo, STI, O);
647void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
652 if (OpNo >=
MI->getNumOperands()) {
653 O <<
"/*Missing OP" << OpNo <<
"*/";
664 int RCID = Desc.
operands()[OpNo].RegClass;
670 <<
"\' register class*/";
673 }
else if (
Op.isImm()) {
674 const uint8_t OpTy = Desc.
operands()[OpNo].OperandType;
688 printImmediate32(
Op.getImm(), STI, O);
695 printImmediate64(
Op.getImm(), STI, O);
700 printImmediateInt16(
Op.getImm(), STI, O);
706 printImmediate16(
Op.getImm(), STI, O);
710 if (!isUInt<16>(
Op.getImm()) &&
712 printImmediate32(
Op.getImm(), STI, O);
718 printImmediate16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
724 printImmediateInt16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
728 printImmediateV216(
Op.getImm(), STI, O);
737 printImmediate32(
Op.getImm(), STI, O);
738 O <<
"/*Invalid immediate*/";
745 }
else if (
Op.isDFPImm()) {
746 double Value = bit_cast<double>(
Op.getDFPImm());
752 int RCID = Desc.
operands()[OpNo].RegClass;
755 printImmediate32(llvm::bit_cast<uint32_t>((
float)
Value), STI, O);
756 else if (RCBits == 64)
757 printImmediate64(llvm::bit_cast<uint64_t>(
Value), STI, O);
761 }
else if (
Op.isExpr()) {
769 switch (
MI->getOpcode()) {
772 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
773 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
774 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
775 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
776 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
777 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
778 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
779 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
780 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
781 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
782 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
783 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
784 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
785 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
786 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
787 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
788 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
789 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
790 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
791 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
792 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
793 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
795 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
796 case AMDGPU::V_CNDMASK_B32_e32_vi:
798 AMDGPU::OpName::src1))
799 printDefaultVccOperand(OpNo == 0, STI, O);
807 if ((
int)OpNo == SOffsetIdx)
808 printSymbolicFormat(
MI, STI, O);
812void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
817 if (needsImpliedVcc(Desc, OpNo))
818 printDefaultVccOperand(
true, STI, O);
820 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
825 bool NegMnemo =
false;
828 if (OpNo + 1 <
MI->getNumOperands() &&
831 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
842 printRegularOperand(
MI, OpNo + 1, STI, O);
851 switch (
MI->getOpcode()) {
855 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
856 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
857 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
860 printDefaultVccOperand(OpNo == 0, STI, O);
865void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
870 if (needsImpliedVcc(Desc, OpNo))
871 printDefaultVccOperand(
true, STI, O);
873 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
876 printRegularOperand(
MI, OpNo + 1, STI, O);
881 switch (
MI->getOpcode()) {
884 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
885 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
886 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
888 AMDGPU::OpName::src1))
889 printDefaultVccOperand(OpNo == 0, STI, O);
894void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
900 unsigned Imm =
MI->getOperand(OpNo).getImm();
902 for (
size_t i = 1; i < 8; ++i) {
903 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
908void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
911 using namespace AMDGPU::DPP;
913 unsigned Imm =
MI->getOperand(OpNo).getImm();
916 AMDGPU::OpName::src0);
919 Desc.
operands()[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID &&
921 O <<
" /* 64 bit dpp only supports row_newbcast */";
923 }
else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
929 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
930 (Imm <= DppCtrl::ROW_SHL_LAST)) {
932 printU4ImmDecOperand(
MI, OpNo, O);
933 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
934 (Imm <= DppCtrl::ROW_SHR_LAST)) {
936 printU4ImmDecOperand(
MI, OpNo, O);
937 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
938 (Imm <= DppCtrl::ROW_ROR_LAST)) {
940 printU4ImmDecOperand(
MI, OpNo, O);
941 }
else if (Imm == DppCtrl::WAVE_SHL1) {
943 O <<
"/* wave_shl is not supported starting from GFX10 */";
947 }
else if (Imm == DppCtrl::WAVE_ROL1) {
949 O <<
"/* wave_rol is not supported starting from GFX10 */";
953 }
else if (Imm == DppCtrl::WAVE_SHR1) {
955 O <<
"/* wave_shr is not supported starting from GFX10 */";
959 }
else if (Imm == DppCtrl::WAVE_ROR1) {
961 O <<
"/* wave_ror is not supported starting from GFX10 */";
965 }
else if (Imm == DppCtrl::ROW_MIRROR) {
967 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
968 O <<
"row_half_mirror";
969 }
else if (Imm == DppCtrl::BCAST15) {
971 O <<
"/* row_bcast is not supported starting from GFX10 */";
975 }
else if (Imm == DppCtrl::BCAST31) {
977 O <<
"/* row_bcast is not supported starting from GFX10 */";
981 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
982 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
984 O <<
"row_newbcast:";
988 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
989 "than GFX90A/GFX10 */";
992 printU4ImmDecOperand(
MI, OpNo, O);
993 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
994 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
996 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
1000 printU4ImmDecOperand(
MI, OpNo, O);
1002 O <<
"/* Invalid dpp_ctrl value */";
1006void AMDGPUInstPrinter::printDppRowMask(
const MCInst *
MI,
unsigned OpNo,
1010 printU4ImmOperand(
MI, OpNo, STI, O);
1013void AMDGPUInstPrinter::printDppBankMask(
const MCInst *
MI,
unsigned OpNo,
1017 printU4ImmOperand(
MI, OpNo, STI, O);
1020void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
1023 unsigned Imm =
MI->getOperand(OpNo).getImm();
1025 O <<
" bound_ctrl:1";
1029void AMDGPUInstPrinter::printDppFI(
const MCInst *
MI,
unsigned OpNo,
1032 unsigned Imm =
MI->getOperand(OpNo).getImm();
1033 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1038void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
1042 unsigned Imm =
MI->getOperand(OpNo).getImm();
1044 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
1045 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
1046 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
1047 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
1048 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
1049 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
1050 case SdwaSel::DWORD:
O <<
"DWORD";
break;
1055void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
1059 printSDWASel(
MI, OpNo, O);
1062void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
1066 printSDWASel(
MI, OpNo, O);
1069void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
1073 printSDWASel(
MI, OpNo, O);
1076void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
1082 unsigned Imm =
MI->getOperand(OpNo).getImm();
1084 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
1085 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
1086 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1091void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1094 unsigned Opc =
MI->getOpcode();
1096 unsigned En =
MI->getOperand(EnIdx).getImm();
1101 if (
MI->getOperand(ComprIdx).getImm())
1102 OpNo = OpNo -
N +
N / 2;
1110void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1113 printExpSrcN(
MI, OpNo, STI, O, 0);
1116void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1119 printExpSrcN(
MI, OpNo, STI, O, 1);
1122void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1125 printExpSrcN(
MI, OpNo, STI, O, 2);
1128void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1131 printExpSrcN(
MI, OpNo, STI, O, 3);
1134void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1140 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1145 O <<
' ' << TgtName;
1149 O <<
" invalid_target_" <<
Id;
1154 bool IsPacked,
bool HasDstSel) {
1157 for (
int I = 0;
I < NumOps; ++
I) {
1158 if (!!(Ops[
I] &
Mod) != DefaultValue)
1168void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1172 unsigned Opc =
MI->getOpcode();
1176 for (
int OpName : { AMDGPU::OpName::src0_modifiers,
1177 AMDGPU::OpName::src1_modifiers,
1178 AMDGPU::OpName::src2_modifiers }) {
1183 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1186 const bool HasDstSel =
1198 for (
int I = 0;
I < NumOps; ++
I) {
1202 O << !!(Ops[
I] &
Mod);
1212void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1215 unsigned Opc =
MI->getOpcode();
1222 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1229void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1235void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1241void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1247void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1250 unsigned Imm =
MI->getOperand(OpNum).getImm();
1262 O <<
"invalid_param_" <<
Imm;
1266void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1269 unsigned Attr =
MI->getOperand(OpNum).getImm();
1270 O <<
"attr" << Attr;
1273void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1276 unsigned Chan =
MI->getOperand(OpNum).getImm();
1277 O <<
'.' <<
"xyzw"[Chan & 0x3];
1280void AMDGPUInstPrinter::printVGPRIndexMode(
const MCInst *
MI,
unsigned OpNo,
1284 unsigned Val =
MI->getOperand(OpNo).getImm();
1286 if ((Val & ~ENABLE_MASK) != 0) {
1287 O << formatHex(static_cast<uint64_t>(Val));
1290 bool NeedComma =
false;
1291 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1292 if (Val & (1 << ModeId)) {
1303void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1306 printRegularOperand(
MI, OpNo, STI, O);
1308 printRegularOperand(
MI, OpNo + 1, STI, O);
1316 if (Op.getImm() == 1) {
1327 if (Op.getImm() == 1)
1334 printNamedBit(
MI, OpNo, O,
"high");
1340 printNamedBit(
MI, OpNo, O,
"clamp");
1346 int Imm =
MI->getOperand(OpNo).getImm();
1360 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1365 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1367 StringRef MsgName = getMsgName(MsgId, STI);
1369 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1370 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1371 O <<
"sendmsg(" << MsgName;
1372 if (msgRequiresOp(MsgId, STI)) {
1373 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1374 if (msgSupportsStream(MsgId, OpId, STI)) {
1379 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1380 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1392 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1393 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1397 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1424 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1431 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1433 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1434 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1441 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1443 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1444 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1445 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1447 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1449 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1454 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1457 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1464 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1465 if (GroupSize > 1 &&
1467 OrMask < GroupSize &&
1470 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1478 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1485 printU16ImmDecOperand(
MI, OpNo, O);
1494 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1495 unsigned Vmcnt, Expcnt, Lgkmcnt;
1501 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1503 bool NeedSpace =
false;
1505 if (!IsDefaultVmcnt || PrintAll) {
1506 O <<
"vmcnt(" << Vmcnt <<
')';
1510 if (!IsDefaultExpcnt || PrintAll) {
1513 O <<
"expcnt(" << Expcnt <<
')';
1517 if (!IsDefaultLgkmcnt || PrintAll) {
1520 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1529 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1531 bool HasNonDefaultVal =
false;
1532 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1537 bool NeedSpace =
false;
1538 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1539 if (!IsDefault || !HasNonDefaultVal) {
1542 O <<
Name <<
'(' << Val <<
')';
1554 const char *BadInstId =
"/* invalid instid value */";
1555 static const std::array<const char *, 12> InstIds = {
1556 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1557 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1558 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1559 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1561 const char *BadInstSkip =
"/* invalid instskip value */";
1562 static const std::array<const char *, 6> InstSkips = {
1563 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1565 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1566 const char *Prefix =
"";
1568 unsigned Value = SImm16 & 0xF;
1570 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1571 O << Prefix <<
"instid0(" <<
Name <<
')';
1575 Value = (SImm16 >> 4) & 7;
1578 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1579 O << Prefix <<
"instskip(" <<
Name <<
')';
1583 Value = (SImm16 >> 7) & 0xF;
1585 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1586 O << Prefix <<
"instid1(" <<
Name <<
')';
1601 unsigned Val =
MI->getOperand(OpNo).getImm();
1606 if (!HwRegName.
empty()) {
1611 if (
Width != WIDTH_DEFAULT_ ||
Offset != OFFSET_DEFAULT_) {
1620 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1628#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
static cl::opt< bool > Keep16BitSuffixes("amdgpu-keep-16-bit-reg-suffixes", cl::desc("Keep .l and .h suffixes in asm for debugging purposes"), cl::init(false), cl::ReallyHidden)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printDelayFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printWaitFlag(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
ArrayRef< MCOperandInfo > operands() const
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.