51void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
54 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xf);
57void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *
MI,
unsigned OpNo,
62 int64_t Imm =
MI->getOperand(OpNo).getImm();
63 if (isInt<16>(Imm) || isUInt<16>(Imm))
64 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
66 printU32ImmOperand(
MI, OpNo, STI, O);
69void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
74void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
79void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *
MI,
unsigned OpNo,
84void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *
MI,
unsigned OpNo,
87 O <<
formatHex(
MI->getOperand(OpNo).getImm() & 0xffffffff);
90void AMDGPUInstPrinter::printNamedBit(
const MCInst *
MI,
unsigned OpNo,
92 if (
MI->getOperand(OpNo).getImm()) {
97void AMDGPUInstPrinter::printOffset(
const MCInst *
MI,
unsigned OpNo,
103 printU16ImmDecOperand(
MI, OpNo, O);
107void AMDGPUInstPrinter::printFlatOffset(
const MCInst *
MI,
unsigned OpNo,
115 bool IsFlatSeg = !(
Desc.TSFlags &
119 printU16ImmDecOperand(
MI, OpNo, O);
125void AMDGPUInstPrinter::printOffset0(
const MCInst *
MI,
unsigned OpNo,
128 if (
MI->getOperand(OpNo).getImm()) {
130 printU8ImmDecOperand(
MI, OpNo, O);
134void AMDGPUInstPrinter::printOffset1(
const MCInst *
MI,
unsigned OpNo,
137 if (
MI->getOperand(OpNo).getImm()) {
139 printU8ImmDecOperand(
MI, OpNo, O);
143void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *
MI,
unsigned OpNo,
146 printU32ImmOperand(
MI, OpNo, STI, O);
149void AMDGPUInstPrinter::printSMEMOffset(
const MCInst *
MI,
unsigned OpNo,
155void AMDGPUInstPrinter::printSMEMOffsetMod(
const MCInst *
MI,
unsigned OpNo,
159 printSMEMOffset(
MI, OpNo, STI, O);
162void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *
MI,
unsigned OpNo,
165 printU32ImmOperand(
MI, OpNo, STI, O);
168void AMDGPUInstPrinter::printCPol(
const MCInst *
MI,
unsigned OpNo,
170 auto Imm =
MI->getOperand(OpNo).getImm();
182 O <<
" /* unexpected cache policy bit */";
185void AMDGPUInstPrinter::printDMask(
const MCInst *
MI,
unsigned OpNo,
187 if (
MI->getOperand(OpNo).getImm()) {
189 printU16ImmOperand(
MI, OpNo, STI, O);
193void AMDGPUInstPrinter::printDim(
const MCInst *
MI,
unsigned OpNo,
195 unsigned Dim =
MI->getOperand(OpNo).getImm();
196 O <<
" dim:SQ_RSRC_IMG_";
205void AMDGPUInstPrinter::printR128A16(
const MCInst *
MI,
unsigned OpNo,
208 printNamedBit(
MI, OpNo, O,
"a16");
210 printNamedBit(
MI, OpNo, O,
"r128");
213void AMDGPUInstPrinter::printFORMAT(
const MCInst *
MI,
unsigned OpNo,
218void AMDGPUInstPrinter::printSymbolicFormat(
const MCInst *
MI,
227 unsigned Val =
MI->getOperand(OpNo).getImm();
229 if (Val == UFMT_DEFAULT)
234 O <<
" format:" << Val;
237 if (Val == DFMT_NFMT_DEFAULT)
244 if (Dfmt != DFMT_DEFAULT) {
246 if (Nfmt != NFMT_DEFAULT) {
250 if (Nfmt != NFMT_DEFAULT) {
255 O <<
" format:" << Val;
266 case AMDGPU::PRIVATE_RSRC_REG:
278void AMDGPUInstPrinter::printVOPDst(
const MCInst *
MI,
unsigned OpNo,
298 printRegularOperand(
MI, OpNo, STI, O);
304 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
305 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
306 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
307 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
308 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
309 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
310 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
311 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
312 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
313 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
314 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
315 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
316 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
317 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
318 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
319 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
320 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
321 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
322 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
323 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
324 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
325 printDefaultVccOperand(
false, STI, O);
330void AMDGPUInstPrinter::printVINTRPDst(
const MCInst *
MI,
unsigned OpNo,
337 printRegularOperand(
MI, OpNo, STI, O);
340void AMDGPUInstPrinter::printImmediateInt16(
uint32_t Imm,
343 int16_t SImm =
static_cast<int16_t
>(
Imm);
352void AMDGPUInstPrinter::printImmediate16(
uint32_t Imm,
355 int16_t SImm =
static_cast<int16_t
>(
Imm);
363 else if (Imm == 0xBC00)
365 else if (Imm == 0x3800)
367 else if (Imm == 0xB800)
369 else if (Imm == 0x4000)
371 else if (Imm == 0xC000)
373 else if (Imm == 0x4400)
375 else if (Imm == 0xC400)
377 else if (Imm == 0x3118 &&
378 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm)) {
386void AMDGPUInstPrinter::printImmediateV216(
uint32_t Imm,
390 printImmediate16(Lo16, STI, O);
393void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
396 int32_t SImm =
static_cast<int32_t
>(
Imm);
397 if (SImm >= -16 && SImm <= 64) {
402 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
404 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
406 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
408 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
410 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
412 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
414 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
416 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
418 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
420 else if (Imm == 0x3e22f983 &&
421 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
424 O << formatHex(static_cast<uint64_t>(Imm));
427void AMDGPUInstPrinter::printImmediate64(
uint64_t Imm,
430 int64_t SImm =
static_cast<int64_t
>(
Imm);
431 if (SImm >= -16 && SImm <= 64) {
436 if (Imm == llvm::bit_cast<uint64_t>(0.0))
438 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
440 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
442 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
444 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
446 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
448 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
450 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
452 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
454 else if (Imm == 0x3fc45f306dc9c882 &&
455 STI.
hasFeature(AMDGPU::FeatureInv2PiInlineImm))
456 O <<
"0.15915494309189532";
459 O << formatHex(static_cast<uint64_t>(
Hi_32(Imm)));
461 assert(isUInt<32>(Imm) || isInt<32>(Imm));
465 O << formatHex(static_cast<uint64_t>(Imm));
469void AMDGPUInstPrinter::printBLGP(
const MCInst *
MI,
unsigned OpNo,
472 unsigned Imm =
MI->getOperand(OpNo).getImm();
477 switch (
MI->getOpcode()) {
478 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
479 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
480 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
481 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
482 O <<
" neg:[" << (
Imm & 1) <<
',' << ((Imm >> 1) & 1) <<
','
483 << ((Imm >> 2) & 1) <<
']';
488 O <<
" blgp:" <<
Imm;
491void AMDGPUInstPrinter::printCBSZ(
const MCInst *
MI,
unsigned OpNo,
494 unsigned Imm =
MI->getOperand(OpNo).getImm();
498 O <<
" cbsz:" <<
Imm;
501void AMDGPUInstPrinter::printABID(
const MCInst *
MI,
unsigned OpNo,
504 unsigned Imm =
MI->getOperand(OpNo).getImm();
508 O <<
" abid:" <<
Imm;
511void AMDGPUInstPrinter::printDefaultVccOperand(
bool FirstOperand,
524void AMDGPUInstPrinter::printWaitVDST(
const MCInst *
MI,
unsigned OpNo,
528 printU4ImmDecOperand(
MI, OpNo, O);
531void AMDGPUInstPrinter::printWaitEXP(
const MCInst *
MI,
unsigned OpNo,
535 printU4ImmDecOperand(
MI, OpNo, O);
539 unsigned OpNo)
const {
542 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
543 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
547void AMDGPUInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
550 unsigned Opc =
MI->getOpcode();
559 (
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
560 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
561 printDefaultVccOperand(
true, STI, O);
563 printRegularOperand(
MI, OpNo, STI, O);
567void AMDGPUInstPrinter::printRegularOperand(
const MCInst *
MI,
unsigned OpNo,
572 if (OpNo >=
MI->getNumOperands()) {
573 O <<
"/*Missing OP" << OpNo <<
"*/";
584 int RCID =
Desc.operands()[OpNo].RegClass;
590 <<
"\' register class*/";
593 }
else if (
Op.isImm()) {
594 const uint8_t OpTy =
Desc.operands()[OpNo].OperandType;
608 printImmediate32(
Op.getImm(), STI, O);
612 printImmediate64(
Op.getImm(), STI, O,
false);
617 printImmediate64(
Op.getImm(), STI, O,
true);
622 printImmediateInt16(
Op.getImm(), STI, O);
628 printImmediate16(
Op.getImm(), STI, O);
632 if (!isUInt<16>(
Op.getImm()) &&
634 printImmediate32(
Op.getImm(), STI, O);
640 printImmediate16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
646 printImmediateInt16(
static_cast<uint16_t>(
Op.getImm()), STI, O);
650 printImmediateV216(
Op.getImm(), STI, O);
659 printImmediate32(
Op.getImm(), STI, O);
660 O <<
"/*Invalid immediate*/";
667 }
else if (
Op.isDFPImm()) {
668 double Value = bit_cast<double>(
Op.getDFPImm());
674 int RCID =
Desc.operands()[OpNo].RegClass;
677 printImmediate32(llvm::bit_cast<uint32_t>((
float)
Value), STI, O);
678 else if (RCBits == 64)
679 printImmediate64(llvm::bit_cast<uint64_t>(
Value), STI, O,
true);
683 }
else if (
Op.isExpr()) {
691 switch (
MI->getOpcode()) {
694 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
695 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
696 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
697 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
698 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
699 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
700 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
701 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
702 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
703 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
704 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
705 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
706 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
707 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
708 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
709 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
710 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
711 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
712 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
713 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
714 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
715 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
717 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
718 case AMDGPU::V_CNDMASK_B32_e32_vi:
720 AMDGPU::OpName::src1))
721 printDefaultVccOperand(OpNo == 0, STI, O);
729 if ((
int)OpNo == SOffsetIdx)
730 printSymbolicFormat(
MI, STI, O);
734void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *
MI,
739 if (needsImpliedVcc(
Desc, OpNo))
740 printDefaultVccOperand(
true, STI, O);
742 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
747 bool NegMnemo =
false;
750 if (OpNo + 1 <
MI->getNumOperands() &&
753 NegMnemo =
Op.isImm() ||
Op.isDFPImm();
764 printRegularOperand(
MI, OpNo + 1, STI, O);
773 switch (
MI->getOpcode()) {
777 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
778 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
779 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
782 printDefaultVccOperand(OpNo == 0, STI, O);
787void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *
MI,
792 if (needsImpliedVcc(
Desc, OpNo))
793 printDefaultVccOperand(
true, STI, O);
795 unsigned InputModifiers =
MI->getOperand(OpNo).getImm();
798 printRegularOperand(
MI, OpNo + 1, STI, O);
803 switch (
MI->getOpcode()) {
806 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
807 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
808 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
810 AMDGPU::OpName::src1))
811 printDefaultVccOperand(OpNo == 0, STI, O);
816void AMDGPUInstPrinter::printDPP8(
const MCInst *
MI,
unsigned OpNo,
822 unsigned Imm =
MI->getOperand(OpNo).getImm();
824 for (
size_t i = 1; i < 8; ++i) {
825 O <<
',' <<
formatDec((Imm >> (3 * i)) & 0x7);
830void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *
MI,
unsigned OpNo,
833 using namespace AMDGPU::DPP;
835 unsigned Imm =
MI->getOperand(OpNo).getImm();
839 O <<
" /* DP ALU dpp only supports row_newbcast */";
841 }
else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
847 }
else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
848 (Imm <= DppCtrl::ROW_SHL_LAST)) {
850 printU4ImmDecOperand(
MI, OpNo, O);
851 }
else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
852 (Imm <= DppCtrl::ROW_SHR_LAST)) {
854 printU4ImmDecOperand(
MI, OpNo, O);
855 }
else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
856 (Imm <= DppCtrl::ROW_ROR_LAST)) {
858 printU4ImmDecOperand(
MI, OpNo, O);
859 }
else if (Imm == DppCtrl::WAVE_SHL1) {
861 O <<
"/* wave_shl is not supported starting from GFX10 */";
865 }
else if (Imm == DppCtrl::WAVE_ROL1) {
867 O <<
"/* wave_rol is not supported starting from GFX10 */";
871 }
else if (Imm == DppCtrl::WAVE_SHR1) {
873 O <<
"/* wave_shr is not supported starting from GFX10 */";
877 }
else if (Imm == DppCtrl::WAVE_ROR1) {
879 O <<
"/* wave_ror is not supported starting from GFX10 */";
883 }
else if (Imm == DppCtrl::ROW_MIRROR) {
885 }
else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
886 O <<
"row_half_mirror";
887 }
else if (Imm == DppCtrl::BCAST15) {
889 O <<
"/* row_bcast is not supported starting from GFX10 */";
893 }
else if (Imm == DppCtrl::BCAST31) {
895 O <<
"/* row_bcast is not supported starting from GFX10 */";
899 }
else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
900 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
902 O <<
"row_newbcast:";
906 O <<
" /* row_newbcast/row_share is not supported on ASICs earlier "
907 "than GFX90A/GFX10 */";
910 printU4ImmDecOperand(
MI, OpNo, O);
911 }
else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
912 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
914 O <<
"/* row_xmask is not supported on ASICs earlier than GFX10 */";
918 printU4ImmDecOperand(
MI, OpNo, O);
920 O <<
"/* Invalid dpp_ctrl value */";
924void AMDGPUInstPrinter::printDppRowMask(
const MCInst *
MI,
unsigned OpNo,
928 printU4ImmOperand(
MI, OpNo, STI, O);
931void AMDGPUInstPrinter::printDppBankMask(
const MCInst *
MI,
unsigned OpNo,
935 printU4ImmOperand(
MI, OpNo, STI, O);
938void AMDGPUInstPrinter::printDppBoundCtrl(
const MCInst *
MI,
unsigned OpNo,
941 unsigned Imm =
MI->getOperand(OpNo).getImm();
943 O <<
" bound_ctrl:1";
947void AMDGPUInstPrinter::printDppFI(
const MCInst *
MI,
unsigned OpNo,
950 unsigned Imm =
MI->getOperand(OpNo).getImm();
951 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
956void AMDGPUInstPrinter::printSDWASel(
const MCInst *
MI,
unsigned OpNo,
960 unsigned Imm =
MI->getOperand(OpNo).getImm();
962 case SdwaSel::BYTE_0:
O <<
"BYTE_0";
break;
963 case SdwaSel::BYTE_1:
O <<
"BYTE_1";
break;
964 case SdwaSel::BYTE_2:
O <<
"BYTE_2";
break;
965 case SdwaSel::BYTE_3:
O <<
"BYTE_3";
break;
966 case SdwaSel::WORD_0:
O <<
"WORD_0";
break;
967 case SdwaSel::WORD_1:
O <<
"WORD_1";
break;
968 case SdwaSel::DWORD:
O <<
"DWORD";
break;
973void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *
MI,
unsigned OpNo,
977 printSDWASel(
MI, OpNo, O);
980void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *
MI,
unsigned OpNo,
984 printSDWASel(
MI, OpNo, O);
987void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *
MI,
unsigned OpNo,
991 printSDWASel(
MI, OpNo, O);
994void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *
MI,
unsigned OpNo,
1000 unsigned Imm =
MI->getOperand(OpNo).getImm();
1002 case DstUnused::UNUSED_PAD:
O <<
"UNUSED_PAD";
break;
1003 case DstUnused::UNUSED_SEXT:
O <<
"UNUSED_SEXT";
break;
1004 case DstUnused::UNUSED_PRESERVE:
O <<
"UNUSED_PRESERVE";
break;
1009void AMDGPUInstPrinter::printExpSrcN(
const MCInst *
MI,
unsigned OpNo,
1012 unsigned Opc =
MI->getOpcode();
1014 unsigned En =
MI->getOperand(EnIdx).getImm();
1019 if (
MI->getOperand(ComprIdx).getImm())
1020 OpNo = OpNo -
N +
N / 2;
1028void AMDGPUInstPrinter::printExpSrc0(
const MCInst *
MI,
unsigned OpNo,
1031 printExpSrcN(
MI, OpNo, STI, O, 0);
1034void AMDGPUInstPrinter::printExpSrc1(
const MCInst *
MI,
unsigned OpNo,
1037 printExpSrcN(
MI, OpNo, STI, O, 1);
1040void AMDGPUInstPrinter::printExpSrc2(
const MCInst *
MI,
unsigned OpNo,
1043 printExpSrcN(
MI, OpNo, STI, O, 2);
1046void AMDGPUInstPrinter::printExpSrc3(
const MCInst *
MI,
unsigned OpNo,
1049 printExpSrcN(
MI, OpNo, STI, O, 3);
1052void AMDGPUInstPrinter::printExpTgt(
const MCInst *
MI,
unsigned OpNo,
1058 unsigned Id =
MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1063 O <<
' ' << TgtName;
1067 O <<
" invalid_target_" <<
Id;
1072 bool IsPacked,
bool HasDstSel) {
1075 for (
int I = 0;
I < NumOps; ++
I) {
1076 if (!!(Ops[
I] &
Mod) != DefaultValue)
1086void AMDGPUInstPrinter::printPackedModifier(
const MCInst *
MI,
1090 unsigned Opc =
MI->getOpcode();
1094 for (
int OpName : { AMDGPU::OpName::src0_modifiers,
1095 AMDGPU::OpName::src1_modifiers,
1096 AMDGPU::OpName::src2_modifiers }) {
1101 Ops[NumOps++] =
MI->getOperand(
Idx).getImm();
1104 const bool HasDstSel =
1116 for (
int I = 0;
I < NumOps; ++
I) {
1120 O << !!(Ops[
I] &
Mod);
1130void AMDGPUInstPrinter::printOpSel(
const MCInst *
MI,
unsigned,
1133 unsigned Opc =
MI->getOpcode();
1140 O <<
" op_sel:[" << FI <<
',' << BC <<
']';
1147void AMDGPUInstPrinter::printOpSelHi(
const MCInst *
MI,
unsigned OpNo,
1153void AMDGPUInstPrinter::printNegLo(
const MCInst *
MI,
unsigned OpNo,
1159void AMDGPUInstPrinter::printNegHi(
const MCInst *
MI,
unsigned OpNo,
1165void AMDGPUInstPrinter::printInterpSlot(
const MCInst *
MI,
unsigned OpNum,
1168 unsigned Imm =
MI->getOperand(OpNum).getImm();
1180 O <<
"invalid_param_" <<
Imm;
1184void AMDGPUInstPrinter::printInterpAttr(
const MCInst *
MI,
unsigned OpNum,
1187 unsigned Attr =
MI->getOperand(OpNum).getImm();
1188 O <<
"attr" << Attr;
1191void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *
MI,
unsigned OpNum,
1194 unsigned Chan =
MI->getOperand(OpNum).getImm();
1195 O <<
'.' <<
"xyzw"[Chan & 0x3];
1198void AMDGPUInstPrinter::printGPRIdxMode(
const MCInst *
MI,
unsigned OpNo,
1202 unsigned Val =
MI->getOperand(OpNo).getImm();
1204 if ((Val & ~ENABLE_MASK) != 0) {
1205 O << formatHex(static_cast<uint64_t>(Val));
1208 bool NeedComma =
false;
1209 for (
unsigned ModeId = ID_MIN; ModeId <=
ID_MAX; ++ModeId) {
1210 if (Val & (1 << ModeId)) {
1221void AMDGPUInstPrinter::printMemOperand(
const MCInst *
MI,
unsigned OpNo,
1224 printRegularOperand(
MI, OpNo, STI, O);
1226 printRegularOperand(
MI, OpNo + 1, STI, O);
1234 if (
Op.getImm() == 1) {
1245 if (
Op.getImm() == 1)
1252 int Imm =
MI->getOperand(OpNo).getImm();
1266 const unsigned Imm16 =
MI->getOperand(OpNo).getImm();
1271 decodeMsg(Imm16, MsgId, OpId,
StreamId, STI);
1273 StringRef MsgName = getMsgName(MsgId, STI);
1275 if (!MsgName.
empty() && isValidMsgOp(MsgId, OpId, STI) &&
1276 isValidMsgStream(MsgId, OpId,
StreamId, STI)) {
1277 O <<
"sendmsg(" << MsgName;
1278 if (msgRequiresOp(MsgId, STI)) {
1279 O <<
", " << getMsgOpName(MsgId, OpId, STI);
1280 if (msgSupportsStream(MsgId, OpId, STI)) {
1285 }
else if (encodeMsg(MsgId, OpId,
StreamId) == Imm16) {
1286 O <<
"sendmsg(" << MsgId <<
", " << OpId <<
", " <<
StreamId <<
')';
1298 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1299 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1303 for (
unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1330 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1337 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1339 O <<
"swizzle(" << IdSymbolic[ID_QUAD_PERM];
1340 for (
unsigned I = 0;
I < LANE_NUM; ++
I) {
1347 }
else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1349 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1350 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1351 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1353 if (AndMask == BITMASK_MAX && OrMask == 0 &&
llvm::popcount(XorMask) == 1) {
1355 O <<
"swizzle(" << IdSymbolic[ID_SWAP];
1360 }
else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1363 O <<
"swizzle(" << IdSymbolic[ID_REVERSE];
1370 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1371 if (GroupSize > 1 &&
1373 OrMask < GroupSize &&
1376 O <<
"swizzle(" << IdSymbolic[ID_BROADCAST];
1384 O <<
"swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1391 printU16ImmDecOperand(
MI, OpNo, O);
1400 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1401 unsigned Vmcnt, Expcnt, Lgkmcnt;
1407 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1409 bool NeedSpace =
false;
1411 if (!IsDefaultVmcnt || PrintAll) {
1412 O <<
"vmcnt(" << Vmcnt <<
')';
1416 if (!IsDefaultExpcnt || PrintAll) {
1419 O <<
"expcnt(" << Expcnt <<
')';
1423 if (!IsDefaultLgkmcnt || PrintAll) {
1426 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1435 uint64_t Imm16 =
MI->getOperand(OpNo).getImm() & 0xffff;
1437 bool HasNonDefaultVal =
false;
1438 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1443 bool NeedSpace =
false;
1444 while (decodeDepCtr(Imm16,
Id,
Name, Val, IsDefault, STI)) {
1445 if (!IsDefault || !HasNonDefaultVal) {
1448 O <<
Name <<
'(' << Val <<
')';
1460 const char *BadInstId =
"/* invalid instid value */";
1461 static const std::array<const char *, 12> InstIds = {
1462 "NO_DEP",
"VALU_DEP_1",
"VALU_DEP_2",
1463 "VALU_DEP_3",
"VALU_DEP_4",
"TRANS32_DEP_1",
1464 "TRANS32_DEP_2",
"TRANS32_DEP_3",
"FMA_ACCUM_CYCLE_1",
1465 "SALU_CYCLE_1",
"SALU_CYCLE_2",
"SALU_CYCLE_3"};
1467 const char *BadInstSkip =
"/* invalid instskip value */";
1468 static const std::array<const char *, 6> InstSkips = {
1469 "SAME",
"NEXT",
"SKIP_1",
"SKIP_2",
"SKIP_3",
"SKIP_4"};
1471 unsigned SImm16 =
MI->getOperand(OpNo).getImm();
1472 const char *Prefix =
"";
1474 unsigned Value = SImm16 & 0xF;
1476 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1477 O << Prefix <<
"instid0(" <<
Name <<
')';
1481 Value = (SImm16 >> 4) & 7;
1484 Value < InstSkips.size() ? InstSkips[
Value] : BadInstSkip;
1485 O << Prefix <<
"instskip(" <<
Name <<
')';
1489 Value = (SImm16 >> 7) & 0xF;
1491 const char *
Name =
Value < InstIds.size() ? InstIds[
Value] : BadInstId;
1492 O << Prefix <<
"instid1(" <<
Name <<
')';
1507 unsigned Val =
MI->getOperand(OpNo).getImm();
1512 if (!HwRegName.
empty()) {
1517 if (
Width != WIDTH_DEFAULT_ ||
Offset != OFFSET_DEFAULT_) {
1526 uint16_t Imm =
MI->getOperand(OpNo).getImm();
1534#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
Provides AMDGPU specific target descriptions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t Opcode
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents an Operation in the Expression.
Base class for the full range of assembler expressions which are needed for parsing.
format_object< int64_t > formatHex(int64_t Value) const
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getRegClassName(const MCRegisterClass *Class) const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool isGFX940(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
bool isSI(const MCSubtargetInfo &STI)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
@ Mod
The access may modify the value stored in memory.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
@ Default
The result values are uniform if and only if all operands are uniform.
Instruction set architecture version.
Description of the encoding of one expression Op.