LLVM  15.0.0git
ARCOptAddrMode.cpp
Go to the documentation of this file.
1 //===- ARCOptAddrMode.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass folds LD/ST + ADD pairs into Pre/Post-increment form of
11 /// load/store instructions.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARC.h"
15 #define GET_INSTRMAP_INFO
16 #include "ARCInstrInfo.h"
17 #include "ARCTargetMachine.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/InitializePasses.h"
27 #include "llvm/Support/Debug.h"
29 
30 using namespace llvm;
31 
32 #define OPTADDRMODE_DESC "ARC load/store address mode"
33 #define OPTADDRMODE_NAME "arc-addr-mode"
34 #define DEBUG_TYPE "arc-addr-mode"
35 
36 namespace llvm {
37 
38 static cl::opt<unsigned> ArcKillAddrMode("arc-kill-addr-mode", cl::init(0),
40 
41 #define DUMP_BEFORE() ((ArcKillAddrMode & 0x0001) != 0)
42 #define DUMP_AFTER() ((ArcKillAddrMode & 0x0002) != 0)
43 #define VIEW_BEFORE() ((ArcKillAddrMode & 0x0004) != 0)
44 #define VIEW_AFTER() ((ArcKillAddrMode & 0x0008) != 0)
45 #define KILL_PASS() ((ArcKillAddrMode & 0x0010) != 0)
46 
49 } // end namespace llvm
50 
51 namespace {
52 class ARCOptAddrMode : public MachineFunctionPass {
53 public:
54  static char ID;
55 
56  ARCOptAddrMode() : MachineFunctionPass(ID) {}
57 
58  StringRef getPassName() const override { return OPTADDRMODE_DESC; }
59 
60  void getAnalysisUsage(AnalysisUsage &AU) const override {
61  AU.setPreservesCFG();
65  }
66 
67  bool runOnMachineFunction(MachineFunction &MF) override;
68 
69 private:
70  const ARCSubtarget *AST = nullptr;
71  const ARCInstrInfo *AII = nullptr;
72  MachineRegisterInfo *MRI = nullptr;
73  MachineDominatorTree *MDT = nullptr;
74 
75  // Tries to combine \p Ldst with increment of its base register to form
76  // single post-increment instruction.
77  MachineInstr *tryToCombine(MachineInstr &Ldst);
78 
79  // Returns true if result of \p Add is not used before \p Ldst
80  bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
81  const MachineInstr *Ldst);
82 
83  // Returns true if load/store instruction \p Ldst can be hoisted up to
84  // instruction \p To
85  bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
86 
87  // // Returns true if load/store instruction \p Ldst can be sunk down
88  // // to instruction \p To
89  // bool canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
90 
91  // Check if instructions \p Ldst and \p Add can be moved to become adjacent
92  // If they can return instruction which need not to move.
93  // If \p Uses is not null, fill it with instructions after \p Ldst which use
94  // \p Ldst's base register
95  MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
97 
98  // Returns true if all instruction in \p Uses array can be adjusted
99  // to accomodate increment of register \p BaseReg by \p Incr
100  bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
101  MachineOperand &Incr, unsigned BaseReg);
102 
103  // Update all instructions in \p Uses to accomodate increment
104  // of \p BaseReg by \p Offset
105  void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
106  int64_t Offset);
107 
108  // Change instruction \p Ldst to postincrement form.
109  // \p NewBase is register to hold update base value
110  // \p NewOffset is instruction's new offset
111  void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
112  unsigned NewBase, MachineOperand &NewOffset);
113 
114  bool processBasicBlock(MachineBasicBlock &MBB);
115 };
116 
117 } // end anonymous namespace
118 
119 char ARCOptAddrMode::ID = 0;
121  false)
124  false)
125 
126 // Return true if \p Off can be used as immediate offset
127 // operand of load/store instruction (S9 literal)
128 static bool isValidLoadStoreOffset(int64_t Off) { return isInt<9>(Off); }
129 
130 // Return true if \p Off can be used as immediate operand of
131 // ADD/SUB instruction (U6 literal)
132 static bool isValidIncrementOffset(int64_t Off) { return isUInt<6>(Off); }
133 
134 static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount) {
135  int64_t Sign = 1;
136  switch (MI.getOpcode()) {
137  case ARC::SUB_rru6:
138  Sign = -1;
140  case ARC::ADD_rru6:
141  assert(MI.getOperand(2).isImm() && "Expected immediate operand");
142  Amount = Sign * MI.getOperand(2).getImm();
143  return true;
144  default:
145  return false;
146  }
147 }
148 
149 // Return true if \p MI dominates of uses of virtual register \p VReg
150 static bool dominatesAllUsesOf(const MachineInstr *MI, unsigned VReg,
153 
154  assert(Register::isVirtualRegister(VReg) && "Expected virtual register!");
155 
156  for (auto it = MRI->use_nodbg_begin(VReg), end = MRI->use_nodbg_end();
157  it != end; ++it) {
158  MachineInstr *User = it->getParent();
159  if (User->isPHI()) {
160  unsigned BBOperandIdx = User->getOperandNo(&*it) + 1;
161  MachineBasicBlock *MBB = User->getOperand(BBOperandIdx).getMBB();
162  if (MBB->empty()) {
163  const MachineBasicBlock *InstBB = MI->getParent();
164  assert(InstBB != MBB && "Instruction found in empty MBB");
165  if (!MDT->dominates(InstBB, MBB))
166  return false;
167  continue;
168  }
169  User = &*MBB->rbegin();
170  }
171 
172  if (!MDT->dominates(MI, User))
173  return false;
174  }
175  return true;
176 }
177 
178 // Return true if \p MI is load/store instruction with immediate offset
179 // which can be adjusted by \p Disp
181  const MachineInstr &MI,
182  int64_t Disp) {
183  unsigned BasePos, OffPos;
184  if (!TII->getBaseAndOffsetPosition(MI, BasePos, OffPos))
185  return false;
186  const MachineOperand &MO = MI.getOperand(OffPos);
187  if (!MO.isImm())
188  return false;
189  int64_t Offset = MO.getImm() + Disp;
190  return isValidLoadStoreOffset(Offset);
191 }
192 
193 bool ARCOptAddrMode::noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
194  const MachineInstr *Ldst) {
195  Register R = Add->getOperand(0).getReg();
196  return dominatesAllUsesOf(Ldst, R, MDT, MRI);
197 }
198 
199 MachineInstr *ARCOptAddrMode::tryToCombine(MachineInstr &Ldst) {
200  assert(Ldst.mayLoadOrStore() && "LD/ST instruction expected");
201 
202  unsigned BasePos, OffsetPos;
203 
204  LLVM_DEBUG(dbgs() << "[ABAW] tryToCombine " << Ldst);
205  if (!AII->getBaseAndOffsetPosition(Ldst, BasePos, OffsetPos)) {
206  LLVM_DEBUG(dbgs() << "[ABAW] Not a recognized load/store\n");
207  return nullptr;
208  }
209 
210  MachineOperand &Base = Ldst.getOperand(BasePos);
211  MachineOperand &Offset = Ldst.getOperand(OffsetPos);
212 
213  assert(Base.isReg() && "Base operand must be register");
214  if (!Offset.isImm()) {
215  LLVM_DEBUG(dbgs() << "[ABAW] Offset is not immediate\n");
216  return nullptr;
217  }
218 
219  Register B = Base.getReg();
221  LLVM_DEBUG(dbgs() << "[ABAW] Base is not VReg\n");
222  return nullptr;
223  }
224 
225  // TODO: try to generate address preincrement
226  if (Offset.getImm() != 0) {
227  LLVM_DEBUG(dbgs() << "[ABAW] Non-zero offset\n");
228  return nullptr;
229  }
230 
231  for (auto &Add : MRI->use_nodbg_instructions(B)) {
232  int64_t Incr;
233  if (!isAddConstantOp(Add, Incr))
234  continue;
235  if (!isValidLoadStoreOffset(Incr))
236  continue;
237 
239  MachineInstr *MoveTo = canJoinInstructions(&Ldst, &Add, &Uses);
240 
241  if (!MoveTo)
242  continue;
243 
244  if (!canFixPastUses(Uses, Add.getOperand(2), B))
245  continue;
246 
247  LLVM_DEBUG(MachineInstr *First = &Ldst; MachineInstr *Last = &Add;
248  if (MDT->dominates(Last, First)) std::swap(First, Last);
249  dbgs() << "[ABAW] Instructions " << *First << " and " << *Last
250  << " combined\n";
251 
252  );
253 
254  MachineInstr *Result = Ldst.getNextNode();
255  if (MoveTo == &Add) {
256  Ldst.removeFromParent();
257  Add.getParent()->insertAfter(Add.getIterator(), &Ldst);
258  }
259  if (Result == &Add)
260  Result = Result->getNextNode();
261 
262  fixPastUses(Uses, B, Incr);
263 
264  int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode());
265  assert(NewOpcode > 0 && "No postincrement form found");
266  unsigned NewBaseReg = Add.getOperand(0).getReg();
267  changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2));
268  Add.eraseFromParent();
269 
270  return Result;
271  }
272  return nullptr;
273 }
274 
275 MachineInstr *
276 ARCOptAddrMode::canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
278  assert(Ldst && Add && "NULL instruction passed");
279 
281  MachineInstr *Last = Ldst;
282  if (MDT->dominates(Ldst, Add))
283  std::swap(First, Last);
284  else if (!MDT->dominates(Add, Ldst))
285  return nullptr;
286 
287  LLVM_DEBUG(dbgs() << "canJoinInstructions: " << *First << *Last);
288 
289  unsigned BasePos, OffPos;
290 
291  if (!AII->getBaseAndOffsetPosition(*Ldst, BasePos, OffPos)) {
292  LLVM_DEBUG(
293  dbgs()
294  << "[canJoinInstructions] Cannot determine base/offset position\n");
295  return nullptr;
296  }
297 
298  Register BaseReg = Ldst->getOperand(BasePos).getReg();
299 
300  // prohibit this:
301  // v1 = add v0, c
302  // st v1, [v0, 0]
303  // and this
304  // st v0, [v0, 0]
305  // v1 = add v0, c
306  if (Ldst->mayStore() && Ldst->getOperand(0).isReg()) {
307  Register StReg = Ldst->getOperand(0).getReg();
308  if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
309  LLVM_DEBUG(dbgs() << "[canJoinInstructions] Store uses result of Add\n");
310  return nullptr;
311  }
312  }
313 
314  SmallVector<MachineInstr *, 4> UsesAfterLdst;
315  SmallVector<MachineInstr *, 4> UsesAfterAdd;
316  for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) {
317  if (&MI == Ldst || &MI == Add)
318  continue;
319  if (&MI != Add && MDT->dominates(Ldst, &MI))
320  UsesAfterLdst.push_back(&MI);
321  else if (!MDT->dominates(&MI, Ldst))
322  return nullptr;
323  if (MDT->dominates(Add, &MI))
324  UsesAfterAdd.push_back(&MI);
325  }
326 
327  MachineInstr *Result = nullptr;
328 
329  if (First == Add) {
330  // n = add b, i
331  // ...
332  // x = ld [b, o] or x = ld [n, o]
333 
334  if (noUseOfAddBeforeLoadOrStore(First, Last)) {
335  Result = Last;
336  LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can sink Add down to Ldst\n");
337  } else if (canHoistLoadStoreTo(Ldst, Add)) {
338  Result = First;
339  LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Ldst to Add\n");
340  }
341  } else {
342  // x = ld [b, o]
343  // ...
344  // n = add b, i
345  Result = First;
346  LLVM_DEBUG(dbgs() << "[canJoinInstructions] Can hoist Add to Ldst\n");
347  }
348  if (Result && Uses)
349  *Uses = (Result == Ldst) ? UsesAfterLdst : UsesAfterAdd;
350  return Result;
351 }
352 
353 bool ARCOptAddrMode::canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
354  MachineOperand &Incr, unsigned BaseReg) {
355 
356  assert(Incr.isImm() && "Expected immediate increment");
357  int64_t NewOffset = Incr.getImm();
358  for (MachineInstr *MI : Uses) {
359  int64_t Dummy;
360  if (isAddConstantOp(*MI, Dummy)) {
361  if (isValidIncrementOffset(Dummy + NewOffset))
362  continue;
363  return false;
364  }
365  if (isLoadStoreThatCanHandleDisplacement(AII, *MI, -NewOffset))
366  continue;
367  LLVM_DEBUG(dbgs() << "Instruction cannot handle displacement " << -NewOffset
368  << ": " << *MI);
369  return false;
370  }
371  return true;
372 }
373 
374 void ARCOptAddrMode::fixPastUses(ArrayRef<MachineInstr *> Uses,
375  unsigned NewBase, int64_t NewOffset) {
376 
377  for (MachineInstr *MI : Uses) {
378  int64_t Amount;
379  unsigned BasePos, OffPos;
380  if (isAddConstantOp(*MI, Amount)) {
381  NewOffset += Amount;
382  assert(isValidIncrementOffset(NewOffset) &&
383  "New offset won't fit into ADD instr");
384  BasePos = 1;
385  OffPos = 2;
386  } else if (AII->getBaseAndOffsetPosition(*MI, BasePos, OffPos)) {
387  MachineOperand &MO = MI->getOperand(OffPos);
388  assert(MO.isImm() && "expected immediate operand");
389  NewOffset += MO.getImm();
390  assert(isValidLoadStoreOffset(NewOffset) &&
391  "New offset won't fit into LD/ST");
392  } else
393  llvm_unreachable("unexpected instruction");
394 
395  MI->getOperand(BasePos).setReg(NewBase);
396  MI->getOperand(OffPos).setImm(NewOffset);
397  }
398 }
399 
400 bool ARCOptAddrMode::canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To) {
401  if (Ldst->getParent() != To->getParent())
402  return false;
404  End(Ldst->getParent()->end());
405 
406  bool IsStore = Ldst->mayStore();
407  for (; MI != ME && MI != End; ++MI) {
408  if (MI->isDebugValue())
409  continue;
410  if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
411  MI->hasUnmodeledSideEffects())
412  return false;
413  if (IsStore && MI->mayLoad())
414  return false;
415  }
416 
417  for (auto &O : Ldst->explicit_operands()) {
418  if (!O.isReg() || !O.isUse())
419  continue;
420  MachineInstr *OpDef = MRI->getVRegDef(O.getReg());
421  if (!OpDef || !MDT->dominates(OpDef, To))
422  return false;
423  }
424  return true;
425 }
426 
427 // bool ARCOptAddrMode::canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To) {
428 // // Can only sink load/store within same BB
429 // if (Ldst->getParent() != To->getParent())
430 // return false;
431 // MachineBasicBlock::const_iterator MI(Ldst), ME(To),
432 // End(Ldst->getParent()->end());
433 
434 // bool IsStore = Ldst->mayStore();
435 // bool IsLoad = Ldst->mayLoad();
436 
437 // Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
438 // for (; MI != ME && MI != End; ++MI) {
439 // if (MI->isDebugValue())
440 // continue;
441 // if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
442 // MI->hasUnmodeledSideEffects())
443 // return false;
444 // if (IsStore && MI->mayLoad())
445 // return false;
446 // if (ValReg && MI->readsVirtualRegister(ValReg))
447 // return false;
448 // }
449 // return true;
450 // }
451 
452 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
453  unsigned NewBase,
454  MachineOperand &NewOffset) {
455  bool IsStore = Ldst.mayStore();
456  unsigned BasePos, OffPos;
457  MachineOperand Src = MachineOperand::CreateImm(0xDEADBEEF);
458  AII->getBaseAndOffsetPosition(Ldst, BasePos, OffPos);
459 
460  Register BaseReg = Ldst.getOperand(BasePos).getReg();
461 
462  Ldst.removeOperand(OffPos);
463  Ldst.removeOperand(BasePos);
464 
465  if (IsStore) {
466  Src = Ldst.getOperand(BasePos - 1);
467  Ldst.removeOperand(BasePos - 1);
468  }
469 
470  Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
471  Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));
472  if (IsStore)
473  Ldst.addOperand(Src);
474  Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
475  Ldst.addOperand(NewOffset);
476  LLVM_DEBUG(dbgs() << "[ABAW] New Ldst: " << Ldst);
477 }
478 
479 bool ARCOptAddrMode::processBasicBlock(MachineBasicBlock &MBB) {
480  bool Changed = false;
481  for (auto MI = MBB.begin(), ME = MBB.end(); MI != ME; ++MI) {
482  if (MI->isDebugValue())
483  continue;
484  if (!MI->mayLoad() && !MI->mayStore())
485  continue;
486  if (ARC::getPostIncOpcode(MI->getOpcode()) < 0)
487  continue;
488  MachineInstr *Res = tryToCombine(*MI);
489  if (Res) {
490  Changed = true;
491  // Res points to the next instruction. Rewind to process it
492  MI = std::prev(Res->getIterator());
493  }
494  }
495  return Changed;
496 }
497 
498 bool ARCOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
499  if (skipFunction(MF.getFunction()) || KILL_PASS())
500  return false;
501 
502 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
503  if (DUMP_BEFORE())
504  MF.dump();
505 #endif
506  if (VIEW_BEFORE())
507  MF.viewCFG();
508 
509  AST = &MF.getSubtarget<ARCSubtarget>();
510  AII = AST->getInstrInfo();
511  MRI = &MF.getRegInfo();
512  MDT = &getAnalysis<MachineDominatorTree>();
513 
514  bool Changed = false;
515  for (auto &MBB : MF)
516  Changed |= processBasicBlock(MBB);
517 
518 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
519  if (DUMP_AFTER())
520  MF.dump();
521 #endif
522  if (VIEW_AFTER())
523  MF.viewCFG();
524  return Changed;
525 }
526 
527 //===----------------------------------------------------------------------===//
528 // Public Constructor Functions
529 //===----------------------------------------------------------------------===//
530 
531 FunctionPass *llvm::createARCOptAddrMode() { return new ARCOptAddrMode(); }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
it
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Definition: README-SSE.txt:81
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::MachineInstr::explicit_operands
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:626
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1036
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::ArcKillAddrMode
static cl::opt< unsigned > ArcKillAddrMode("arc-kill-addr-mode", cl::init(0), cl::ReallyHidden, cl::ZeroOrMore)
llvm::HexagonInstrInfo::getBaseAndOffsetPosition
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
Definition: HexagonInstrInfo.cpp:3329
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:551
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
isValidIncrementOffset
static bool isValidIncrementOffset(int64_t Off)
Definition: ARCOptAddrMode.cpp:132
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:114
dominatesAllUsesOf
static bool dominatesAllUsesOf(const MachineInstr *MI, unsigned VReg, MachineDominatorTree *MDT, MachineRegisterInfo *MRI)
Definition: ARCOptAddrMode.cpp:150
llvm::createARCOptAddrMode
FunctionPass * createARCOptAddrMode()
Definition: ARCOptAddrMode.cpp:531
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:140
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:240
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:526
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:585
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
DUMP_BEFORE
#define DUMP_BEFORE()
Definition: ARCOptAddrMode.cpp:41
CommandLine.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
DUMP_AFTER
#define DUMP_AFTER()
Definition: ARCOptAddrMode.cpp:42
isValidLoadStoreOffset
static false bool isValidLoadStoreOffset(int64_t Off)
Definition: ARCOptAddrMode.cpp:128
llvm::User
Definition: User.h:44
llvm::ARCSubtarget
Definition: ARCSubtarget.h:31
llvm::Register::isStackSlot
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
Definition: Register.h:44
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:640
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ARCSubtarget::getInstrInfo
const ARCInstrInfo * getInstrInfo() const override
Definition: ARCSubtarget.h:51
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::MachineFunction::viewCFG
void viewCFG() const
viewCFG - This function is meant for use from the debugger.
Definition: MachineFunction.cpp:657
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:529
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:116
llvm::initializeARCOptAddrModePass
void initializeARCOptAddrModePass(PassRegistry &)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:394
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
VIEW_BEFORE
#define VIEW_BEFORE()
Definition: ARCOptAddrMode.cpp:43
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::MachineFunction::dump
void dump() const
dump - Print the current MachineFunction to cerr, useful for debugger use.
Definition: MachineFunction.cpp:562
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
isLoadStoreThatCanHandleDisplacement
static bool isLoadStoreThatCanHandleDisplacement(const TargetInstrInfo *TII, const MachineInstr &MI, int64_t Disp)
Definition: ARCOptAddrMode.cpp:180
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::IndexedInstrProf::HashT::Last
@ Last
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::NVPTXISD::Dummy
@ Dummy
Definition: NVPTXISelLowering.h:60
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:281
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(ARCOptAddrMode, OPTADDRMODE_NAME, OPTADDRMODE_DESC, false, false) INITIALIZE_PASS_END(ARCOptAddrMode
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
ARCTargetMachine.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
ARCInstrInfo.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::ARCInstrInfo
Definition: ARCInstrInfo.h:26
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1026
OPTADDRMODE_DESC
#define OPTADDRMODE_DESC
Definition: ARCOptAddrMode.cpp:32
Function.h
OPTADDRMODE_NAME
#define OPTADDRMODE_NAME
Definition: ARCOptAddrMode.cpp:33
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1720
isAddConstantOp
static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount)
Definition: ARCOptAddrMode.cpp:134
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:276
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
VIEW_AFTER
#define VIEW_AFTER()
Definition: ARCOptAddrMode.cpp:44
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:184
ARC.h
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:249
llvm::SmallVectorImpl< MachineInstr * >
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::MachineInstrBundleIterator< const MachineInstr >
KILL_PASS
#define KILL_PASS()
Definition: ARCOptAddrMode.cpp:45
InitializePasses.h
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37