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33 #define DEBUG_TYPE "arc-reg-info"
35 #define GET_REGINFO_TARGET_DESC
36 #include "ARCGenRegisterInfo.inc"
40 unsigned FrameReg,
int Offset,
int StackSize,
42 assert(RS &&
"Need register scavenger.");
46 unsigned BaseReg = FrameReg;
47 unsigned KillState = 0;
48 if (
MI.getOpcode() == ARC::LD_rs9 && (Offset >= 256 || Offset < -256)) {
58 if (
MI.getOpcode() != ARC::GETFI && (Offset >= 256 || Offset < -256)) {
67 assert(BaseReg &&
"Register scavenging failed.");
70 <<
"+Offset=" << Offset <<
"\n");
74 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
82 switch (
MI.getOpcode()) {
84 assert((Offset % 4 == 0) &&
"LD needs 4 byte alignment.");
88 assert((Offset % 2 == 0) &&
"LDH needs 2 byte alignment.");
94 .
addReg(BaseReg, KillState)
99 assert((Offset % 4 == 0) &&
"ST needs 4 byte alignment.");
102 assert((Offset % 2 == 0) &&
"STH needs 2 byte alignment.");
108 .
addReg(BaseReg, KillState)
115 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
137 return CSR_ARC_SaveList;
143 Reserved.
set(ARC::ILINK);
144 Reserved.
set(ARC::SP);
145 Reserved.
set(ARC::GP);
146 Reserved.
set(ARC::R25);
147 Reserved.
set(ARC::BLINK);
148 Reserved.
set(ARC::FP);
163 int SPAdj,
unsigned FIOperandNum,
165 assert(SPAdj == 0 &&
"Unexpected");
185 LLVM_DEBUG(
dbgs() <<
"LocalFrameSize : " << LocalFrameSize <<
"\n");
186 (void)LocalFrameSize;
189 if (
MI.isDebugValue()) {
191 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false );
192 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
197 Offset +=
MI.getOperand(FIOperandNum + 1).getImm();
209 if (!TFI->
hasFP(MF)) {
210 Offset = StackSize + Offset;
212 assert((Offset >= 0 && Offset < StackSize) &&
"SP Offset not in bounds.");
215 assert((Offset < 0 && -Offset <= StackSize) &&
216 "FP Offset not in bounds.");
225 return TFI->
hasFP(MF) ? ARC::FP : ARC::SP;
231 return CSR_ARC_RegMask;
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
@ Define
Register definition.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
Reg
All possible values of the reg field in the ModR/M byte.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Register getFrameRegister(const MachineFunction &MF) const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
unsigned const TargetRegisterInfo * TRI
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
ARCRegisterInfo(const ARCSubtarget &)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
BitVector getReservedRegs(const MachineFunction &MF) const override
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Wrapper class representing virtual and physical registers.
static void replaceFrameIndex(MachineBasicBlock::iterator II, const ARCInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, int StackSize, int ObjSize, RegScavenger *RS, int SPAdj)
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
unsigned getKillRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
@ Kill
The last use of a register.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.