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34 #define DEBUG_TYPE "arm-mve-vpt"
53 return "MVE VPT block insertion pass";
68 unsigned &NewOpcode) {
73 while (CmpMI !=
MI->getParent()->begin()) {
75 if (CmpMI->modifiesRegister(ARM::VPR,
TRI))
77 if (CmpMI->readsRegister(ARM::VPR,
TRI))
104 unsigned &NumInstrsSteppedOver) {
107 NumInstrsSteppedOver = 0;
109 while (Iter != EndIter) {
110 if (Iter->isDebugInstr()) {
118 "VPT block pass does not expect Else preds");
123 ++NumInstrsSteppedOver;
126 return NumInstrsSteppedOver != 0 &&
134 for (; Iter != End; ++Iter)
135 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR))
169 "Expected a Predicated Instruction");
178 AddedInstIter != Iter; ++AddedInstIter) {
179 if (AddedInstIter->isDebugInstr())
181 dbgs() <<
" adding: ";
182 AddedInstIter->dump();
191 while (
BlockSize < 4 && Iter != EndIter &&
192 Iter->getOpcode() == ARM::MVE_VPNOT) {
196 unsigned ElseInstCnt = 0;
215 DeadInstructions.push_back(&*Iter);
221 for (; Iter != VPNOTBlockEndIter; ++Iter) {
222 if (Iter->isDebugInstr())
230 Iter->getOperand(OpIdx).setImm(CurrentPredicate);
249 while (MBIter != EndIter) {
276 LLVM_DEBUG(
dbgs() <<
" final block mask: " << (
unsigned)BlockMask <<
"\n");
281 MIBuilder.
add(
VCMP->getOperand(1));
282 MIBuilder.
add(
VCMP->getOperand(2));
283 MIBuilder.
add(
VCMP->getOperand(3));
289 MII.clearRegisterKills(
VCMP->getOperand(1).getReg(),
TRI);
290 MII.clearRegisterKills(
VCMP->getOperand(2).getReg(),
TRI);
293 VCMP->eraseFromParent();
303 DeadInstructions.clear();
317 if (!STI.
isThumb2() || !STI.hasMVEIntegerOps())
324 <<
"********** Function: " << Fn.
getName() <<
'\n');
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
static const int BlockSize
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const ARMBaseInstrInfo * getInstrInfo() const override
static MachineInstr * findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI, const TargetRegisterInfo *TRI, unsigned &NewOpcode)
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
Properties which a MachineFunction may have at a given point in time.
static bool IsVPRDefinedOrKilledByBlock(MachineBasicBlock::iterator Iter, MachineBasicBlock::iterator End)
static ARM::PredBlockMask CreateVPTBlock(MachineBasicBlock::instr_iterator &Iter, MachineBasicBlock::instr_iterator EndIter, SmallVectorImpl< MachineInstr * > &DeadInstructions)
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static ARM::PredBlockMask GetInitialBlockMask(unsigned BlockSize)
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
const HexagonInstrInfo * TII
MachineFunctionProperties & set(Property P)
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
static bool StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator &Iter, MachineBasicBlock::instr_iterator EndIter, unsigned MaxSteps, unsigned &NumInstrsSteppedOver)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const ARMBaseRegisterInfo * getRegisterInfo() const override
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Wrapper class representing virtual and physical registers.
Iterator for intrusive lists based on ilist_node.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)
FunctionPass class - This class is used to implement most global optimizations.
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.