Go to the documentation of this file.
40 return MIRBuilder.
buildInstr(SPIRV::OpReturnValue)
51 if (
F.hasFnAttribute(Attribute::AttrKind::AlwaysInline)) {
54 if (
F.hasFnAttribute(Attribute::AttrKind::ReadNone)) {
57 if (
F.hasFnAttribute(Attribute::AttrKind::ReadOnly)) {
60 if (
F.hasFnAttribute(Attribute::AttrKind::NoInline)) {
70 assert(GR &&
"Must initialize the SPIRV type registry before lowering args.");
74 if (VRegs.size() > 0) {
76 for (
const auto &
Arg :
F.args()) {
79 if (VRegs[
i].
size() > 1)
87 if (
Arg.getType()->isPointerTy()) {
88 auto DerefBytes =
static_cast<unsigned>(
Arg.getDereferenceableBytes());
93 if (
Arg.hasAttribute(Attribute::Alignment)) {
95 {
static_cast<unsigned>(
Arg.getParamAlignment())});
97 if (
Arg.hasAttribute(Attribute::ReadOnly)) {
103 if (
Arg.hasAttribute(Attribute::ZExt)) {
118 auto *FTy =
F.getFunctionType();
122 Register ReturnTypeID = FuncTy->getOperand(1).getReg();
132 const unsigned NumArgs = ArgTypeVRegs.size();
133 for (
unsigned i = 0;
i < NumArgs; ++
i) {
134 assert(VRegs[
i].
size() == 1 &&
"Formal arg has multiple vregs");
136 MIRBuilder.
buildInstr(SPIRV::OpFunctionParameter)
146 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpEntryPoint)
150 }
else if (
F.getLinkage() == GlobalValue::LinkageTypes::ExternalLinkage ||
155 {
static_cast<uint32_t>(LnkTy)},
F.getGlobalIdentifier());
165 if (
Info.OrigRet.Regs.size() > 1)
173 if (
Info.Callee.isGlobal()) {
174 auto *CF = dyn_cast_or_null<const Function>(
Info.Callee.getGlobal());
178 if (CF->isDeclaration()) {
191 ToInsert.push_back({MIRBuilder.
getMRI()->createGenericVirtualRegister(
193 VRegArgs.push_back(ToInsert.back());
210 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpFunctionCall)
215 for (
const auto &
Arg :
Info.OrigArgs) {
217 if (
Arg.Regs.size() > 1)
This class represents an incoming formal argument to a Function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MachineInstrBuilder & add(const MachineOperand &MO) const
static uint32_t getFunctionControl(const Function &F)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const DataLayout & getDataLayout() const
MachineFunction & getMF()
Getter for the function we currently build.
Analysis containing CSE Info
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB)
const RegisterBankInfo * getRegBankInfo() const override
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Helper class to build MachineInstr.
Representation of each machine instruction.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, llvm::SPIRV::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
instr_iterator instr_end()
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
const TargetInstrInfo & getTII()
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
size_t size() const
size - Get the array size.
SPIRVCallLowering(const SPIRVTargetLowering &TLI, const SPIRVSubtarget &ST, SPIRVGlobalRegistry *GR)
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
@ LinkOnceODRLinkage
Same, but only replaced by something equivalent.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
LLVM Value Representation.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const SPIRVRegisterInfo * getRegisterInfo() const override