LLVM  16.0.0git
TargetTransformInfo.cpp
Go to the documentation of this file.
1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/Dominators.h"
15 #include "llvm/IR/Instruction.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/Module.h"
19 #include "llvm/IR/Operator.h"
20 #include "llvm/IR/PatternMatch.h"
21 #include "llvm/InitializePasses.h"
23 #include <optional>
24 #include <utility>
25 
26 using namespace llvm;
27 using namespace PatternMatch;
28 
29 #define DEBUG_TYPE "tti"
30 
31 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
32  cl::Hidden,
33  cl::desc("Recognize reduction patterns."));
34 
36  "cache-line-size", cl::init(0), cl::Hidden,
37  cl::desc("Use this to override the target cache line size when "
38  "specified by the user."));
39 
40 namespace {
41 /// No-op implementation of the TTI interface using the utility base
42 /// classes.
43 ///
44 /// This is used when no target specific information is available.
45 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
46  explicit NoTTIImpl(const DataLayout &DL)
47  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
48 };
49 } // namespace
50 
52  // If the loop has irreducible control flow, it can not be converted to
53  // Hardware loop.
54  LoopBlocksRPO RPOT(L);
55  RPOT.perform(&LI);
56  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
57  return false;
58  return true;
59 }
60 
62  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
63  bool TypeBasedOnly)
64  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
65  ScalarizationCost(ScalarizationCost) {
66 
67  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
68  FMF = FPMO->getFastMathFlags();
69 
70  if (!TypeBasedOnly)
71  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
73  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
74 }
75 
77  ArrayRef<Type *> Tys,
78  FastMathFlags Flags,
79  const IntrinsicInst *I,
80  InstructionCost ScalarCost)
81  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
82  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
83 }
84 
87  : RetTy(Ty), IID(Id) {
88 
89  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
90  ParamTys.reserve(Arguments.size());
91  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
92  ParamTys.push_back(Arguments[Idx]->getType());
93 }
94 
97  ArrayRef<Type *> Tys,
98  FastMathFlags Flags,
99  const IntrinsicInst *I,
100  InstructionCost ScalarCost)
101  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
102  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
103  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 }
105 
107  LoopInfo &LI, DominatorTree &DT,
108  bool ForceNestedLoop,
109  bool ForceHardwareLoopPHI) {
110  SmallVector<BasicBlock *, 4> ExitingBlocks;
111  L->getExitingBlocks(ExitingBlocks);
112 
113  for (BasicBlock *BB : ExitingBlocks) {
114  // If we pass the updated counter back through a phi, we need to know
115  // which latch the updated value will be coming from.
116  if (!L->isLoopLatch(BB)) {
118  continue;
119  }
120 
121  const SCEV *EC = SE.getExitCount(L, BB);
122  if (isa<SCEVCouldNotCompute>(EC))
123  continue;
124  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
125  if (ConstEC->getValue()->isZero())
126  continue;
127  } else if (!SE.isLoopInvariant(EC, L))
128  continue;
129 
130  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
131  continue;
132 
133  // If this exiting block is contained in a nested loop, it is not eligible
134  // for insertion of the branch-and-decrement since the inner loop would
135  // end up messing up the value in the CTR.
136  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
137  continue;
138 
139  // We now have a loop-invariant count of loop iterations (which is not the
140  // constant zero) for which we know that this loop will not exit via this
141  // existing block.
142 
143  // We need to make sure that this block will run on every loop iteration.
144  // For this to be true, we must dominate all blocks with backedges. Such
145  // blocks are in-loop predecessors to the header block.
146  bool NotAlways = false;
147  for (BasicBlock *Pred : predecessors(L->getHeader())) {
148  if (!L->contains(Pred))
149  continue;
150 
151  if (!DT.dominates(BB, Pred)) {
152  NotAlways = true;
153  break;
154  }
155  }
156 
157  if (NotAlways)
158  continue;
159 
160  // Make sure this blocks ends with a conditional branch.
161  Instruction *TI = BB->getTerminator();
162  if (!TI)
163  continue;
164 
165  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
166  if (!BI->isConditional())
167  continue;
168 
169  ExitBranch = BI;
170  } else
171  continue;
172 
173  // Note that this block may not be the loop latch block, even if the loop
174  // has a latch block.
175  ExitBlock = BB;
176  ExitCount = EC;
177  break;
178  }
179 
180  if (!ExitBlock)
181  return false;
182  return true;
183 }
184 
186  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
187 
189 
191  : TTIImpl(std::move(Arg.TTIImpl)) {}
192 
194  TTIImpl = std::move(RHS.TTIImpl);
195  return *this;
196 }
197 
199  return TTIImpl->getInliningThresholdMultiplier();
200 }
201 
202 unsigned
204  return TTIImpl->adjustInliningThreshold(CB);
205 }
206 
208  return TTIImpl->getInlinerVectorBonusPercent();
209 }
210 
215  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
216 }
217 
219  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
220  BlockFrequencyInfo *BFI) const {
221  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
222 }
223 
227  enum TargetCostKind CostKind) const {
228  InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
230  "TTI should not produce negative costs!");
231  return Cost;
232 }
233 
235  return TTIImpl->getPredictableBranchThreshold();
236 }
237 
239  return TTIImpl->hasBranchDivergence();
240 }
241 
243  return TTIImpl->useGPUDivergenceAnalysis();
244 }
245 
247  return TTIImpl->isSourceOfDivergence(V);
248 }
249 
251  return TTIImpl->isAlwaysUniform(V);
252 }
253 
255  return TTIImpl->getFlatAddressSpace();
256 }
257 
259  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
260  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
261 }
262 
264  unsigned ToAS) const {
265  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
266 }
267 
269  unsigned AS) const {
270  return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
271 }
272 
274  return TTIImpl->getAssumedAddrSpace(V);
275 }
276 
278  return TTIImpl->isSingleThreaded();
279 }
280 
281 std::pair<const Value *, unsigned>
283  return TTIImpl->getPredicatedAddrSpace(V);
284 }
285 
287  IntrinsicInst *II, Value *OldV, Value *NewV) const {
288  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
289 }
290 
292  return TTIImpl->isLoweredToCall(F);
293 }
294 
296  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
297  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
298  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
299 }
300 
302  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
304  InterleavedAccessInfo *IAI) const {
305  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
306 }
307 
309  return TTIImpl->emitGetActiveLaneMask();
310 }
311 
312 std::optional<Instruction *>
314  IntrinsicInst &II) const {
315  return TTIImpl->instCombineIntrinsic(IC, II);
316 }
317 
319  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
320  bool &KnownBitsComputed) const {
321  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
322  KnownBitsComputed);
323 }
324 
326  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
327  APInt &UndefElts2, APInt &UndefElts3,
328  std::function<void(Instruction *, unsigned, APInt, APInt &)>
329  SimplifyAndSetOp) const {
330  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
331  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
332  SimplifyAndSetOp);
333 }
334 
337  OptimizationRemarkEmitter *ORE) const {
338  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
339 }
340 
342  PeelingPreferences &PP) const {
343  return TTIImpl->getPeelingPreferences(L, SE, PP);
344 }
345 
347  return TTIImpl->isLegalAddImmediate(Imm);
348 }
349 
351  return TTIImpl->isLegalICmpImmediate(Imm);
352 }
353 
355  int64_t BaseOffset,
356  bool HasBaseReg, int64_t Scale,
357  unsigned AddrSpace,
358  Instruction *I) const {
359  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
360  Scale, AddrSpace, I);
361 }
362 
364  const LSRCost &C2) const {
365  return TTIImpl->isLSRCostLess(C1, C2);
366 }
367 
369  return TTIImpl->isNumRegsMajorCostOfLSR();
370 }
371 
373  return TTIImpl->isProfitableLSRChainElement(I);
374 }
375 
377  return TTIImpl->canMacroFuseCmp();
378 }
379 
381  ScalarEvolution *SE, LoopInfo *LI,
383  TargetLibraryInfo *LibInfo) const {
384  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
385 }
386 
389  ScalarEvolution *SE) const {
390  return TTIImpl->getPreferredAddressingMode(L, SE);
391 }
392 
394  Align Alignment) const {
395  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
396 }
397 
399  Align Alignment) const {
400  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
401 }
402 
404  Align Alignment) const {
405  return TTIImpl->isLegalNTStore(DataType, Alignment);
406 }
407 
409  return TTIImpl->isLegalNTLoad(DataType, Alignment);
410 }
411 
413  ElementCount NumElements) const {
414  return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
415 }
416 
418  Align Alignment) const {
419  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
420 }
421 
423  VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
424  const SmallBitVector &OpcodeMask) const {
425  return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
426 }
427 
429  Align Alignment) const {
430  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
431 }
432 
434  Align Alignment) const {
435  return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
436 }
437 
439  Align Alignment) const {
440  return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
441 }
442 
444  return TTIImpl->isLegalMaskedCompressStore(DataType);
445 }
446 
448  return TTIImpl->isLegalMaskedExpandLoad(DataType);
449 }
450 
452  return TTIImpl->enableOrderedReductions();
453 }
454 
455 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
456  return TTIImpl->hasDivRemOp(DataType, IsSigned);
457 }
458 
460  unsigned AddrSpace) const {
461  return TTIImpl->hasVolatileVariant(I, AddrSpace);
462 }
463 
465  return TTIImpl->prefersVectorizedAddressing();
466 }
467 
469  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
470  int64_t Scale, unsigned AddrSpace) const {
471  InstructionCost Cost = TTIImpl->getScalingFactorCost(
472  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
473  assert(Cost >= 0 && "TTI should not produce negative costs!");
474  return Cost;
475 }
476 
478  return TTIImpl->LSRWithInstrQueries();
479 }
480 
482  return TTIImpl->isTruncateFree(Ty1, Ty2);
483 }
484 
486  return TTIImpl->isProfitableToHoist(I);
487 }
488 
489 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
490 
492  return TTIImpl->isTypeLegal(Ty);
493 }
494 
496  return TTIImpl->getRegUsageForType(Ty);
497 }
498 
500  return TTIImpl->shouldBuildLookupTables();
501 }
502 
504  Constant *C) const {
505  return TTIImpl->shouldBuildLookupTablesForConstant(C);
506 }
507 
509  return TTIImpl->shouldBuildRelLookupTables();
510 }
511 
513  return TTIImpl->useColdCCForColdCall(F);
514 }
515 
518  const APInt &DemandedElts,
519  bool Insert, bool Extract) const {
520  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
521 }
522 
525  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
526 }
527 
529  return TTIImpl->supportsEfficientVectorElementLoadStore();
530 }
531 
533  return TTIImpl->supportsTailCalls();
534 }
535 
537  return TTIImpl->supportsTailCallFor(CB);
538 }
539 
541  bool LoopHasReductions) const {
542  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
543 }
544 
546 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
547  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
548 }
549 
551  return TTIImpl->enableSelectOptimize();
552 }
553 
555  return TTIImpl->enableInterleavedAccessVectorization();
556 }
557 
559  return TTIImpl->enableMaskedInterleavedAccessVectorization();
560 }
561 
563  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
564 }
565 
566 bool
568  unsigned BitWidth,
569  unsigned AddressSpace,
570  Align Alignment,
571  unsigned *Fast) const {
572  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
573  AddressSpace, Alignment, Fast);
574 }
575 
577 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
578  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
579 }
580 
582  return TTIImpl->haveFastSqrt(Ty);
583 }
584 
586  const Instruction *I) const {
587  return TTIImpl->isExpensiveToSpeculativelyExecute(I);
588 }
589 
591  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
592 }
593 
595  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
596  assert(Cost >= 0 && "TTI should not produce negative costs!");
597  return Cost;
598 }
599 
601  unsigned Idx,
602  const APInt &Imm,
603  Type *Ty) const {
604  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
605  assert(Cost >= 0 && "TTI should not produce negative costs!");
606  return Cost;
607 }
608 
612  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
613  assert(Cost >= 0 && "TTI should not produce negative costs!");
614  return Cost;
615 }
616 
618  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
621  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
622  assert(Cost >= 0 && "TTI should not produce negative costs!");
623  return Cost;
624 }
625 
628  const APInt &Imm, Type *Ty,
631  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
632  assert(Cost >= 0 && "TTI should not produce negative costs!");
633  return Cost;
634 }
635 
636 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
637  return TTIImpl->getNumberOfRegisters(ClassID);
638 }
639 
641  Type *Ty) const {
642  return TTIImpl->getRegisterClassForType(Vector, Ty);
643 }
644 
645 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
646  return TTIImpl->getRegisterClassName(ClassID);
647 }
648 
651  return TTIImpl->getRegisterBitWidth(K);
652 }
653 
655  return TTIImpl->getMinVectorRegisterBitWidth();
656 }
657 
658 std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
659  return TTIImpl->getMaxVScale();
660 }
661 
662 std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
663  return TTIImpl->getVScaleForTuning();
664 }
665 
668  return TTIImpl->shouldMaximizeVectorBandwidth(K);
669 }
670 
672  bool IsScalable) const {
673  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
674 }
675 
676 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
677  unsigned Opcode) const {
678  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
679 }
680 
681 unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
682  Type *ScalarValTy) const {
683  return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
684 }
685 
687  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
688  return TTIImpl->shouldConsiderAddressTypePromotion(
689  I, AllowPromotionWithoutCommonHeader);
690 }
691 
693  return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
694  : TTIImpl->getCacheLineSize();
695 }
696 
697 std::optional<unsigned>
699  return TTIImpl->getCacheSize(Level);
700 }
701 
702 std::optional<unsigned>
704  return TTIImpl->getCacheAssociativity(Level);
705 }
706 
708  return TTIImpl->getPrefetchDistance();
709 }
710 
712  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
713  unsigned NumPrefetches, bool HasCall) const {
714  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
715  NumPrefetches, HasCall);
716 }
717 
719  return TTIImpl->getMaxPrefetchIterationsAhead();
720 }
721 
723  return TTIImpl->enableWritePrefetching();
724 }
725 
727  return TTIImpl->shouldPrefetchAddressSpace(AS);
728 }
729 
730 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
731  return TTIImpl->getMaxInterleaveFactor(VF);
732 }
733 
736  OperandValueKind OpInfo = OK_AnyValue;
738 
739  if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
740  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
741  if (CI->getValue().isPowerOf2())
742  OpProps = OP_PowerOf2;
743  else if (CI->getValue().isNegatedPowerOf2())
744  OpProps = OP_NegatedPowerOf2;
745  }
746  return {OK_UniformConstantValue, OpProps};
747  }
748 
749  // A broadcast shuffle creates a uniform value.
750  // TODO: Add support for non-zero index broadcasts.
751  // TODO: Add support for different source vector width.
752  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
753  if (ShuffleInst->isZeroEltSplat())
754  OpInfo = OK_UniformValue;
755 
756  const Value *Splat = getSplatValue(V);
757 
758  // Check for a splat of a constant or for a non uniform vector of constants
759  // and check if the constant(s) are all powers of two.
760  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
762  if (Splat) {
763  OpInfo = OK_UniformConstantValue;
764  if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
765  if (CI->getValue().isPowerOf2())
766  OpProps = OP_PowerOf2;
767  else if (CI->getValue().isNegatedPowerOf2())
768  OpProps = OP_NegatedPowerOf2;
769  }
770  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
771  bool AllPow2 = true, AllNegPow2 = true;
772  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
773  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
774  AllPow2 &= CI->getValue().isPowerOf2();
775  AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
776  if (AllPow2 || AllNegPow2)
777  continue;
778  }
779  AllPow2 = AllNegPow2 = false;
780  break;
781  }
782  OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
783  OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
784  }
785  }
786 
787  // Check for a splat of a uniform value. This is not loop aware, so return
788  // true only for the obviously uniform cases (argument, globalvalue)
789  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
790  OpInfo = OK_UniformValue;
791 
792  return {OpInfo, OpProps};
793 }
794 
796  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
797  OperandValueInfo Op1Info, OperandValueInfo Op2Info,
798  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
800  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
801  Op1Info, Op2Info,
802  Args, CxtI);
803  assert(Cost >= 0 && "TTI should not produce negative costs!");
804  return Cost;
805 }
806 
812  TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind, Index, SubTp, Args);
813  assert(Cost >= 0 && "TTI should not produce negative costs!");
814  return Cost;
815 }
816 
819  if (!I)
820  return CastContextHint::None;
821 
822  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
823  unsigned GatScatOp) {
824  const Instruction *I = dyn_cast<Instruction>(V);
825  if (!I)
826  return CastContextHint::None;
827 
828  if (I->getOpcode() == LdStOp)
830 
831  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
832  if (II->getIntrinsicID() == MaskedOp)
834  if (II->getIntrinsicID() == GatScatOp)
836  }
837 
839  };
840 
841  switch (I->getOpcode()) {
842  case Instruction::ZExt:
843  case Instruction::SExt:
844  case Instruction::FPExt:
845  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
846  Intrinsic::masked_load, Intrinsic::masked_gather);
847  case Instruction::Trunc:
848  case Instruction::FPTrunc:
849  if (I->hasOneUse())
850  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
851  Intrinsic::masked_store,
852  Intrinsic::masked_scatter);
853  break;
854  default:
855  return CastContextHint::None;
856  }
857 
859 }
860 
862  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
863  TTI::TargetCostKind CostKind, const Instruction *I) const {
864  assert((I == nullptr || I->getOpcode() == Opcode) &&
865  "Opcode should reflect passed instruction.");
867  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
868  assert(Cost >= 0 && "TTI should not produce negative costs!");
869  return Cost;
870 }
871 
873  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
875  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
876  assert(Cost >= 0 && "TTI should not produce negative costs!");
877  return Cost;
878 }
879 
881  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
882  assert((I == nullptr || I->getOpcode() == Opcode) &&
883  "Opcode should reflect passed instruction.");
884  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
885  assert(Cost >= 0 && "TTI should not produce negative costs!");
886  return Cost;
887 }
888 
890  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
891  TTI::TargetCostKind CostKind, const Instruction *I) const {
892  assert((I == nullptr || I->getOpcode() == Opcode) &&
893  "Opcode should reflect passed instruction.");
895  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
896  assert(Cost >= 0 && "TTI should not produce negative costs!");
897  return Cost;
898 }
899 
901  Type *Val,
902  unsigned Index) const {
903  // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
904  // This is mentioned in the interface description and respected by all
905  // callers, but never asserted upon.
906  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
907  assert(Cost >= 0 && "TTI should not produce negative costs!");
908  return Cost;
909 }
910 
912  Type *Val,
913  unsigned Index) const {
914  // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
915  // This is mentioned in the interface description and respected by all
916  // callers, but never asserted upon.
917  InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, Index);
918  assert(Cost >= 0 && "TTI should not produce negative costs!");
919  return Cost;
920 }
921 
923  Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
925  InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
926  EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
927  assert(Cost >= 0 && "TTI should not produce negative costs!");
928  return Cost;
929 }
930 
932  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
934  const Instruction *I) const {
935  assert((I == nullptr || I->getOpcode() == Opcode) &&
936  "Opcode should reflect passed instruction.");
937  InstructionCost Cost = TTIImpl->getMemoryOpCost(
938  Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
939  assert(Cost >= 0 && "TTI should not produce negative costs!");
940  return Cost;
941 }
942 
944  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
946  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
948  assert(Cost >= 0 && "TTI should not produce negative costs!");
949  return Cost;
950 }
951 
953  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
954  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
955  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
956  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
957  assert(Cost >= 0 && "TTI should not produce negative costs!");
958  return Cost;
959 }
960 
962  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
963  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
964  bool UseMaskForCond, bool UseMaskForGaps) const {
965  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
966  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
967  UseMaskForCond, UseMaskForGaps);
968  assert(Cost >= 0 && "TTI should not produce negative costs!");
969  return Cost;
970 }
971 
975  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
976  assert(Cost >= 0 && "TTI should not produce negative costs!");
977  return Cost;
978 }
979 
982  ArrayRef<Type *> Tys,
984  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
985  assert(Cost >= 0 && "TTI should not produce negative costs!");
986  return Cost;
987 }
988 
990  return TTIImpl->getNumberOfParts(Tp);
991 }
992 
995  const SCEV *Ptr) const {
996  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
997  assert(Cost >= 0 && "TTI should not produce negative costs!");
998  return Cost;
999 }
1000 
1002  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1003  assert(Cost >= 0 && "TTI should not produce negative costs!");
1004  return Cost;
1005 }
1006 
1008  unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1009  TTI::TargetCostKind CostKind) const {
1011  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1012  assert(Cost >= 0 && "TTI should not produce negative costs!");
1013  return Cost;
1014 }
1015 
1017  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
1018  TTI::TargetCostKind CostKind) const {
1020  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
1021  assert(Cost >= 0 && "TTI should not produce negative costs!");
1022  return Cost;
1023 }
1024 
1026  unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1027  std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1028  return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1029  CostKind);
1030 }
1031 
1033  bool IsUnsigned, Type *ResTy, VectorType *Ty,
1034  TTI::TargetCostKind CostKind) const {
1035  return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
1036 }
1037 
1040  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1041 }
1042 
1044  MemIntrinsicInfo &Info) const {
1045  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1046 }
1047 
1049  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1050 }
1051 
1053  IntrinsicInst *Inst, Type *ExpectedType) const {
1054  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1055 }
1056 
1058  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1059  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1060  std::optional<uint32_t> AtomicElementSize) const {
1061  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1062  DestAddrSpace, SrcAlign, DestAlign,
1063  AtomicElementSize);
1064 }
1065 
1068  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1069  unsigned SrcAlign, unsigned DestAlign,
1070  std::optional<uint32_t> AtomicCpySize) const {
1071  TTIImpl->getMemcpyLoopResidualLoweringType(
1072  OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1073  DestAlign, AtomicCpySize);
1074 }
1075 
1077  const Function *Callee) const {
1078  return TTIImpl->areInlineCompatible(Caller, Callee);
1079 }
1080 
1082  const Function *Caller, const Function *Callee,
1083  const ArrayRef<Type *> &Types) const {
1084  return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1085 }
1086 
1088  Type *Ty) const {
1089  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1090 }
1091 
1093  Type *Ty) const {
1094  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1095 }
1096 
1098  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1099 }
1100 
1102  return TTIImpl->isLegalToVectorizeLoad(LI);
1103 }
1104 
1106  return TTIImpl->isLegalToVectorizeStore(SI);
1107 }
1108 
1110  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1111  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1112  AddrSpace);
1113 }
1114 
1116  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1117  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1118  AddrSpace);
1119 }
1120 
1122  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1123  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1124 }
1125 
1127  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1128 }
1129 
1131  unsigned LoadSize,
1132  unsigned ChainSizeInBytes,
1133  VectorType *VecTy) const {
1134  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1135 }
1136 
1138  unsigned StoreSize,
1139  unsigned ChainSizeInBytes,
1140  VectorType *VecTy) const {
1141  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1142 }
1143 
1145  ReductionFlags Flags) const {
1146  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1147 }
1148 
1150  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1151  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1152 }
1153 
1155  return TTIImpl->preferEpilogueVectorization();
1156 }
1157 
1160  return TTIImpl->getVPLegalizationStrategy(VPI);
1161 }
1162 
1164  return TTIImpl->shouldExpandReduction(II);
1165 }
1166 
1168  return TTIImpl->getGISelRematGlobalCost();
1169 }
1170 
1172  return TTIImpl->getMinTripCountTailFoldingThreshold();
1173 }
1174 
1176  return TTIImpl->supportsScalableVectors();
1177 }
1178 
1180  return TTIImpl->enableScalableVectorization();
1181 }
1182 
1184  Align Alignment) const {
1185  return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1186 }
1187 
1189 
1190 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1191 
1193  std::function<Result(const Function &)> TTICallback)
1194  : TTICallback(std::move(TTICallback)) {}
1195 
1198  return TTICallback(F);
1199 }
1200 
1201 AnalysisKey TargetIRAnalysis::Key;
1202 
1203 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1204  return Result(F.getParent()->getDataLayout());
1205 }
1206 
1207 // Register the basic pass.
1209  "Target Transform Information", false, true)
1211 
1212 void TargetTransformInfoWrapperPass::anchor() {}
1213 
1215  : ImmutablePass(ID) {
1218 }
1219 
1221  TargetIRAnalysis TIRA)
1222  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1225 }
1226 
1228  FunctionAnalysisManager DummyFAM;
1229  TTI = TIRA.run(F, DummyFAM);
1230  return *TTI;
1231 }
1232 
1233 ImmutablePass *
1235  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1236 }
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:295
llvm::InstructionCost
Definition: InstructionCost.h:30
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2592
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1457
llvm::TargetTransformInfo::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:225
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:654
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1405
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:645
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:911
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:889
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1214
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:376
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:139
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:649
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:585
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1159
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1227
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:994
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::TargetTransformInfo::instCombineIntrinsic
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:313
llvm::TargetTransformInfo::getMaxVScale
std::optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:658
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:468
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:973
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:273
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:350
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:325
llvm::TargetTransformInfo::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
Definition: TargetTransformInfo.cpp:412
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:102
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:4335
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1515
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:499
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:106
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:676
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:512
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:193
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:100
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:408
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:403
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:880
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
Definition: TargetTransformInfo.cpp:61
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:919
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:234
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:600
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:207
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:627
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:256
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1316
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:617
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:926
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:554
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:523
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1144
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:1023
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:268
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:107
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:335
llvm::TargetTransformInfo::getCacheAssociativity
std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:703
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:428
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Instruction.h
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1167
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:1076
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:491
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:103
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:671
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:372
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:818
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:1052
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:1101
llvm::TargetTransformInfo::supportsTailCallFor
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
Definition: TargetTransformInfo.cpp:536
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:795
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:647
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:577
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:918
InlinePriorityMode::Cost
@ Cost
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:889
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:388
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1142
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:242
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:129
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1396
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:238
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1121
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:610
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:989
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1175
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1087
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::dwarf::Index
Index
Definition: Dwarf.h:490
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:447
llvm::TargetTransformInfo::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfo.cpp:1179
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:128
llvm::Instruction
Definition: Instruction.h:42
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:759
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:398
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:246
llvm::predecessors
auto predecessors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:30
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:707
llvm::TargetTransformInfo::getVScaleForTuning
std::optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfo.cpp:662
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:109
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:944
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:590
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfo::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfo.cpp:1081
LoopIterator.h
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:120
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:459
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:443
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:581
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1234
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:301
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:254
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:503
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:403
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:258
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:417
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2648
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1149
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:961
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:912
llvm::TargetTransformInfo::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
Definition: TargetTransformInfo.cpp:433
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2594
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:730
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:640
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::TargetTransformInfo::preferEpilogueVectorization
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
Definition: TargetTransformInfo.cpp:1154
llvm::TargetTransformInfo::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
Definition: TargetTransformInfo.cpp:422
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:69
llvm::TargetTransformInfo::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
Definition: TargetTransformInfo.cpp:1025
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:1039
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:992
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:917
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:446
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:686
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:517
llvm::TargetTransformInfo::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfo.cpp:922
llvm::TargetTransformInfo::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
Definition: TargetTransformInfo.cpp:585
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:286
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
Definition: TargetTransformInfo.cpp:363
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:952
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1861
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:477
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
Definition: TargetTransformInfo.cpp:1066
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:1016
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1109
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:212
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:346
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:291
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:861
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:909
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1322
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
getType
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
Definition: M68kELFObjectWriter.cpp:48
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:380
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:481
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:464
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:780
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:528
llvm::TargetTransformInfo::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the...
Definition: TargetTransformInfo.cpp:308
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:546
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1108
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1126
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:393
llvm::TargetTransformInfo::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:282
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:455
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:636
llvm::TargetTransformInfo::shouldPrefetchAddressSpace
bool shouldPrefetchAddressSpace(unsigned AS) const
Definition: TargetTransformInfo.cpp:726
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:632
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:718
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:432
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:910
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1130
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:1105
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:13637
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1190
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:451
llvm::TargetTransformInfo::OP_NegatedPowerOf2
@ OP_NegatedPowerOf2
Definition: TargetTransformInfo.h:920
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:318
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:1007
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:692
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=std::nullopt, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=std::nullopt) const
Definition: TargetTransformInfo.cpp:807
llvm::TargetTransformInfo::supportsTailCalls
bool supportsTailCalls() const
If the target supports tail calls.
Definition: TargetTransformInfo.cpp:532
std
Definition: BitVector.h:851
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:558
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:101
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::TargetTransformInfo::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:1032
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:476
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:263
llvm::TargetTransformInfo::getOperandInfo
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:735
llvm::TypeSize
Definition: TypeSize.h:435
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1097
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
Definition: TargetTransformInfo.cpp:1057
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfo.cpp:666
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:105
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:562
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:226
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfo.cpp:1183
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::TargetTransformInfo::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
Definition: TargetTransformInfo.cpp:438
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:931
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1196
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:198
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:900
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:166
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:203
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:943
llvm::TargetTransformInfo::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: TargetTransformInfo.cpp:1171
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:97
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:218
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2578
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:967
Dominators.h
llvm::TargetTransformInfo::enableSelectOptimize
bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
Definition: TargetTransformInfo.cpp:550
DataType
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:711
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1092
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:368
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1163
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfo.cpp:872
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:341
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1137
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:51
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1115
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:72
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:1048
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:540
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:567
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:981
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3276
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:485
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:508
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3132
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:244
llvm::TargetTransformInfo::isSingleThreaded
bool isSingleThreaded() const
Definition: TargetTransformInfo.cpp:277
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:913
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:1043
llvm::TargetTransformInfo::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
Definition: TargetTransformInfo.cpp:681
llvm::TargetTransformInfo::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:495
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:489
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:104
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:722
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:594
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:219
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:8222
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::TargetTransformInfo::getCacheSize
std::optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:698
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:250
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:354
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:1001
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39