LLVM  15.0.0git
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/Dominators.h"
15 #include "llvm/IR/Instruction.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/Module.h"
19 #include "llvm/IR/Operator.h"
20 #include "llvm/IR/PatternMatch.h"
21 #include "llvm/InitializePasses.h"
23 #include <utility>
24 
25 using namespace llvm;
26 using namespace PatternMatch;
27 
28 #define DEBUG_TYPE "tti"
29 
30 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
31  cl::Hidden,
32  cl::desc("Recognize reduction patterns."));
33 
35  "cache-line-size", cl::init(0), cl::Hidden,
36  cl::desc("Use this to override the target cache line size when "
37  "specified by the user."));
38 
39 namespace {
40 /// No-op implementation of the TTI interface using the utility base
41 /// classes.
42 ///
43 /// This is used when no target specific information is available.
44 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
45  explicit NoTTIImpl(const DataLayout &DL)
46  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
47 };
48 } // namespace
49 
51  // If the loop has irreducible control flow, it can not be converted to
52  // Hardware loop.
53  LoopBlocksRPO RPOT(L);
54  RPOT.perform(&LI);
55  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
56  return false;
57  return true;
58 }
59 
61  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost)
62  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
63  ScalarizationCost(ScalarizationCost) {
64 
65  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
66  FMF = FPMO->getFastMathFlags();
67 
68  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
70  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
71 }
72 
74  ArrayRef<Type *> Tys,
75  FastMathFlags Flags,
76  const IntrinsicInst *I,
77  InstructionCost ScalarCost)
78  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
79  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
80 }
81 
84  : RetTy(Ty), IID(Id) {
85 
86  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
87  ParamTys.reserve(Arguments.size());
88  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
89  ParamTys.push_back(Arguments[Idx]->getType());
90 }
91 
94  ArrayRef<Type *> Tys,
95  FastMathFlags Flags,
96  const IntrinsicInst *I,
97  InstructionCost ScalarCost)
98  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
99  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
100  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
101 }
102 
104  LoopInfo &LI, DominatorTree &DT,
105  bool ForceNestedLoop,
106  bool ForceHardwareLoopPHI) {
107  SmallVector<BasicBlock *, 4> ExitingBlocks;
108  L->getExitingBlocks(ExitingBlocks);
109 
110  for (BasicBlock *BB : ExitingBlocks) {
111  // If we pass the updated counter back through a phi, we need to know
112  // which latch the updated value will be coming from.
113  if (!L->isLoopLatch(BB)) {
115  continue;
116  }
117 
118  const SCEV *EC = SE.getExitCount(L, BB);
119  if (isa<SCEVCouldNotCompute>(EC))
120  continue;
121  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
122  if (ConstEC->getValue()->isZero())
123  continue;
124  } else if (!SE.isLoopInvariant(EC, L))
125  continue;
126 
127  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
128  continue;
129 
130  // If this exiting block is contained in a nested loop, it is not eligible
131  // for insertion of the branch-and-decrement since the inner loop would
132  // end up messing up the value in the CTR.
133  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
134  continue;
135 
136  // We now have a loop-invariant count of loop iterations (which is not the
137  // constant zero) for which we know that this loop will not exit via this
138  // existing block.
139 
140  // We need to make sure that this block will run on every loop iteration.
141  // For this to be true, we must dominate all blocks with backedges. Such
142  // blocks are in-loop predecessors to the header block.
143  bool NotAlways = false;
144  for (BasicBlock *Pred : predecessors(L->getHeader())) {
145  if (!L->contains(Pred))
146  continue;
147 
148  if (!DT.dominates(BB, Pred)) {
149  NotAlways = true;
150  break;
151  }
152  }
153 
154  if (NotAlways)
155  continue;
156 
157  // Make sure this blocks ends with a conditional branch.
158  Instruction *TI = BB->getTerminator();
159  if (!TI)
160  continue;
161 
162  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
163  if (!BI->isConditional())
164  continue;
165 
166  ExitBranch = BI;
167  } else
168  continue;
169 
170  // Note that this block may not be the loop latch block, even if the loop
171  // has a latch block.
172  ExitBlock = BB;
173  ExitCount = EC;
174  break;
175  }
176 
177  if (!ExitBlock)
178  return false;
179  return true;
180 }
181 
183  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
184 
186 
188  : TTIImpl(std::move(Arg.TTIImpl)) {}
189 
191  TTIImpl = std::move(RHS.TTIImpl);
192  return *this;
193 }
194 
196  return TTIImpl->getInliningThresholdMultiplier();
197 }
198 
199 unsigned
201  return TTIImpl->adjustInliningThreshold(CB);
202 }
203 
205  return TTIImpl->getInlinerVectorBonusPercent();
206 }
207 
209 TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
212  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
213 }
214 
216  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
217  BlockFrequencyInfo *BFI) const {
218  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
219 }
220 
224  enum TargetCostKind CostKind) const {
225  InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
226  assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
227  "TTI should not produce negative costs!");
228  return Cost;
229 }
230 
232  return TTIImpl->getPredictableBranchThreshold();
233 }
234 
236  return TTIImpl->hasBranchDivergence();
237 }
238 
240  return TTIImpl->useGPUDivergenceAnalysis();
241 }
242 
244  return TTIImpl->isSourceOfDivergence(V);
245 }
246 
248  return TTIImpl->isAlwaysUniform(V);
249 }
250 
252  return TTIImpl->getFlatAddressSpace();
253 }
254 
256  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
257  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
258 }
259 
261  unsigned ToAS) const {
262  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
263 }
264 
266  unsigned AS) const {
267  return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
268 }
269 
271  return TTIImpl->getAssumedAddrSpace(V);
272 }
273 
274 std::pair<const Value *, unsigned>
276  return TTIImpl->getPredicatedAddrSpace(V);
277 }
278 
280  IntrinsicInst *II, Value *OldV, Value *NewV) const {
281  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
282 }
283 
285  return TTIImpl->isLoweredToCall(F);
286 }
287 
289  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
290  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
291  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
292 }
293 
295  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
297  const LoopAccessInfo *LAI) const {
298  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
299 }
300 
302  return TTIImpl->emitGetActiveLaneMask();
303 }
304 
307  IntrinsicInst &II) const {
308  return TTIImpl->instCombineIntrinsic(IC, II);
309 }
310 
312  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
313  bool &KnownBitsComputed) const {
314  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
315  KnownBitsComputed);
316 }
317 
319  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
320  APInt &UndefElts2, APInt &UndefElts3,
321  std::function<void(Instruction *, unsigned, APInt, APInt &)>
322  SimplifyAndSetOp) const {
323  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
324  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
325  SimplifyAndSetOp);
326 }
327 
330  OptimizationRemarkEmitter *ORE) const {
331  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
332 }
333 
335  PeelingPreferences &PP) const {
336  return TTIImpl->getPeelingPreferences(L, SE, PP);
337 }
338 
340  return TTIImpl->isLegalAddImmediate(Imm);
341 }
342 
344  return TTIImpl->isLegalICmpImmediate(Imm);
345 }
346 
348  int64_t BaseOffset,
349  bool HasBaseReg, int64_t Scale,
350  unsigned AddrSpace,
351  Instruction *I) const {
352  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
353  Scale, AddrSpace, I);
354 }
355 
357  const LSRCost &C2) const {
358  return TTIImpl->isLSRCostLess(C1, C2);
359 }
360 
362  return TTIImpl->isNumRegsMajorCostOfLSR();
363 }
364 
366  return TTIImpl->isProfitableLSRChainElement(I);
367 }
368 
370  return TTIImpl->canMacroFuseCmp();
371 }
372 
374  ScalarEvolution *SE, LoopInfo *LI,
376  TargetLibraryInfo *LibInfo) const {
377  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
378 }
379 
382  ScalarEvolution *SE) const {
383  return TTIImpl->getPreferredAddressingMode(L, SE);
384 }
385 
387  Align Alignment) const {
388  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
389 }
390 
392  Align Alignment) const {
393  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
394 }
395 
397  Align Alignment) const {
398  return TTIImpl->isLegalNTStore(DataType, Alignment);
399 }
400 
401 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
402  return TTIImpl->isLegalNTLoad(DataType, Alignment);
403 }
404 
406  ElementCount NumElements) const {
407  return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
408 }
409 
411  Align Alignment) const {
412  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
413 }
414 
416  VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
417  const SmallBitVector &OpcodeMask) const {
418  return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
419 }
420 
422  Align Alignment) const {
423  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
424 }
425 
427  Align Alignment) const {
428  return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
429 }
430 
432  Align Alignment) const {
433  return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
434 }
435 
437  return TTIImpl->isLegalMaskedCompressStore(DataType);
438 }
439 
441  return TTIImpl->isLegalMaskedExpandLoad(DataType);
442 }
443 
445  return TTIImpl->enableOrderedReductions();
446 }
447 
448 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
449  return TTIImpl->hasDivRemOp(DataType, IsSigned);
450 }
451 
453  unsigned AddrSpace) const {
454  return TTIImpl->hasVolatileVariant(I, AddrSpace);
455 }
456 
458  return TTIImpl->prefersVectorizedAddressing();
459 }
460 
462  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
463  int64_t Scale, unsigned AddrSpace) const {
464  InstructionCost Cost = TTIImpl->getScalingFactorCost(
465  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
466  assert(Cost >= 0 && "TTI should not produce negative costs!");
467  return Cost;
468 }
469 
471  return TTIImpl->LSRWithInstrQueries();
472 }
473 
475  return TTIImpl->isTruncateFree(Ty1, Ty2);
476 }
477 
479  return TTIImpl->isProfitableToHoist(I);
480 }
481 
482 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
483 
485  return TTIImpl->isTypeLegal(Ty);
486 }
487 
489  return TTIImpl->getRegUsageForType(Ty);
490 }
491 
493  return TTIImpl->shouldBuildLookupTables();
494 }
495 
497  Constant *C) const {
498  return TTIImpl->shouldBuildLookupTablesForConstant(C);
499 }
500 
502  return TTIImpl->shouldBuildRelLookupTables();
503 }
504 
506  return TTIImpl->useColdCCForColdCall(F);
507 }
508 
511  const APInt &DemandedElts,
512  bool Insert, bool Extract) const {
513  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
514 }
515 
518  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
519 }
520 
522  return TTIImpl->supportsEfficientVectorElementLoadStore();
523 }
524 
526  return TTIImpl->supportsTailCalls();
527 }
528 
530  bool LoopHasReductions) const {
531  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
532 }
533 
535 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
536  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
537 }
538 
540  return TTIImpl->enableInterleavedAccessVectorization();
541 }
542 
544  return TTIImpl->enableMaskedInterleavedAccessVectorization();
545 }
546 
548  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
549 }
550 
552  unsigned BitWidth,
553  unsigned AddressSpace,
554  Align Alignment,
555  bool *Fast) const {
556  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
557  AddressSpace, Alignment, Fast);
558 }
559 
561 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
562  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
563 }
564 
566  return TTIImpl->haveFastSqrt(Ty);
567 }
568 
570  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
571 }
572 
574  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
575  assert(Cost >= 0 && "TTI should not produce negative costs!");
576  return Cost;
577 }
578 
580  unsigned Idx,
581  const APInt &Imm,
582  Type *Ty) const {
583  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
584  assert(Cost >= 0 && "TTI should not produce negative costs!");
585  return Cost;
586 }
587 
591  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
592  assert(Cost >= 0 && "TTI should not produce negative costs!");
593  return Cost;
594 }
595 
597  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
599  InstructionCost Cost =
600  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
601  assert(Cost >= 0 && "TTI should not produce negative costs!");
602  return Cost;
603 }
604 
607  const APInt &Imm, Type *Ty,
609  InstructionCost Cost =
610  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
611  assert(Cost >= 0 && "TTI should not produce negative costs!");
612  return Cost;
613 }
614 
615 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
616  return TTIImpl->getNumberOfRegisters(ClassID);
617 }
618 
620  Type *Ty) const {
621  return TTIImpl->getRegisterClassForType(Vector, Ty);
622 }
623 
624 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
625  return TTIImpl->getRegisterClassName(ClassID);
626 }
627 
630  return TTIImpl->getRegisterBitWidth(K);
631 }
632 
634  return TTIImpl->getMinVectorRegisterBitWidth();
635 }
636 
638  return TTIImpl->getMaxVScale();
639 }
640 
642  return TTIImpl->getVScaleForTuning();
643 }
644 
647  return TTIImpl->shouldMaximizeVectorBandwidth(K);
648 }
649 
651  bool IsScalable) const {
652  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
653 }
654 
655 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
656  unsigned Opcode) const {
657  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
658 }
659 
660 unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
661  Type *ScalarValTy) const {
662  return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
663 }
664 
666  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
667  return TTIImpl->shouldConsiderAddressTypePromotion(
668  I, AllowPromotionWithoutCommonHeader);
669 }
670 
672  return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
673  : TTIImpl->getCacheLineSize();
674 }
675 
678  return TTIImpl->getCacheSize(Level);
679 }
680 
683  return TTIImpl->getCacheAssociativity(Level);
684 }
685 
687  return TTIImpl->getPrefetchDistance();
688 }
689 
691  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
692  unsigned NumPrefetches, bool HasCall) const {
693  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
694  NumPrefetches, HasCall);
695 }
696 
698  return TTIImpl->getMaxPrefetchIterationsAhead();
699 }
700 
702  return TTIImpl->enableWritePrefetching();
703 }
704 
705 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
706  return TTIImpl->getMaxInterleaveFactor(VF);
707 }
708 
711  OperandValueProperties &OpProps) {
712  OperandValueKind OpInfo = OK_AnyValue;
713  OpProps = OP_None;
714 
715  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
716  if (CI->getValue().isPowerOf2())
717  OpProps = OP_PowerOf2;
719  }
720 
721  // A broadcast shuffle creates a uniform value.
722  // TODO: Add support for non-zero index broadcasts.
723  // TODO: Add support for different source vector width.
724  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
725  if (ShuffleInst->isZeroEltSplat())
726  OpInfo = OK_UniformValue;
727 
728  const Value *Splat = getSplatValue(V);
729 
730  // Check for a splat of a constant or for a non uniform vector of constants
731  // and check if the constant(s) are all powers of two.
732  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
734  if (Splat) {
735  OpInfo = OK_UniformConstantValue;
736  if (auto *CI = dyn_cast<ConstantInt>(Splat))
737  if (CI->getValue().isPowerOf2())
738  OpProps = OP_PowerOf2;
739  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
740  OpProps = OP_PowerOf2;
741  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
742  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
743  if (CI->getValue().isPowerOf2())
744  continue;
745  OpProps = OP_None;
746  break;
747  }
748  }
749  }
750 
751  // Check for a splat of a uniform value. This is not loop aware, so return
752  // true only for the obviously uniform cases (argument, globalvalue)
753  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
754  OpInfo = OK_UniformValue;
755 
756  return OpInfo;
757 }
758 
760  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
761  OperandValueKind Opd1Info, OperandValueKind Opd2Info,
762  OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo,
763  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
764  InstructionCost Cost =
765  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
766  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
767  assert(Cost >= 0 && "TTI should not produce negative costs!");
768  return Cost;
769 }
770 
773  VectorType *SubTp, ArrayRef<const Value *> Args) const {
774  InstructionCost Cost =
775  TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp, Args);
776  assert(Cost >= 0 && "TTI should not produce negative costs!");
777  return Cost;
778 }
779 
782  if (!I)
783  return CastContextHint::None;
784 
785  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
786  unsigned GatScatOp) {
787  const Instruction *I = dyn_cast<Instruction>(V);
788  if (!I)
789  return CastContextHint::None;
790 
791  if (I->getOpcode() == LdStOp)
793 
794  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
795  if (II->getIntrinsicID() == MaskedOp)
797  if (II->getIntrinsicID() == GatScatOp)
799  }
800 
802  };
803 
804  switch (I->getOpcode()) {
805  case Instruction::ZExt:
806  case Instruction::SExt:
807  case Instruction::FPExt:
808  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
809  Intrinsic::masked_load, Intrinsic::masked_gather);
810  case Instruction::Trunc:
811  case Instruction::FPTrunc:
812  if (I->hasOneUse())
813  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
814  Intrinsic::masked_store,
815  Intrinsic::masked_scatter);
816  break;
817  default:
818  return CastContextHint::None;
819  }
820 
822 }
823 
825  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
826  TTI::TargetCostKind CostKind, const Instruction *I) const {
827  assert((I == nullptr || I->getOpcode() == Opcode) &&
828  "Opcode should reflect passed instruction.");
829  InstructionCost Cost =
830  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
831  assert(Cost >= 0 && "TTI should not produce negative costs!");
832  return Cost;
833 }
834 
836  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
837  InstructionCost Cost =
838  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
839  assert(Cost >= 0 && "TTI should not produce negative costs!");
840  return Cost;
841 }
842 
844  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
845  assert((I == nullptr || I->getOpcode() == Opcode) &&
846  "Opcode should reflect passed instruction.");
847  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
848  assert(Cost >= 0 && "TTI should not produce negative costs!");
849  return Cost;
850 }
851 
853  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
854  TTI::TargetCostKind CostKind, const Instruction *I) const {
855  assert((I == nullptr || I->getOpcode() == Opcode) &&
856  "Opcode should reflect passed instruction.");
857  InstructionCost Cost =
858  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
859  assert(Cost >= 0 && "TTI should not produce negative costs!");
860  return Cost;
861 }
862 
864  Type *Val,
865  unsigned Index) const {
866  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
867  assert(Cost >= 0 && "TTI should not produce negative costs!");
868  return Cost;
869 }
870 
872  Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
874  InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
875  EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
876  assert(Cost >= 0 && "TTI should not produce negative costs!");
877  return Cost;
878 }
879 
881  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
882  TTI::TargetCostKind CostKind, const Instruction *I) const {
883  assert((I == nullptr || I->getOpcode() == Opcode) &&
884  "Opcode should reflect passed instruction.");
885  InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment,
887  assert(Cost >= 0 && "TTI should not produce negative costs!");
888  return Cost;
889 }
890 
892  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
894  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
896  assert(Cost >= 0 && "TTI should not produce negative costs!");
897  return Cost;
898 }
899 
901  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
902  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
903  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
904  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
905  assert(Cost >= 0 && "TTI should not produce negative costs!");
906  return Cost;
907 }
908 
910  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
911  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
912  bool UseMaskForCond, bool UseMaskForGaps) const {
913  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
914  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
915  UseMaskForCond, UseMaskForGaps);
916  assert(Cost >= 0 && "TTI should not produce negative costs!");
917  return Cost;
918 }
919 
923  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
924  assert(Cost >= 0 && "TTI should not produce negative costs!");
925  return Cost;
926 }
927 
930  ArrayRef<Type *> Tys,
932  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
933  assert(Cost >= 0 && "TTI should not produce negative costs!");
934  return Cost;
935 }
936 
938  return TTIImpl->getNumberOfParts(Tp);
939 }
940 
943  const SCEV *Ptr) const {
944  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
945  assert(Cost >= 0 && "TTI should not produce negative costs!");
946  return Cost;
947 }
948 
950  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
951  assert(Cost >= 0 && "TTI should not produce negative costs!");
952  return Cost;
953 }
954 
956  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
958  InstructionCost Cost =
959  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
960  assert(Cost >= 0 && "TTI should not produce negative costs!");
961  return Cost;
962 }
963 
965  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
967  InstructionCost Cost =
968  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
969  assert(Cost >= 0 && "TTI should not produce negative costs!");
970  return Cost;
971 }
972 
974  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
976  return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
977  CostKind);
978 }
979 
982  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
983 }
984 
986  MemIntrinsicInfo &Info) const {
987  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
988 }
989 
991  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
992 }
993 
995  IntrinsicInst *Inst, Type *ExpectedType) const {
996  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
997 }
998 
1000  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1001  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1002  Optional<uint32_t> AtomicElementSize) const {
1003  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1004  DestAddrSpace, SrcAlign, DestAlign,
1005  AtomicElementSize);
1006 }
1007 
1010  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1011  unsigned SrcAlign, unsigned DestAlign,
1012  Optional<uint32_t> AtomicCpySize) const {
1013  TTIImpl->getMemcpyLoopResidualLoweringType(
1014  OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1015  DestAlign, AtomicCpySize);
1016 }
1017 
1019  const Function *Callee) const {
1020  return TTIImpl->areInlineCompatible(Caller, Callee);
1021 }
1022 
1024  const Function *Caller, const Function *Callee,
1025  const ArrayRef<Type *> &Types) const {
1026  return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1027 }
1028 
1030  Type *Ty) const {
1031  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1032 }
1033 
1035  Type *Ty) const {
1036  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1037 }
1038 
1040  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1041 }
1042 
1044  return TTIImpl->isLegalToVectorizeLoad(LI);
1045 }
1046 
1048  return TTIImpl->isLegalToVectorizeStore(SI);
1049 }
1050 
1052  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1053  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1054  AddrSpace);
1055 }
1056 
1058  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1059  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1060  AddrSpace);
1061 }
1062 
1064  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1065  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1066 }
1067 
1069  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1070 }
1071 
1073  unsigned LoadSize,
1074  unsigned ChainSizeInBytes,
1075  VectorType *VecTy) const {
1076  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1077 }
1078 
1080  unsigned StoreSize,
1081  unsigned ChainSizeInBytes,
1082  VectorType *VecTy) const {
1083  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1084 }
1085 
1087  ReductionFlags Flags) const {
1088  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1089 }
1090 
1092  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1093  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1094 }
1095 
1098  return TTIImpl->getVPLegalizationStrategy(VPI);
1099 }
1100 
1102  return TTIImpl->shouldExpandReduction(II);
1103 }
1104 
1106  return TTIImpl->getGISelRematGlobalCost();
1107 }
1108 
1110  return TTIImpl->supportsScalableVectors();
1111 }
1112 
1114  return TTIImpl->enableScalableVectorization();
1115 }
1116 
1117 bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1118  Align Alignment) const {
1119  return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1120 }
1121 
1123 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1124  return TTIImpl->getInstructionLatency(I);
1125 }
1126 
1128 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1130 
1131  switch (I->getOpcode()) {
1132  case Instruction::GetElementPtr:
1133  case Instruction::Ret:
1134  case Instruction::PHI:
1135  case Instruction::Br:
1136  case Instruction::Add:
1137  case Instruction::FAdd:
1138  case Instruction::Sub:
1139  case Instruction::FSub:
1140  case Instruction::Mul:
1141  case Instruction::FMul:
1142  case Instruction::UDiv:
1143  case Instruction::SDiv:
1144  case Instruction::FDiv:
1145  case Instruction::URem:
1146  case Instruction::SRem:
1147  case Instruction::FRem:
1148  case Instruction::Shl:
1149  case Instruction::LShr:
1150  case Instruction::AShr:
1151  case Instruction::And:
1152  case Instruction::Or:
1153  case Instruction::Xor:
1154  case Instruction::FNeg:
1155  case Instruction::Select:
1156  case Instruction::ICmp:
1157  case Instruction::FCmp:
1158  case Instruction::Store:
1159  case Instruction::Load:
1160  case Instruction::ZExt:
1161  case Instruction::SExt:
1162  case Instruction::FPToUI:
1163  case Instruction::FPToSI:
1164  case Instruction::FPExt:
1165  case Instruction::PtrToInt:
1166  case Instruction::IntToPtr:
1167  case Instruction::SIToFP:
1168  case Instruction::UIToFP:
1169  case Instruction::Trunc:
1170  case Instruction::FPTrunc:
1171  case Instruction::BitCast:
1172  case Instruction::AddrSpaceCast:
1173  case Instruction::ExtractElement:
1174  case Instruction::InsertElement:
1175  case Instruction::ExtractValue:
1176  case Instruction::ShuffleVector:
1177  case Instruction::Call:
1178  case Instruction::Switch:
1179  return getUserCost(I, CostKind);
1180  default:
1181  // We don't have any information on this instruction.
1182  return -1;
1183  }
1184 }
1185 
1187 
1188 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1189 
1191  std::function<Result(const Function &)> TTICallback)
1192  : TTICallback(std::move(TTICallback)) {}
1193 
1196  return TTICallback(F);
1197 }
1198 
1199 AnalysisKey TargetIRAnalysis::Key;
1200 
1201 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1202  return Result(F.getParent()->getDataLayout());
1203 }
1204 
1205 // Register the basic pass.
1207  "Target Transform Information", false, true)
1209 
1210 void TargetTransformInfoWrapperPass::anchor() {}
1211 
1213  : ImmutablePass(ID) {
1216 }
1217 
1219  TargetIRAnalysis TIRA)
1220  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1223 }
1224 
1226  FunctionAnalysisManager DummyFAM;
1227  TTI = TIRA.run(F, DummyFAM);
1228  return *TTI;
1229 }
1230 
1231 ImmutablePass *
1233  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1234 }
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:288
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2485
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1401
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:306
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:294
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:633
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1349
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::TargetTransformInfo::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfo.cpp:641
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:624
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:906
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:852
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1212
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:369
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:138
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:628
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:595
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:880
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1097
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1225
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:942
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:461
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:921
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:270
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:343
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::TargetTransformInfo::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
Definition: TargetTransformInfo.cpp:405
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:100
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:4295
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1451
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:492
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:103
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:655
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:505
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:538
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:190
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:98
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:401
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:396
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:843
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:912
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:231
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:579
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:204
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:606
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:255
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1316
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:596
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:539
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:516
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1086
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:989
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:265
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:105
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:328
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:421
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
Instruction.h
CommandLine.h
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1105
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:1018
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1374
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:484
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:101
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:650
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:365
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:781
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:994
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:1043
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:561
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:912
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:885
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:381
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1106
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:239
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:129
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1396
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:235
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1063
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:589
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:937
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1109
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1029
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:440
llvm::TargetTransformInfo::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfo.cpp:1113
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:128
llvm::Instruction
Definition: Instruction.h:42
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:391
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:243
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:318
llvm::predecessors
auto predecessors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:30
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:686
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:107
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:907
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:569
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfo::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfo.cpp:1023
LoopIterator.h
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:452
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:436
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:565
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1232
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:251
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:496
CacheLineSize
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:255
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:410
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2541
llvm::TargetTransformInfo::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported.
Definition: TargetTransformInfo.cpp:301
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1091
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:909
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:907
llvm::TargetTransformInfo::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
Definition: TargetTransformInfo.cpp:426
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2487
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:705
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:619
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::TargetTransformInfo::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
Definition: TargetTransformInfo.cpp:415
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:69
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:431
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:981
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:986
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:912
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:665
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:559
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:510
llvm::TargetTransformInfo::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfo.cpp:871
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:279
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
Definition: TargetTransformInfo.cpp:356
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:900
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1675
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:470
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:964
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1051
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:209
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:339
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:551
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:284
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:824
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:904
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1322
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:373
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:474
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:457
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:787
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:521
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:535
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1102
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1068
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:386
llvm::TargetTransformInfo::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:275
llvm::TargetTransformInfo::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:222
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:448
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:311
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:677
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:615
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:642
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:697
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:905
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1072
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:1047
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:13416
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1188
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=None) const
Definition: TargetTransformInfo.cpp:771
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:444
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:637
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize=None) const
Definition: TargetTransformInfo.cpp:1008
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize=None) const
Definition: TargetTransformInfo.cpp:999
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:682
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:671
llvm::TargetTransformInfo::supportsTailCalls
bool supportsTailCalls() const
If the target supports tail calls.
Definition: TargetTransformInfo.cpp:525
std
Definition: BitVector.h:851
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:543
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:99
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:152
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:391
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:260
llvm::TypeSize
Definition: TypeSize.h:435
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1039
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfo.cpp:645
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:547
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:222
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfo.cpp:1117
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::TargetTransformInfo::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
Definition: TargetTransformInfo.cpp:431
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1194
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:195
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:863
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:200
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:891
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:215
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2471
llvm::TargetTransformInfo::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:973
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:955
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:933
Dominators.h
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:690
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1034
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:361
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1101
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:334
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1079
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:50
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1057
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:990
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:529
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:929
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:710
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:835
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3230
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:759
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::cl::desc
Definition: CommandLine.h:405
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:478
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:501
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3086
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:908
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:985
llvm::TargetTransformInfo::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
Definition: TargetTransformInfo.cpp:660
llvm::TargetTransformInfo::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:488
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:482
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:102
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:701
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:573
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:8073
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:153
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:247
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:347
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:949
llvm::dyn_cast
decltype(auto) LLVM_NODISCARD dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:597
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid())
Definition: TargetTransformInfo.cpp:60