LLVM  13.0.0git
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33  cl::Hidden,
34  cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42  explicit NoTTIImpl(const DataLayout &DL)
43  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
48  // If the loop has irreducible control flow, it can not be converted to
49  // Hardware loop.
50  LoopBlocksRPO RPOT(L);
51  RPOT.perform(&LI);
52  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53  return false;
54  return true;
55 }
56 
58  const CallBase &CI,
59  unsigned ScalarizationCost)
60  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
61  ScalarizationCost(ScalarizationCost) {
62 
63  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
64  FMF = FPMO->getFastMathFlags();
65 
66  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
68  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
69 }
70 
72  ArrayRef<Type *> Tys,
73  FastMathFlags Flags,
74  const IntrinsicInst *I,
75  unsigned ScalarCost)
76  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
77  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
78 }
79 
82  : RetTy(Ty), IID(Id) {
83 
84  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
85  ParamTys.reserve(Arguments.size());
86  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
87  ParamTys.push_back(Arguments[Idx]->getType());
88 }
89 
92  ArrayRef<Type *> Tys,
93  FastMathFlags Flags,
94  const IntrinsicInst *I,
95  unsigned ScalarCost)
96  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
97  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
98  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
99 }
100 
102  LoopInfo &LI, DominatorTree &DT,
103  bool ForceNestedLoop,
104  bool ForceHardwareLoopPHI) {
105  SmallVector<BasicBlock *, 4> ExitingBlocks;
106  L->getExitingBlocks(ExitingBlocks);
107 
108  for (BasicBlock *BB : ExitingBlocks) {
109  // If we pass the updated counter back through a phi, we need to know
110  // which latch the updated value will be coming from.
111  if (!L->isLoopLatch(BB)) {
113  continue;
114  }
115 
116  const SCEV *EC = SE.getExitCount(L, BB);
117  if (isa<SCEVCouldNotCompute>(EC))
118  continue;
119  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
120  if (ConstEC->getValue()->isZero())
121  continue;
122  } else if (!SE.isLoopInvariant(EC, L))
123  continue;
124 
125  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
126  continue;
127 
128  // If this exiting block is contained in a nested loop, it is not eligible
129  // for insertion of the branch-and-decrement since the inner loop would
130  // end up messing up the value in the CTR.
131  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
132  continue;
133 
134  // We now have a loop-invariant count of loop iterations (which is not the
135  // constant zero) for which we know that this loop will not exit via this
136  // existing block.
137 
138  // We need to make sure that this block will run on every loop iteration.
139  // For this to be true, we must dominate all blocks with backedges. Such
140  // blocks are in-loop predecessors to the header block.
141  bool NotAlways = false;
142  for (BasicBlock *Pred : predecessors(L->getHeader())) {
143  if (!L->contains(Pred))
144  continue;
145 
146  if (!DT.dominates(BB, Pred)) {
147  NotAlways = true;
148  break;
149  }
150  }
151 
152  if (NotAlways)
153  continue;
154 
155  // Make sure this blocks ends with a conditional branch.
156  Instruction *TI = BB->getTerminator();
157  if (!TI)
158  continue;
159 
160  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
161  if (!BI->isConditional())
162  continue;
163 
164  ExitBranch = BI;
165  } else
166  continue;
167 
168  // Note that this block may not be the loop latch block, even if the loop
169  // has a latch block.
170  ExitBlock = BB;
171  TripCount = SE.getAddExpr(EC, SE.getOne(EC->getType()));
172 
173  if (!EC->getType()->isPointerTy() && EC->getType() != CountType)
175 
176  break;
177  }
178 
179  if (!ExitBlock)
180  return false;
181  return true;
182 }
183 
185  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
186 
188 
190  : TTIImpl(std::move(Arg.TTIImpl)) {}
191 
193  TTIImpl = std::move(RHS.TTIImpl);
194  return *this;
195 }
196 
198  return TTIImpl->getInliningThresholdMultiplier();
199 }
200 
201 unsigned
203  return TTIImpl->adjustInliningThreshold(CB);
204 }
205 
207  return TTIImpl->getInlinerVectorBonusPercent();
208 }
209 
210 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
213  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
214 }
215 
217  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
218  BlockFrequencyInfo *BFI) const {
219  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
220 }
221 
225  enum TargetCostKind CostKind) const {
226  InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
227  assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
228  "TTI should not produce negative costs!");
229  return Cost;
230 }
231 
233  return TTIImpl->getPredictableBranchThreshold();
234 }
235 
237  return TTIImpl->hasBranchDivergence();
238 }
239 
241  return TTIImpl->useGPUDivergenceAnalysis();
242 }
243 
245  return TTIImpl->isSourceOfDivergence(V);
246 }
247 
249  return TTIImpl->isAlwaysUniform(V);
250 }
251 
253  return TTIImpl->getFlatAddressSpace();
254 }
255 
257  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
258  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
259 }
260 
262  unsigned ToAS) const {
263  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
264 }
265 
267  return TTIImpl->getAssumedAddrSpace(V);
268 }
269 
271  IntrinsicInst *II, Value *OldV, Value *NewV) const {
272  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
273 }
274 
276  return TTIImpl->isLoweredToCall(F);
277 }
278 
280  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
281  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
282  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
283 }
284 
286  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
288  const LoopAccessInfo *LAI) const {
289  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
290 }
291 
293  return TTIImpl->emitGetActiveLaneMask();
294 }
295 
298  IntrinsicInst &II) const {
299  return TTIImpl->instCombineIntrinsic(IC, II);
300 }
301 
303  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
304  bool &KnownBitsComputed) const {
305  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
306  KnownBitsComputed);
307 }
308 
310  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
311  APInt &UndefElts2, APInt &UndefElts3,
312  std::function<void(Instruction *, unsigned, APInt, APInt &)>
313  SimplifyAndSetOp) const {
314  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
315  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
316  SimplifyAndSetOp);
317 }
318 
320  Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
321  return TTIImpl->getUnrollingPreferences(L, SE, UP);
322 }
323 
325  PeelingPreferences &PP) const {
326  return TTIImpl->getPeelingPreferences(L, SE, PP);
327 }
328 
330  return TTIImpl->isLegalAddImmediate(Imm);
331 }
332 
334  return TTIImpl->isLegalICmpImmediate(Imm);
335 }
336 
338  int64_t BaseOffset,
339  bool HasBaseReg, int64_t Scale,
340  unsigned AddrSpace,
341  Instruction *I) const {
342  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
343  Scale, AddrSpace, I);
344 }
345 
347  return TTIImpl->isLSRCostLess(C1, C2);
348 }
349 
351  return TTIImpl->isNumRegsMajorCostOfLSR();
352 }
353 
355  return TTIImpl->isProfitableLSRChainElement(I);
356 }
357 
359  return TTIImpl->canMacroFuseCmp();
360 }
361 
363  ScalarEvolution *SE, LoopInfo *LI,
365  TargetLibraryInfo *LibInfo) const {
366  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
367 }
368 
371  ScalarEvolution *SE) const {
372  return TTIImpl->getPreferredAddressingMode(L, SE);
373 }
374 
376  Align Alignment) const {
377  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
378 }
379 
381  Align Alignment) const {
382  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
383 }
384 
386  Align Alignment) const {
387  return TTIImpl->isLegalNTStore(DataType, Alignment);
388 }
389 
390 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
391  return TTIImpl->isLegalNTLoad(DataType, Alignment);
392 }
393 
395  Align Alignment) const {
396  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
397 }
398 
400  Align Alignment) const {
401  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
402 }
403 
405  return TTIImpl->isLegalMaskedCompressStore(DataType);
406 }
407 
409  return TTIImpl->isLegalMaskedExpandLoad(DataType);
410 }
411 
412 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
413  return TTIImpl->hasDivRemOp(DataType, IsSigned);
414 }
415 
417  unsigned AddrSpace) const {
418  return TTIImpl->hasVolatileVariant(I, AddrSpace);
419 }
420 
422  return TTIImpl->prefersVectorizedAddressing();
423 }
424 
426  int64_t BaseOffset,
427  bool HasBaseReg, int64_t Scale,
428  unsigned AddrSpace) const {
429  int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
430  Scale, AddrSpace);
431  assert(Cost >= 0 && "TTI should not produce negative costs!");
432  return Cost;
433 }
434 
436  return TTIImpl->LSRWithInstrQueries();
437 }
438 
440  return TTIImpl->isTruncateFree(Ty1, Ty2);
441 }
442 
444  return TTIImpl->isProfitableToHoist(I);
445 }
446 
447 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
448 
450  return TTIImpl->isTypeLegal(Ty);
451 }
452 
454  return TTIImpl->getRegUsageForType(Ty);
455 }
456 
458  return TTIImpl->shouldBuildLookupTables();
459 }
460 
462  Constant *C) const {
463  return TTIImpl->shouldBuildLookupTablesForConstant(C);
464 }
465 
467  return TTIImpl->shouldBuildRelLookupTables();
468 }
469 
471  return TTIImpl->useColdCCForColdCall(F);
472 }
473 
474 unsigned
476  const APInt &DemandedElts,
477  bool Insert, bool Extract) const {
478  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
479 }
480 
483  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
484 }
485 
487  return TTIImpl->supportsEfficientVectorElementLoadStore();
488 }
489 
491  bool LoopHasReductions) const {
492  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
493 }
494 
496 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
497  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
498 }
499 
501  return TTIImpl->enableInterleavedAccessVectorization();
502 }
503 
505  return TTIImpl->enableMaskedInterleavedAccessVectorization();
506 }
507 
509  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
510 }
511 
513  unsigned BitWidth,
514  unsigned AddressSpace,
515  Align Alignment,
516  bool *Fast) const {
517  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
518  AddressSpace, Alignment, Fast);
519 }
520 
522 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
523  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
524 }
525 
527  return TTIImpl->haveFastSqrt(Ty);
528 }
529 
531  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
532 }
533 
535  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
536  assert(Cost >= 0 && "TTI should not produce negative costs!");
537  return Cost;
538 }
539 
540 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
541  const APInt &Imm,
542  Type *Ty) const {
543  int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
544  assert(Cost >= 0 && "TTI should not produce negative costs!");
545  return Cost;
546 }
547 
550  int Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
551  assert(Cost >= 0 && "TTI should not produce negative costs!");
552  return Cost;
553 }
554 
555 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
556  const APInt &Imm, Type *Ty,
558  Instruction *Inst) const {
559  int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
560  assert(Cost >= 0 && "TTI should not produce negative costs!");
561  return Cost;
562 }
563 
564 int
566  const APInt &Imm, Type *Ty,
568  int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
569  assert(Cost >= 0 && "TTI should not produce negative costs!");
570  return Cost;
571 }
572 
573 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
574  return TTIImpl->getNumberOfRegisters(ClassID);
575 }
576 
578  Type *Ty) const {
579  return TTIImpl->getRegisterClassForType(Vector, Ty);
580 }
581 
582 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
583  return TTIImpl->getRegisterClassName(ClassID);
584 }
585 
588  return TTIImpl->getRegisterBitWidth(K);
589 }
590 
592  return TTIImpl->getMinVectorRegisterBitWidth();
593 }
594 
596  return TTIImpl->getMaxVScale();
597 }
598 
600  return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
601 }
602 
604  bool IsScalable) const {
605  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
606 }
607 
608 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
609  unsigned Opcode) const {
610  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
611 }
612 
614  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
615  return TTIImpl->shouldConsiderAddressTypePromotion(
616  I, AllowPromotionWithoutCommonHeader);
617 }
618 
620  return TTIImpl->getCacheLineSize();
621 }
622 
625  return TTIImpl->getCacheSize(Level);
626 }
627 
630  return TTIImpl->getCacheAssociativity(Level);
631 }
632 
634  return TTIImpl->getPrefetchDistance();
635 }
636 
638  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
639  unsigned NumPrefetches, bool HasCall) const {
640  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
641  NumPrefetches, HasCall);
642 }
643 
645  return TTIImpl->getMaxPrefetchIterationsAhead();
646 }
647 
649  return TTIImpl->enableWritePrefetching();
650 }
651 
652 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
653  return TTIImpl->getMaxInterleaveFactor(VF);
654 }
655 
658  OperandValueProperties &OpProps) {
659  OperandValueKind OpInfo = OK_AnyValue;
660  OpProps = OP_None;
661 
662  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
663  if (CI->getValue().isPowerOf2())
664  OpProps = OP_PowerOf2;
666  }
667 
668  // A broadcast shuffle creates a uniform value.
669  // TODO: Add support for non-zero index broadcasts.
670  // TODO: Add support for different source vector width.
671  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
672  if (ShuffleInst->isZeroEltSplat())
673  OpInfo = OK_UniformValue;
674 
675  const Value *Splat = getSplatValue(V);
676 
677  // Check for a splat of a constant or for a non uniform vector of constants
678  // and check if the constant(s) are all powers of two.
679  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
681  if (Splat) {
682  OpInfo = OK_UniformConstantValue;
683  if (auto *CI = dyn_cast<ConstantInt>(Splat))
684  if (CI->getValue().isPowerOf2())
685  OpProps = OP_PowerOf2;
686  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
687  OpProps = OP_PowerOf2;
688  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
689  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
690  if (CI->getValue().isPowerOf2())
691  continue;
692  OpProps = OP_None;
693  break;
694  }
695  }
696  }
697 
698  // Check for a splat of a uniform value. This is not loop aware, so return
699  // true only for the obviously uniform cases (argument, globalvalue)
700  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
701  OpInfo = OK_UniformValue;
702 
703  return OpInfo;
704 }
705 
707  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
708  OperandValueKind Opd1Info, OperandValueKind Opd2Info,
709  OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo,
710  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
711  InstructionCost Cost =
712  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
713  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
714  assert(Cost >= 0 && "TTI should not produce negative costs!");
715  return Cost;
716 }
717 
719  VectorType *Ty,
721  int Index,
722  VectorType *SubTp) const {
723  InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
724  assert(Cost >= 0 && "TTI should not produce negative costs!");
725  return Cost;
726 }
727 
730  if (!I)
731  return CastContextHint::None;
732 
733  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
734  unsigned GatScatOp) {
735  const Instruction *I = dyn_cast<Instruction>(V);
736  if (!I)
737  return CastContextHint::None;
738 
739  if (I->getOpcode() == LdStOp)
741 
742  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
743  if (II->getIntrinsicID() == MaskedOp)
745  if (II->getIntrinsicID() == GatScatOp)
747  }
748 
750  };
751 
752  switch (I->getOpcode()) {
753  case Instruction::ZExt:
754  case Instruction::SExt:
755  case Instruction::FPExt:
756  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
757  Intrinsic::masked_load, Intrinsic::masked_gather);
758  case Instruction::Trunc:
759  case Instruction::FPTrunc:
760  if (I->hasOneUse())
761  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
762  Intrinsic::masked_store,
763  Intrinsic::masked_scatter);
764  break;
765  default:
766  return CastContextHint::None;
767  }
768 
770 }
771 
773  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
774  TTI::TargetCostKind CostKind, const Instruction *I) const {
775  assert((I == nullptr || I->getOpcode() == Opcode) &&
776  "Opcode should reflect passed instruction.");
777  InstructionCost Cost =
778  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
779  assert(Cost >= 0 && "TTI should not produce negative costs!");
780  return Cost;
781 }
782 
784  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
785  InstructionCost Cost =
786  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
787  assert(Cost >= 0 && "TTI should not produce negative costs!");
788  return Cost;
789 }
790 
792  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
793  assert((I == nullptr || I->getOpcode() == Opcode) &&
794  "Opcode should reflect passed instruction.");
795  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
796  assert(Cost >= 0 && "TTI should not produce negative costs!");
797  return Cost;
798 }
799 
801  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
802  TTI::TargetCostKind CostKind, const Instruction *I) const {
803  assert((I == nullptr || I->getOpcode() == Opcode) &&
804  "Opcode should reflect passed instruction.");
805  InstructionCost Cost =
806  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
807  assert(Cost >= 0 && "TTI should not produce negative costs!");
808  return Cost;
809 }
810 
812  Type *Val,
813  unsigned Index) const {
814  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
815  assert(Cost >= 0 && "TTI should not produce negative costs!");
816  return Cost;
817 }
818 
820  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
821  TTI::TargetCostKind CostKind, const Instruction *I) const {
822  assert((I == nullptr || I->getOpcode() == Opcode) &&
823  "Opcode should reflect passed instruction.");
824  InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment,
826  assert(Cost >= 0 && "TTI should not produce negative costs!");
827  return Cost;
828 }
829 
831  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
833  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
835  assert(Cost >= 0 && "TTI should not produce negative costs!");
836  return Cost;
837 }
838 
840  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
841  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
842  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
843  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
844  assert(Cost >= 0 && "TTI should not produce negative costs!");
845  return Cost;
846 }
847 
849  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
850  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
851  bool UseMaskForCond, bool UseMaskForGaps) const {
852  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
853  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
854  UseMaskForCond, UseMaskForGaps);
855  assert(Cost >= 0 && "TTI should not produce negative costs!");
856  return Cost;
857 }
858 
862  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
863  assert(Cost >= 0 && "TTI should not produce negative costs!");
864  return Cost;
865 }
866 
869  ArrayRef<Type *> Tys,
871  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
872  assert(Cost >= 0 && "TTI should not produce negative costs!");
873  return Cost;
874 }
875 
877  return TTIImpl->getNumberOfParts(Tp);
878 }
879 
881  ScalarEvolution *SE,
882  const SCEV *Ptr) const {
883  int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
884  assert(Cost >= 0 && "TTI should not produce negative costs!");
885  return Cost;
886 }
887 
889  int Cost = TTIImpl->getMemcpyCost(I);
890  assert(Cost >= 0 && "TTI should not produce negative costs!");
891  return Cost;
892 }
893 
895  unsigned Opcode, VectorType *Ty, bool IsPairwiseForm,
897  InstructionCost Cost =
898  TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm, CostKind);
899  assert(Cost >= 0 && "TTI should not produce negative costs!");
900  return Cost;
901 }
902 
904  VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned,
906  InstructionCost Cost = TTIImpl->getMinMaxReductionCost(
907  Ty, CondTy, IsPairwiseForm, IsUnsigned, CostKind);
908  assert(Cost >= 0 && "TTI should not produce negative costs!");
909  return Cost;
910 }
911 
913  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
915  return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
916  CostKind);
917 }
918 
919 unsigned
921  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
922 }
923 
925  MemIntrinsicInfo &Info) const {
926  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
927 }
928 
930  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
931 }
932 
934  IntrinsicInst *Inst, Type *ExpectedType) const {
935  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
936 }
937 
939  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
940  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
941  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
942  DestAddrSpace, SrcAlign, DestAlign);
943 }
944 
947  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
948  unsigned SrcAlign, unsigned DestAlign) const {
949  TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
950  SrcAddrSpace, DestAddrSpace,
951  SrcAlign, DestAlign);
952 }
953 
955  const Function *Callee) const {
956  return TTIImpl->areInlineCompatible(Caller, Callee);
957 }
958 
960  const Function *Caller, const Function *Callee,
962  return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
963 }
964 
966  Type *Ty) const {
967  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
968 }
969 
971  Type *Ty) const {
972  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
973 }
974 
976  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
977 }
978 
980  return TTIImpl->isLegalToVectorizeLoad(LI);
981 }
982 
984  return TTIImpl->isLegalToVectorizeStore(SI);
985 }
986 
988  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
989  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
990  AddrSpace);
991 }
992 
994  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
995  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
996  AddrSpace);
997 }
998 
1000  RecurrenceDescriptor RdxDesc, ElementCount VF) const {
1001  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1002 }
1003 
1005  unsigned LoadSize,
1006  unsigned ChainSizeInBytes,
1007  VectorType *VecTy) const {
1008  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1009 }
1010 
1012  unsigned StoreSize,
1013  unsigned ChainSizeInBytes,
1014  VectorType *VecTy) const {
1015  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1016 }
1017 
1019  ReductionFlags Flags) const {
1020  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1021 }
1022 
1024  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1025  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1026 }
1027 
1029  return TTIImpl->shouldExpandReduction(II);
1030 }
1031 
1033  return TTIImpl->getGISelRematGlobalCost();
1034 }
1035 
1037  return TTIImpl->supportsScalableVectors();
1038 }
1039 
1041 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1042  return TTIImpl->getInstructionLatency(I);
1043 }
1044 
1046  unsigned Level) {
1047  // We don't need a shuffle if we just want to have element 0 in position 0 of
1048  // the vector.
1049  if (!SI && Level == 0 && IsLeft)
1050  return true;
1051  else if (!SI)
1052  return false;
1053 
1055  cast<FixedVectorType>(SI->getType())->getNumElements(), -1);
1056 
1057  // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
1058  // we look at the left or right side.
1059  for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
1060  Mask[i] = val;
1061 
1062  ArrayRef<int> ActualMask = SI->getShuffleMask();
1063  return Mask == ActualMask;
1064 }
1065 
1067  Value *L, *R;
1068  if (m_BinOp(m_Value(L), m_Value(R)).match(I))
1069  return TTI::ReductionData(TTI::RK_Arithmetic, I->getOpcode(), L, R);
1070  if (auto *SI = dyn_cast<SelectInst>(I)) {
1071  if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
1072  m_SMax(m_Value(L), m_Value(R)).match(SI) ||
1073  m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
1074  m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
1075  m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
1076  m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
1077  auto *CI = cast<CmpInst>(SI->getCondition());
1078  return TTI::ReductionData(TTI::RK_MinMax, CI->getOpcode(), L, R);
1079  }
1080  if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
1081  m_UMax(m_Value(L), m_Value(R)).match(SI)) {
1082  auto *CI = cast<CmpInst>(SI->getCondition());
1083  return TTI::ReductionData(TTI::RK_UnsignedMinMax, CI->getOpcode(), L, R);
1084  }
1085  }
1086  return llvm::None;
1087 }
1088 
1090  unsigned Level,
1091  unsigned NumLevels) {
1092  // Match one level of pairwise operations.
1093  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1094  // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1095  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1096  // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1097  // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1098  if (!I)
1099  return TTI::RK_None;
1100 
1101  assert(I->getType()->isVectorTy() && "Expecting a vector type");
1102 
1104  if (!RD)
1105  return TTI::RK_None;
1106 
1107  ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
1108  if (!LS && Level)
1109  return TTI::RK_None;
1110  ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
1111  if (!RS && Level)
1112  return TTI::RK_None;
1113 
1114  // On level 0 we can omit one shufflevector instruction.
1115  if (!Level && !RS && !LS)
1116  return TTI::RK_None;
1117 
1118  // Shuffle inputs must match.
1119  Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
1120  Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
1121  Value *NextLevelOp = nullptr;
1122  if (NextLevelOpR && NextLevelOpL) {
1123  // If we have two shuffles their operands must match.
1124  if (NextLevelOpL != NextLevelOpR)
1125  return TTI::RK_None;
1126 
1127  NextLevelOp = NextLevelOpL;
1128  } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
1129  // On the first level we can omit the shufflevector <0, undef,...>. So the
1130  // input to the other shufflevector <1, undef> must match with one of the
1131  // inputs to the current binary operation.
1132  // Example:
1133  // %NextLevelOpL = shufflevector %R, <1, undef ...>
1134  // %BinOp = fadd %NextLevelOpL, %R
1135  if (NextLevelOpL && NextLevelOpL != RD->RHS)
1136  return TTI::RK_None;
1137  else if (NextLevelOpR && NextLevelOpR != RD->LHS)
1138  return TTI::RK_None;
1139 
1140  NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
1141  } else
1142  return TTI::RK_None;
1143 
1144  // Check that the next levels binary operation exists and matches with the
1145  // current one.
1146  if (Level + 1 != NumLevels) {
1147  if (!isa<Instruction>(NextLevelOp))
1148  return TTI::RK_None;
1149  Optional<TTI::ReductionData> NextLevelRD =
1150  getReductionData(cast<Instruction>(NextLevelOp));
1151  if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
1152  return TTI::RK_None;
1153  }
1154 
1155  // Shuffle mask for pairwise operation must match.
1156  if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
1157  if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
1158  return TTI::RK_None;
1159  } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1160  if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1161  return TTI::RK_None;
1162  } else {
1163  return TTI::RK_None;
1164  }
1165 
1166  if (++Level == NumLevels)
1167  return RD->Kind;
1168 
1169  // Match next level.
1170  return matchPairwiseReductionAtLevel(dyn_cast<Instruction>(NextLevelOp), Level,
1171  NumLevels);
1172 }
1173 
1175  const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1176  if (!EnableReduxCost)
1177  return TTI::RK_None;
1178 
1179  // Need to extract the first element.
1180  ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1181  unsigned Idx = ~0u;
1182  if (CI)
1183  Idx = CI->getZExtValue();
1184  if (Idx != 0)
1185  return TTI::RK_None;
1186 
1187  auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1188  if (!RdxStart)
1189  return TTI::RK_None;
1191  if (!RD)
1192  return TTI::RK_None;
1193 
1194  auto *VecTy = cast<FixedVectorType>(RdxStart->getType());
1195  unsigned NumVecElems = VecTy->getNumElements();
1196  if (!isPowerOf2_32(NumVecElems))
1197  return TTI::RK_None;
1198 
1199  // We look for a sequence of shuffle,shuffle,add triples like the following
1200  // that builds a pairwise reduction tree.
1201  //
1202  // (X0, X1, X2, X3)
1203  // (X0 + X1, X2 + X3, undef, undef)
1204  // ((X0 + X1) + (X2 + X3), undef, undef, undef)
1205  //
1206  // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1207  // <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1208  // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1209  // <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1210  // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1211  // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1212  // <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1213  // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1214  // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1215  // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1216  // %r = extractelement <4 x float> %bin.rdx8, i32 0
1217  if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1218  TTI::RK_None)
1219  return TTI::RK_None;
1220 
1221  Opcode = RD->Opcode;
1222  Ty = VecTy;
1223 
1224  return RD->Kind;
1225 }
1226 
1227 static std::pair<Value *, ShuffleVectorInst *>
1229  ShuffleVectorInst *S = nullptr;
1230 
1231  if ((S = dyn_cast<ShuffleVectorInst>(L)))
1232  return std::make_pair(R, S);
1233 
1234  S = dyn_cast<ShuffleVectorInst>(R);
1235  return std::make_pair(L, S);
1236 }
1237 
1239  const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1240 
1241  if (!EnableReduxCost)
1242  return TTI::RK_None;
1243 
1244  // Need to extract the first element.
1245  ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1246  unsigned Idx = ~0u;
1247  if (CI)
1248  Idx = CI->getZExtValue();
1249  if (Idx != 0)
1250  return TTI::RK_None;
1251 
1252  auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1253  if (!RdxStart)
1254  return TTI::RK_None;
1256  if (!RD)
1257  return TTI::RK_None;
1258 
1259  auto *VecTy = cast<FixedVectorType>(ReduxRoot->getOperand(0)->getType());
1260  unsigned NumVecElems = VecTy->getNumElements();
1261  if (!isPowerOf2_32(NumVecElems))
1262  return TTI::RK_None;
1263 
1264  // We look for a sequence of shuffles and adds like the following matching one
1265  // fadd, shuffle vector pair at a time.
1266  //
1267  // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1268  // <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1269  // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1270  // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1271  // <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1272  // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1273  // %r = extractelement <4 x float> %bin.rdx8, i32 0
1274 
1275  unsigned MaskStart = 1;
1276  Instruction *RdxOp = RdxStart;
1277  SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1278  unsigned NumVecElemsRemain = NumVecElems;
1279  while (NumVecElemsRemain - 1) {
1280  // Check for the right reduction operation.
1281  if (!RdxOp)
1282  return TTI::RK_None;
1284  if (!RDLevel || !RDLevel->hasSameData(*RD))
1285  return TTI::RK_None;
1286 
1287  Value *NextRdxOp;
1288  ShuffleVectorInst *Shuffle;
1289  std::tie(NextRdxOp, Shuffle) =
1290  getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1291 
1292  // Check the current reduction operation and the shuffle use the same value.
1293  if (Shuffle == nullptr)
1294  return TTI::RK_None;
1295  if (Shuffle->getOperand(0) != NextRdxOp)
1296  return TTI::RK_None;
1297 
1298  // Check that shuffle masks matches.
1299  for (unsigned j = 0; j != MaskStart; ++j)
1300  ShuffleMask[j] = MaskStart + j;
1301  // Fill the rest of the mask with -1 for undef.
1302  std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1303 
1304  ArrayRef<int> Mask = Shuffle->getShuffleMask();
1305  if (ShuffleMask != Mask)
1306  return TTI::RK_None;
1307 
1308  RdxOp = dyn_cast<Instruction>(NextRdxOp);
1309  NumVecElemsRemain /= 2;
1310  MaskStart *= 2;
1311  }
1312 
1313  Opcode = RD->Opcode;
1314  Ty = VecTy;
1315  return RD->Kind;
1316 }
1317 
1319 TTI::matchVectorReduction(const ExtractElementInst *Root, unsigned &Opcode,
1320  VectorType *&Ty, bool &IsPairwise) {
1321  TTI::ReductionKind RdxKind = matchVectorSplittingReduction(Root, Opcode, Ty);
1322  if (RdxKind != TTI::ReductionKind::RK_None) {
1323  IsPairwise = false;
1324  return RdxKind;
1325  }
1326  IsPairwise = true;
1327  return matchPairwiseReduction(Root, Opcode, Ty);
1328 }
1329 
1331 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1333 
1334  switch (I->getOpcode()) {
1335  case Instruction::GetElementPtr:
1336  case Instruction::Ret:
1337  case Instruction::PHI:
1338  case Instruction::Br:
1339  case Instruction::Add:
1340  case Instruction::FAdd:
1341  case Instruction::Sub:
1342  case Instruction::FSub:
1343  case Instruction::Mul:
1344  case Instruction::FMul:
1345  case Instruction::UDiv:
1346  case Instruction::SDiv:
1347  case Instruction::FDiv:
1348  case Instruction::URem:
1349  case Instruction::SRem:
1350  case Instruction::FRem:
1351  case Instruction::Shl:
1352  case Instruction::LShr:
1353  case Instruction::AShr:
1354  case Instruction::And:
1355  case Instruction::Or:
1356  case Instruction::Xor:
1357  case Instruction::FNeg:
1358  case Instruction::Select:
1359  case Instruction::ICmp:
1360  case Instruction::FCmp:
1361  case Instruction::Store:
1362  case Instruction::Load:
1363  case Instruction::ZExt:
1364  case Instruction::SExt:
1365  case Instruction::FPToUI:
1366  case Instruction::FPToSI:
1367  case Instruction::FPExt:
1368  case Instruction::PtrToInt:
1369  case Instruction::IntToPtr:
1370  case Instruction::SIToFP:
1371  case Instruction::UIToFP:
1372  case Instruction::Trunc:
1373  case Instruction::FPTrunc:
1374  case Instruction::BitCast:
1375  case Instruction::AddrSpaceCast:
1376  case Instruction::ExtractElement:
1377  case Instruction::InsertElement:
1378  case Instruction::ExtractValue:
1379  case Instruction::ShuffleVector:
1380  case Instruction::Call:
1381  case Instruction::Switch:
1382  return getUserCost(I, CostKind);
1383  default:
1384  // We don't have any information on this instruction.
1385  return -1;
1386  }
1387 }
1388 
1390 
1391 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1392 
1394  std::function<Result(const Function &)> TTICallback)
1395  : TTICallback(std::move(TTICallback)) {}
1396 
1399  return TTICallback(F);
1400 }
1401 
1402 AnalysisKey TargetIRAnalysis::Key;
1403 
1404 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1405  return Result(F.getParent()->getDataLayout());
1406 }
1407 
1408 // Register the basic pass.
1410  "Target Transform Information", false, true)
1412 
1413 void TargetTransformInfoWrapperPass::anchor() {}
1414 
1416  : ImmutablePass(ID) {
1419 }
1420 
1422  TargetIRAnalysis TIRA)
1423  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1426 }
1427 
1429  FunctionAnalysisManager DummyFAM;
1430  TTI = TIRA.run(F, DummyFAM);
1431  return *TTI;
1432 }
1433 
1434 ImmutablePass *
1436  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1437 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:279
i
i
Definition: README.txt:29
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:938
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(RecurrenceDescriptor RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:999
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2265
llvm::predecessors
pred_range predecessors(BasicBlock *BB)
Definition: CFG.h:127
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1334
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:297
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:903
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:285
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:591
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, int Index=0, VectorType *SubTp=nullptr) const
Definition: TargetTransformInfo.cpp:718
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1285
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
IntrinsicInst.h
llvm::ShuffleVectorInst::getShuffleMask
static void getShuffleMask(const Constant *Mask, SmallVectorImpl< int > &Result)
Convert the input shuffle mask operand to a vector of integers.
Definition: Instructions.cpp:2047
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:582
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:897
llvm::TargetTransformInfo::getScalarizationOverhead
unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:475
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1415
llvm::ExtractElementInst
This instruction extracts a single (scalar) element from a VectorType value.
Definition: Instructions.h:1850
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:358
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:586
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:819
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1428
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:880
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:350
ErrorHandling.h
llvm::TargetTransformInfo::getIntImmCost
int getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:548
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
matchPairwiseShuffleMask
static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft, unsigned Level)
Definition: TargetTransformInfo.cpp:1045
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:860
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:266
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:333
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfo::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfo.cpp:959
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:98
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:3758
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:457
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:101
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:608
llvm::dyn_cast
LLVM_NODISCARD std::enable_if_t< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type > dyn_cast(const Y &Val)
Definition: Casting.h:334
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:470
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:192
llvm::PatternMatch::m_UnordFMin
MaxMin_match< FCmpInst, LHS, RHS, ufmin_pred_ty > m_UnordFMin(const LHS &L, const RHS &R)
Match an 'unordered' floating point minimum function.
Definition: PatternMatch.h:1904
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:96
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:390
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:385
llvm::Optional
Definition: APInt.h:34
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:791
llvm::PatternMatch::m_BinOp
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:84
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:903
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:232
Operator.h
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:206
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:239
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1306
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:160
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:500
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1018
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:965
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
llvm::TargetTransformInfo::getIntImmCodeSizeCost
int getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:540
F
#define F(x, y, z)
Definition: MD5.cpp:56
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:103
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of performing a vector reduction.
Definition: TargetTransformInfo.cpp:894
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:115
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:399
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
Instruction.h
CommandLine.h
llvm::PatternMatch::m_UMax
MaxMin_match< ICmpInst, LHS, RHS, umax_pred_ty > m_UMax(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1826
llvm::PatternMatch::m_OrdFMin
MaxMin_match< FCmpInst, LHS, RHS, ofmin_pred_ty > m_OrdFMin(const LHS &L, const RHS &R)
Match an 'ordered' floating point minimum function.
Definition: PatternMatch.h:1873
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1032
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:954
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1251
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:449
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:603
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:354
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:729
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:933
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:979
llvm::TargetTransformInfo::ReductionKind
ReductionKind
Kind of the reduction data.
Definition: TargetTransformInfo.h:861
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::ScalarEvolution::getOne
const SCEV * getOne(Type *Ty)
Return a SCEV for the constant 1 of a specific type.
Definition: ScalarEvolution.h:596
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:522
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:903
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:845
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::TargetTransformInfo::getGEPCost
int getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:210
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:370
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1079
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:240
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:128
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1396
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:236
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:876
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(bool OptSize) const
Definition: TargetTransformInfo.cpp:599
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1036
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:965
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:596
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:408
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:127
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::RK_Arithmetic
@ RK_Arithmetic
Not a reduction.
Definition: TargetTransformInfo.h:863
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
Definition: TargetTransformInfo.cpp:346
llvm::PatternMatch::m_UMin
MaxMin_match< ICmpInst, LHS, RHS, umin_pred_ty > m_UMin(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1832
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:380
llvm::TargetTransformInfo::getIntImmCostInst
int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:555
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:244
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:309
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:633
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:105
llvm::TargetTransformInfo::matchVectorReduction
static ReductionKind matchVectorReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty, bool &IsPairwise)
Definition: TargetTransformInfo.cpp:1319
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:834
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:319
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::PatternMatch::m_UnordFMax
MaxMin_match< FCmpInst, LHS, RHS, ufmax_pred_ty > m_UnordFMax(const LHS &L, const RHS &R)
Match an 'unordered' floating point maximum function.
Definition: PatternMatch.h:1889
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:530
PatternMatch.h
llvm::TargetTransformInfo::getScalingFactorCost
int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:425
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:154
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::None
const NoneType None
Definition: None.h:23
LoopIterator.h
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:116
llvm::TargetTransformInfo::RK_UnsignedMinMax
@ RK_UnsignedMinMax
Min/max reduction data.
Definition: TargetTransformInfo.h:865
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:416
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:404
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:526
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1435
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:252
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
Definition: TargetTransformInfo.cpp:1389
llvm::cl::opt< bool >
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:461
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:409
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:256
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:394
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2321
llvm::TargetTransformInfo::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported.
Definition: TargetTransformInfo.cpp:292
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1023
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:848
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:898
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2267
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:652
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:577
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:964
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:903
llvm::TargetTransformInfo::ReductionData::hasSameData
bool hasSameData(ReductionData &RD) const
Definition: TargetTransformInfo.h:879
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:613
matchPairwiseReductionAtLevel
static TTI::ReductionKind matchPairwiseReductionAtLevel(Instruction *I, unsigned Level, unsigned NumLevels)
Definition: TargetTransformInfo.cpp:1089
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:519
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:270
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:839
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1563
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:435
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:987
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:329
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::PatternMatch::m_SMin
MaxMin_match< ICmpInst, LHS, RHS, smin_pred_ty > m_SMin(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1820
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:512
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:275
llvm::TargetTransformInfo::getIntImmCostIntrin
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:565
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:772
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
unsigned getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:920
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:895
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:945
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1312
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:362
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:439
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:421
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:750
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:486
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:496
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::LoopInfo
Definition: LoopInfo.h:1080
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
DataLayout.h
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
getShuffleAndOtherOprd
static std::pair< Value *, ShuffleVectorInst * > getShuffleAndOtherOprd(Value *L, Value *R)
Definition: TargetTransformInfo.cpp:1228
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:375
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::TargetTransformInfo::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:223
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy=nullptr, CmpInst::Predicate VecPred=CmpInst::BAD_ICMP_PREDICATE, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:800
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:412
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:302
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:624
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:573
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:644
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:419
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:896
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1004
llvm::PatternMatch::m_SMax
MaxMin_match< ICmpInst, LHS, RHS, smax_pred_ty > m_SMax(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1814
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::PatternMatch::m_OrdFMax
MaxMin_match< FCmpInst, LHS, RHS, ofmax_pred_ty > m_OrdFMax(const LHS &L, const RHS &R)
Match an 'ordered' floating point maximum function.
Definition: PatternMatch.h:1858
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:983
llvm::TargetTransformInfo::matchVectorSplittingReduction
static ReductionKind matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty)
Definition: TargetTransformInfo.cpp:1238
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:12477
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1391
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:140
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:595
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
unsigned getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:481
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
j
return j(j<< 16)
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:629
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:619
std
Definition: BitVector.h:838
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:504
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfo::ReductionData::Kind
ReductionKind Kind
Definition: TargetTransformInfo.h:878
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:97
llvm::TargetTransformInfo::ReductionData::Opcode
unsigned Opcode
Definition: TargetTransformInfo.h:875
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:261
llvm::TypeSize
Definition: TypeSize.h:417
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:245
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:975
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:508
llvm::TargetTransformInfo::ReductionData::RHS
Value * RHS
Definition: TargetTransformInfo.h:877
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::TargetTransformInfo::ReductionData::LHS
Value * LHS
Definition: TargetTransformInfo.h:876
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:165
llvm::HardwareLoopInfo::TripCount
const SCEV * TripCount
Definition: TargetTransformInfo.h:99
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1397
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:197
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:811
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:202
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:830
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:93
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:216
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2251
llvm::TargetTransformInfo::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:912
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:66
llvm::ShuffleVectorInst
This instruction constructs a fixed permutation of two input vectors.
Definition: Instructions.h:1986
getReductionData
static Optional< TTI::ReductionData > getReductionData(Instruction *I)
Definition: TargetTransformInfo.cpp:1066
llvm::ScalarEvolution::getZeroExtendExpr
const SCEV * getZeroExtendExpr(const SCEV *Op, Type *Ty, unsigned Depth=0)
Definition: ScalarEvolution.cpp:1553
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:924
Dominators.h
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, unsigned ScalarizationCost=std::numeric_limits< unsigned >::max())
Definition: TargetTransformInfo.cpp:57
llvm::TargetTransformInfo::RK_MinMax
@ RK_MinMax
Binary reduction data.
Definition: TargetTransformInfo.h:864
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:71
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:637
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:970
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:350
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1028
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:324
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1011
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:47
llvm::TargetTransformInfo::getMemcpyCost
int getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:888
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:993
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:68
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:929
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1164
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:490
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetTransformInfo::RK_None
@ RK_None
Definition: TargetTransformInfo.h:862
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:43
llvm::ScalarEvolution::getAddExpr
const SCEV * getAddExpr(SmallVectorImpl< const SCEV * > &Ops, SCEV::NoWrapFlags Flags=SCEV::FlagAnyWrap, unsigned Depth=0)
Get a canonical add expression, or something simpler if possible.
Definition: ScalarEvolution.cpp:2300
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:868
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:657
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:783
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3149
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:706
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::cl::desc
Definition: CommandLine.h:411
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:443
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:466
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3005
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
Definition: TargetTransformInfo.cpp:187
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:899
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:924
llvm::TargetTransformInfo::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:453
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:447
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:100
llvm::TargetTransformInfo::ReductionData
Contains opcode + LHS/RHS parts of the reduction operations.
Definition: TargetTransformInfo.h:869
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:648
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:534
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:6986
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:248
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:337
llvm::TargetTransformInfo::matchPairwiseReduction
static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty)
Definition: TargetTransformInfo.cpp:1174
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:102
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38