30#define DEBUG_TYPE "tti"
34 cl::desc(
"Recognize reduction patterns."));
38 cl::desc(
"Use this to override the target cache line size when "
39 "specified by the user."));
43 cl::desc(
"Use this to override the target's minimum page size."));
48 "Use this to override the target's predictable branch threshold (%)."));
62 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
79 ScalarizationCost(ScalarizationCost), LibInfo(LibInfo) {
82 FMF = FPMO->getFastMathFlags();
87 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
95 : II(
I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96 ParamTys.insert(ParamTys.begin(), Tys.
begin(), Tys.
end());
101 : RetTy(Ty), IID(Id) {
103 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
104 ParamTys.reserve(Arguments.size());
113 : II(
I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
115 ParamTys.insert(ParamTys.begin(), Tys.
begin(), Tys.
end());
116 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
132 L->getExitingBlocks(ExitingBlocks);
137 if (!
L->isLoopLatch(BB)) {
146 if (ConstEC->getValue()->isZero())
167 bool NotAlways =
false;
169 if (!
L->contains(Pred))
187 if (!BI->isConditional())
207 : TTIImpl(
std::make_unique<NoTTIImpl>(
DL)) {}
212 : TTIImpl(
std::
move(Arg.TTIImpl)) {}
215 TTIImpl = std::move(RHS.TTIImpl);
220 return TTIImpl->getInliningThresholdMultiplier();
225 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
231 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
235 return TTIImpl->getInliningLastCallToStaticBonus();
240 return TTIImpl->adjustInliningThreshold(CB);
245 return TTIImpl->getCallerAllocaCost(CB, AI);
249 return TTIImpl->getInlinerVectorBonusPercent();
255 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, AccessType,
CostKind);
263 "If pointers have same base address it has to be provided.");
264 return TTIImpl->getPointersChainCost(Ptrs,
Base, Info, AccessTy,
CostKind);
270 return TTIImpl->getEstimatedNumberOfCaseClusters(
SI, JTSize, PSI, BFI);
279 "TTI should not produce negative costs!");
286 : TTIImpl->getPredictableBranchThreshold();
290 return TTIImpl->getBranchMispredictPenalty();
294 return TTIImpl->hasBranchDivergence(
F);
301 if (
Call->hasFnAttr(Attribute::NoDivergenceSource))
304 return TTIImpl->getInstructionUniformity(V);
308 unsigned ToAS)
const {
309 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
313 unsigned ToAS)
const {
314 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
318 return TTIImpl->getFlatAddressSpace();
323 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
327 unsigned ToAS)
const {
328 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
331std::pair<KnownBits, KnownBits>
333 const Value &PtrOp)
const {
334 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
338 unsigned FromAS,
unsigned ToAS,
const KnownBits &FromPtrBits)
const {
339 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
344 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
348 return TTIImpl->getAssumedAddrSpace(V);
352 return TTIImpl->isSingleThreaded();
355std::pair<const Value *, unsigned>
357 return TTIImpl->getPredicatedAddrSpace(V);
362 return TTIImpl->rewriteIntrinsicWithAddressSpace(
II, OldV, NewV);
366 return TTIImpl->isLoweredToCall(
F);
372 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
376 return TTIImpl->getEpilogueVectorizationMinVF();
381 return TTIImpl->preferPredicateOverEpilogue(TFI);
385 bool IVUpdateMayOverflow)
const {
386 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
389std::optional<Instruction *>
392 return TTIImpl->instCombineIntrinsic(IC,
II);
397 bool &KnownBitsComputed)
const {
398 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC,
II, DemandedMask, Known,
406 SimplifyAndSetOp)
const {
407 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
408 IC,
II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
415 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
420 return TTIImpl->getPeelingPreferences(L, SE, PP);
424 return TTIImpl->isLegalAddImmediate(Imm);
428 return TTIImpl->isLegalAddScalableImmediate(Imm);
432 return TTIImpl->isLegalICmpImmediate(Imm);
437 bool HasBaseReg, int64_t Scale,
440 int64_t ScalableOffset)
const {
441 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
442 Scale, AddrSpace,
I, ScalableOffset);
447 return TTIImpl->isLSRCostLess(C1, C2);
451 return TTIImpl->isNumRegsMajorCostOfLSR();
455 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
459 return TTIImpl->isProfitableLSRChainElement(
I);
463 return TTIImpl->canMacroFuseCmp();
470 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
476 return TTIImpl->getPreferredAddressingMode(L, SE);
482 return TTIImpl->isLegalMaskedStore(DataType, Alignment,
AddressSpace,
489 return TTIImpl->isLegalMaskedLoad(DataType, Alignment,
AddressSpace,
494 Align Alignment)
const {
495 return TTIImpl->isLegalNTStore(DataType, Alignment);
499 return TTIImpl->isLegalNTLoad(DataType, Alignment);
504 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
508 Align Alignment)
const {
509 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
513 VectorType *VecTy,
unsigned Opcode0,
unsigned Opcode1,
515 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
519 Align Alignment)
const {
520 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
524 Align Alignment)
const {
525 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
529 Align Alignment)
const {
530 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
534 Align Alignment)
const {
535 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
539 Align Alignment)
const {
540 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
544 Align Alignment)
const {
545 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
550 unsigned AddrSpace)
const {
551 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
556 Type *DataType)
const {
557 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
561 return TTIImpl->enableOrderedReductions();
565 return TTIImpl->hasDivRemOp(DataType, IsSigned);
569 unsigned AddrSpace)
const {
570 return TTIImpl->hasVolatileVariant(
I, AddrSpace);
574 return TTIImpl->prefersVectorizedAddressing();
579 int64_t Scale,
unsigned AddrSpace)
const {
581 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
582 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
587 return TTIImpl->LSRWithInstrQueries();
591 return TTIImpl->isTruncateFree(Ty1, Ty2);
595 return TTIImpl->isProfitableToHoist(
I);
601 return TTIImpl->isTypeLegal(Ty);
605 return TTIImpl->getRegUsageForType(Ty);
609 return TTIImpl->shouldBuildLookupTables();
614 return TTIImpl->shouldBuildLookupTablesForConstant(
C);
618 return TTIImpl->shouldBuildRelLookupTables();
622 return TTIImpl->useColdCCForColdCall(
F);
626 return TTIImpl->useFastCCForInternalCall(
F);
631 return TTIImpl->isTargetIntrinsicTriviallyScalarizable(
ID);
636 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(
ID, ScalarOpdIdx);
641 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(
ID, OpdIdx);
646 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(
ID, RetIdx);
657 I->getOperand(1)->hasOneUse())
672 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
679 return TTIImpl->getOperandsScalarizationOverhead(Tys,
CostKind, VIC);
683 return TTIImpl->supportsEfficientVectorElementLoadStore();
687 return TTIImpl->supportsTailCalls();
691 return TTIImpl->supportsTailCallFor(CB);
695 bool LoopHasReductions)
const {
696 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
701 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
705 return TTIImpl->enableSelectOptimize();
710 return TTIImpl->shouldTreatInstructionLikeSelect(
I);
714 return TTIImpl->enableInterleavedAccessVectorization();
718 return TTIImpl->enableMaskedInterleavedAccessVectorization();
722 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
730 unsigned *
Fast)
const {
731 return TTIImpl->allowsMisalignedMemoryAccesses(Context,
BitWidth,
737 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
741 return TTIImpl->haveFastSqrt(Ty);
746 return TTIImpl->isExpensiveToSpeculativelyExecute(
I);
750 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
755 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
764 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
772 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
777 unsigned Opcode,
unsigned Idx,
const APInt &Imm,
Type *Ty,
780 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty,
CostKind, Inst);
781 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
790 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty,
CostKind);
791 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
797 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
801 return TTIImpl->getNumberOfRegisters(ClassID);
805 bool IsStore)
const {
806 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
811 return TTIImpl->getRegisterClassForType(
Vector, Ty);
815 return TTIImpl->getRegisterClassName(ClassID);
820 return TTIImpl->getRegisterBitWidth(K);
824 return TTIImpl->getMinVectorRegisterBitWidth();
828 return TTIImpl->getMaxVScale();
832 return TTIImpl->getVScaleForTuning();
836 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
841 return TTIImpl->shouldMaximizeVectorBandwidth(K);
845 bool IsScalable)
const {
846 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
850 unsigned Opcode)
const {
851 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
855 Type *ScalarValTy)
const {
856 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
860 const Instruction &
I,
bool &AllowPromotionWithoutCommonHeader)
const {
861 return TTIImpl->shouldConsiderAddressTypePromotion(
862 I, AllowPromotionWithoutCommonHeader);
867 : TTIImpl->getCacheLineSize();
870std::optional<unsigned>
872 return TTIImpl->getCacheSize(Level);
875std::optional<unsigned>
877 return TTIImpl->getCacheAssociativity(Level);
882 : TTIImpl->getMinPageSize();
886 return TTIImpl->getPrefetchDistance();
890 unsigned NumMemAccesses,
unsigned NumStridedMemAccesses,
891 unsigned NumPrefetches,
bool HasCall)
const {
892 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
893 NumPrefetches, HasCall);
897 return TTIImpl->getMaxPrefetchIterationsAhead();
901 return TTIImpl->enableWritePrefetching();
905 return TTIImpl->shouldPrefetchAddressSpace(AS);
909 unsigned Opcode,
Type *InputTypeA,
Type *InputTypeB,
Type *AccumType,
913 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
914 AccumType, VF, OpAExtend, OpBExtend,
919 return TTIImpl->getMaxInterleaveFactor(VF);
933 if (CI->getValue().isPowerOf2())
935 else if (CI->getValue().isNegatedPowerOf2())
945 if (ShuffleInst->isZeroEltSplat())
960 if (CI->getValue().isPowerOf2())
962 else if (CI->getValue().isNegatedPowerOf2())
968 bool AllPow2 =
true, AllNegPow2 =
true;
969 for (
uint64_t I = 0, E = CDS->getNumElements();
I != E; ++
I) {
971 AllPow2 &= CI->getValue().isPowerOf2();
972 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
973 if (AllPow2 || AllNegPow2)
976 AllPow2 = AllNegPow2 =
false;
985 return {OpInfo, OpProps};
1005 if (TLibInfo && Opcode == Instruction::FRem) {
1009 TLibInfo->
getLibFunc(Instruction::FRem, Ty->getScalarType(), Func) &&
1016 Opcode, Ty,
CostKind, Op1Info, Op2Info, Args, CxtI);
1017 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1022 VectorType *VecTy,
unsigned Opcode0,
unsigned Opcode1,
1025 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask,
CostKind);
1026 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1036 "Expected the Mask to match the return size if given");
1038 "Expected the same scalar types");
1040 Kind, DstTy, SrcTy, Mask,
CostKind, Index, SubTp, Args, CxtI);
1041 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1056 case Instruction::CastOps::ZExt:
1058 case Instruction::CastOps::SExt:
1060 case Instruction::CastOps::FPExt:
1073 auto getLoadStoreKind = [](
const Value *V,
unsigned LdStOp,
unsigned MaskedOp,
1074 unsigned GatScatOp) {
1079 if (
I->getOpcode() == LdStOp)
1083 if (
II->getIntrinsicID() == MaskedOp)
1085 if (
II->getIntrinsicID() == GatScatOp)
1092 switch (
I->getOpcode()) {
1093 case Instruction::ZExt:
1094 case Instruction::SExt:
1095 case Instruction::FPExt:
1096 return getLoadStoreKind(
I->getOperand(0), Instruction::Load,
1097 Intrinsic::masked_load, Intrinsic::masked_gather);
1098 case Instruction::Trunc:
1099 case Instruction::FPTrunc:
1101 return getLoadStoreKind(*
I->user_begin(), Instruction::Store,
1102 Intrinsic::masked_store,
1103 Intrinsic::masked_scatter);
1115 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
1116 "Opcode should reflect passed instruction.");
1118 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH,
CostKind,
I);
1119 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1127 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index,
CostKind);
1128 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1134 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
1135 "Opcode should reflect passed instruction.");
1137 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1145 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
1146 "Opcode should reflect passed instruction.");
1148 Opcode, ValTy, CondTy, VecPred,
CostKind, Op1Info, Op2Info,
I);
1149 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1156 assert((Opcode == Instruction::InsertElement ||
1157 Opcode == Instruction::ExtractElement) &&
1158 "Expecting Opcode to be insertelement/extractelement.");
1160 TTIImpl->getVectorInstrCost(Opcode, Val,
CostKind, Index, Op0, Op1, VIC);
1161 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1167 Value *Scalar,
ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1169 assert((Opcode == Instruction::InsertElement ||
1170 Opcode == Instruction::ExtractElement) &&
1171 "Expecting Opcode to be insertelement/extractelement.");
1173 Opcode, Val,
CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1174 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1185 TTIImpl->getVectorInstrCost(
I, Val,
CostKind, Index, VIC);
1186 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1192 unsigned Index)
const {
1194 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val,
CostKind, Index);
1195 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1201 assert((Opcode == Instruction::InsertValue ||
1202 Opcode == Instruction::ExtractValue) &&
1203 "Expecting Opcode to be insertvalue/extractvalue.");
1205 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1210 Type *EltTy,
int ReplicationFactor,
int VF,
const APInt &DemandedDstElts,
1213 EltTy, ReplicationFactor, VF, DemandedDstElts,
CostKind);
1214 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1222 assert((
I ==
nullptr ||
I->getOpcode() == Opcode) &&
1223 "Opcode should reflect passed instruction.");
1226 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1233 bool UseMaskForCond,
bool UseMaskForGaps)
const {
1236 UseMaskForCond, UseMaskForGaps);
1237 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1245 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1253 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1262 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1267 return TTIImpl->getNumberOfParts(Tp);
1274 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr,
CostKind);
1275 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1281 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1286 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1290 unsigned Opcode,
VectorType *Ty, std::optional<FastMathFlags> FMF,
1293 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF,
CostKind);
1294 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1302 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF,
CostKind);
1303 assert(
Cost >= 0 &&
"TTI should not produce negative costs!");
1310 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1315 bool IsUnsigned,
unsigned RedOpcode,
Type *ResTy,
VectorType *Ty,
1317 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1323 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1328 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1332 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1337 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1343 unsigned DestAddrSpace,
Align SrcAlign,
Align DestAlign,
1344 std::optional<uint32_t> AtomicElementSize)
const {
1345 return TTIImpl->getMemcpyLoopLoweringType(Context,
Length, SrcAddrSpace,
1346 DestAddrSpace, SrcAlign, DestAlign,
1352 unsigned RemainingBytes,
unsigned SrcAddrSpace,
unsigned DestAddrSpace,
1354 std::optional<uint32_t> AtomicCpySize)
const {
1355 TTIImpl->getMemcpyLoopResidualLoweringType(
1356 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1357 DestAlign, AtomicCpySize);
1362 return TTIImpl->areInlineCompatible(Caller, Callee);
1368 unsigned DefaultCallPenalty)
const {
1369 return TTIImpl->getInlineCallPenalty(
F,
Call, DefaultCallPenalty);
1375 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1380 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1385 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1389 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1393 return TTIImpl->isLegalToVectorizeLoad(LI);
1397 return TTIImpl->isLegalToVectorizeStore(
SI);
1401 unsigned ChainSizeInBytes,
Align Alignment,
unsigned AddrSpace)
const {
1402 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1407 unsigned ChainSizeInBytes,
Align Alignment,
unsigned AddrSpace)
const {
1408 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1414 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1418 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1423 unsigned ChainSizeInBytes,
1425 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1430 unsigned ChainSizeInBytes,
1432 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1436 bool IsEpilogue)
const {
1437 return TTIImpl->preferFixedOverScalableIfEqualCost(IsEpilogue);
1442 return TTIImpl->preferInLoopReduction(Kind, Ty);
1446 return TTIImpl->preferAlternateOpcodeVectorization();
1450 return TTIImpl->preferPredicatedReductionSelect();
1454 return TTIImpl->preferEpilogueVectorization();
1458 return TTIImpl->shouldConsiderVectorizationRegPressure();
1463 return TTIImpl->getVPLegalizationStrategy(VPI);
1467 return TTIImpl->hasArmWideBranch(Thumb);
1471 return TTIImpl->getFeatureMask(
F);
1475 return TTIImpl->getPriorityMask(
F);
1479 return TTIImpl->isMultiversionedFunction(
F);
1483 return TTIImpl->getMaxNumArgs();
1487 return TTIImpl->shouldExpandReduction(
II);
1493 return TTIImpl->getPreferredExpandedReductionShuffle(
II);
1497 return TTIImpl->getGISelRematGlobalCost();
1501 return TTIImpl->getMinTripCountTailFoldingThreshold();
1505 return TTIImpl->supportsScalableVectors();
1509 return TTIImpl->enableScalableVectorization();
1513 return TTIImpl->hasActiveVectorLength();
1518 return TTIImpl->isProfitableToSinkOperands(
I, OpsToSink);
1522 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1528 return TTIImpl->getNumBytesToPadGlobalArray(
Size,
ArrayType);
1534 return TTIImpl->collectKernelLaunchBounds(
F, LB);
1538 return TTIImpl->allowVectorElementIndexingUsingGEP();
1547 : TTICallback(
std::
move(TTICallback)) {}
1551 assert(!
F.isIntrinsic() &&
"Should not request TTI for intrinsics");
1552 return TTICallback(
F);
1558 return Result(
F.getDataLayout());
1563 "Target Transform Information",
false,
true)
1577 TTI = TIRA.run(
F, DummyFAM);
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static cl::opt< OutputCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(OutputCostKind::RecipThroughput), cl::values(clEnumValN(OutputCostKind::RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(OutputCostKind::Latency, "latency", "Instruction latency"), clEnumValN(OutputCostKind::CodeSize, "code-size", "Code size"), clEnumValN(OutputCostKind::SizeAndLatency, "size-latency", "Code size and latency"), clEnumValN(OutputCostKind::All, "all", "Print all cost kinds")))
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
uint64_t IntrinsicInst * II
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")
static SymbolRef::Type getType(const Symbol *Sym)
Class for arbitrary precision integers.
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Class to represent array types.
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Class to represent function types.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
ImmutablePass class - This class is used to provide information that does not need to be run.
The core instruction combiner logic.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false, TargetLibraryInfo const *LibInfo=nullptr)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Information for memory intrinsic cost model.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
An instruction for storing to memory.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM_ABI bool isScalableTy(SmallPtrSetImpl< const Type * > &Visited) const
Return true if this is a type whose size is a known multiple of vscale.
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
@ AlwaysUniform
The result values are always uniform.
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
A special type used by analysis passes to provide an address that identifies that particular analysis...
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
HardwareLoopInfo()=delete
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.