LLVM  14.0.0git
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33  cl::Hidden,
34  cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42  explicit NoTTIImpl(const DataLayout &DL)
43  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
48  // If the loop has irreducible control flow, it can not be converted to
49  // Hardware loop.
50  LoopBlocksRPO RPOT(L);
51  RPOT.perform(&LI);
52  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53  return false;
54  return true;
55 }
56 
58  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost)
59  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
60  ScalarizationCost(ScalarizationCost) {
61 
62  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
63  FMF = FPMO->getFastMathFlags();
64 
65  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
67  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
68 }
69 
71  ArrayRef<Type *> Tys,
72  FastMathFlags Flags,
73  const IntrinsicInst *I,
74  InstructionCost ScalarCost)
75  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
76  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
77 }
78 
81  : RetTy(Ty), IID(Id) {
82 
83  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
84  ParamTys.reserve(Arguments.size());
85  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
86  ParamTys.push_back(Arguments[Idx]->getType());
87 }
88 
91  ArrayRef<Type *> Tys,
92  FastMathFlags Flags,
93  const IntrinsicInst *I,
94  InstructionCost ScalarCost)
95  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
98 }
99 
101  LoopInfo &LI, DominatorTree &DT,
102  bool ForceNestedLoop,
103  bool ForceHardwareLoopPHI) {
104  SmallVector<BasicBlock *, 4> ExitingBlocks;
105  L->getExitingBlocks(ExitingBlocks);
106 
107  for (BasicBlock *BB : ExitingBlocks) {
108  // If we pass the updated counter back through a phi, we need to know
109  // which latch the updated value will be coming from.
110  if (!L->isLoopLatch(BB)) {
112  continue;
113  }
114 
115  const SCEV *EC = SE.getExitCount(L, BB);
116  if (isa<SCEVCouldNotCompute>(EC))
117  continue;
118  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
119  if (ConstEC->getValue()->isZero())
120  continue;
121  } else if (!SE.isLoopInvariant(EC, L))
122  continue;
123 
124  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
125  continue;
126 
127  // If this exiting block is contained in a nested loop, it is not eligible
128  // for insertion of the branch-and-decrement since the inner loop would
129  // end up messing up the value in the CTR.
130  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
131  continue;
132 
133  // We now have a loop-invariant count of loop iterations (which is not the
134  // constant zero) for which we know that this loop will not exit via this
135  // existing block.
136 
137  // We need to make sure that this block will run on every loop iteration.
138  // For this to be true, we must dominate all blocks with backedges. Such
139  // blocks are in-loop predecessors to the header block.
140  bool NotAlways = false;
141  for (BasicBlock *Pred : predecessors(L->getHeader())) {
142  if (!L->contains(Pred))
143  continue;
144 
145  if (!DT.dominates(BB, Pred)) {
146  NotAlways = true;
147  break;
148  }
149  }
150 
151  if (NotAlways)
152  continue;
153 
154  // Make sure this blocks ends with a conditional branch.
155  Instruction *TI = BB->getTerminator();
156  if (!TI)
157  continue;
158 
159  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
160  if (!BI->isConditional())
161  continue;
162 
163  ExitBranch = BI;
164  } else
165  continue;
166 
167  // Note that this block may not be the loop latch block, even if the loop
168  // has a latch block.
169  ExitBlock = BB;
170  ExitCount = EC;
171  break;
172  }
173 
174  if (!ExitBlock)
175  return false;
176  return true;
177 }
178 
180  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
181 
183 
185  : TTIImpl(std::move(Arg.TTIImpl)) {}
186 
188  TTIImpl = std::move(RHS.TTIImpl);
189  return *this;
190 }
191 
193  return TTIImpl->getInliningThresholdMultiplier();
194 }
195 
196 unsigned
198  return TTIImpl->adjustInliningThreshold(CB);
199 }
200 
202  return TTIImpl->getInlinerVectorBonusPercent();
203 }
204 
206 TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
209  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
210 }
211 
213  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
214  BlockFrequencyInfo *BFI) const {
215  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
216 }
217 
221  enum TargetCostKind CostKind) const {
222  InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
223  assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
224  "TTI should not produce negative costs!");
225  return Cost;
226 }
227 
229  return TTIImpl->getPredictableBranchThreshold();
230 }
231 
233  return TTIImpl->hasBranchDivergence();
234 }
235 
237  return TTIImpl->useGPUDivergenceAnalysis();
238 }
239 
241  return TTIImpl->isSourceOfDivergence(V);
242 }
243 
245  return TTIImpl->isAlwaysUniform(V);
246 }
247 
249  return TTIImpl->getFlatAddressSpace();
250 }
251 
253  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
254  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
255 }
256 
258  unsigned ToAS) const {
259  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
260 }
261 
263  unsigned AS) const {
264  return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
265 }
266 
268  return TTIImpl->getAssumedAddrSpace(V);
269 }
270 
271 std::pair<const Value *, unsigned>
273  return TTIImpl->getPredicatedAddrSpace(V);
274 }
275 
277  IntrinsicInst *II, Value *OldV, Value *NewV) const {
278  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
279 }
280 
282  return TTIImpl->isLoweredToCall(F);
283 }
284 
286  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
287  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
288  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
289 }
290 
292  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
294  const LoopAccessInfo *LAI) const {
295  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
296 }
297 
299  return TTIImpl->emitGetActiveLaneMask();
300 }
301 
304  IntrinsicInst &II) const {
305  return TTIImpl->instCombineIntrinsic(IC, II);
306 }
307 
309  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
310  bool &KnownBitsComputed) const {
311  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
312  KnownBitsComputed);
313 }
314 
316  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
317  APInt &UndefElts2, APInt &UndefElts3,
318  std::function<void(Instruction *, unsigned, APInt, APInt &)>
319  SimplifyAndSetOp) const {
320  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
321  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
322  SimplifyAndSetOp);
323 }
324 
327  OptimizationRemarkEmitter *ORE) const {
328  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
329 }
330 
332  PeelingPreferences &PP) const {
333  return TTIImpl->getPeelingPreferences(L, SE, PP);
334 }
335 
337  return TTIImpl->isLegalAddImmediate(Imm);
338 }
339 
341  return TTIImpl->isLegalICmpImmediate(Imm);
342 }
343 
345  int64_t BaseOffset,
346  bool HasBaseReg, int64_t Scale,
347  unsigned AddrSpace,
348  Instruction *I) const {
349  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
350  Scale, AddrSpace, I);
351 }
352 
354  return TTIImpl->isLSRCostLess(C1, C2);
355 }
356 
358  return TTIImpl->isNumRegsMajorCostOfLSR();
359 }
360 
362  return TTIImpl->isProfitableLSRChainElement(I);
363 }
364 
366  return TTIImpl->canMacroFuseCmp();
367 }
368 
370  ScalarEvolution *SE, LoopInfo *LI,
372  TargetLibraryInfo *LibInfo) const {
373  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
374 }
375 
378  ScalarEvolution *SE) const {
379  return TTIImpl->getPreferredAddressingMode(L, SE);
380 }
381 
383  Align Alignment) const {
384  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
385 }
386 
388  Align Alignment) const {
389  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
390 }
391 
393  Align Alignment) const {
394  return TTIImpl->isLegalNTStore(DataType, Alignment);
395 }
396 
397 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
398  return TTIImpl->isLegalNTLoad(DataType, Alignment);
399 }
400 
402  Align Alignment) const {
403  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
404 }
405 
407  Align Alignment) const {
408  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
409 }
410 
412  Align Alignment) const {
413  return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
414 }
415 
417  Align Alignment) const {
418  return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
419 }
420 
422  return TTIImpl->isLegalMaskedCompressStore(DataType);
423 }
424 
426  return TTIImpl->isLegalMaskedExpandLoad(DataType);
427 }
428 
430  return TTIImpl->enableOrderedReductions();
431 }
432 
433 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
434  return TTIImpl->hasDivRemOp(DataType, IsSigned);
435 }
436 
438  unsigned AddrSpace) const {
439  return TTIImpl->hasVolatileVariant(I, AddrSpace);
440 }
441 
443  return TTIImpl->prefersVectorizedAddressing();
444 }
445 
447  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
448  int64_t Scale, unsigned AddrSpace) const {
449  InstructionCost Cost = TTIImpl->getScalingFactorCost(
450  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
451  assert(Cost >= 0 && "TTI should not produce negative costs!");
452  return Cost;
453 }
454 
456  return TTIImpl->LSRWithInstrQueries();
457 }
458 
460  return TTIImpl->isTruncateFree(Ty1, Ty2);
461 }
462 
464  return TTIImpl->isProfitableToHoist(I);
465 }
466 
467 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
468 
470  return TTIImpl->isTypeLegal(Ty);
471 }
472 
474  return TTIImpl->getRegUsageForType(Ty);
475 }
476 
478  return TTIImpl->shouldBuildLookupTables();
479 }
480 
482  Constant *C) const {
483  return TTIImpl->shouldBuildLookupTablesForConstant(C);
484 }
485 
487  return TTIImpl->shouldBuildRelLookupTables();
488 }
489 
491  return TTIImpl->useColdCCForColdCall(F);
492 }
493 
496  const APInt &DemandedElts,
497  bool Insert, bool Extract) const {
498  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
499 }
500 
503  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
504 }
505 
507  return TTIImpl->supportsEfficientVectorElementLoadStore();
508 }
509 
511  bool LoopHasReductions) const {
512  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
513 }
514 
516 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
517  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
518 }
519 
521  return TTIImpl->enableInterleavedAccessVectorization();
522 }
523 
525  return TTIImpl->enableMaskedInterleavedAccessVectorization();
526 }
527 
529  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
530 }
531 
533  unsigned BitWidth,
534  unsigned AddressSpace,
535  Align Alignment,
536  bool *Fast) const {
537  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
538  AddressSpace, Alignment, Fast);
539 }
540 
542 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
543  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
544 }
545 
547  return TTIImpl->haveFastSqrt(Ty);
548 }
549 
551  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
552 }
553 
555  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
556  assert(Cost >= 0 && "TTI should not produce negative costs!");
557  return Cost;
558 }
559 
561  unsigned Idx,
562  const APInt &Imm,
563  Type *Ty) const {
564  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
565  assert(Cost >= 0 && "TTI should not produce negative costs!");
566  return Cost;
567 }
568 
572  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
573  assert(Cost >= 0 && "TTI should not produce negative costs!");
574  return Cost;
575 }
576 
578  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
580  InstructionCost Cost =
581  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
582  assert(Cost >= 0 && "TTI should not produce negative costs!");
583  return Cost;
584 }
585 
588  const APInt &Imm, Type *Ty,
590  InstructionCost Cost =
591  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
592  assert(Cost >= 0 && "TTI should not produce negative costs!");
593  return Cost;
594 }
595 
596 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
597  return TTIImpl->getNumberOfRegisters(ClassID);
598 }
599 
601  Type *Ty) const {
602  return TTIImpl->getRegisterClassForType(Vector, Ty);
603 }
604 
605 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
606  return TTIImpl->getRegisterClassName(ClassID);
607 }
608 
611  return TTIImpl->getRegisterBitWidth(K);
612 }
613 
615  return TTIImpl->getMinVectorRegisterBitWidth();
616 }
617 
619  return TTIImpl->getMaxVScale();
620 }
621 
623  return TTIImpl->getVScaleForTuning();
624 }
625 
627  return TTIImpl->shouldMaximizeVectorBandwidth();
628 }
629 
631  bool IsScalable) const {
632  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
633 }
634 
635 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
636  unsigned Opcode) const {
637  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
638 }
639 
641  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
642  return TTIImpl->shouldConsiderAddressTypePromotion(
643  I, AllowPromotionWithoutCommonHeader);
644 }
645 
647  return TTIImpl->getCacheLineSize();
648 }
649 
652  return TTIImpl->getCacheSize(Level);
653 }
654 
657  return TTIImpl->getCacheAssociativity(Level);
658 }
659 
661  return TTIImpl->getPrefetchDistance();
662 }
663 
665  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
666  unsigned NumPrefetches, bool HasCall) const {
667  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
668  NumPrefetches, HasCall);
669 }
670 
672  return TTIImpl->getMaxPrefetchIterationsAhead();
673 }
674 
676  return TTIImpl->enableWritePrefetching();
677 }
678 
679 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
680  return TTIImpl->getMaxInterleaveFactor(VF);
681 }
682 
685  OperandValueProperties &OpProps) {
686  OperandValueKind OpInfo = OK_AnyValue;
687  OpProps = OP_None;
688 
689  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
690  if (CI->getValue().isPowerOf2())
691  OpProps = OP_PowerOf2;
693  }
694 
695  // A broadcast shuffle creates a uniform value.
696  // TODO: Add support for non-zero index broadcasts.
697  // TODO: Add support for different source vector width.
698  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
699  if (ShuffleInst->isZeroEltSplat())
700  OpInfo = OK_UniformValue;
701 
702  const Value *Splat = getSplatValue(V);
703 
704  // Check for a splat of a constant or for a non uniform vector of constants
705  // and check if the constant(s) are all powers of two.
706  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
708  if (Splat) {
709  OpInfo = OK_UniformConstantValue;
710  if (auto *CI = dyn_cast<ConstantInt>(Splat))
711  if (CI->getValue().isPowerOf2())
712  OpProps = OP_PowerOf2;
713  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
714  OpProps = OP_PowerOf2;
715  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
716  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
717  if (CI->getValue().isPowerOf2())
718  continue;
719  OpProps = OP_None;
720  break;
721  }
722  }
723  }
724 
725  // Check for a splat of a uniform value. This is not loop aware, so return
726  // true only for the obviously uniform cases (argument, globalvalue)
727  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
728  OpInfo = OK_UniformValue;
729 
730  return OpInfo;
731 }
732 
734  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
735  OperandValueKind Opd1Info, OperandValueKind Opd2Info,
736  OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo,
737  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
738  InstructionCost Cost =
739  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
740  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
741  assert(Cost >= 0 && "TTI should not produce negative costs!");
742  return Cost;
743 }
744 
746  VectorType *Ty,
748  int Index,
749  VectorType *SubTp) const {
750  InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
751  assert(Cost >= 0 && "TTI should not produce negative costs!");
752  return Cost;
753 }
754 
757  if (!I)
758  return CastContextHint::None;
759 
760  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
761  unsigned GatScatOp) {
762  const Instruction *I = dyn_cast<Instruction>(V);
763  if (!I)
764  return CastContextHint::None;
765 
766  if (I->getOpcode() == LdStOp)
768 
769  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
770  if (II->getIntrinsicID() == MaskedOp)
772  if (II->getIntrinsicID() == GatScatOp)
774  }
775 
777  };
778 
779  switch (I->getOpcode()) {
780  case Instruction::ZExt:
781  case Instruction::SExt:
782  case Instruction::FPExt:
783  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
784  Intrinsic::masked_load, Intrinsic::masked_gather);
785  case Instruction::Trunc:
786  case Instruction::FPTrunc:
787  if (I->hasOneUse())
788  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
789  Intrinsic::masked_store,
790  Intrinsic::masked_scatter);
791  break;
792  default:
793  return CastContextHint::None;
794  }
795 
797 }
798 
800  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
801  TTI::TargetCostKind CostKind, const Instruction *I) const {
802  assert((I == nullptr || I->getOpcode() == Opcode) &&
803  "Opcode should reflect passed instruction.");
804  InstructionCost Cost =
805  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
806  assert(Cost >= 0 && "TTI should not produce negative costs!");
807  return Cost;
808 }
809 
811  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
812  InstructionCost Cost =
813  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
814  assert(Cost >= 0 && "TTI should not produce negative costs!");
815  return Cost;
816 }
817 
819  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
820  assert((I == nullptr || I->getOpcode() == Opcode) &&
821  "Opcode should reflect passed instruction.");
822  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
823  assert(Cost >= 0 && "TTI should not produce negative costs!");
824  return Cost;
825 }
826 
828  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
829  TTI::TargetCostKind CostKind, const Instruction *I) const {
830  assert((I == nullptr || I->getOpcode() == Opcode) &&
831  "Opcode should reflect passed instruction.");
832  InstructionCost Cost =
833  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
834  assert(Cost >= 0 && "TTI should not produce negative costs!");
835  return Cost;
836 }
837 
839  Type *Val,
840  unsigned Index) const {
841  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
842  assert(Cost >= 0 && "TTI should not produce negative costs!");
843  return Cost;
844 }
845 
847  Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
849  InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
850  EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
851  assert(Cost >= 0 && "TTI should not produce negative costs!");
852  return Cost;
853 }
854 
856  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
857  TTI::TargetCostKind CostKind, const Instruction *I) const {
858  assert((I == nullptr || I->getOpcode() == Opcode) &&
859  "Opcode should reflect passed instruction.");
860  InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment,
862  assert(Cost >= 0 && "TTI should not produce negative costs!");
863  return Cost;
864 }
865 
867  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
869  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
871  assert(Cost >= 0 && "TTI should not produce negative costs!");
872  return Cost;
873 }
874 
876  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
877  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
878  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
879  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
880  assert(Cost >= 0 && "TTI should not produce negative costs!");
881  return Cost;
882 }
883 
885  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
886  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
887  bool UseMaskForCond, bool UseMaskForGaps) const {
888  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
889  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
890  UseMaskForCond, UseMaskForGaps);
891  assert(Cost >= 0 && "TTI should not produce negative costs!");
892  return Cost;
893 }
894 
898  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
899  assert(Cost >= 0 && "TTI should not produce negative costs!");
900  return Cost;
901 }
902 
905  ArrayRef<Type *> Tys,
907  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
908  assert(Cost >= 0 && "TTI should not produce negative costs!");
909  return Cost;
910 }
911 
913  return TTIImpl->getNumberOfParts(Tp);
914 }
915 
918  const SCEV *Ptr) const {
919  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
920  assert(Cost >= 0 && "TTI should not produce negative costs!");
921  return Cost;
922 }
923 
925  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
926  assert(Cost >= 0 && "TTI should not produce negative costs!");
927  return Cost;
928 }
929 
931  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
933  InstructionCost Cost =
934  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
935  assert(Cost >= 0 && "TTI should not produce negative costs!");
936  return Cost;
937 }
938 
940  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
942  InstructionCost Cost =
943  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
944  assert(Cost >= 0 && "TTI should not produce negative costs!");
945  return Cost;
946 }
947 
949  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
951  return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
952  CostKind);
953 }
954 
957  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
958 }
959 
961  MemIntrinsicInfo &Info) const {
962  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
963 }
964 
966  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
967 }
968 
970  IntrinsicInst *Inst, Type *ExpectedType) const {
971  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
972 }
973 
975  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
976  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
977  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
978  DestAddrSpace, SrcAlign, DestAlign);
979 }
980 
983  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
984  unsigned SrcAlign, unsigned DestAlign) const {
985  TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
986  SrcAddrSpace, DestAddrSpace,
987  SrcAlign, DestAlign);
988 }
989 
991  const Function *Callee) const {
992  return TTIImpl->areInlineCompatible(Caller, Callee);
993 }
994 
996  const Function *Caller, const Function *Callee,
997  const ArrayRef<Type *> &Types) const {
998  return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
999 }
1000 
1002  Type *Ty) const {
1003  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1004 }
1005 
1007  Type *Ty) const {
1008  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1009 }
1010 
1012  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1013 }
1014 
1016  return TTIImpl->isLegalToVectorizeLoad(LI);
1017 }
1018 
1020  return TTIImpl->isLegalToVectorizeStore(SI);
1021 }
1022 
1024  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1025  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1026  AddrSpace);
1027 }
1028 
1030  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1031  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1032  AddrSpace);
1033 }
1034 
1036  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1037  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1038 }
1039 
1041  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1042 }
1043 
1045  unsigned LoadSize,
1046  unsigned ChainSizeInBytes,
1047  VectorType *VecTy) const {
1048  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1049 }
1050 
1052  unsigned StoreSize,
1053  unsigned ChainSizeInBytes,
1054  VectorType *VecTy) const {
1055  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1056 }
1057 
1059  ReductionFlags Flags) const {
1060  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1061 }
1062 
1064  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1065  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1066 }
1067 
1070  return TTIImpl->getVPLegalizationStrategy(VPI);
1071 }
1072 
1074  return TTIImpl->shouldExpandReduction(II);
1075 }
1076 
1078  return TTIImpl->getGISelRematGlobalCost();
1079 }
1080 
1082  return TTIImpl->supportsScalableVectors();
1083 }
1084 
1086  return TTIImpl->enableScalableVectorization();
1087 }
1088 
1089 bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1090  Align Alignment) const {
1091  return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1092 }
1093 
1095 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1096  return TTIImpl->getInstructionLatency(I);
1097 }
1098 
1100 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1102 
1103  switch (I->getOpcode()) {
1104  case Instruction::GetElementPtr:
1105  case Instruction::Ret:
1106  case Instruction::PHI:
1107  case Instruction::Br:
1108  case Instruction::Add:
1109  case Instruction::FAdd:
1110  case Instruction::Sub:
1111  case Instruction::FSub:
1112  case Instruction::Mul:
1113  case Instruction::FMul:
1114  case Instruction::UDiv:
1115  case Instruction::SDiv:
1116  case Instruction::FDiv:
1117  case Instruction::URem:
1118  case Instruction::SRem:
1119  case Instruction::FRem:
1120  case Instruction::Shl:
1121  case Instruction::LShr:
1122  case Instruction::AShr:
1123  case Instruction::And:
1124  case Instruction::Or:
1125  case Instruction::Xor:
1126  case Instruction::FNeg:
1127  case Instruction::Select:
1128  case Instruction::ICmp:
1129  case Instruction::FCmp:
1130  case Instruction::Store:
1131  case Instruction::Load:
1132  case Instruction::ZExt:
1133  case Instruction::SExt:
1134  case Instruction::FPToUI:
1135  case Instruction::FPToSI:
1136  case Instruction::FPExt:
1137  case Instruction::PtrToInt:
1138  case Instruction::IntToPtr:
1139  case Instruction::SIToFP:
1140  case Instruction::UIToFP:
1141  case Instruction::Trunc:
1142  case Instruction::FPTrunc:
1143  case Instruction::BitCast:
1144  case Instruction::AddrSpaceCast:
1145  case Instruction::ExtractElement:
1146  case Instruction::InsertElement:
1147  case Instruction::ExtractValue:
1148  case Instruction::ShuffleVector:
1149  case Instruction::Call:
1150  case Instruction::Switch:
1151  return getUserCost(I, CostKind);
1152  default:
1153  // We don't have any information on this instruction.
1154  return -1;
1155  }
1156 }
1157 
1159 
1160 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1161 
1163  std::function<Result(const Function &)> TTICallback)
1164  : TTICallback(std::move(TTICallback)) {}
1165 
1168  return TTICallback(F);
1169 }
1170 
1171 AnalysisKey TargetIRAnalysis::Key;
1172 
1173 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1174  return Result(F.getParent()->getDataLayout());
1175 }
1176 
1177 // Register the basic pass.
1179  "Target Transform Information", false, true)
1181 
1182 void TargetTransformInfoWrapperPass::anchor() {}
1183 
1185  : ImmutablePass(ID) {
1188 }
1189 
1191  TargetIRAnalysis TIRA)
1192  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1195 }
1196 
1198  FunctionAnalysisManager DummyFAM;
1199  TTI = TIRA.run(F, DummyFAM);
1200  return *TTI;
1201 }
1202 
1203 ImmutablePass *
1205  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1206 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:285
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:974
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2418
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1366
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:303
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:291
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:614
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, int Index=0, VectorType *SubTp=nullptr) const
Definition: TargetTransformInfo.cpp:745
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1314
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::TargetTransformInfo::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfo.cpp:622
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:605
llvm::ElementCount
Definition: TypeSize.h:385
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:889
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:827
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1184
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:365
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:609
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:595
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:855
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1069
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1197
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:917
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:366
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:446
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:896
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:267
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:340
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:100
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:4204
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1414
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:477
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:100
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:635
llvm::dyn_cast
LLVM_NODISCARD std::enable_if_t< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type > dyn_cast(const Y &Val)
Definition: Casting.h:334
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:490
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:538
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:187
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:98
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:397
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:392
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:818
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:895
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:228
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:560
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:201
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:587
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:239
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1318
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:577
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:165
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:520
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:501
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1058
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:960
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:262
TargetTransformInfoImpl.h
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:105
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:325
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:115
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:406
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
Instruction.h
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1077
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:990
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1355
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:469
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:101
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:630
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:361
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:756
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:969
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:1015
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:542
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:895
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:868
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:377
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1074
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:236
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:129
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1398
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:232
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1035
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:570
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:912
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1081
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1001
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:425
llvm::TargetTransformInfo::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfo.cpp:1085
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:128
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
Definition: TargetTransformInfo.cpp:353
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:387
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:240
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:315
llvm::predecessors
auto predecessors(MachineBasicBlock *BB)
Definition: MachineSSAContext.h:32
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:660
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:107
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:888
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:550
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfo::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfo.cpp:995
LoopIterator.h
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:437
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:421
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:546
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1204
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:248
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
Definition: TargetTransformInfo.cpp:1158
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:77
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:309
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:481
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfo.cpp:626
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:417
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:252
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:401
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2474
llvm::TargetTransformInfo::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported.
Definition: TargetTransformInfo.cpp:298
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1063
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:884
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:890
llvm::TargetTransformInfo::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
Definition: TargetTransformInfo.cpp:411
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2420
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:679
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:600
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:431
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:956
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:970
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:895
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:640
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:514
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:60
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:495
llvm::TargetTransformInfo::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfo.cpp:846
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:276
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:875
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1707
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:455
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:939
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1023
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:206
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:336
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:532
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:281
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:799
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:887
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:981
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1324
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:369
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:459
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:442
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:770
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:506
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:516
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1086
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:68
DataLayout.h
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1040
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:382
llvm::TargetTransformInfo::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:272
llvm::TargetTransformInfo::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:473
llvm::TargetTransformInfo::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:219
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:433
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:308
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:651
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:596
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:642
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:671
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:431
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:888
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1044
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:180
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:1019
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:12996
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1160
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:185
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:429
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:618
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:656
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:646
std
Definition: BitVector.h:838
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:524
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:99
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:151
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:257
llvm::TypeSize
Definition: TypeSize.h:416
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1011
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:528
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfo.cpp:1089
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:177
llvm::TargetTransformInfo::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
Definition: TargetTransformInfo.cpp:416
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1166
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:192
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:838
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:197
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:866
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:212
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2404
llvm::TargetTransformInfo::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:948
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:73
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:930
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:916
Dominators.h
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:664
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1006
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:357
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1073
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:331
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1051
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:47
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1029
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:965
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1176
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:510
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:904
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:684
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:810
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3236
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:733
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:463
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:486
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3092
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
Definition: TargetTransformInfo.cpp:182
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:232
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:891
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:960
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:467
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:102
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:675
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:554
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:7701
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:152
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:244
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:344
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:924
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid())
Definition: TargetTransformInfo.cpp:57