LLVM  14.0.0git
TargetTransformInfo.cpp
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1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33  cl::Hidden,
34  cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42  explicit NoTTIImpl(const DataLayout &DL)
43  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
48  // If the loop has irreducible control flow, it can not be converted to
49  // Hardware loop.
50  LoopBlocksRPO RPOT(L);
51  RPOT.perform(&LI);
52  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53  return false;
54  return true;
55 }
56 
58  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost)
59  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
60  ScalarizationCost(ScalarizationCost) {
61 
62  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
63  FMF = FPMO->getFastMathFlags();
64 
65  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
67  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
68 }
69 
71  ArrayRef<Type *> Tys,
72  FastMathFlags Flags,
73  const IntrinsicInst *I,
74  InstructionCost ScalarCost)
75  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
76  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
77 }
78 
81  : RetTy(Ty), IID(Id) {
82 
83  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
84  ParamTys.reserve(Arguments.size());
85  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
86  ParamTys.push_back(Arguments[Idx]->getType());
87 }
88 
91  ArrayRef<Type *> Tys,
92  FastMathFlags Flags,
93  const IntrinsicInst *I,
94  InstructionCost ScalarCost)
95  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
98 }
99 
101  LoopInfo &LI, DominatorTree &DT,
102  bool ForceNestedLoop,
103  bool ForceHardwareLoopPHI) {
104  SmallVector<BasicBlock *, 4> ExitingBlocks;
105  L->getExitingBlocks(ExitingBlocks);
106 
107  for (BasicBlock *BB : ExitingBlocks) {
108  // If we pass the updated counter back through a phi, we need to know
109  // which latch the updated value will be coming from.
110  if (!L->isLoopLatch(BB)) {
112  continue;
113  }
114 
115  const SCEV *EC = SE.getExitCount(L, BB);
116  if (isa<SCEVCouldNotCompute>(EC))
117  continue;
118  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
119  if (ConstEC->getValue()->isZero())
120  continue;
121  } else if (!SE.isLoopInvariant(EC, L))
122  continue;
123 
124  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
125  continue;
126 
127  // If this exiting block is contained in a nested loop, it is not eligible
128  // for insertion of the branch-and-decrement since the inner loop would
129  // end up messing up the value in the CTR.
130  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
131  continue;
132 
133  // We now have a loop-invariant count of loop iterations (which is not the
134  // constant zero) for which we know that this loop will not exit via this
135  // existing block.
136 
137  // We need to make sure that this block will run on every loop iteration.
138  // For this to be true, we must dominate all blocks with backedges. Such
139  // blocks are in-loop predecessors to the header block.
140  bool NotAlways = false;
141  for (BasicBlock *Pred : predecessors(L->getHeader())) {
142  if (!L->contains(Pred))
143  continue;
144 
145  if (!DT.dominates(BB, Pred)) {
146  NotAlways = true;
147  break;
148  }
149  }
150 
151  if (NotAlways)
152  continue;
153 
154  // Make sure this blocks ends with a conditional branch.
155  Instruction *TI = BB->getTerminator();
156  if (!TI)
157  continue;
158 
159  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
160  if (!BI->isConditional())
161  continue;
162 
163  ExitBranch = BI;
164  } else
165  continue;
166 
167  // Note that this block may not be the loop latch block, even if the loop
168  // has a latch block.
169  ExitBlock = BB;
170  ExitCount = EC;
171  break;
172  }
173 
174  if (!ExitBlock)
175  return false;
176  return true;
177 }
178 
180  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
181 
183 
185  : TTIImpl(std::move(Arg.TTIImpl)) {}
186 
188  TTIImpl = std::move(RHS.TTIImpl);
189  return *this;
190 }
191 
193  return TTIImpl->getInliningThresholdMultiplier();
194 }
195 
196 unsigned
198  return TTIImpl->adjustInliningThreshold(CB);
199 }
200 
202  return TTIImpl->getInlinerVectorBonusPercent();
203 }
204 
206 TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
209  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
210 }
211 
213  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
214  BlockFrequencyInfo *BFI) const {
215  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
216 }
217 
221  enum TargetCostKind CostKind) const {
222  InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
223  assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
224  "TTI should not produce negative costs!");
225  return Cost;
226 }
227 
229  return TTIImpl->getPredictableBranchThreshold();
230 }
231 
233  return TTIImpl->hasBranchDivergence();
234 }
235 
237  return TTIImpl->useGPUDivergenceAnalysis();
238 }
239 
241  return TTIImpl->isSourceOfDivergence(V);
242 }
243 
245  return TTIImpl->isAlwaysUniform(V);
246 }
247 
249  return TTIImpl->getFlatAddressSpace();
250 }
251 
253  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
254  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
255 }
256 
258  unsigned ToAS) const {
259  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
260 }
261 
263  unsigned AS) const {
264  return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
265 }
266 
268  return TTIImpl->getAssumedAddrSpace(V);
269 }
270 
272  IntrinsicInst *II, Value *OldV, Value *NewV) const {
273  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
274 }
275 
277  return TTIImpl->isLoweredToCall(F);
278 }
279 
281  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
282  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
283  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
284 }
285 
287  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
289  const LoopAccessInfo *LAI) const {
290  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
291 }
292 
294  return TTIImpl->emitGetActiveLaneMask();
295 }
296 
299  IntrinsicInst &II) const {
300  return TTIImpl->instCombineIntrinsic(IC, II);
301 }
302 
304  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
305  bool &KnownBitsComputed) const {
306  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
307  KnownBitsComputed);
308 }
309 
311  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
312  APInt &UndefElts2, APInt &UndefElts3,
313  std::function<void(Instruction *, unsigned, APInt, APInt &)>
314  SimplifyAndSetOp) const {
315  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
316  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
317  SimplifyAndSetOp);
318 }
319 
322  OptimizationRemarkEmitter *ORE) const {
323  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
324 }
325 
327  PeelingPreferences &PP) const {
328  return TTIImpl->getPeelingPreferences(L, SE, PP);
329 }
330 
332  return TTIImpl->isLegalAddImmediate(Imm);
333 }
334 
336  return TTIImpl->isLegalICmpImmediate(Imm);
337 }
338 
340  int64_t BaseOffset,
341  bool HasBaseReg, int64_t Scale,
342  unsigned AddrSpace,
343  Instruction *I) const {
344  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
345  Scale, AddrSpace, I);
346 }
347 
349  return TTIImpl->isLSRCostLess(C1, C2);
350 }
351 
353  return TTIImpl->isNumRegsMajorCostOfLSR();
354 }
355 
357  return TTIImpl->isProfitableLSRChainElement(I);
358 }
359 
361  return TTIImpl->canMacroFuseCmp();
362 }
363 
365  ScalarEvolution *SE, LoopInfo *LI,
367  TargetLibraryInfo *LibInfo) const {
368  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
369 }
370 
373  ScalarEvolution *SE) const {
374  return TTIImpl->getPreferredAddressingMode(L, SE);
375 }
376 
378  Align Alignment) const {
379  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
380 }
381 
383  Align Alignment) const {
384  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
385 }
386 
388  Align Alignment) const {
389  return TTIImpl->isLegalNTStore(DataType, Alignment);
390 }
391 
392 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
393  return TTIImpl->isLegalNTLoad(DataType, Alignment);
394 }
395 
397  Align Alignment) const {
398  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
399 }
400 
402  Align Alignment) const {
403  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
404 }
405 
407  return TTIImpl->isLegalMaskedCompressStore(DataType);
408 }
409 
411  return TTIImpl->isLegalMaskedExpandLoad(DataType);
412 }
413 
415  return TTIImpl->enableOrderedReductions();
416 }
417 
418 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
419  return TTIImpl->hasDivRemOp(DataType, IsSigned);
420 }
421 
423  unsigned AddrSpace) const {
424  return TTIImpl->hasVolatileVariant(I, AddrSpace);
425 }
426 
428  return TTIImpl->prefersVectorizedAddressing();
429 }
430 
432  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
433  int64_t Scale, unsigned AddrSpace) const {
434  InstructionCost Cost = TTIImpl->getScalingFactorCost(
435  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
436  assert(Cost >= 0 && "TTI should not produce negative costs!");
437  return Cost;
438 }
439 
441  return TTIImpl->LSRWithInstrQueries();
442 }
443 
445  return TTIImpl->isTruncateFree(Ty1, Ty2);
446 }
447 
449  return TTIImpl->isProfitableToHoist(I);
450 }
451 
452 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
453 
455  return TTIImpl->isTypeLegal(Ty);
456 }
457 
459  return TTIImpl->getRegUsageForType(Ty);
460 }
461 
463  return TTIImpl->shouldBuildLookupTables();
464 }
465 
467  Constant *C) const {
468  return TTIImpl->shouldBuildLookupTablesForConstant(C);
469 }
470 
472  return TTIImpl->shouldBuildRelLookupTables();
473 }
474 
476  return TTIImpl->useColdCCForColdCall(F);
477 }
478 
481  const APInt &DemandedElts,
482  bool Insert, bool Extract) const {
483  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
484 }
485 
488  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
489 }
490 
492  return TTIImpl->supportsEfficientVectorElementLoadStore();
493 }
494 
496  bool LoopHasReductions) const {
497  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
498 }
499 
501 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
502  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
503 }
504 
506  return TTIImpl->enableInterleavedAccessVectorization();
507 }
508 
510  return TTIImpl->enableMaskedInterleavedAccessVectorization();
511 }
512 
514  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
515 }
516 
518  unsigned BitWidth,
519  unsigned AddressSpace,
520  Align Alignment,
521  bool *Fast) const {
522  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
523  AddressSpace, Alignment, Fast);
524 }
525 
527 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
528  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
529 }
530 
532  return TTIImpl->haveFastSqrt(Ty);
533 }
534 
536  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
537 }
538 
540  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
541  assert(Cost >= 0 && "TTI should not produce negative costs!");
542  return Cost;
543 }
544 
546  unsigned Idx,
547  const APInt &Imm,
548  Type *Ty) const {
549  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
550  assert(Cost >= 0 && "TTI should not produce negative costs!");
551  return Cost;
552 }
553 
557  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
558  assert(Cost >= 0 && "TTI should not produce negative costs!");
559  return Cost;
560 }
561 
563  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
565  InstructionCost Cost =
566  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
567  assert(Cost >= 0 && "TTI should not produce negative costs!");
568  return Cost;
569 }
570 
573  const APInt &Imm, Type *Ty,
575  InstructionCost Cost =
576  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
577  assert(Cost >= 0 && "TTI should not produce negative costs!");
578  return Cost;
579 }
580 
581 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
582  return TTIImpl->getNumberOfRegisters(ClassID);
583 }
584 
586  Type *Ty) const {
587  return TTIImpl->getRegisterClassForType(Vector, Ty);
588 }
589 
590 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
591  return TTIImpl->getRegisterClassName(ClassID);
592 }
593 
596  return TTIImpl->getRegisterBitWidth(K);
597 }
598 
600  return TTIImpl->getMinVectorRegisterBitWidth();
601 }
602 
604  return TTIImpl->getMaxVScale();
605 }
606 
608  return TTIImpl->shouldMaximizeVectorBandwidth();
609 }
610 
612  bool IsScalable) const {
613  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
614 }
615 
616 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
617  unsigned Opcode) const {
618  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
619 }
620 
622  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
623  return TTIImpl->shouldConsiderAddressTypePromotion(
624  I, AllowPromotionWithoutCommonHeader);
625 }
626 
628  return TTIImpl->getCacheLineSize();
629 }
630 
633  return TTIImpl->getCacheSize(Level);
634 }
635 
638  return TTIImpl->getCacheAssociativity(Level);
639 }
640 
642  return TTIImpl->getPrefetchDistance();
643 }
644 
646  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
647  unsigned NumPrefetches, bool HasCall) const {
648  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
649  NumPrefetches, HasCall);
650 }
651 
653  return TTIImpl->getMaxPrefetchIterationsAhead();
654 }
655 
657  return TTIImpl->enableWritePrefetching();
658 }
659 
660 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
661  return TTIImpl->getMaxInterleaveFactor(VF);
662 }
663 
666  OperandValueProperties &OpProps) {
667  OperandValueKind OpInfo = OK_AnyValue;
668  OpProps = OP_None;
669 
670  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
671  if (CI->getValue().isPowerOf2())
672  OpProps = OP_PowerOf2;
674  }
675 
676  // A broadcast shuffle creates a uniform value.
677  // TODO: Add support for non-zero index broadcasts.
678  // TODO: Add support for different source vector width.
679  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
680  if (ShuffleInst->isZeroEltSplat())
681  OpInfo = OK_UniformValue;
682 
683  const Value *Splat = getSplatValue(V);
684 
685  // Check for a splat of a constant or for a non uniform vector of constants
686  // and check if the constant(s) are all powers of two.
687  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
689  if (Splat) {
690  OpInfo = OK_UniformConstantValue;
691  if (auto *CI = dyn_cast<ConstantInt>(Splat))
692  if (CI->getValue().isPowerOf2())
693  OpProps = OP_PowerOf2;
694  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
695  OpProps = OP_PowerOf2;
696  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
697  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
698  if (CI->getValue().isPowerOf2())
699  continue;
700  OpProps = OP_None;
701  break;
702  }
703  }
704  }
705 
706  // Check for a splat of a uniform value. This is not loop aware, so return
707  // true only for the obviously uniform cases (argument, globalvalue)
708  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
709  OpInfo = OK_UniformValue;
710 
711  return OpInfo;
712 }
713 
715  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
716  OperandValueKind Opd1Info, OperandValueKind Opd2Info,
717  OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo,
718  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
719  InstructionCost Cost =
720  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
721  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
722  assert(Cost >= 0 && "TTI should not produce negative costs!");
723  return Cost;
724 }
725 
727  VectorType *Ty,
729  int Index,
730  VectorType *SubTp) const {
731  InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
732  assert(Cost >= 0 && "TTI should not produce negative costs!");
733  return Cost;
734 }
735 
738  if (!I)
739  return CastContextHint::None;
740 
741  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
742  unsigned GatScatOp) {
743  const Instruction *I = dyn_cast<Instruction>(V);
744  if (!I)
745  return CastContextHint::None;
746 
747  if (I->getOpcode() == LdStOp)
749 
750  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
751  if (II->getIntrinsicID() == MaskedOp)
753  if (II->getIntrinsicID() == GatScatOp)
755  }
756 
758  };
759 
760  switch (I->getOpcode()) {
761  case Instruction::ZExt:
762  case Instruction::SExt:
763  case Instruction::FPExt:
764  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
765  Intrinsic::masked_load, Intrinsic::masked_gather);
766  case Instruction::Trunc:
767  case Instruction::FPTrunc:
768  if (I->hasOneUse())
769  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
770  Intrinsic::masked_store,
771  Intrinsic::masked_scatter);
772  break;
773  default:
774  return CastContextHint::None;
775  }
776 
778 }
779 
781  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
782  TTI::TargetCostKind CostKind, const Instruction *I) const {
783  assert((I == nullptr || I->getOpcode() == Opcode) &&
784  "Opcode should reflect passed instruction.");
785  InstructionCost Cost =
786  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
787  assert(Cost >= 0 && "TTI should not produce negative costs!");
788  return Cost;
789 }
790 
792  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
793  InstructionCost Cost =
794  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
795  assert(Cost >= 0 && "TTI should not produce negative costs!");
796  return Cost;
797 }
798 
800  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
801  assert((I == nullptr || I->getOpcode() == Opcode) &&
802  "Opcode should reflect passed instruction.");
803  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
804  assert(Cost >= 0 && "TTI should not produce negative costs!");
805  return Cost;
806 }
807 
809  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
810  TTI::TargetCostKind CostKind, const Instruction *I) const {
811  assert((I == nullptr || I->getOpcode() == Opcode) &&
812  "Opcode should reflect passed instruction.");
813  InstructionCost Cost =
814  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
815  assert(Cost >= 0 && "TTI should not produce negative costs!");
816  return Cost;
817 }
818 
820  Type *Val,
821  unsigned Index) const {
822  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
823  assert(Cost >= 0 && "TTI should not produce negative costs!");
824  return Cost;
825 }
826 
828  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
829  TTI::TargetCostKind CostKind, const Instruction *I) const {
830  assert((I == nullptr || I->getOpcode() == Opcode) &&
831  "Opcode should reflect passed instruction.");
832  InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment,
834  assert(Cost >= 0 && "TTI should not produce negative costs!");
835  return Cost;
836 }
837 
839  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
841  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
843  assert(Cost >= 0 && "TTI should not produce negative costs!");
844  return Cost;
845 }
846 
848  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
849  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
850  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
851  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
852  assert(Cost >= 0 && "TTI should not produce negative costs!");
853  return Cost;
854 }
855 
857  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
858  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
859  bool UseMaskForCond, bool UseMaskForGaps) const {
860  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
861  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
862  UseMaskForCond, UseMaskForGaps);
863  assert(Cost >= 0 && "TTI should not produce negative costs!");
864  return Cost;
865 }
866 
870  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
871  assert(Cost >= 0 && "TTI should not produce negative costs!");
872  return Cost;
873 }
874 
877  ArrayRef<Type *> Tys,
879  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
880  assert(Cost >= 0 && "TTI should not produce negative costs!");
881  return Cost;
882 }
883 
885  return TTIImpl->getNumberOfParts(Tp);
886 }
887 
890  const SCEV *Ptr) const {
891  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
892  assert(Cost >= 0 && "TTI should not produce negative costs!");
893  return Cost;
894 }
895 
897  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
898  assert(Cost >= 0 && "TTI should not produce negative costs!");
899  return Cost;
900 }
901 
903  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
905  InstructionCost Cost =
906  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
907  assert(Cost >= 0 && "TTI should not produce negative costs!");
908  return Cost;
909 }
910 
912  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
914  InstructionCost Cost =
915  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
916  assert(Cost >= 0 && "TTI should not produce negative costs!");
917  return Cost;
918 }
919 
921  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
923  return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
924  CostKind);
925 }
926 
929  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
930 }
931 
933  MemIntrinsicInfo &Info) const {
934  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
935 }
936 
938  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
939 }
940 
942  IntrinsicInst *Inst, Type *ExpectedType) const {
943  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
944 }
945 
947  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
948  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
949  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
950  DestAddrSpace, SrcAlign, DestAlign);
951 }
952 
955  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
956  unsigned SrcAlign, unsigned DestAlign) const {
957  TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
958  SrcAddrSpace, DestAddrSpace,
959  SrcAlign, DestAlign);
960 }
961 
963  const Function *Callee) const {
964  return TTIImpl->areInlineCompatible(Caller, Callee);
965 }
966 
968  const Function *Caller, const Function *Callee,
970  return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
971 }
972 
974  Type *Ty) const {
975  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
976 }
977 
979  Type *Ty) const {
980  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
981 }
982 
984  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
985 }
986 
988  return TTIImpl->isLegalToVectorizeLoad(LI);
989 }
990 
992  return TTIImpl->isLegalToVectorizeStore(SI);
993 }
994 
996  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
997  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
998  AddrSpace);
999 }
1000 
1002  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1003  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1004  AddrSpace);
1005 }
1006 
1008  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1009  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1010 }
1011 
1013  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1014 }
1015 
1017  unsigned LoadSize,
1018  unsigned ChainSizeInBytes,
1019  VectorType *VecTy) const {
1020  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1021 }
1022 
1024  unsigned StoreSize,
1025  unsigned ChainSizeInBytes,
1026  VectorType *VecTy) const {
1027  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1028 }
1029 
1031  ReductionFlags Flags) const {
1032  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1033 }
1034 
1036  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1037  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1038 }
1039 
1042  return TTIImpl->getVPLegalizationStrategy(VPI);
1043 }
1044 
1046  return TTIImpl->shouldExpandReduction(II);
1047 }
1048 
1050  return TTIImpl->getGISelRematGlobalCost();
1051 }
1052 
1054  return TTIImpl->supportsScalableVectors();
1055 }
1056 
1058  return TTIImpl->hasActiveVectorLength();
1059 }
1060 
1062 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1063  return TTIImpl->getInstructionLatency(I);
1064 }
1065 
1067 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1069 
1070  switch (I->getOpcode()) {
1071  case Instruction::GetElementPtr:
1072  case Instruction::Ret:
1073  case Instruction::PHI:
1074  case Instruction::Br:
1075  case Instruction::Add:
1076  case Instruction::FAdd:
1077  case Instruction::Sub:
1078  case Instruction::FSub:
1079  case Instruction::Mul:
1080  case Instruction::FMul:
1081  case Instruction::UDiv:
1082  case Instruction::SDiv:
1083  case Instruction::FDiv:
1084  case Instruction::URem:
1085  case Instruction::SRem:
1086  case Instruction::FRem:
1087  case Instruction::Shl:
1088  case Instruction::LShr:
1089  case Instruction::AShr:
1090  case Instruction::And:
1091  case Instruction::Or:
1092  case Instruction::Xor:
1093  case Instruction::FNeg:
1094  case Instruction::Select:
1095  case Instruction::ICmp:
1096  case Instruction::FCmp:
1097  case Instruction::Store:
1098  case Instruction::Load:
1099  case Instruction::ZExt:
1100  case Instruction::SExt:
1101  case Instruction::FPToUI:
1102  case Instruction::FPToSI:
1103  case Instruction::FPExt:
1104  case Instruction::PtrToInt:
1105  case Instruction::IntToPtr:
1106  case Instruction::SIToFP:
1107  case Instruction::UIToFP:
1108  case Instruction::Trunc:
1109  case Instruction::FPTrunc:
1110  case Instruction::BitCast:
1111  case Instruction::AddrSpaceCast:
1112  case Instruction::ExtractElement:
1113  case Instruction::InsertElement:
1114  case Instruction::ExtractValue:
1115  case Instruction::ShuffleVector:
1116  case Instruction::Call:
1117  case Instruction::Switch:
1118  return getUserCost(I, CostKind);
1119  default:
1120  // We don't have any information on this instruction.
1121  return -1;
1122  }
1123 }
1124 
1126 
1127 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1128 
1130  std::function<Result(const Function &)> TTICallback)
1131  : TTICallback(std::move(TTICallback)) {}
1132 
1135  return TTICallback(F);
1136 }
1137 
1138 AnalysisKey TargetIRAnalysis::Key;
1139 
1140 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1141  return Result(F.getParent()->getDataLayout());
1142 }
1143 
1144 // Register the basic pass.
1146  "Target Transform Information", false, true)
1148 
1149 void TargetTransformInfoWrapperPass::anchor() {}
1150 
1152  : ImmutablePass(ID) {
1155 }
1156 
1158  TargetIRAnalysis TIRA)
1159  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1162 }
1163 
1165  FunctionAnalysisManager DummyFAM;
1166  TTI = TIRA.run(F, DummyFAM);
1167  return *TTI;
1168 }
1169 
1170 ImmutablePass *
1172  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1173 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:280
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:946
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2331
llvm::predecessors
pred_range predecessors(BasicBlock *BB)
Definition: CFG.h:127
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1338
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:298
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:286
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:599
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, int Index=0, VectorType *SubTp=nullptr) const
Definition: TargetTransformInfo.cpp:726
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1286
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:590
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:880
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:808
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1151
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:360
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:594
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:592
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:827
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1041
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1164
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:889
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:366
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:431
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:868
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:267
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:335
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfo::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfo.cpp:967
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:100
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:3963
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1381
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:462
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:100
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:616
llvm::dyn_cast
LLVM_NODISCARD std::enable_if_t< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type > dyn_cast(const Y &Val)
Definition: Casting.h:334
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:475
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:535
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:187
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:98
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:392
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:387
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:799
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:228
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:545
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:201
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:572
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:239
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1303
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:562
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:161
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:505
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:486
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1030
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:948
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:262
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:105
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:320
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:115
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:401
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
Instruction.h
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1049
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:962
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1335
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:454
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:101
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:611
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:356
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:737
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:941
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:987
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:527
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:859
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:372
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1062
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:236
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:129
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1383
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:232
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1007
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:555
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:884
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1053
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:973
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:410
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:128
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
Definition: TargetTransformInfo.cpp:348
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:382
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:240
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:310
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:641
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:107
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:855
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:535
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
LoopIterator.h
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:422
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:406
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:531
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1171
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:248
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
Definition: TargetTransformInfo.cpp:1125
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:77
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:466
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfo.cpp:607
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:414
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:252
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:396
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2387
llvm::TargetTransformInfo::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported.
Definition: TargetTransformInfo.cpp:293
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1035
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:856
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:881
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2333
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:660
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:585
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:428
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:928
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:967
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:886
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:621
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:515
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:480
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:271
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:847
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1609
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:440
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:911
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:995
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:206
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:331
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:517
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:276
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:780
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:878
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:953
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1309
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:364
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:444
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:427
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:761
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:491
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:501
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1012
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:377
llvm::TargetTransformInfo::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:458
llvm::TargetTransformInfo::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:219
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:418
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:303
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:632
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:581
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:639
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:652
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:879
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1016
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:991
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:12720
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1127
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:414
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:603
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:637
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:627
std
Definition: BitVector.h:838
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:509
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:99
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:153
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:257
llvm::TypeSize
Definition: TypeSize.h:417
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:983
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:513
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:177
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1133
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:192
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:819
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:197
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:838
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:212
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2317
llvm::TargetTransformInfo::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:920
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:902
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:907
Dominators.h
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:645
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:978
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:352
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1045
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:326
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1023
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:47
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1001
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:937
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:495
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfo.cpp:1057
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:876
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:665
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:791
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3212
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:714
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:448
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:471
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3068
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
Definition: TargetTransformInfo.cpp:182
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:231
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:882
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:932
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:452
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:102
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:656
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:539
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:7336
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:154
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:244
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:339
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:896
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid())
Definition: TargetTransformInfo.cpp:57