LLVM 19.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/Analysis/CFG.h"
13#include "llvm/IR/CFG.h"
14#include "llvm/IR/Dominators.h"
15#include "llvm/IR/Instruction.h"
18#include "llvm/IR/Module.h"
19#include "llvm/IR/Operator.h"
23#include <optional>
24#include <utility>
25
26using namespace llvm;
27using namespace PatternMatch;
28
29#define DEBUG_TYPE "tti"
30
31static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33 cl::desc("Recognize reduction patterns."));
34
36 "cache-line-size", cl::init(0), cl::Hidden,
37 cl::desc("Use this to override the target cache line size when "
38 "specified by the user."));
39
41 "min-page-size", cl::init(0), cl::Hidden,
42 cl::desc("Use this to override the target's minimum page size."));
43
45 "predictable-branch-threshold", cl::init(99), cl::Hidden,
47 "Use this to override the target's predictable branch threshold (%)."));
48
49namespace {
50/// No-op implementation of the TTI interface using the utility base
51/// classes.
52///
53/// This is used when no target specific information is available.
54struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
55 explicit NoTTIImpl(const DataLayout &DL)
56 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
57};
58} // namespace
59
61 // If the loop has irreducible control flow, it can not be converted to
62 // Hardware loop.
63 LoopBlocksRPO RPOT(L);
64 RPOT.perform(&LI);
65 if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
66 return false;
67 return true;
68}
69
71 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
72 bool TypeBasedOnly)
73 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
74 ScalarizationCost(ScalarizationCost) {
75
76 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
77 FMF = FPMO->getFastMathFlags();
78
79 if (!TypeBasedOnly)
80 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
82 ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
83}
84
87 FastMathFlags Flags,
88 const IntrinsicInst *I,
89 InstructionCost ScalarCost)
90 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
91 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
92}
93
96 : RetTy(Ty), IID(Id) {
97
98 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
99 ParamTys.reserve(Arguments.size());
100 for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
101 ParamTys.push_back(Arguments[Idx]->getType());
102}
103
107 FastMathFlags Flags,
108 const IntrinsicInst *I,
109 InstructionCost ScalarCost)
110 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
111 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
112 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
113}
114
116 // Match default options:
117 // - hardware-loop-counter-bitwidth = 32
118 // - hardware-loop-decrement = 1
120 LoopDecrement = ConstantInt::get(CountType, 1);
121}
122
124 LoopInfo &LI, DominatorTree &DT,
125 bool ForceNestedLoop,
127 SmallVector<BasicBlock *, 4> ExitingBlocks;
128 L->getExitingBlocks(ExitingBlocks);
129
130 for (BasicBlock *BB : ExitingBlocks) {
131 // If we pass the updated counter back through a phi, we need to know
132 // which latch the updated value will be coming from.
133 if (!L->isLoopLatch(BB)) {
135 continue;
136 }
137
138 const SCEV *EC = SE.getExitCount(L, BB);
139 if (isa<SCEVCouldNotCompute>(EC))
140 continue;
141 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
142 if (ConstEC->getValue()->isZero())
143 continue;
144 } else if (!SE.isLoopInvariant(EC, L))
145 continue;
146
147 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
148 continue;
149
150 // If this exiting block is contained in a nested loop, it is not eligible
151 // for insertion of the branch-and-decrement since the inner loop would
152 // end up messing up the value in the CTR.
153 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
154 continue;
155
156 // We now have a loop-invariant count of loop iterations (which is not the
157 // constant zero) for which we know that this loop will not exit via this
158 // existing block.
159
160 // We need to make sure that this block will run on every loop iteration.
161 // For this to be true, we must dominate all blocks with backedges. Such
162 // blocks are in-loop predecessors to the header block.
163 bool NotAlways = false;
164 for (BasicBlock *Pred : predecessors(L->getHeader())) {
165 if (!L->contains(Pred))
166 continue;
167
168 if (!DT.dominates(BB, Pred)) {
169 NotAlways = true;
170 break;
171 }
172 }
173
174 if (NotAlways)
175 continue;
176
177 // Make sure this blocks ends with a conditional branch.
178 Instruction *TI = BB->getTerminator();
179 if (!TI)
180 continue;
181
182 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
183 if (!BI->isConditional())
184 continue;
185
186 ExitBranch = BI;
187 } else
188 continue;
189
190 // Note that this block may not be the loop latch block, even if the loop
191 // has a latch block.
192 ExitBlock = BB;
193 ExitCount = EC;
194 break;
195 }
196
197 if (!ExitBlock)
198 return false;
199 return true;
200}
201
203 : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
204
206
208 : TTIImpl(std::move(Arg.TTIImpl)) {}
209
211 TTIImpl = std::move(RHS.TTIImpl);
212 return *this;
213}
214
216 return TTIImpl->getInliningThresholdMultiplier();
217}
218
219unsigned
221 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
222}
223
224unsigned
226 const {
227 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
228}
229
230unsigned
232 return TTIImpl->adjustInliningThreshold(CB);
233}
234
236 const AllocaInst *AI) const {
237 return TTIImpl->getCallerAllocaCost(CB, AI);
238}
239
241 return TTIImpl->getInlinerVectorBonusPercent();
242}
243
245 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
246 Type *AccessType, TTI::TargetCostKind CostKind) const {
247 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, AccessType, CostKind);
248}
249
252 const TTI::PointersChainInfo &Info, Type *AccessTy,
254 assert((Base || !Info.isSameBase()) &&
255 "If pointers have same base address it has to be provided.");
256 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
257}
258
260 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
261 BlockFrequencyInfo *BFI) const {
262 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
263}
264
268 enum TargetCostKind CostKind) const {
269 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
271 "TTI should not produce negative costs!");
272 return Cost;
273}
274
276 return PredictableBranchThreshold.getNumOccurrences() > 0
278 : TTIImpl->getPredictableBranchThreshold();
279}
280
282 return TTIImpl->hasBranchDivergence(F);
283}
284
286 return TTIImpl->isSourceOfDivergence(V);
287}
288
290 return TTIImpl->isAlwaysUniform(V);
291}
292
294 unsigned ToAS) const {
295 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
296}
297
299 unsigned ToAS) const {
300 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
301}
302
304 return TTIImpl->getFlatAddressSpace();
305}
306
308 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
309 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
310}
311
313 unsigned ToAS) const {
314 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
315}
316
318 unsigned AS) const {
319 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
320}
321
323 return TTIImpl->getAssumedAddrSpace(V);
324}
325
327 return TTIImpl->isSingleThreaded();
328}
329
330std::pair<const Value *, unsigned>
332 return TTIImpl->getPredicatedAddrSpace(V);
333}
334
336 IntrinsicInst *II, Value *OldV, Value *NewV) const {
337 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
338}
339
341 return TTIImpl->isLoweredToCall(F);
342}
343
346 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
347 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
348}
349
351 TailFoldingInfo *TFI) const {
352 return TTIImpl->preferPredicateOverEpilogue(TFI);
353}
354
356 bool IVUpdateMayOverflow) const {
357 return TTIImpl->getPreferredTailFoldingStyle(IVUpdateMayOverflow);
358}
359
360std::optional<Instruction *>
362 IntrinsicInst &II) const {
363 return TTIImpl->instCombineIntrinsic(IC, II);
364}
365
367 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
368 bool &KnownBitsComputed) const {
369 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
370 KnownBitsComputed);
371}
372
374 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
375 APInt &UndefElts2, APInt &UndefElts3,
376 std::function<void(Instruction *, unsigned, APInt, APInt &)>
377 SimplifyAndSetOp) const {
378 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
379 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
380 SimplifyAndSetOp);
381}
382
385 OptimizationRemarkEmitter *ORE) const {
386 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
387}
388
390 PeelingPreferences &PP) const {
391 return TTIImpl->getPeelingPreferences(L, SE, PP);
392}
393
395 return TTIImpl->isLegalAddImmediate(Imm);
396}
397
399 return TTIImpl->isLegalICmpImmediate(Imm);
400}
401
403 int64_t BaseOffset,
404 bool HasBaseReg, int64_t Scale,
405 unsigned AddrSpace,
406 Instruction *I) const {
407 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
408 Scale, AddrSpace, I);
409}
410
412 const LSRCost &C2) const {
413 return TTIImpl->isLSRCostLess(C1, C2);
414}
415
417 return TTIImpl->isNumRegsMajorCostOfLSR();
418}
419
421 return TTIImpl->shouldFoldTerminatingConditionAfterLSR();
422}
423
425 return TTIImpl->isProfitableLSRChainElement(I);
426}
427
429 return TTIImpl->canMacroFuseCmp();
430}
431
433 ScalarEvolution *SE, LoopInfo *LI,
435 TargetLibraryInfo *LibInfo) const {
436 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
437}
438
441 ScalarEvolution *SE) const {
442 return TTIImpl->getPreferredAddressingMode(L, SE);
443}
444
446 Align Alignment) const {
447 return TTIImpl->isLegalMaskedStore(DataType, Alignment);
448}
449
451 Align Alignment) const {
452 return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
453}
454
456 Align Alignment) const {
457 return TTIImpl->isLegalNTStore(DataType, Alignment);
458}
459
460bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
461 return TTIImpl->isLegalNTLoad(DataType, Alignment);
462}
463
465 ElementCount NumElements) const {
466 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
467}
468
470 Align Alignment) const {
471 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
472}
473
475 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
476 const SmallBitVector &OpcodeMask) const {
477 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
478}
479
481 Align Alignment) const {
482 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
483}
484
486 Align Alignment) const {
487 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
488}
489
491 Align Alignment) const {
492 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
493}
494
496 return TTIImpl->isLegalMaskedCompressStore(DataType);
497}
498
500 return TTIImpl->isLegalMaskedExpandLoad(DataType);
501}
502
504 Align Alignment) const {
505 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
506}
507
509 return TTIImpl->enableOrderedReductions();
510}
511
512bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
513 return TTIImpl->hasDivRemOp(DataType, IsSigned);
514}
515
517 unsigned AddrSpace) const {
518 return TTIImpl->hasVolatileVariant(I, AddrSpace);
519}
520
522 return TTIImpl->prefersVectorizedAddressing();
523}
524
526 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
527 int64_t Scale, unsigned AddrSpace) const {
528 InstructionCost Cost = TTIImpl->getScalingFactorCost(
529 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
530 assert(Cost >= 0 && "TTI should not produce negative costs!");
531 return Cost;
532}
533
535 return TTIImpl->LSRWithInstrQueries();
536}
537
539 return TTIImpl->isTruncateFree(Ty1, Ty2);
540}
541
543 return TTIImpl->isProfitableToHoist(I);
544}
545
546bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
547
549 return TTIImpl->isTypeLegal(Ty);
550}
551
553 return TTIImpl->getRegUsageForType(Ty);
554}
555
557 return TTIImpl->shouldBuildLookupTables();
558}
559
561 Constant *C) const {
562 return TTIImpl->shouldBuildLookupTablesForConstant(C);
563}
564
566 return TTIImpl->shouldBuildRelLookupTables();
567}
568
570 return TTIImpl->useColdCCForColdCall(F);
571}
572
574 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
576 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
577 CostKind);
578}
579
583 return TTIImpl->getOperandsScalarizationOverhead(Args, Tys, CostKind);
584}
585
587 return TTIImpl->supportsEfficientVectorElementLoadStore();
588}
589
591 return TTIImpl->supportsTailCalls();
592}
593
595 return TTIImpl->supportsTailCallFor(CB);
596}
597
599 bool LoopHasReductions) const {
600 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
601}
602
604TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
605 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
606}
607
609 return TTIImpl->enableSelectOptimize();
610}
611
613 const Instruction *I) const {
614 return TTIImpl->shouldTreatInstructionLikeSelect(I);
615}
616
618 return TTIImpl->enableInterleavedAccessVectorization();
619}
620
622 return TTIImpl->enableMaskedInterleavedAccessVectorization();
623}
624
626 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
627}
628
629bool
631 unsigned BitWidth,
632 unsigned AddressSpace,
633 Align Alignment,
634 unsigned *Fast) const {
635 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
636 AddressSpace, Alignment, Fast);
637}
638
640TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
641 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
642}
643
645 return TTIImpl->haveFastSqrt(Ty);
646}
647
649 const Instruction *I) const {
650 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
651}
652
654 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
655}
656
658 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
659 assert(Cost >= 0 && "TTI should not produce negative costs!");
660 return Cost;
661}
662
664 unsigned Idx,
665 const APInt &Imm,
666 Type *Ty) const {
667 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
668 assert(Cost >= 0 && "TTI should not produce negative costs!");
669 return Cost;
670}
671
675 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
676 assert(Cost >= 0 && "TTI should not produce negative costs!");
677 return Cost;
678}
679
681 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
684 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
685 assert(Cost >= 0 && "TTI should not produce negative costs!");
686 return Cost;
687}
688
691 const APInt &Imm, Type *Ty,
694 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
695 assert(Cost >= 0 && "TTI should not produce negative costs!");
696 return Cost;
697}
698
700 const Instruction &Inst, const Function &Fn) const {
701 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
702}
703
704unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
705 return TTIImpl->getNumberOfRegisters(ClassID);
706}
707
709 Type *Ty) const {
710 return TTIImpl->getRegisterClassForType(Vector, Ty);
711}
712
713const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
714 return TTIImpl->getRegisterClassName(ClassID);
715}
716
719 return TTIImpl->getRegisterBitWidth(K);
720}
721
723 return TTIImpl->getMinVectorRegisterBitWidth();
724}
725
726std::optional<unsigned> TargetTransformInfo::getMaxVScale() const {
727 return TTIImpl->getMaxVScale();
728}
729
730std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
731 return TTIImpl->getVScaleForTuning();
732}
733
735 return TTIImpl->isVScaleKnownToBeAPowerOfTwo();
736}
737
740 return TTIImpl->shouldMaximizeVectorBandwidth(K);
741}
742
744 bool IsScalable) const {
745 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
746}
747
748unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
749 unsigned Opcode) const {
750 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
751}
752
753unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
754 Type *ScalarValTy) const {
755 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
756}
757
759 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
760 return TTIImpl->shouldConsiderAddressTypePromotion(
761 I, AllowPromotionWithoutCommonHeader);
762}
763
765 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
766 : TTIImpl->getCacheLineSize();
767}
768
769std::optional<unsigned>
771 return TTIImpl->getCacheSize(Level);
772}
773
774std::optional<unsigned>
776 return TTIImpl->getCacheAssociativity(Level);
777}
778
779std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
780 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
781 : TTIImpl->getMinPageSize();
782}
783
785 return TTIImpl->getPrefetchDistance();
786}
787
789 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
790 unsigned NumPrefetches, bool HasCall) const {
791 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
792 NumPrefetches, HasCall);
793}
794
796 return TTIImpl->getMaxPrefetchIterationsAhead();
797}
798
800 return TTIImpl->enableWritePrefetching();
801}
802
804 return TTIImpl->shouldPrefetchAddressSpace(AS);
805}
806
808 return TTIImpl->getMaxInterleaveFactor(VF);
809}
810
815
816 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
817 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
818 if (CI->getValue().isPowerOf2())
819 OpProps = OP_PowerOf2;
820 else if (CI->getValue().isNegatedPowerOf2())
821 OpProps = OP_NegatedPowerOf2;
822 }
823 return {OK_UniformConstantValue, OpProps};
824 }
825
826 // A broadcast shuffle creates a uniform value.
827 // TODO: Add support for non-zero index broadcasts.
828 // TODO: Add support for different source vector width.
829 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
830 if (ShuffleInst->isZeroEltSplat())
831 OpInfo = OK_UniformValue;
832
833 const Value *Splat = getSplatValue(V);
834
835 // Check for a splat of a constant or for a non uniform vector of constants
836 // and check if the constant(s) are all powers of two.
837 if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
839 if (Splat) {
841 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
842 if (CI->getValue().isPowerOf2())
843 OpProps = OP_PowerOf2;
844 else if (CI->getValue().isNegatedPowerOf2())
845 OpProps = OP_NegatedPowerOf2;
846 }
847 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
848 bool AllPow2 = true, AllNegPow2 = true;
849 for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
850 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
851 AllPow2 &= CI->getValue().isPowerOf2();
852 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
853 if (AllPow2 || AllNegPow2)
854 continue;
855 }
856 AllPow2 = AllNegPow2 = false;
857 break;
858 }
859 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
860 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
861 }
862 }
863
864 // Check for a splat of a uniform value. This is not loop aware, so return
865 // true only for the obviously uniform cases (argument, globalvalue)
866 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
867 OpInfo = OK_UniformValue;
868
869 return {OpInfo, OpProps};
870}
871
873 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
874 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
875 ArrayRef<const Value *> Args, const Instruction *CxtI) const {
877 TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
878 Op1Info, Op2Info,
879 Args, CxtI);
880 assert(Cost >= 0 && "TTI should not produce negative costs!");
881 return Cost;
882}
883
885 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
886 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
888 TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
889 assert(Cost >= 0 && "TTI should not produce negative costs!");
890 return Cost;
891}
892
894 ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
896 ArrayRef<const Value *> Args) const {
898 TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind, Index, SubTp, Args);
899 assert(Cost >= 0 && "TTI should not produce negative costs!");
900 return Cost;
901}
902
905 if (!I)
907
908 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
909 unsigned GatScatOp) {
910 const Instruction *I = dyn_cast<Instruction>(V);
911 if (!I)
913
914 if (I->getOpcode() == LdStOp)
916
917 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
918 if (II->getIntrinsicID() == MaskedOp)
920 if (II->getIntrinsicID() == GatScatOp)
922 }
923
925 };
926
927 switch (I->getOpcode()) {
928 case Instruction::ZExt:
929 case Instruction::SExt:
930 case Instruction::FPExt:
931 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
932 Intrinsic::masked_load, Intrinsic::masked_gather);
933 case Instruction::Trunc:
934 case Instruction::FPTrunc:
935 if (I->hasOneUse())
936 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
937 Intrinsic::masked_store,
938 Intrinsic::masked_scatter);
939 break;
940 default:
942 }
943
945}
946
948 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
950 assert((I == nullptr || I->getOpcode() == Opcode) &&
951 "Opcode should reflect passed instruction.");
953 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
954 assert(Cost >= 0 && "TTI should not produce negative costs!");
955 return Cost;
956}
957
959 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
961 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
962 assert(Cost >= 0 && "TTI should not produce negative costs!");
963 return Cost;
964}
965
967 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
968 assert((I == nullptr || I->getOpcode() == Opcode) &&
969 "Opcode should reflect passed instruction.");
970 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
971 assert(Cost >= 0 && "TTI should not produce negative costs!");
972 return Cost;
973}
974
976 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
978 assert((I == nullptr || I->getOpcode() == Opcode) &&
979 "Opcode should reflect passed instruction.");
981 TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
982 assert(Cost >= 0 && "TTI should not produce negative costs!");
983 return Cost;
984}
985
987 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
988 Value *Op0, Value *Op1) const {
989 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
990 // This is mentioned in the interface description and respected by all
991 // callers, but never asserted upon.
993 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1);
994 assert(Cost >= 0 && "TTI should not produce negative costs!");
995 return Cost;
996}
997
1001 unsigned Index) const {
1002 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1003 // This is mentioned in the interface description and respected by all
1004 // callers, but never asserted upon.
1005 InstructionCost Cost = TTIImpl->getVectorInstrCost(I, Val, CostKind, Index);
1006 assert(Cost >= 0 && "TTI should not produce negative costs!");
1007 return Cost;
1008}
1009
1011 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1013 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1014 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1015 assert(Cost >= 0 && "TTI should not produce negative costs!");
1016 return Cost;
1017}
1018
1020 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1022 const Instruction *I) const {
1023 assert((I == nullptr || I->getOpcode() == Opcode) &&
1024 "Opcode should reflect passed instruction.");
1025 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1026 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1027 assert(Cost >= 0 && "TTI should not produce negative costs!");
1028 return Cost;
1029}
1030
1032 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1034 InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
1036 assert(Cost >= 0 && "TTI should not produce negative costs!");
1037 return Cost;
1038}
1039
1041 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1042 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1043 InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
1044 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1045 assert((!Cost.isValid() || Cost >= 0) &&
1046 "TTI should not produce negative costs!");
1047 return Cost;
1048}
1049
1051 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1052 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
1053 InstructionCost Cost = TTIImpl->getStridedMemoryOpCost(
1054 Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
1055 assert(Cost >= 0 && "TTI should not produce negative costs!");
1056 return Cost;
1057}
1058
1060 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1061 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1062 bool UseMaskForCond, bool UseMaskForGaps) const {
1063 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1064 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1065 UseMaskForCond, UseMaskForGaps);
1066 assert(Cost >= 0 && "TTI should not produce negative costs!");
1067 return Cost;
1068}
1069
1073 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1074 assert(Cost >= 0 && "TTI should not produce negative costs!");
1075 return Cost;
1076}
1077
1080 ArrayRef<Type *> Tys,
1082 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1083 assert(Cost >= 0 && "TTI should not produce negative costs!");
1084 return Cost;
1085}
1086
1088 return TTIImpl->getNumberOfParts(Tp);
1089}
1090
1093 const SCEV *Ptr) const {
1094 InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
1095 assert(Cost >= 0 && "TTI should not produce negative costs!");
1096 return Cost;
1097}
1098
1100 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1101 assert(Cost >= 0 && "TTI should not produce negative costs!");
1102 return Cost;
1103}
1104
1106 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1107}
1108
1110 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1113 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1114 assert(Cost >= 0 && "TTI should not produce negative costs!");
1115 return Cost;
1116}
1117
1122 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1123 assert(Cost >= 0 && "TTI should not produce negative costs!");
1124 return Cost;
1125}
1126
1128 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1130 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1131 CostKind);
1132}
1133
1135 bool IsUnsigned, Type *ResTy, VectorType *Ty,
1137 return TTIImpl->getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
1138}
1139
1142 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1143}
1144
1146 MemIntrinsicInfo &Info) const {
1147 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1148}
1149
1151 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1152}
1153
1155 IntrinsicInst *Inst, Type *ExpectedType) const {
1156 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
1157}
1158
1160 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1161 unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
1162 std::optional<uint32_t> AtomicElementSize) const {
1163 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1164 DestAddrSpace, SrcAlign, DestAlign,
1165 AtomicElementSize);
1166}
1167
1169 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1170 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1171 unsigned SrcAlign, unsigned DestAlign,
1172 std::optional<uint32_t> AtomicCpySize) const {
1173 TTIImpl->getMemcpyLoopResidualLoweringType(
1174 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1175 DestAlign, AtomicCpySize);
1176}
1177
1179 const Function *Callee) const {
1180 return TTIImpl->areInlineCompatible(Caller, Callee);
1181}
1182
1183unsigned
1185 const CallBase &Call,
1186 unsigned DefaultCallPenalty) const {
1187 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1188}
1189
1191 const Function *Caller, const Function *Callee,
1192 const ArrayRef<Type *> &Types) const {
1193 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1194}
1195
1197 Type *Ty) const {
1198 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1199}
1200
1202 Type *Ty) const {
1203 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1204}
1205
1207 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1208}
1209
1211 return TTIImpl->isLegalToVectorizeLoad(LI);
1212}
1213
1215 return TTIImpl->isLegalToVectorizeStore(SI);
1216}
1217
1219 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1220 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1221 AddrSpace);
1222}
1223
1225 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1226 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1227 AddrSpace);
1228}
1229
1231 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1232 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1233}
1234
1236 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1237}
1238
1240 unsigned LoadSize,
1241 unsigned ChainSizeInBytes,
1242 VectorType *VecTy) const {
1243 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1244}
1245
1247 unsigned StoreSize,
1248 unsigned ChainSizeInBytes,
1249 VectorType *VecTy) const {
1250 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1251}
1252
1254 ReductionFlags Flags) const {
1255 return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1256}
1257
1259 unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1260 return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1261}
1262
1264 return TTIImpl->preferEpilogueVectorization();
1265}
1266
1269 return TTIImpl->getVPLegalizationStrategy(VPI);
1270}
1271
1273 return TTIImpl->hasArmWideBranch(Thumb);
1274}
1275
1277 return TTIImpl->getMaxNumArgs();
1278}
1279
1281 return TTIImpl->shouldExpandReduction(II);
1282}
1283
1285 return TTIImpl->getGISelRematGlobalCost();
1286}
1287
1289 return TTIImpl->getMinTripCountTailFoldingThreshold();
1290}
1291
1293 return TTIImpl->supportsScalableVectors();
1294}
1295
1297 return TTIImpl->enableScalableVectorization();
1298}
1299
1300bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
1301 Align Alignment) const {
1302 return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
1303}
1304
1306
1307TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1308
1310 std::function<Result(const Function &)> TTICallback)
1311 : TTICallback(std::move(TTICallback)) {}
1312
1315 return TTICallback(F);
1316}
1317
1318AnalysisKey TargetIRAnalysis::Key;
1319
1320TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1321 return Result(F.getParent()->getDataLayout());
1322}
1323
1324// Register the basic pass.
1326 "Target Transform Information", false, true)
1328
1329void TargetTransformInfoWrapperPass::anchor() {}
1330
1332 : ImmutablePass(ID) {
1335}
1336
1338 TargetIRAnalysis TIRA)
1339 : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1342}
1343
1345 FunctionAnalysisManager DummyFAM;
1346 TTI = TIRA.run(F, DummyFAM);
1347 return *TTI;
1348}
1349
1352 return new TargetTransformInfoWrapperPass(std::move(TIRA));
1353}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Value * RHS
Class for arbitrary precision integers.
Definition: APInt.h:76
an instruction to allocate memory on the stack
Definition: Instructions.h:59
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:348
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:154
iterator begin() const
Definition: ArrayRef.h:153
A cache of @llvm.assume calls within a function.
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
LLVMContext & getContext() const
Get the context in which this basic block lives.
Definition: BasicBlock.cpp:150
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1455
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
Definition: InstrTypes.h:1703
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1623
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1629
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:965
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:122
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
Class to represent function types.
Definition: DerivedTypes.h:103
param_iterator param_begin() const
Definition: DerivedTypes.h:128
param_iterator param_end() const
Definition: DerivedTypes.h:129
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:200
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
The core instruction combiner logic.
Definition: InstCombiner.h:47
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:72
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
bool isLoopLatch(const BlockT *BB) const
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
The optimization diagnostic interface.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
Multiway switch.
Analysis pass providing the TargetTransformInfo.
Result run(const Function &F, FunctionAnalysisManager &)
TargetTransformInfo Result
TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
bool isLegalToVectorizeLoad(LoadInst *LI) const
std::optional< unsigned > getVScaleForTuning() const
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
bool isLegalToVectorizeStore(StoreInst *SI) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
bool isAlwaysUniform(const Value *V) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
bool shouldFoldTerminatingConditionAfterLSR() const
Return true if LSR should attempts to replace a use of an otherwise dead primary IV in the latch cond...
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
bool isProfitableLSRChainElement(Instruction *I) const
TypeSize getRegisterBitWidth(RegisterKind K) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
std::optional< unsigned > getMaxVScale() const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
unsigned getAtomicMemIntrinsicMaxElementSize() const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
Query the target what the preferred style of tail folding is.
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType=nullptr, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
unsigned getMaxPrefetchIterationsAhead() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF=FastMathFlags(), TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned adjustInliningThreshold(const CallBase *CB) const
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
unsigned getMinVectorRegisterBitWidth() const
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
bool hasArmWideBranch(bool Thumb) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
const char * getRegisterClassName(unsigned ClassID) const
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=std::nullopt, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=std::nullopt) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
PopcntSupportKind
Flags indicating the kind of support for population count.
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
unsigned getInliningThresholdMultiplier() const
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
std::optional< unsigned > getMinPageSize() const
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
std::optional< unsigned > getCacheSize(CacheLevel Level) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
unsigned getMinTripCountTailFoldingThreshold() const
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
unsigned getMaxInterleaveFactor(ElementCount VF) const
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
unsigned getGISelRematGlobalCost() const
MemIndexedMode
The type of load/store indexing.
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
bool supportsTailCalls() const
If the target supports tail calls.
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
unsigned getNumberOfParts(Type *Tp) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
Estimate the overhead of scalarizing an instruction.
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
bool shouldExpandReduction(const IntrinsicInst *II) const
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, Value *Op0=nullptr, Value *Op1=nullptr) const
ShuffleKind
The various kinds of shuffle patterns for vector queries.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static IntegerType * getInt32Ty(LLVMContext &C)
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition: Casting.h:649
AddressSpace
Definition: NVPTXBaseInfo.h:21
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
auto predecessors(const MachineBasicBlock *BB)
InstructionCost Cost
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: Analysis.h:26
Attributes of a target dependent hardware loop.
bool canAnalyze(LoopInfo &LI)
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.