LLVM  14.0.0git
TargetTransformInfo.cpp
Go to the documentation of this file.
1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/Analysis/CFG.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33  cl::Hidden,
34  cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42  explicit NoTTIImpl(const DataLayout &DL)
43  : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
48  // If the loop has irreducible control flow, it can not be converted to
49  // Hardware loop.
50  LoopBlocksRPO RPOT(L);
51  RPOT.perform(&LI);
52  if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53  return false;
54  return true;
55 }
56 
58  Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost)
59  : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
60  ScalarizationCost(ScalarizationCost) {
61 
62  if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
63  FMF = FPMO->getFastMathFlags();
64 
65  Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
67  ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
68 }
69 
71  ArrayRef<Type *> Tys,
72  FastMathFlags Flags,
73  const IntrinsicInst *I,
74  InstructionCost ScalarCost)
75  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
76  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
77 }
78 
81  : RetTy(Ty), IID(Id) {
82 
83  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
84  ParamTys.reserve(Arguments.size());
85  for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
86  ParamTys.push_back(Arguments[Idx]->getType());
87 }
88 
91  ArrayRef<Type *> Tys,
92  FastMathFlags Flags,
93  const IntrinsicInst *I,
94  InstructionCost ScalarCost)
95  : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
96  ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
97  Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
98 }
99 
101  LoopInfo &LI, DominatorTree &DT,
102  bool ForceNestedLoop,
103  bool ForceHardwareLoopPHI) {
104  SmallVector<BasicBlock *, 4> ExitingBlocks;
105  L->getExitingBlocks(ExitingBlocks);
106 
107  for (BasicBlock *BB : ExitingBlocks) {
108  // If we pass the updated counter back through a phi, we need to know
109  // which latch the updated value will be coming from.
110  if (!L->isLoopLatch(BB)) {
112  continue;
113  }
114 
115  const SCEV *EC = SE.getExitCount(L, BB);
116  if (isa<SCEVCouldNotCompute>(EC))
117  continue;
118  if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
119  if (ConstEC->getValue()->isZero())
120  continue;
121  } else if (!SE.isLoopInvariant(EC, L))
122  continue;
123 
124  if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
125  continue;
126 
127  // If this exiting block is contained in a nested loop, it is not eligible
128  // for insertion of the branch-and-decrement since the inner loop would
129  // end up messing up the value in the CTR.
130  if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
131  continue;
132 
133  // We now have a loop-invariant count of loop iterations (which is not the
134  // constant zero) for which we know that this loop will not exit via this
135  // existing block.
136 
137  // We need to make sure that this block will run on every loop iteration.
138  // For this to be true, we must dominate all blocks with backedges. Such
139  // blocks are in-loop predecessors to the header block.
140  bool NotAlways = false;
141  for (BasicBlock *Pred : predecessors(L->getHeader())) {
142  if (!L->contains(Pred))
143  continue;
144 
145  if (!DT.dominates(BB, Pred)) {
146  NotAlways = true;
147  break;
148  }
149  }
150 
151  if (NotAlways)
152  continue;
153 
154  // Make sure this blocks ends with a conditional branch.
155  Instruction *TI = BB->getTerminator();
156  if (!TI)
157  continue;
158 
159  if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
160  if (!BI->isConditional())
161  continue;
162 
163  ExitBranch = BI;
164  } else
165  continue;
166 
167  // Note that this block may not be the loop latch block, even if the loop
168  // has a latch block.
169  ExitBlock = BB;
170  TripCount = SE.getAddExpr(EC, SE.getOne(EC->getType()));
171 
172  if (!EC->getType()->isPointerTy() && EC->getType() != CountType)
174 
175  break;
176  }
177 
178  if (!ExitBlock)
179  return false;
180  return true;
181 }
182 
184  : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
185 
187 
189  : TTIImpl(std::move(Arg.TTIImpl)) {}
190 
192  TTIImpl = std::move(RHS.TTIImpl);
193  return *this;
194 }
195 
197  return TTIImpl->getInliningThresholdMultiplier();
198 }
199 
200 unsigned
202  return TTIImpl->adjustInliningThreshold(CB);
203 }
204 
206  return TTIImpl->getInlinerVectorBonusPercent();
207 }
208 
210 TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
213  return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
214 }
215 
217  const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
218  BlockFrequencyInfo *BFI) const {
219  return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
220 }
221 
225  enum TargetCostKind CostKind) const {
226  InstructionCost Cost = TTIImpl->getUserCost(U, Operands, CostKind);
227  assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
228  "TTI should not produce negative costs!");
229  return Cost;
230 }
231 
233  return TTIImpl->getPredictableBranchThreshold();
234 }
235 
237  return TTIImpl->hasBranchDivergence();
238 }
239 
241  return TTIImpl->useGPUDivergenceAnalysis();
242 }
243 
245  return TTIImpl->isSourceOfDivergence(V);
246 }
247 
249  return TTIImpl->isAlwaysUniform(V);
250 }
251 
253  return TTIImpl->getFlatAddressSpace();
254 }
255 
257  SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
258  return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
259 }
260 
262  unsigned ToAS) const {
263  return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
264 }
265 
267  return TTIImpl->getAssumedAddrSpace(V);
268 }
269 
271  IntrinsicInst *II, Value *OldV, Value *NewV) const {
272  return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
273 }
274 
276  return TTIImpl->isLoweredToCall(F);
277 }
278 
280  Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
281  TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
282  return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
283 }
284 
286  Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
288  const LoopAccessInfo *LAI) const {
289  return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
290 }
291 
293  return TTIImpl->emitGetActiveLaneMask();
294 }
295 
298  IntrinsicInst &II) const {
299  return TTIImpl->instCombineIntrinsic(IC, II);
300 }
301 
303  InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
304  bool &KnownBitsComputed) const {
305  return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
306  KnownBitsComputed);
307 }
308 
310  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
311  APInt &UndefElts2, APInt &UndefElts3,
312  std::function<void(Instruction *, unsigned, APInt, APInt &)>
313  SimplifyAndSetOp) const {
314  return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
315  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
316  SimplifyAndSetOp);
317 }
318 
321  OptimizationRemarkEmitter *ORE) const {
322  return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
323 }
324 
326  PeelingPreferences &PP) const {
327  return TTIImpl->getPeelingPreferences(L, SE, PP);
328 }
329 
331  return TTIImpl->isLegalAddImmediate(Imm);
332 }
333 
335  return TTIImpl->isLegalICmpImmediate(Imm);
336 }
337 
339  int64_t BaseOffset,
340  bool HasBaseReg, int64_t Scale,
341  unsigned AddrSpace,
342  Instruction *I) const {
343  return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
344  Scale, AddrSpace, I);
345 }
346 
348  return TTIImpl->isLSRCostLess(C1, C2);
349 }
350 
352  return TTIImpl->isNumRegsMajorCostOfLSR();
353 }
354 
356  return TTIImpl->isProfitableLSRChainElement(I);
357 }
358 
360  return TTIImpl->canMacroFuseCmp();
361 }
362 
364  ScalarEvolution *SE, LoopInfo *LI,
366  TargetLibraryInfo *LibInfo) const {
367  return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
368 }
369 
372  ScalarEvolution *SE) const {
373  return TTIImpl->getPreferredAddressingMode(L, SE);
374 }
375 
377  Align Alignment) const {
378  return TTIImpl->isLegalMaskedStore(DataType, Alignment);
379 }
380 
382  Align Alignment) const {
383  return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
384 }
385 
387  Align Alignment) const {
388  return TTIImpl->isLegalNTStore(DataType, Alignment);
389 }
390 
391 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
392  return TTIImpl->isLegalNTLoad(DataType, Alignment);
393 }
394 
396  Align Alignment) const {
397  return TTIImpl->isLegalMaskedGather(DataType, Alignment);
398 }
399 
401  Align Alignment) const {
402  return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
403 }
404 
406  return TTIImpl->isLegalMaskedCompressStore(DataType);
407 }
408 
410  return TTIImpl->isLegalMaskedExpandLoad(DataType);
411 }
412 
413 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
414  return TTIImpl->hasDivRemOp(DataType, IsSigned);
415 }
416 
418  unsigned AddrSpace) const {
419  return TTIImpl->hasVolatileVariant(I, AddrSpace);
420 }
421 
423  return TTIImpl->prefersVectorizedAddressing();
424 }
425 
427  Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
428  int64_t Scale, unsigned AddrSpace) const {
429  InstructionCost Cost = TTIImpl->getScalingFactorCost(
430  Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
431  assert(Cost >= 0 && "TTI should not produce negative costs!");
432  return Cost;
433 }
434 
436  return TTIImpl->LSRWithInstrQueries();
437 }
438 
440  return TTIImpl->isTruncateFree(Ty1, Ty2);
441 }
442 
444  return TTIImpl->isProfitableToHoist(I);
445 }
446 
447 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
448 
450  return TTIImpl->isTypeLegal(Ty);
451 }
452 
454  return TTIImpl->getRegUsageForType(Ty);
455 }
456 
458  return TTIImpl->shouldBuildLookupTables();
459 }
460 
462  Constant *C) const {
463  return TTIImpl->shouldBuildLookupTablesForConstant(C);
464 }
465 
467  return TTIImpl->shouldBuildRelLookupTables();
468 }
469 
471  return TTIImpl->useColdCCForColdCall(F);
472 }
473 
476  const APInt &DemandedElts,
477  bool Insert, bool Extract) const {
478  return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
479 }
480 
483  return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
484 }
485 
487  return TTIImpl->supportsEfficientVectorElementLoadStore();
488 }
489 
491  bool LoopHasReductions) const {
492  return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
493 }
494 
496 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
497  return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
498 }
499 
501  return TTIImpl->enableInterleavedAccessVectorization();
502 }
503 
505  return TTIImpl->enableMaskedInterleavedAccessVectorization();
506 }
507 
509  return TTIImpl->isFPVectorizationPotentiallyUnsafe();
510 }
511 
513  unsigned BitWidth,
514  unsigned AddressSpace,
515  Align Alignment,
516  bool *Fast) const {
517  return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
518  AddressSpace, Alignment, Fast);
519 }
520 
522 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
523  return TTIImpl->getPopcntSupport(IntTyWidthInBit);
524 }
525 
527  return TTIImpl->haveFastSqrt(Ty);
528 }
529 
531  return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
532 }
533 
535  InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
536  assert(Cost >= 0 && "TTI should not produce negative costs!");
537  return Cost;
538 }
539 
541  unsigned Idx,
542  const APInt &Imm,
543  Type *Ty) const {
544  InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
545  assert(Cost >= 0 && "TTI should not produce negative costs!");
546  return Cost;
547 }
548 
552  InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
553  assert(Cost >= 0 && "TTI should not produce negative costs!");
554  return Cost;
555 }
556 
558  unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
560  InstructionCost Cost =
561  TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
562  assert(Cost >= 0 && "TTI should not produce negative costs!");
563  return Cost;
564 }
565 
568  const APInt &Imm, Type *Ty,
570  InstructionCost Cost =
571  TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
572  assert(Cost >= 0 && "TTI should not produce negative costs!");
573  return Cost;
574 }
575 
576 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
577  return TTIImpl->getNumberOfRegisters(ClassID);
578 }
579 
581  Type *Ty) const {
582  return TTIImpl->getRegisterClassForType(Vector, Ty);
583 }
584 
585 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
586  return TTIImpl->getRegisterClassName(ClassID);
587 }
588 
591  return TTIImpl->getRegisterBitWidth(K);
592 }
593 
595  return TTIImpl->getMinVectorRegisterBitWidth();
596 }
597 
599  return TTIImpl->getMaxVScale();
600 }
601 
603  return TTIImpl->shouldMaximizeVectorBandwidth();
604 }
605 
607  bool IsScalable) const {
608  return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
609 }
610 
611 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
612  unsigned Opcode) const {
613  return TTIImpl->getMaximumVF(ElemWidth, Opcode);
614 }
615 
617  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
618  return TTIImpl->shouldConsiderAddressTypePromotion(
619  I, AllowPromotionWithoutCommonHeader);
620 }
621 
623  return TTIImpl->getCacheLineSize();
624 }
625 
628  return TTIImpl->getCacheSize(Level);
629 }
630 
633  return TTIImpl->getCacheAssociativity(Level);
634 }
635 
637  return TTIImpl->getPrefetchDistance();
638 }
639 
641  unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
642  unsigned NumPrefetches, bool HasCall) const {
643  return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
644  NumPrefetches, HasCall);
645 }
646 
648  return TTIImpl->getMaxPrefetchIterationsAhead();
649 }
650 
652  return TTIImpl->enableWritePrefetching();
653 }
654 
655 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
656  return TTIImpl->getMaxInterleaveFactor(VF);
657 }
658 
661  OperandValueProperties &OpProps) {
662  OperandValueKind OpInfo = OK_AnyValue;
663  OpProps = OP_None;
664 
665  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
666  if (CI->getValue().isPowerOf2())
667  OpProps = OP_PowerOf2;
669  }
670 
671  // A broadcast shuffle creates a uniform value.
672  // TODO: Add support for non-zero index broadcasts.
673  // TODO: Add support for different source vector width.
674  if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
675  if (ShuffleInst->isZeroEltSplat())
676  OpInfo = OK_UniformValue;
677 
678  const Value *Splat = getSplatValue(V);
679 
680  // Check for a splat of a constant or for a non uniform vector of constants
681  // and check if the constant(s) are all powers of two.
682  if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
684  if (Splat) {
685  OpInfo = OK_UniformConstantValue;
686  if (auto *CI = dyn_cast<ConstantInt>(Splat))
687  if (CI->getValue().isPowerOf2())
688  OpProps = OP_PowerOf2;
689  } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
690  OpProps = OP_PowerOf2;
691  for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
692  if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
693  if (CI->getValue().isPowerOf2())
694  continue;
695  OpProps = OP_None;
696  break;
697  }
698  }
699  }
700 
701  // Check for a splat of a uniform value. This is not loop aware, so return
702  // true only for the obviously uniform cases (argument, globalvalue)
703  if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
704  OpInfo = OK_UniformValue;
705 
706  return OpInfo;
707 }
708 
710  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
711  OperandValueKind Opd1Info, OperandValueKind Opd2Info,
712  OperandValueProperties Opd1PropInfo, OperandValueProperties Opd2PropInfo,
713  ArrayRef<const Value *> Args, const Instruction *CxtI) const {
714  InstructionCost Cost =
715  TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
716  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
717  assert(Cost >= 0 && "TTI should not produce negative costs!");
718  return Cost;
719 }
720 
722  VectorType *Ty,
724  int Index,
725  VectorType *SubTp) const {
726  InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
727  assert(Cost >= 0 && "TTI should not produce negative costs!");
728  return Cost;
729 }
730 
733  if (!I)
734  return CastContextHint::None;
735 
736  auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
737  unsigned GatScatOp) {
738  const Instruction *I = dyn_cast<Instruction>(V);
739  if (!I)
740  return CastContextHint::None;
741 
742  if (I->getOpcode() == LdStOp)
744 
745  if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
746  if (II->getIntrinsicID() == MaskedOp)
748  if (II->getIntrinsicID() == GatScatOp)
750  }
751 
753  };
754 
755  switch (I->getOpcode()) {
756  case Instruction::ZExt:
757  case Instruction::SExt:
758  case Instruction::FPExt:
759  return getLoadStoreKind(I->getOperand(0), Instruction::Load,
760  Intrinsic::masked_load, Intrinsic::masked_gather);
761  case Instruction::Trunc:
762  case Instruction::FPTrunc:
763  if (I->hasOneUse())
764  return getLoadStoreKind(*I->user_begin(), Instruction::Store,
765  Intrinsic::masked_store,
766  Intrinsic::masked_scatter);
767  break;
768  default:
769  return CastContextHint::None;
770  }
771 
773 }
774 
776  unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
777  TTI::TargetCostKind CostKind, const Instruction *I) const {
778  assert((I == nullptr || I->getOpcode() == Opcode) &&
779  "Opcode should reflect passed instruction.");
780  InstructionCost Cost =
781  TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
782  assert(Cost >= 0 && "TTI should not produce negative costs!");
783  return Cost;
784 }
785 
787  unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const {
788  InstructionCost Cost =
789  TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
790  assert(Cost >= 0 && "TTI should not produce negative costs!");
791  return Cost;
792 }
793 
795  unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
796  assert((I == nullptr || I->getOpcode() == Opcode) &&
797  "Opcode should reflect passed instruction.");
798  InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
799  assert(Cost >= 0 && "TTI should not produce negative costs!");
800  return Cost;
801 }
802 
804  unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
805  TTI::TargetCostKind CostKind, const Instruction *I) const {
806  assert((I == nullptr || I->getOpcode() == Opcode) &&
807  "Opcode should reflect passed instruction.");
808  InstructionCost Cost =
809  TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
810  assert(Cost >= 0 && "TTI should not produce negative costs!");
811  return Cost;
812 }
813 
815  Type *Val,
816  unsigned Index) const {
817  InstructionCost Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
818  assert(Cost >= 0 && "TTI should not produce negative costs!");
819  return Cost;
820 }
821 
823  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
824  TTI::TargetCostKind CostKind, const Instruction *I) const {
825  assert((I == nullptr || I->getOpcode() == Opcode) &&
826  "Opcode should reflect passed instruction.");
827  InstructionCost Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment,
829  assert(Cost >= 0 && "TTI should not produce negative costs!");
830  return Cost;
831 }
832 
834  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
836  InstructionCost Cost = TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment,
838  assert(Cost >= 0 && "TTI should not produce negative costs!");
839  return Cost;
840 }
841 
843  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
844  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
845  InstructionCost Cost = TTIImpl->getGatherScatterOpCost(
846  Opcode, DataTy, Ptr, VariableMask, Alignment, CostKind, I);
847  assert(Cost >= 0 && "TTI should not produce negative costs!");
848  return Cost;
849 }
850 
852  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
853  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
854  bool UseMaskForCond, bool UseMaskForGaps) const {
855  InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
856  Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
857  UseMaskForCond, UseMaskForGaps);
858  assert(Cost >= 0 && "TTI should not produce negative costs!");
859  return Cost;
860 }
861 
865  InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
866  assert(Cost >= 0 && "TTI should not produce negative costs!");
867  return Cost;
868 }
869 
872  ArrayRef<Type *> Tys,
874  InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
875  assert(Cost >= 0 && "TTI should not produce negative costs!");
876  return Cost;
877 }
878 
880  return TTIImpl->getNumberOfParts(Tp);
881 }
882 
885  const SCEV *Ptr) const {
886  InstructionCost Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
887  assert(Cost >= 0 && "TTI should not produce negative costs!");
888  return Cost;
889 }
890 
892  InstructionCost Cost = TTIImpl->getMemcpyCost(I);
893  assert(Cost >= 0 && "TTI should not produce negative costs!");
894  return Cost;
895 }
896 
898  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
900  InstructionCost Cost =
901  TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
902  assert(Cost >= 0 && "TTI should not produce negative costs!");
903  return Cost;
904 }
905 
907  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
909  InstructionCost Cost =
910  TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
911  assert(Cost >= 0 && "TTI should not produce negative costs!");
912  return Cost;
913 }
914 
916  bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
918  return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
919  CostKind);
920 }
921 
924  return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
925 }
926 
928  MemIntrinsicInfo &Info) const {
929  return TTIImpl->getTgtMemIntrinsic(Inst, Info);
930 }
931 
933  return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
934 }
935 
937  IntrinsicInst *Inst, Type *ExpectedType) const {
938  return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
939 }
940 
942  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
943  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
944  return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
945  DestAddrSpace, SrcAlign, DestAlign);
946 }
947 
950  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
951  unsigned SrcAlign, unsigned DestAlign) const {
952  TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
953  SrcAddrSpace, DestAddrSpace,
954  SrcAlign, DestAlign);
955 }
956 
958  const Function *Callee) const {
959  return TTIImpl->areInlineCompatible(Caller, Callee);
960 }
961 
963  const Function *Caller, const Function *Callee,
965  return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
966 }
967 
969  Type *Ty) const {
970  return TTIImpl->isIndexedLoadLegal(Mode, Ty);
971 }
972 
974  Type *Ty) const {
975  return TTIImpl->isIndexedStoreLegal(Mode, Ty);
976 }
977 
979  return TTIImpl->getLoadStoreVecRegBitWidth(AS);
980 }
981 
983  return TTIImpl->isLegalToVectorizeLoad(LI);
984 }
985 
987  return TTIImpl->isLegalToVectorizeStore(SI);
988 }
989 
991  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
992  return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
993  AddrSpace);
994 }
995 
997  unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
998  return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
999  AddrSpace);
1000 }
1001 
1003  const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1004  return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1005 }
1006 
1008  return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1009 }
1010 
1012  unsigned LoadSize,
1013  unsigned ChainSizeInBytes,
1014  VectorType *VecTy) const {
1015  return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1016 }
1017 
1019  unsigned StoreSize,
1020  unsigned ChainSizeInBytes,
1021  VectorType *VecTy) const {
1022  return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1023 }
1024 
1026  ReductionFlags Flags) const {
1027  return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1028 }
1029 
1031  unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1032  return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1033 }
1034 
1037  return TTIImpl->getVPLegalizationStrategy(VPI);
1038 }
1039 
1041  return TTIImpl->shouldExpandReduction(II);
1042 }
1043 
1045  return TTIImpl->getGISelRematGlobalCost();
1046 }
1047 
1049  return TTIImpl->supportsScalableVectors();
1050 }
1051 
1053  return TTIImpl->hasActiveVectorLength();
1054 }
1055 
1057 TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1058  return TTIImpl->getInstructionLatency(I);
1059 }
1060 
1062 TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1064 
1065  switch (I->getOpcode()) {
1066  case Instruction::GetElementPtr:
1067  case Instruction::Ret:
1068  case Instruction::PHI:
1069  case Instruction::Br:
1070  case Instruction::Add:
1071  case Instruction::FAdd:
1072  case Instruction::Sub:
1073  case Instruction::FSub:
1074  case Instruction::Mul:
1075  case Instruction::FMul:
1076  case Instruction::UDiv:
1077  case Instruction::SDiv:
1078  case Instruction::FDiv:
1079  case Instruction::URem:
1080  case Instruction::SRem:
1081  case Instruction::FRem:
1082  case Instruction::Shl:
1083  case Instruction::LShr:
1084  case Instruction::AShr:
1085  case Instruction::And:
1086  case Instruction::Or:
1087  case Instruction::Xor:
1088  case Instruction::FNeg:
1089  case Instruction::Select:
1090  case Instruction::ICmp:
1091  case Instruction::FCmp:
1092  case Instruction::Store:
1093  case Instruction::Load:
1094  case Instruction::ZExt:
1095  case Instruction::SExt:
1096  case Instruction::FPToUI:
1097  case Instruction::FPToSI:
1098  case Instruction::FPExt:
1099  case Instruction::PtrToInt:
1100  case Instruction::IntToPtr:
1101  case Instruction::SIToFP:
1102  case Instruction::UIToFP:
1103  case Instruction::Trunc:
1104  case Instruction::FPTrunc:
1105  case Instruction::BitCast:
1106  case Instruction::AddrSpaceCast:
1107  case Instruction::ExtractElement:
1108  case Instruction::InsertElement:
1109  case Instruction::ExtractValue:
1110  case Instruction::ShuffleVector:
1111  case Instruction::Call:
1112  case Instruction::Switch:
1113  return getUserCost(I, CostKind);
1114  default:
1115  // We don't have any information on this instruction.
1116  return -1;
1117  }
1118 }
1119 
1121 
1122 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1123 
1125  std::function<Result(const Function &)> TTICallback)
1126  : TTICallback(std::move(TTICallback)) {}
1127 
1130  return TTICallback(F);
1131 }
1132 
1133 AnalysisKey TargetIRAnalysis::Key;
1134 
1135 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1136  return Result(F.getParent()->getDataLayout());
1137 }
1138 
1139 // Register the basic pass.
1141  "Target Transform Information", false, true)
1143 
1144 void TargetTransformInfoWrapperPass::anchor() {}
1145 
1147  : ImmutablePass(ID) {
1150 }
1151 
1153  TargetIRAnalysis TIRA)
1154  : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1157 }
1158 
1160  FunctionAnalysisManager DummyFAM;
1161  TTI = TIRA.run(F, DummyFAM);
1162  return *TTI;
1163 }
1164 
1165 ImmutablePass *
1167  return new TargetTransformInfoWrapperPass(std::move(TIRA));
1168 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:279
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:941
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2313
llvm::predecessors
pred_range predecessors(BasicBlock *BB)
Definition: CFG.h:127
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1331
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:297
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:285
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:594
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, int Index=0, VectorType *SubTp=nullptr) const
Definition: TargetTransformInfo.cpp:721
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1279
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
IntrinsicInst.h
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:585
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:873
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1146
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:359
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:589
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:588
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:822
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1036
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1159
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:884
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:360
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:426
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:863
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:266
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:334
llvm::initializeTargetTransformInfoWrapperPassPass
void initializeTargetTransformInfoWrapperPassPass(PassRegistry &)
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:151
llvm::TargetTransformInfo::areFunctionArgsABICompatible
bool areFunctionArgsABICompatible(const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
Definition: TargetTransformInfo.cpp:962
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:100
llvm::ScalarEvolution::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
Definition: ScalarEvolution.cpp:3921
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1374
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:457
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:100
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:611
llvm::dyn_cast
LLVM_NODISCARD std::enable_if_t< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type > dyn_cast(const Y &Val)
Definition: Casting.h:334
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:470
Module.h
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:531
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:191
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:98
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:391
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:386
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:794
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:879
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:232
Operator.h
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:540
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:205
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:567
llvm::LoopBase::isLoopLatch
bool isLoopLatch(const BlockT *BB) const
Definition: LoopInfo.h:239
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1303
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:557
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: Operator.h:161
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:500
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:481
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1025
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:941
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
F
#define F(x, y, z)
Definition: MD5.cpp:56
TargetTransformInfoImpl.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:105
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::LoopBlocksRPO
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
Definition: LoopIterator.h:172
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:319
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::DominatorTree::dominates
bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Definition: Dominators.cpp:115
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:400
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
Instruction.h
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1044
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:957
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1292
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:449
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:606
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:355
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:732
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:936
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:982
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::ScalarEvolution::getOne
const SCEV * getOne(Type *Ty)
Return a SCEV for the constant 1 of a specific type.
Definition: ScalarEvolution.h:607
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:522
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:879
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:852
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
EnableReduxCost
static cl::opt< bool > EnableReduxCost("costmodel-reduxcost", cl::init(false), cl::Hidden, cl::desc("Recognize reduction patterns."))
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:371
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1055
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:240
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:128
llvm::CallBase::getCalledFunction
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1393
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:236
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1002
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:550
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:879
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1048
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:968
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:409
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:127
llvm::Instruction
Definition: Instruction.h:45
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C1.
Definition: TargetTransformInfo.cpp:347
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:381
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:244
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:309
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:636
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:107
llvm::TargetTransformInfoImplCRTPBase
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Definition: TargetTransformInfoImpl.h:850
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:530
PatternMatch.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
LoopIterator.h
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:417
CFG.h
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:405
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:526
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1166
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:252
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:388
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
Definition: TargetTransformInfo.cpp:1120
llvm::cl::opt< bool >
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:461
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth() const
Definition: TargetTransformInfo.cpp:602
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:410
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:256
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:395
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2369
llvm::TargetTransformInfo::emitGetActiveLaneMask
bool emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported.
Definition: TargetTransformInfo.cpp:292
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1030
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:851
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:874
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2315
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:655
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:580
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:72
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:424
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:923
llvm::LoopInfoBase::getLoopFor
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Definition: LoopInfo.h:967
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:879
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:616
llvm::LoopAccessInfo
Drive the analysis of memory accesses in the loop.
Definition: LoopAccessAnalysis.h:525
llvm::SCEVConstant
This class represents a constant integer value.
Definition: ScalarEvolutionExpressions.h:47
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:475
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:270
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:842
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1605
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:435
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:906
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:990
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:210
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:330
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), bool *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:512
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:275
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:775
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:871
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: TargetTransformInfo.cpp:948
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1309
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:363
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:439
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:422
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:754
CFG.h
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:486
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:496
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1083
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
DataLayout.h
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:41
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1007
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:376
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfo::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:453
llvm::TargetTransformInfo::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:223
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy=nullptr, CmpInst::Predicate VecPred=CmpInst::BAD_ICMP_PREDICATE, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:803
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:413
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:302
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:627
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:576
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:635
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:647
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:872
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1011
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:986
llvm::ScalarEvolution::isLoopInvariant
bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
Definition: ScalarEvolution.cpp:13027
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1122
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:598
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:632
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:622
std
Definition: BitVector.h:838
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:504
llvm::KnownBits
Definition: KnownBits.h:23
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:99
llvm::ArrayRef::begin
iterator begin() const
Definition: ArrayRef.h:153
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:390
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:261
llvm::TypeSize
Definition: TypeSize.h:417
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:978
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:508
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:219
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:175
llvm::HardwareLoopInfo::TripCount
const SCEV * TripCount
Definition: TargetTransformInfo.h:101
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1128
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:196
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:814
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:201
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:833
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:95
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:216
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2299
llvm::TargetTransformInfo::getExtendedAddReductionCost
InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:915
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:67
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:897
llvm::ScalarEvolution::getZeroExtendExpr
const SCEV * getZeroExtendExpr(const SCEV *Op, Type *Ty, unsigned Depth=0)
Definition: ScalarEvolution.cpp:1577
Instructions.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:900
Dominators.h
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:71
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:640
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:973
TargetTransformInfo.h
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:351
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1040
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:325
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1018
llvm::HardwareLoopInfo::canAnalyze
bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:47
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:996
llvm::SmallVectorImpl< int >
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:70
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:932
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:490
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
llvm::ScalarEvolution::getAddExpr
const SCEV * getAddExpr(SmallVectorImpl< const SCEV * > &Ops, SCEV::NoWrapFlags Flags=SCEV::FlagAnyWrap, unsigned Depth=0)
Get a canonical add expression, or something simpler if possible.
Definition: ScalarEvolution.cpp:2401
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength() const
Definition: TargetTransformInfo.cpp:1052
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:871
llvm::TargetTransformInfo::getOperandInfo
static OperandValueKind getOperandInfo(const Value *V, OperandValueProperties &OpProps)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:660
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:786
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3206
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueKind Opd1Info=OK_AnyValue, OperandValueKind Opd2Info=OK_AnyValue, OperandValueProperties Opd1PropInfo=OP_None, OperandValueProperties Opd2PropInfo=OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:709
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:414
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:443
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:466
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3062
llvm::LoopBlocksRPO::perform
void perform(LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
Definition: LoopIterator.h:180
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
Definition: TargetTransformInfo.cpp:186
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:875
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:927
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:447
InitializePasses.h
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:102
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:651
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:534
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::ScalarEvolution::getExitCount
const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
Definition: ScalarEvolution.cpp:7253
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:154
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:248
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:338
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:891
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:102
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid())
Definition: TargetTransformInfo.cpp:57