LLVM 20.0.0git
VectorUtils.cpp
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1//===----------- VectorUtils.cpp - Vectorizer utility functions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines vectorizer utilities.
10//
11//===----------------------------------------------------------------------===//
12
23#include "llvm/IR/Constants.h"
25#include "llvm/IR/IRBuilder.h"
28#include "llvm/IR/Value.h"
30
31#define DEBUG_TYPE "vectorutils"
32
33using namespace llvm;
34using namespace llvm::PatternMatch;
35
36/// Maximum factor for an interleaved memory access.
38 "max-interleave-group-factor", cl::Hidden,
39 cl::desc("Maximum factor for an interleaved access group (default = 8)"),
40 cl::init(8));
41
42/// Return true if all of the intrinsic's arguments and return type are scalars
43/// for the scalar form of the intrinsic, and vectors for the vector form of the
44/// intrinsic (except operands that are marked as always being scalar by
45/// isVectorIntrinsicWithScalarOpAtArg).
47 switch (ID) {
48 case Intrinsic::abs: // Begin integer bit-manipulation.
49 case Intrinsic::bswap:
50 case Intrinsic::bitreverse:
51 case Intrinsic::ctpop:
52 case Intrinsic::ctlz:
53 case Intrinsic::cttz:
54 case Intrinsic::fshl:
55 case Intrinsic::fshr:
56 case Intrinsic::smax:
57 case Intrinsic::smin:
58 case Intrinsic::umax:
59 case Intrinsic::umin:
60 case Intrinsic::sadd_sat:
61 case Intrinsic::ssub_sat:
62 case Intrinsic::uadd_sat:
63 case Intrinsic::usub_sat:
64 case Intrinsic::smul_fix:
65 case Intrinsic::smul_fix_sat:
66 case Intrinsic::umul_fix:
67 case Intrinsic::umul_fix_sat:
68 case Intrinsic::sqrt: // Begin floating-point.
69 case Intrinsic::sin:
70 case Intrinsic::cos:
71 case Intrinsic::tan:
72 case Intrinsic::exp:
73 case Intrinsic::exp2:
74 case Intrinsic::log:
75 case Intrinsic::log10:
76 case Intrinsic::log2:
77 case Intrinsic::fabs:
78 case Intrinsic::minnum:
79 case Intrinsic::maxnum:
80 case Intrinsic::minimum:
81 case Intrinsic::maximum:
82 case Intrinsic::copysign:
83 case Intrinsic::floor:
84 case Intrinsic::ceil:
85 case Intrinsic::trunc:
86 case Intrinsic::rint:
87 case Intrinsic::nearbyint:
88 case Intrinsic::round:
89 case Intrinsic::roundeven:
90 case Intrinsic::pow:
91 case Intrinsic::fma:
92 case Intrinsic::fmuladd:
93 case Intrinsic::is_fpclass:
94 case Intrinsic::powi:
95 case Intrinsic::canonicalize:
96 case Intrinsic::fptosi_sat:
97 case Intrinsic::fptoui_sat:
98 case Intrinsic::lrint:
99 case Intrinsic::llrint:
100 return true;
101 default:
102 return false;
103 }
104}
105
106/// Identifies if the vector form of the intrinsic has a scalar operand.
108 unsigned ScalarOpdIdx) {
109 switch (ID) {
110 case Intrinsic::abs:
111 case Intrinsic::ctlz:
112 case Intrinsic::cttz:
113 case Intrinsic::is_fpclass:
114 case Intrinsic::powi:
115 return (ScalarOpdIdx == 1);
116 case Intrinsic::smul_fix:
117 case Intrinsic::smul_fix_sat:
118 case Intrinsic::umul_fix:
119 case Intrinsic::umul_fix_sat:
120 return (ScalarOpdIdx == 2);
121 default:
122 return false;
123 }
124}
125
127 int OpdIdx) {
128 assert(ID != Intrinsic::not_intrinsic && "Not an intrinsic!");
129
130 switch (ID) {
131 case Intrinsic::fptosi_sat:
132 case Intrinsic::fptoui_sat:
133 case Intrinsic::lrint:
134 case Intrinsic::llrint:
135 return OpdIdx == -1 || OpdIdx == 0;
136 case Intrinsic::is_fpclass:
137 return OpdIdx == 0;
138 case Intrinsic::powi:
139 return OpdIdx == -1 || OpdIdx == 1;
140 default:
141 return OpdIdx == -1;
142 }
143}
144
145/// Returns intrinsic ID for call.
146/// For the input call instruction it finds mapping intrinsic and returns
147/// its ID, in case it does not found it return not_intrinsic.
149 const TargetLibraryInfo *TLI) {
153
154 if (isTriviallyVectorizable(ID) || ID == Intrinsic::lifetime_start ||
155 ID == Intrinsic::lifetime_end || ID == Intrinsic::assume ||
156 ID == Intrinsic::experimental_noalias_scope_decl ||
157 ID == Intrinsic::sideeffect || ID == Intrinsic::pseudoprobe)
158 return ID;
160}
161
162/// Given a vector and an element number, see if the scalar value is
163/// already around as a register, for example if it were inserted then extracted
164/// from the vector.
165Value *llvm::findScalarElement(Value *V, unsigned EltNo) {
166 assert(V->getType()->isVectorTy() && "Not looking at a vector?");
167 VectorType *VTy = cast<VectorType>(V->getType());
168 // For fixed-length vector, return poison for out of range access.
169 if (auto *FVTy = dyn_cast<FixedVectorType>(VTy)) {
170 unsigned Width = FVTy->getNumElements();
171 if (EltNo >= Width)
172 return PoisonValue::get(FVTy->getElementType());
173 }
174
175 if (Constant *C = dyn_cast<Constant>(V))
176 return C->getAggregateElement(EltNo);
177
178 if (InsertElementInst *III = dyn_cast<InsertElementInst>(V)) {
179 // If this is an insert to a variable element, we don't know what it is.
180 if (!isa<ConstantInt>(III->getOperand(2)))
181 return nullptr;
182 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
183
184 // If this is an insert to the element we are looking for, return the
185 // inserted value.
186 if (EltNo == IIElt)
187 return III->getOperand(1);
188
189 // Guard against infinite loop on malformed, unreachable IR.
190 if (III == III->getOperand(0))
191 return nullptr;
192
193 // Otherwise, the insertelement doesn't modify the value, recurse on its
194 // vector input.
195 return findScalarElement(III->getOperand(0), EltNo);
196 }
197
198 ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(V);
199 // Restrict the following transformation to fixed-length vector.
200 if (SVI && isa<FixedVectorType>(SVI->getType())) {
201 unsigned LHSWidth =
202 cast<FixedVectorType>(SVI->getOperand(0)->getType())->getNumElements();
203 int InEl = SVI->getMaskValue(EltNo);
204 if (InEl < 0)
205 return PoisonValue::get(VTy->getElementType());
206 if (InEl < (int)LHSWidth)
207 return findScalarElement(SVI->getOperand(0), InEl);
208 return findScalarElement(SVI->getOperand(1), InEl - LHSWidth);
209 }
210
211 // Extract a value from a vector add operation with a constant zero.
212 // TODO: Use getBinOpIdentity() to generalize this.
213 Value *Val; Constant *C;
214 if (match(V, m_Add(m_Value(Val), m_Constant(C))))
215 if (Constant *Elt = C->getAggregateElement(EltNo))
216 if (Elt->isNullValue())
217 return findScalarElement(Val, EltNo);
218
219 // If the vector is a splat then we can trivially find the scalar element.
220 if (isa<ScalableVectorType>(VTy))
221 if (Value *Splat = getSplatValue(V))
222 if (EltNo < VTy->getElementCount().getKnownMinValue())
223 return Splat;
224
225 // Otherwise, we don't know.
226 return nullptr;
227}
228
230 int SplatIndex = -1;
231 for (int M : Mask) {
232 // Ignore invalid (undefined) mask elements.
233 if (M < 0)
234 continue;
235
236 // There can be only 1 non-negative mask element value if this is a splat.
237 if (SplatIndex != -1 && SplatIndex != M)
238 return -1;
239
240 // Initialize the splat index to the 1st non-negative mask element.
241 SplatIndex = M;
242 }
243 assert((SplatIndex == -1 || SplatIndex >= 0) && "Negative index?");
244 return SplatIndex;
245}
246
247/// Get splat value if the input is a splat vector or return nullptr.
248/// This function is not fully general. It checks only 2 cases:
249/// the input value is (1) a splat constant vector or (2) a sequence
250/// of instructions that broadcasts a scalar at element 0.
252 if (isa<VectorType>(V->getType()))
253 if (auto *C = dyn_cast<Constant>(V))
254 return C->getSplatValue();
255
256 // shuf (inselt ?, Splat, 0), ?, <0, undef, 0, ...>
257 Value *Splat;
258 if (match(V,
260 m_Value(), m_ZeroMask())))
261 return Splat;
262
263 return nullptr;
264}
265
266bool llvm::isSplatValue(const Value *V, int Index, unsigned Depth) {
267 assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");
268
269 if (isa<VectorType>(V->getType())) {
270 if (isa<UndefValue>(V))
271 return true;
272 // FIXME: We can allow undefs, but if Index was specified, we may want to
273 // check that the constant is defined at that index.
274 if (auto *C = dyn_cast<Constant>(V))
275 return C->getSplatValue() != nullptr;
276 }
277
278 if (auto *Shuf = dyn_cast<ShuffleVectorInst>(V)) {
279 // FIXME: We can safely allow undefs here. If Index was specified, we will
280 // check that the mask elt is defined at the required index.
281 if (!all_equal(Shuf->getShuffleMask()))
282 return false;
283
284 // Match any index.
285 if (Index == -1)
286 return true;
287
288 // Match a specific element. The mask should be defined at and match the
289 // specified index.
290 return Shuf->getMaskValue(Index) == Index;
291 }
292
293 // The remaining tests are all recursive, so bail out if we hit the limit.
295 return false;
296
297 // If both operands of a binop are splats, the result is a splat.
298 Value *X, *Y, *Z;
299 if (match(V, m_BinOp(m_Value(X), m_Value(Y))))
301
302 // If all operands of a select are splats, the result is a splat.
303 if (match(V, m_Select(m_Value(X), m_Value(Y), m_Value(Z))))
304 return isSplatValue(X, Index, Depth) && isSplatValue(Y, Index, Depth) &&
306
307 // TODO: Add support for unary ops (fneg), casts, intrinsics (overflow ops).
308
309 return false;
310}
311
313 const APInt &DemandedElts, APInt &DemandedLHS,
314 APInt &DemandedRHS, bool AllowUndefElts) {
315 DemandedLHS = DemandedRHS = APInt::getZero(SrcWidth);
316
317 // Early out if we don't demand any elements.
318 if (DemandedElts.isZero())
319 return true;
320
321 // Simple case of a shuffle with zeroinitializer.
322 if (all_of(Mask, [](int Elt) { return Elt == 0; })) {
323 DemandedLHS.setBit(0);
324 return true;
325 }
326
327 for (unsigned I = 0, E = Mask.size(); I != E; ++I) {
328 int M = Mask[I];
329 assert((-1 <= M) && (M < (SrcWidth * 2)) &&
330 "Invalid shuffle mask constant");
331
332 if (!DemandedElts[I] || (AllowUndefElts && (M < 0)))
333 continue;
334
335 // For undef elements, we don't know anything about the common state of
336 // the shuffle result.
337 if (M < 0)
338 return false;
339
340 if (M < SrcWidth)
341 DemandedLHS.setBit(M);
342 else
343 DemandedRHS.setBit(M - SrcWidth);
344 }
345
346 return true;
347}
348
350 SmallVectorImpl<int> &ScaledMask) {
351 assert(Scale > 0 && "Unexpected scaling factor");
352
353 // Fast-path: if no scaling, then it is just a copy.
354 if (Scale == 1) {
355 ScaledMask.assign(Mask.begin(), Mask.end());
356 return;
357 }
358
359 ScaledMask.clear();
360 for (int MaskElt : Mask) {
361 if (MaskElt >= 0) {
362 assert(((uint64_t)Scale * MaskElt + (Scale - 1)) <= INT32_MAX &&
363 "Overflowed 32-bits");
364 }
365 for (int SliceElt = 0; SliceElt != Scale; ++SliceElt)
366 ScaledMask.push_back(MaskElt < 0 ? MaskElt : Scale * MaskElt + SliceElt);
367 }
368}
369
371 SmallVectorImpl<int> &ScaledMask) {
372 assert(Scale > 0 && "Unexpected scaling factor");
373
374 // Fast-path: if no scaling, then it is just a copy.
375 if (Scale == 1) {
376 ScaledMask.assign(Mask.begin(), Mask.end());
377 return true;
378 }
379
380 // We must map the original elements down evenly to a type with less elements.
381 int NumElts = Mask.size();
382 if (NumElts % Scale != 0)
383 return false;
384
385 ScaledMask.clear();
386 ScaledMask.reserve(NumElts / Scale);
387
388 // Step through the input mask by splitting into Scale-sized slices.
389 do {
390 ArrayRef<int> MaskSlice = Mask.take_front(Scale);
391 assert((int)MaskSlice.size() == Scale && "Expected Scale-sized slice.");
392
393 // The first element of the slice determines how we evaluate this slice.
394 int SliceFront = MaskSlice.front();
395 if (SliceFront < 0) {
396 // Negative values (undef or other "sentinel" values) must be equal across
397 // the entire slice.
398 if (!all_equal(MaskSlice))
399 return false;
400 ScaledMask.push_back(SliceFront);
401 } else {
402 // A positive mask element must be cleanly divisible.
403 if (SliceFront % Scale != 0)
404 return false;
405 // Elements of the slice must be consecutive.
406 for (int i = 1; i < Scale; ++i)
407 if (MaskSlice[i] != SliceFront + i)
408 return false;
409 ScaledMask.push_back(SliceFront / Scale);
410 }
411 Mask = Mask.drop_front(Scale);
412 } while (!Mask.empty());
413
414 assert((int)ScaledMask.size() * Scale == NumElts && "Unexpected scaled mask");
415
416 // All elements of the original mask can be scaled down to map to the elements
417 // of a mask with wider elements.
418 return true;
419}
420
421bool llvm::scaleShuffleMaskElts(unsigned NumDstElts, ArrayRef<int> Mask,
422 SmallVectorImpl<int> &ScaledMask) {
423 unsigned NumSrcElts = Mask.size();
424 assert(NumSrcElts > 0 && NumDstElts > 0 && "Unexpected scaling factor");
425
426 // Fast-path: if no scaling, then it is just a copy.
427 if (NumSrcElts == NumDstElts) {
428 ScaledMask.assign(Mask.begin(), Mask.end());
429 return true;
430 }
431
432 // Ensure we can find a whole scale factor.
433 assert(((NumSrcElts % NumDstElts) == 0 || (NumDstElts % NumSrcElts) == 0) &&
434 "Unexpected scaling factor");
435
436 if (NumSrcElts > NumDstElts) {
437 int Scale = NumSrcElts / NumDstElts;
438 return widenShuffleMaskElts(Scale, Mask, ScaledMask);
439 }
440
441 int Scale = NumDstElts / NumSrcElts;
442 narrowShuffleMaskElts(Scale, Mask, ScaledMask);
443 return true;
444}
445
447 SmallVectorImpl<int> &ScaledMask) {
448 std::array<SmallVector<int, 16>, 2> TmpMasks;
449 SmallVectorImpl<int> *Output = &TmpMasks[0], *Tmp = &TmpMasks[1];
450 ArrayRef<int> InputMask = Mask;
451 for (unsigned Scale = 2; Scale <= InputMask.size(); ++Scale) {
452 while (widenShuffleMaskElts(Scale, InputMask, *Output)) {
453 InputMask = *Output;
454 std::swap(Output, Tmp);
455 }
456 }
457 ScaledMask.assign(InputMask.begin(), InputMask.end());
458}
459
461 ArrayRef<int> Mask, unsigned NumOfSrcRegs, unsigned NumOfDestRegs,
462 unsigned NumOfUsedRegs, function_ref<void()> NoInputAction,
463 function_ref<void(ArrayRef<int>, unsigned, unsigned)> SingleInputAction,
464 function_ref<void(ArrayRef<int>, unsigned, unsigned)> ManyInputsAction) {
465 SmallVector<SmallVector<SmallVector<int>>> Res(NumOfDestRegs);
466 // Try to perform better estimation of the permutation.
467 // 1. Split the source/destination vectors into real registers.
468 // 2. Do the mask analysis to identify which real registers are
469 // permuted.
470 int Sz = Mask.size();
471 unsigned SzDest = Sz / NumOfDestRegs;
472 unsigned SzSrc = Sz / NumOfSrcRegs;
473 for (unsigned I = 0; I < NumOfDestRegs; ++I) {
474 auto &RegMasks = Res[I];
475 RegMasks.assign(NumOfSrcRegs, {});
476 // Check that the values in dest registers are in the one src
477 // register.
478 for (unsigned K = 0; K < SzDest; ++K) {
479 int Idx = I * SzDest + K;
480 if (Idx == Sz)
481 break;
482 if (Mask[Idx] >= Sz || Mask[Idx] == PoisonMaskElem)
483 continue;
484 int SrcRegIdx = Mask[Idx] / SzSrc;
485 // Add a cost of PermuteTwoSrc for each new source register permute,
486 // if we have more than one source registers.
487 if (RegMasks[SrcRegIdx].empty())
488 RegMasks[SrcRegIdx].assign(SzDest, PoisonMaskElem);
489 RegMasks[SrcRegIdx][K] = Mask[Idx] % SzSrc;
490 }
491 }
492 // Process split mask.
493 for (unsigned I = 0; I < NumOfUsedRegs; ++I) {
494 auto &Dest = Res[I];
495 int NumSrcRegs =
496 count_if(Dest, [](ArrayRef<int> Mask) { return !Mask.empty(); });
497 switch (NumSrcRegs) {
498 case 0:
499 // No input vectors were used!
500 NoInputAction();
501 break;
502 case 1: {
503 // Find the only mask with at least single undef mask elem.
504 auto *It =
505 find_if(Dest, [](ArrayRef<int> Mask) { return !Mask.empty(); });
506 unsigned SrcReg = std::distance(Dest.begin(), It);
507 SingleInputAction(*It, SrcReg, I);
508 break;
509 }
510 default: {
511 // The first mask is a permutation of a single register. Since we have >2
512 // input registers to shuffle, we merge the masks for 2 first registers
513 // and generate a shuffle of 2 registers rather than the reordering of the
514 // first register and then shuffle with the second register. Next,
515 // generate the shuffles of the resulting register + the remaining
516 // registers from the list.
517 auto &&CombineMasks = [](MutableArrayRef<int> FirstMask,
518 ArrayRef<int> SecondMask) {
519 for (int Idx = 0, VF = FirstMask.size(); Idx < VF; ++Idx) {
520 if (SecondMask[Idx] != PoisonMaskElem) {
521 assert(FirstMask[Idx] == PoisonMaskElem &&
522 "Expected undefined mask element.");
523 FirstMask[Idx] = SecondMask[Idx] + VF;
524 }
525 }
526 };
527 auto &&NormalizeMask = [](MutableArrayRef<int> Mask) {
528 for (int Idx = 0, VF = Mask.size(); Idx < VF; ++Idx) {
529 if (Mask[Idx] != PoisonMaskElem)
530 Mask[Idx] = Idx;
531 }
532 };
533 int SecondIdx;
534 do {
535 int FirstIdx = -1;
536 SecondIdx = -1;
537 MutableArrayRef<int> FirstMask, SecondMask;
538 for (unsigned I = 0; I < NumOfDestRegs; ++I) {
539 SmallVectorImpl<int> &RegMask = Dest[I];
540 if (RegMask.empty())
541 continue;
542
543 if (FirstIdx == SecondIdx) {
544 FirstIdx = I;
545 FirstMask = RegMask;
546 continue;
547 }
548 SecondIdx = I;
549 SecondMask = RegMask;
550 CombineMasks(FirstMask, SecondMask);
551 ManyInputsAction(FirstMask, FirstIdx, SecondIdx);
552 NormalizeMask(FirstMask);
553 RegMask.clear();
554 SecondMask = FirstMask;
555 SecondIdx = FirstIdx;
556 }
557 if (FirstIdx != SecondIdx && SecondIdx >= 0) {
558 CombineMasks(SecondMask, FirstMask);
559 ManyInputsAction(SecondMask, SecondIdx, FirstIdx);
560 Dest[FirstIdx].clear();
561 NormalizeMask(SecondMask);
562 }
563 } while (SecondIdx >= 0);
564 break;
566 }
567 }
568}
569
570void llvm::getHorizDemandedEltsForFirstOperand(unsigned VectorBitWidth,
571 const APInt &DemandedElts,
572 APInt &DemandedLHS,
573 APInt &DemandedRHS) {
574 assert(VectorBitWidth >= 128 && "Vectors smaller than 128 bit not supported");
575 int NumLanes = VectorBitWidth / 128;
576 int NumElts = DemandedElts.getBitWidth();
577 int NumEltsPerLane = NumElts / NumLanes;
578 int HalfEltsPerLane = NumEltsPerLane / 2;
579
580 DemandedLHS = APInt::getZero(NumElts);
581 DemandedRHS = APInt::getZero(NumElts);
582
583 // Map DemandedElts to the horizontal operands.
584 for (int Idx = 0; Idx != NumElts; ++Idx) {
585 if (!DemandedElts[Idx])
586 continue;
587 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane;
588 int LocalIdx = Idx % NumEltsPerLane;
589 if (LocalIdx < HalfEltsPerLane) {
590 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx);
591 } else {
592 LocalIdx -= HalfEltsPerLane;
593 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx);
594 }
595 }
596}
597
600 const TargetTransformInfo *TTI) {
601
602 // DemandedBits will give us every value's live-out bits. But we want
603 // to ensure no extra casts would need to be inserted, so every DAG
604 // of connected values must have the same minimum bitwidth.
610 SmallPtrSet<Instruction *, 4> InstructionSet;
612
613 // Determine the roots. We work bottom-up, from truncs or icmps.
614 bool SeenExtFromIllegalType = false;
615 for (auto *BB : Blocks)
616 for (auto &I : *BB) {
617 InstructionSet.insert(&I);
618
619 if (TTI && (isa<ZExtInst>(&I) || isa<SExtInst>(&I)) &&
620 !TTI->isTypeLegal(I.getOperand(0)->getType()))
621 SeenExtFromIllegalType = true;
622
623 // Only deal with non-vector integers up to 64-bits wide.
624 if ((isa<TruncInst>(&I) || isa<ICmpInst>(&I)) &&
625 !I.getType()->isVectorTy() &&
626 I.getOperand(0)->getType()->getScalarSizeInBits() <= 64) {
627 // Don't make work for ourselves. If we know the loaded type is legal,
628 // don't add it to the worklist.
629 if (TTI && isa<TruncInst>(&I) && TTI->isTypeLegal(I.getType()))
630 continue;
631
632 Worklist.push_back(&I);
633 Roots.insert(&I);
634 }
635 }
636 // Early exit.
637 if (Worklist.empty() || (TTI && !SeenExtFromIllegalType))
638 return MinBWs;
639
640 // Now proceed breadth-first, unioning values together.
641 while (!Worklist.empty()) {
642 Value *Val = Worklist.pop_back_val();
643 Value *Leader = ECs.getOrInsertLeaderValue(Val);
644
645 if (!Visited.insert(Val).second)
646 continue;
647
648 // Non-instructions terminate a chain successfully.
649 if (!isa<Instruction>(Val))
650 continue;
651 Instruction *I = cast<Instruction>(Val);
652
653 // If we encounter a type that is larger than 64 bits, we can't represent
654 // it so bail out.
655 if (DB.getDemandedBits(I).getBitWidth() > 64)
657
658 uint64_t V = DB.getDemandedBits(I).getZExtValue();
659 DBits[Leader] |= V;
660 DBits[I] = V;
661
662 // Casts, loads and instructions outside of our range terminate a chain
663 // successfully.
664 if (isa<SExtInst>(I) || isa<ZExtInst>(I) || isa<LoadInst>(I) ||
665 !InstructionSet.count(I))
666 continue;
667
668 // Unsafe casts terminate a chain unsuccessfully. We can't do anything
669 // useful with bitcasts, ptrtoints or inttoptrs and it'd be unsafe to
670 // transform anything that relies on them.
671 if (isa<BitCastInst>(I) || isa<PtrToIntInst>(I) || isa<IntToPtrInst>(I) ||
672 !I->getType()->isIntegerTy()) {
673 DBits[Leader] |= ~0ULL;
674 continue;
675 }
676
677 // We don't modify the types of PHIs. Reductions will already have been
678 // truncated if possible, and inductions' sizes will have been chosen by
679 // indvars.
680 if (isa<PHINode>(I))
681 continue;
682
683 if (DBits[Leader] == ~0ULL)
684 // All bits demanded, no point continuing.
685 continue;
686
687 for (Value *O : cast<User>(I)->operands()) {
688 ECs.unionSets(Leader, O);
689 Worklist.push_back(O);
690 }
691 }
692
693 // Now we've discovered all values, walk them to see if there are
694 // any users we didn't see. If there are, we can't optimize that
695 // chain.
696 for (auto &I : DBits)
697 for (auto *U : I.first->users())
698 if (U->getType()->isIntegerTy() && DBits.count(U) == 0)
699 DBits[ECs.getOrInsertLeaderValue(I.first)] |= ~0ULL;
700
701 for (auto I = ECs.begin(), E = ECs.end(); I != E; ++I) {
702 uint64_t LeaderDemandedBits = 0;
703 for (Value *M : llvm::make_range(ECs.member_begin(I), ECs.member_end()))
704 LeaderDemandedBits |= DBits[M];
705
706 uint64_t MinBW = llvm::bit_width(LeaderDemandedBits);
707 // Round up to a power of 2
708 MinBW = llvm::bit_ceil(MinBW);
709
710 // We don't modify the types of PHIs. Reductions will already have been
711 // truncated if possible, and inductions' sizes will have been chosen by
712 // indvars.
713 // If we are required to shrink a PHI, abandon this entire equivalence class.
714 bool Abort = false;
715 for (Value *M : llvm::make_range(ECs.member_begin(I), ECs.member_end()))
716 if (isa<PHINode>(M) && MinBW < M->getType()->getScalarSizeInBits()) {
717 Abort = true;
718 break;
719 }
720 if (Abort)
721 continue;
722
723 for (Value *M : llvm::make_range(ECs.member_begin(I), ECs.member_end())) {
724 auto *MI = dyn_cast<Instruction>(M);
725 if (!MI)
726 continue;
727 Type *Ty = M->getType();
728 if (Roots.count(M))
729 Ty = MI->getOperand(0)->getType();
730
731 if (MinBW >= Ty->getScalarSizeInBits())
732 continue;
733
734 // If any of M's operands demand more bits than MinBW then M cannot be
735 // performed safely in MinBW.
736 if (any_of(MI->operands(), [&DB, MinBW](Use &U) {
737 auto *CI = dyn_cast<ConstantInt>(U);
738 // For constants shift amounts, check if the shift would result in
739 // poison.
740 if (CI &&
741 isa<ShlOperator, LShrOperator, AShrOperator>(U.getUser()) &&
742 U.getOperandNo() == 1)
743 return CI->uge(MinBW);
744 uint64_t BW = bit_width(DB.getDemandedBits(&U).getZExtValue());
745 return bit_ceil(BW) > MinBW;
746 }))
747 continue;
748
749 MinBWs[MI] = MinBW;
750 }
751 }
752
753 return MinBWs;
754}
755
756/// Add all access groups in @p AccGroups to @p List.
757template <typename ListT>
758static void addToAccessGroupList(ListT &List, MDNode *AccGroups) {
759 // Interpret an access group as a list containing itself.
760 if (AccGroups->getNumOperands() == 0) {
761 assert(isValidAsAccessGroup(AccGroups) && "Node must be an access group");
762 List.insert(AccGroups);
763 return;
764 }
765
766 for (const auto &AccGroupListOp : AccGroups->operands()) {
767 auto *Item = cast<MDNode>(AccGroupListOp.get());
768 assert(isValidAsAccessGroup(Item) && "List item must be an access group");
769 List.insert(Item);
770 }
771}
772
773MDNode *llvm::uniteAccessGroups(MDNode *AccGroups1, MDNode *AccGroups2) {
774 if (!AccGroups1)
775 return AccGroups2;
776 if (!AccGroups2)
777 return AccGroups1;
778 if (AccGroups1 == AccGroups2)
779 return AccGroups1;
780
782 addToAccessGroupList(Union, AccGroups1);
783 addToAccessGroupList(Union, AccGroups2);
784
785 if (Union.size() == 0)
786 return nullptr;
787 if (Union.size() == 1)
788 return cast<MDNode>(Union.front());
789
790 LLVMContext &Ctx = AccGroups1->getContext();
791 return MDNode::get(Ctx, Union.getArrayRef());
792}
793
795 const Instruction *Inst2) {
796 bool MayAccessMem1 = Inst1->mayReadOrWriteMemory();
797 bool MayAccessMem2 = Inst2->mayReadOrWriteMemory();
798
799 if (!MayAccessMem1 && !MayAccessMem2)
800 return nullptr;
801 if (!MayAccessMem1)
802 return Inst2->getMetadata(LLVMContext::MD_access_group);
803 if (!MayAccessMem2)
804 return Inst1->getMetadata(LLVMContext::MD_access_group);
805
806 MDNode *MD1 = Inst1->getMetadata(LLVMContext::MD_access_group);
807 MDNode *MD2 = Inst2->getMetadata(LLVMContext::MD_access_group);
808 if (!MD1 || !MD2)
809 return nullptr;
810 if (MD1 == MD2)
811 return MD1;
812
813 // Use set for scalable 'contains' check.
814 SmallPtrSet<Metadata *, 4> AccGroupSet2;
815 addToAccessGroupList(AccGroupSet2, MD2);
816
817 SmallVector<Metadata *, 4> Intersection;
818 if (MD1->getNumOperands() == 0) {
819 assert(isValidAsAccessGroup(MD1) && "Node must be an access group");
820 if (AccGroupSet2.count(MD1))
821 Intersection.push_back(MD1);
822 } else {
823 for (const MDOperand &Node : MD1->operands()) {
824 auto *Item = cast<MDNode>(Node.get());
825 assert(isValidAsAccessGroup(Item) && "List item must be an access group");
826 if (AccGroupSet2.count(Item))
827 Intersection.push_back(Item);
828 }
829 }
830
831 if (Intersection.size() == 0)
832 return nullptr;
833 if (Intersection.size() == 1)
834 return cast<MDNode>(Intersection.front());
835
836 LLVMContext &Ctx = Inst1->getContext();
837 return MDNode::get(Ctx, Intersection);
838}
839
840/// \returns \p I after propagating metadata from \p VL.
842 if (VL.empty())
843 return Inst;
844 Instruction *I0 = cast<Instruction>(VL[0]);
847
848 for (auto Kind : {LLVMContext::MD_tbaa, LLVMContext::MD_alias_scope,
849 LLVMContext::MD_noalias, LLVMContext::MD_fpmath,
850 LLVMContext::MD_nontemporal, LLVMContext::MD_invariant_load,
851 LLVMContext::MD_access_group, LLVMContext::MD_mmra}) {
852 MDNode *MD = I0->getMetadata(Kind);
853 for (int J = 1, E = VL.size(); MD && J != E; ++J) {
854 const Instruction *IJ = cast<Instruction>(VL[J]);
855 MDNode *IMD = IJ->getMetadata(Kind);
856
857 switch (Kind) {
858 case LLVMContext::MD_mmra: {
859 MD = MMRAMetadata::combine(Inst->getContext(), MD, IMD);
860 break;
861 }
862 case LLVMContext::MD_tbaa:
863 MD = MDNode::getMostGenericTBAA(MD, IMD);
864 break;
865 case LLVMContext::MD_alias_scope:
867 break;
868 case LLVMContext::MD_fpmath:
869 MD = MDNode::getMostGenericFPMath(MD, IMD);
870 break;
871 case LLVMContext::MD_noalias:
872 case LLVMContext::MD_nontemporal:
873 case LLVMContext::MD_invariant_load:
874 MD = MDNode::intersect(MD, IMD);
875 break;
876 case LLVMContext::MD_access_group:
877 MD = intersectAccessGroups(Inst, IJ);
878 break;
879 default:
880 llvm_unreachable("unhandled metadata");
881 }
882 }
883
884 Inst->setMetadata(Kind, MD);
885 }
886
887 return Inst;
888}
889
890Constant *
892 const InterleaveGroup<Instruction> &Group) {
893 // All 1's means mask is not needed.
894 if (Group.getNumMembers() == Group.getFactor())
895 return nullptr;
896
897 // TODO: support reversed access.
898 assert(!Group.isReverse() && "Reversed group not supported.");
899
901 for (unsigned i = 0; i < VF; i++)
902 for (unsigned j = 0; j < Group.getFactor(); ++j) {
903 unsigned HasMember = Group.getMember(j) ? 1 : 0;
904 Mask.push_back(Builder.getInt1(HasMember));
905 }
906
907 return ConstantVector::get(Mask);
908}
909
911llvm::createReplicatedMask(unsigned ReplicationFactor, unsigned VF) {
912 SmallVector<int, 16> MaskVec;
913 for (unsigned i = 0; i < VF; i++)
914 for (unsigned j = 0; j < ReplicationFactor; j++)
915 MaskVec.push_back(i);
916
917 return MaskVec;
918}
919
921 unsigned NumVecs) {
923 for (unsigned i = 0; i < VF; i++)
924 for (unsigned j = 0; j < NumVecs; j++)
925 Mask.push_back(j * VF + i);
926
927 return Mask;
928}
929
931llvm::createStrideMask(unsigned Start, unsigned Stride, unsigned VF) {
933 for (unsigned i = 0; i < VF; i++)
934 Mask.push_back(Start + i * Stride);
935
936 return Mask;
937}
938
940 unsigned NumInts,
941 unsigned NumUndefs) {
943 for (unsigned i = 0; i < NumInts; i++)
944 Mask.push_back(Start + i);
945
946 for (unsigned i = 0; i < NumUndefs; i++)
947 Mask.push_back(-1);
948
949 return Mask;
950}
951
953 unsigned NumElts) {
954 // Avoid casts in the loop and make sure we have a reasonable number.
955 int NumEltsSigned = NumElts;
956 assert(NumEltsSigned > 0 && "Expected smaller or non-zero element count");
957
958 // If the mask chooses an element from operand 1, reduce it to choose from the
959 // corresponding element of operand 0. Undef mask elements are unchanged.
960 SmallVector<int, 16> UnaryMask;
961 for (int MaskElt : Mask) {
962 assert((MaskElt < NumEltsSigned * 2) && "Expected valid shuffle mask");
963 int UnaryElt = MaskElt >= NumEltsSigned ? MaskElt - NumEltsSigned : MaskElt;
964 UnaryMask.push_back(UnaryElt);
965 }
966 return UnaryMask;
967}
968
969/// A helper function for concatenating vectors. This function concatenates two
970/// vectors having the same element type. If the second vector has fewer
971/// elements than the first, it is padded with undefs.
973 Value *V2) {
974 VectorType *VecTy1 = dyn_cast<VectorType>(V1->getType());
975 VectorType *VecTy2 = dyn_cast<VectorType>(V2->getType());
976 assert(VecTy1 && VecTy2 &&
977 VecTy1->getScalarType() == VecTy2->getScalarType() &&
978 "Expect two vectors with the same element type");
979
980 unsigned NumElts1 = cast<FixedVectorType>(VecTy1)->getNumElements();
981 unsigned NumElts2 = cast<FixedVectorType>(VecTy2)->getNumElements();
982 assert(NumElts1 >= NumElts2 && "Unexpect the first vector has less elements");
983
984 if (NumElts1 > NumElts2) {
985 // Extend with UNDEFs.
986 V2 = Builder.CreateShuffleVector(
987 V2, createSequentialMask(0, NumElts2, NumElts1 - NumElts2));
988 }
989
990 return Builder.CreateShuffleVector(
991 V1, V2, createSequentialMask(0, NumElts1 + NumElts2, 0));
992}
993
995 ArrayRef<Value *> Vecs) {
996 unsigned NumVecs = Vecs.size();
997 assert(NumVecs > 1 && "Should be at least two vectors");
998
1000 ResList.append(Vecs.begin(), Vecs.end());
1001 do {
1003 for (unsigned i = 0; i < NumVecs - 1; i += 2) {
1004 Value *V0 = ResList[i], *V1 = ResList[i + 1];
1005 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
1006 "Only the last vector may have a different type");
1007
1008 TmpList.push_back(concatenateTwoVectors(Builder, V0, V1));
1009 }
1010
1011 // Push the last vector if the total number of vectors is odd.
1012 if (NumVecs % 2 != 0)
1013 TmpList.push_back(ResList[NumVecs - 1]);
1014
1015 ResList = TmpList;
1016 NumVecs = ResList.size();
1017 } while (NumVecs > 1);
1018
1019 return ResList[0];
1020}
1021
1023 assert(isa<VectorType>(Mask->getType()) &&
1024 isa<IntegerType>(Mask->getType()->getScalarType()) &&
1025 cast<IntegerType>(Mask->getType()->getScalarType())->getBitWidth() ==
1026 1 &&
1027 "Mask must be a vector of i1");
1028
1029 auto *ConstMask = dyn_cast<Constant>(Mask);
1030 if (!ConstMask)
1031 return false;
1032 if (ConstMask->isNullValue() || isa<UndefValue>(ConstMask))
1033 return true;
1034 if (isa<ScalableVectorType>(ConstMask->getType()))
1035 return false;
1036 for (unsigned
1037 I = 0,
1038 E = cast<FixedVectorType>(ConstMask->getType())->getNumElements();
1039 I != E; ++I) {
1040 if (auto *MaskElt = ConstMask->getAggregateElement(I))
1041 if (MaskElt->isNullValue() || isa<UndefValue>(MaskElt))
1042 continue;
1043 return false;
1044 }
1045 return true;
1046}
1047
1049 assert(isa<VectorType>(Mask->getType()) &&
1050 isa<IntegerType>(Mask->getType()->getScalarType()) &&
1051 cast<IntegerType>(Mask->getType()->getScalarType())->getBitWidth() ==
1052 1 &&
1053 "Mask must be a vector of i1");
1054
1055 auto *ConstMask = dyn_cast<Constant>(Mask);
1056 if (!ConstMask)
1057 return false;
1058 if (ConstMask->isAllOnesValue() || isa<UndefValue>(ConstMask))
1059 return true;
1060 if (isa<ScalableVectorType>(ConstMask->getType()))
1061 return false;
1062 for (unsigned
1063 I = 0,
1064 E = cast<FixedVectorType>(ConstMask->getType())->getNumElements();
1065 I != E; ++I) {
1066 if (auto *MaskElt = ConstMask->getAggregateElement(I))
1067 if (MaskElt->isAllOnesValue() || isa<UndefValue>(MaskElt))
1068 continue;
1069 return false;
1070 }
1071 return true;
1072}
1073
1075 assert(isa<VectorType>(Mask->getType()) &&
1076 isa<IntegerType>(Mask->getType()->getScalarType()) &&
1077 cast<IntegerType>(Mask->getType()->getScalarType())->getBitWidth() ==
1078 1 &&
1079 "Mask must be a vector of i1");
1080
1081 auto *ConstMask = dyn_cast<Constant>(Mask);
1082 if (!ConstMask)
1083 return false;
1084 if (ConstMask->isAllOnesValue() || isa<UndefValue>(ConstMask))
1085 return true;
1086 if (isa<ScalableVectorType>(ConstMask->getType()))
1087 return false;
1088 for (unsigned
1089 I = 0,
1090 E = cast<FixedVectorType>(ConstMask->getType())->getNumElements();
1091 I != E; ++I) {
1092 if (auto *MaskElt = ConstMask->getAggregateElement(I))
1093 if (MaskElt->isAllOnesValue() || isa<UndefValue>(MaskElt))
1094 return true;
1095 }
1096 return false;
1097}
1098
1099/// TODO: This is a lot like known bits, but for
1100/// vectors. Is there something we can common this with?
1102 assert(isa<FixedVectorType>(Mask->getType()) &&
1103 isa<IntegerType>(Mask->getType()->getScalarType()) &&
1104 cast<IntegerType>(Mask->getType()->getScalarType())->getBitWidth() ==
1105 1 &&
1106 "Mask must be a fixed width vector of i1");
1107
1108 const unsigned VWidth =
1109 cast<FixedVectorType>(Mask->getType())->getNumElements();
1110 APInt DemandedElts = APInt::getAllOnes(VWidth);
1111 if (auto *CV = dyn_cast<ConstantVector>(Mask))
1112 for (unsigned i = 0; i < VWidth; i++)
1113 if (CV->getAggregateElement(i)->isNullValue())
1114 DemandedElts.clearBit(i);
1115 return DemandedElts;
1116}
1117
1118bool InterleavedAccessInfo::isStrided(int Stride) {
1119 unsigned Factor = std::abs(Stride);
1120 return Factor >= 2 && Factor <= MaxInterleaveGroupFactor;
1121}
1122
1123void InterleavedAccessInfo::collectConstStrideAccesses(
1125 const DenseMap<Value*, const SCEV*> &Strides) {
1126 auto &DL = TheLoop->getHeader()->getDataLayout();
1127
1128 // Since it's desired that the load/store instructions be maintained in
1129 // "program order" for the interleaved access analysis, we have to visit the
1130 // blocks in the loop in reverse postorder (i.e., in a topological order).
1131 // Such an ordering will ensure that any load/store that may be executed
1132 // before a second load/store will precede the second load/store in
1133 // AccessStrideInfo.
1134 LoopBlocksDFS DFS(TheLoop);
1135 DFS.perform(LI);
1136 for (BasicBlock *BB : make_range(DFS.beginRPO(), DFS.endRPO()))
1137 for (auto &I : *BB) {
1139 if (!Ptr)
1140 continue;
1141 Type *ElementTy = getLoadStoreType(&I);
1142
1143 // Currently, codegen doesn't support cases where the type size doesn't
1144 // match the alloc size. Skip them for now.
1145 uint64_t Size = DL.getTypeAllocSize(ElementTy);
1146 if (Size * 8 != DL.getTypeSizeInBits(ElementTy))
1147 continue;
1148
1149 // We don't check wrapping here because we don't know yet if Ptr will be
1150 // part of a full group or a group with gaps. Checking wrapping for all
1151 // pointers (even those that end up in groups with no gaps) will be overly
1152 // conservative. For full groups, wrapping should be ok since if we would
1153 // wrap around the address space we would do a memory access at nullptr
1154 // even without the transformation. The wrapping checks are therefore
1155 // deferred until after we've formed the interleaved groups.
1156 int64_t Stride =
1157 getPtrStride(PSE, ElementTy, Ptr, TheLoop, Strides,
1158 /*Assume=*/true, /*ShouldCheckWrap=*/false).value_or(0);
1159
1160 const SCEV *Scev = replaceSymbolicStrideSCEV(PSE, Strides, Ptr);
1161 AccessStrideInfo[&I] = StrideDescriptor(Stride, Scev, Size,
1163 }
1164}
1165
1166// Analyze interleaved accesses and collect them into interleaved load and
1167// store groups.
1168//
1169// When generating code for an interleaved load group, we effectively hoist all
1170// loads in the group to the location of the first load in program order. When
1171// generating code for an interleaved store group, we sink all stores to the
1172// location of the last store. This code motion can change the order of load
1173// and store instructions and may break dependences.
1174//
1175// The code generation strategy mentioned above ensures that we won't violate
1176// any write-after-read (WAR) dependences.
1177//
1178// E.g., for the WAR dependence: a = A[i]; // (1)
1179// A[i] = b; // (2)
1180//
1181// The store group of (2) is always inserted at or below (2), and the load
1182// group of (1) is always inserted at or above (1). Thus, the instructions will
1183// never be reordered. All other dependences are checked to ensure the
1184// correctness of the instruction reordering.
1185//
1186// The algorithm visits all memory accesses in the loop in bottom-up program
1187// order. Program order is established by traversing the blocks in the loop in
1188// reverse postorder when collecting the accesses.
1189//
1190// We visit the memory accesses in bottom-up order because it can simplify the
1191// construction of store groups in the presence of write-after-write (WAW)
1192// dependences.
1193//
1194// E.g., for the WAW dependence: A[i] = a; // (1)
1195// A[i] = b; // (2)
1196// A[i + 1] = c; // (3)
1197//
1198// We will first create a store group with (3) and (2). (1) can't be added to
1199// this group because it and (2) are dependent. However, (1) can be grouped
1200// with other accesses that may precede it in program order. Note that a
1201// bottom-up order does not imply that WAW dependences should not be checked.
1203 bool EnablePredicatedInterleavedMemAccesses) {
1204 LLVM_DEBUG(dbgs() << "LV: Analyzing interleaved accesses...\n");
1205 const auto &Strides = LAI->getSymbolicStrides();
1206
1207 // Holds all accesses with a constant stride.
1209 collectConstStrideAccesses(AccessStrideInfo, Strides);
1210
1211 if (AccessStrideInfo.empty())
1212 return;
1213
1214 // Collect the dependences in the loop.
1215 collectDependences();
1216
1217 // Holds all interleaved store groups temporarily.
1219 // Holds all interleaved load groups temporarily.
1221 // Groups added to this set cannot have new members added.
1222 SmallPtrSet<InterleaveGroup<Instruction> *, 4> CompletedLoadGroups;
1223
1224 // Search in bottom-up program order for pairs of accesses (A and B) that can
1225 // form interleaved load or store groups. In the algorithm below, access A
1226 // precedes access B in program order. We initialize a group for B in the
1227 // outer loop of the algorithm, and then in the inner loop, we attempt to
1228 // insert each A into B's group if:
1229 //
1230 // 1. A and B have the same stride,
1231 // 2. A and B have the same memory object size, and
1232 // 3. A belongs in B's group according to its distance from B.
1233 //
1234 // Special care is taken to ensure group formation will not break any
1235 // dependences.
1236 for (auto BI = AccessStrideInfo.rbegin(), E = AccessStrideInfo.rend();
1237 BI != E; ++BI) {
1238 Instruction *B = BI->first;
1239 StrideDescriptor DesB = BI->second;
1240
1241 // Initialize a group for B if it has an allowable stride. Even if we don't
1242 // create a group for B, we continue with the bottom-up algorithm to ensure
1243 // we don't break any of B's dependences.
1244 InterleaveGroup<Instruction> *GroupB = nullptr;
1245 if (isStrided(DesB.Stride) &&
1246 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) {
1247 GroupB = getInterleaveGroup(B);
1248 if (!GroupB) {
1249 LLVM_DEBUG(dbgs() << "LV: Creating an interleave group with:" << *B
1250 << '\n');
1251 GroupB = createInterleaveGroup(B, DesB.Stride, DesB.Alignment);
1252 if (B->mayWriteToMemory())
1253 StoreGroups.insert(GroupB);
1254 else
1255 LoadGroups.insert(GroupB);
1256 }
1257 }
1258
1259 for (auto AI = std::next(BI); AI != E; ++AI) {
1260 Instruction *A = AI->first;
1261 StrideDescriptor DesA = AI->second;
1262
1263 // Our code motion strategy implies that we can't have dependences
1264 // between accesses in an interleaved group and other accesses located
1265 // between the first and last member of the group. Note that this also
1266 // means that a group can't have more than one member at a given offset.
1267 // The accesses in a group can have dependences with other accesses, but
1268 // we must ensure we don't extend the boundaries of the group such that
1269 // we encompass those dependent accesses.
1270 //
1271 // For example, assume we have the sequence of accesses shown below in a
1272 // stride-2 loop:
1273 //
1274 // (1, 2) is a group | A[i] = a; // (1)
1275 // | A[i-1] = b; // (2) |
1276 // A[i-3] = c; // (3)
1277 // A[i] = d; // (4) | (2, 4) is not a group
1278 //
1279 // Because accesses (2) and (3) are dependent, we can group (2) with (1)
1280 // but not with (4). If we did, the dependent access (3) would be within
1281 // the boundaries of the (2, 4) group.
1282 auto DependentMember = [&](InterleaveGroup<Instruction> *Group,
1283 StrideEntry *A) -> Instruction * {
1284 for (uint32_t Index = 0; Index < Group->getFactor(); ++Index) {
1285 Instruction *MemberOfGroupB = Group->getMember(Index);
1286 if (MemberOfGroupB && !canReorderMemAccessesForInterleavedGroups(
1287 A, &*AccessStrideInfo.find(MemberOfGroupB)))
1288 return MemberOfGroupB;
1289 }
1290 return nullptr;
1291 };
1292
1293 auto GroupA = getInterleaveGroup(A);
1294 // If A is a load, dependencies are tolerable, there's nothing to do here.
1295 // If both A and B belong to the same (store) group, they are independent,
1296 // even if dependencies have not been recorded.
1297 // If both GroupA and GroupB are null, there's nothing to do here.
1298 if (A->mayWriteToMemory() && GroupA != GroupB) {
1299 Instruction *DependentInst = nullptr;
1300 // If GroupB is a load group, we have to compare AI against all
1301 // members of GroupB because if any load within GroupB has a dependency
1302 // on AI, we need to mark GroupB as complete and also release the
1303 // store GroupA (if A belongs to one). The former prevents incorrect
1304 // hoisting of load B above store A while the latter prevents incorrect
1305 // sinking of store A below load B.
1306 if (GroupB && LoadGroups.contains(GroupB))
1307 DependentInst = DependentMember(GroupB, &*AI);
1308 else if (!canReorderMemAccessesForInterleavedGroups(&*AI, &*BI))
1309 DependentInst = B;
1310
1311 if (DependentInst) {
1312 // A has a store dependence on B (or on some load within GroupB) and
1313 // is part of a store group. Release A's group to prevent illegal
1314 // sinking of A below B. A will then be free to form another group
1315 // with instructions that precede it.
1316 if (GroupA && StoreGroups.contains(GroupA)) {
1317 LLVM_DEBUG(dbgs() << "LV: Invalidated store group due to "
1318 "dependence between "
1319 << *A << " and " << *DependentInst << '\n');
1320 StoreGroups.remove(GroupA);
1321 releaseGroup(GroupA);
1322 }
1323 // If B is a load and part of an interleave group, no earlier loads
1324 // can be added to B's interleave group, because this would mean the
1325 // DependentInst would move across store A. Mark the interleave group
1326 // as complete.
1327 if (GroupB && LoadGroups.contains(GroupB)) {
1328 LLVM_DEBUG(dbgs() << "LV: Marking interleave group for " << *B
1329 << " as complete.\n");
1330 CompletedLoadGroups.insert(GroupB);
1331 }
1332 }
1333 }
1334 if (CompletedLoadGroups.contains(GroupB)) {
1335 // Skip trying to add A to B, continue to look for other conflicting A's
1336 // in groups to be released.
1337 continue;
1338 }
1339
1340 // At this point, we've checked for illegal code motion. If either A or B
1341 // isn't strided, there's nothing left to do.
1342 if (!isStrided(DesA.Stride) || !isStrided(DesB.Stride))
1343 continue;
1344
1345 // Ignore A if it's already in a group or isn't the same kind of memory
1346 // operation as B.
1347 // Note that mayReadFromMemory() isn't mutually exclusive to
1348 // mayWriteToMemory in the case of atomic loads. We shouldn't see those
1349 // here, canVectorizeMemory() should have returned false - except for the
1350 // case we asked for optimization remarks.
1351 if (isInterleaved(A) ||
1352 (A->mayReadFromMemory() != B->mayReadFromMemory()) ||
1353 (A->mayWriteToMemory() != B->mayWriteToMemory()))
1354 continue;
1355
1356 // Check rules 1 and 2. Ignore A if its stride or size is different from
1357 // that of B.
1358 if (DesA.Stride != DesB.Stride || DesA.Size != DesB.Size)
1359 continue;
1360
1361 // Ignore A if the memory object of A and B don't belong to the same
1362 // address space
1364 continue;
1365
1366 // Calculate the distance from A to B.
1367 const SCEVConstant *DistToB = dyn_cast<SCEVConstant>(
1368 PSE.getSE()->getMinusSCEV(DesA.Scev, DesB.Scev));
1369 if (!DistToB)
1370 continue;
1371 int64_t DistanceToB = DistToB->getAPInt().getSExtValue();
1372
1373 // Check rule 3. Ignore A if its distance to B is not a multiple of the
1374 // size.
1375 if (DistanceToB % static_cast<int64_t>(DesB.Size))
1376 continue;
1377
1378 // All members of a predicated interleave-group must have the same predicate,
1379 // and currently must reside in the same BB.
1380 BasicBlock *BlockA = A->getParent();
1381 BasicBlock *BlockB = B->getParent();
1382 if ((isPredicated(BlockA) || isPredicated(BlockB)) &&
1383 (!EnablePredicatedInterleavedMemAccesses || BlockA != BlockB))
1384 continue;
1385
1386 // The index of A is the index of B plus A's distance to B in multiples
1387 // of the size.
1388 int IndexA =
1389 GroupB->getIndex(B) + DistanceToB / static_cast<int64_t>(DesB.Size);
1390
1391 // Try to insert A into B's group.
1392 if (GroupB->insertMember(A, IndexA, DesA.Alignment)) {
1393 LLVM_DEBUG(dbgs() << "LV: Inserted:" << *A << '\n'
1394 << " into the interleave group with" << *B
1395 << '\n');
1396 InterleaveGroupMap[A] = GroupB;
1397
1398 // Set the first load in program order as the insert position.
1399 if (A->mayReadFromMemory())
1400 GroupB->setInsertPos(A);
1401 }
1402 } // Iteration over A accesses.
1403 } // Iteration over B accesses.
1404
1405 auto InvalidateGroupIfMemberMayWrap = [&](InterleaveGroup<Instruction> *Group,
1406 int Index,
1407 std::string FirstOrLast) -> bool {
1408 Instruction *Member = Group->getMember(Index);
1409 assert(Member && "Group member does not exist");
1410 Value *MemberPtr = getLoadStorePointerOperand(Member);
1411 Type *AccessTy = getLoadStoreType(Member);
1412 if (getPtrStride(PSE, AccessTy, MemberPtr, TheLoop, Strides,
1413 /*Assume=*/false, /*ShouldCheckWrap=*/true).value_or(0))
1414 return false;
1415 LLVM_DEBUG(dbgs() << "LV: Invalidate candidate interleaved group due to "
1416 << FirstOrLast
1417 << " group member potentially pointer-wrapping.\n");
1418 releaseGroup(Group);
1419 return true;
1420 };
1421
1422 // Remove interleaved groups with gaps whose memory
1423 // accesses may wrap around. We have to revisit the getPtrStride analysis,
1424 // this time with ShouldCheckWrap=true, since collectConstStrideAccesses does
1425 // not check wrapping (see documentation there).
1426 // FORNOW we use Assume=false;
1427 // TODO: Change to Assume=true but making sure we don't exceed the threshold
1428 // of runtime SCEV assumptions checks (thereby potentially failing to
1429 // vectorize altogether).
1430 // Additional optional optimizations:
1431 // TODO: If we are peeling the loop and we know that the first pointer doesn't
1432 // wrap then we can deduce that all pointers in the group don't wrap.
1433 // This means that we can forcefully peel the loop in order to only have to
1434 // check the first pointer for no-wrap. When we'll change to use Assume=true
1435 // we'll only need at most one runtime check per interleaved group.
1436 for (auto *Group : LoadGroups) {
1437 // Case 1: A full group. Can Skip the checks; For full groups, if the wide
1438 // load would wrap around the address space we would do a memory access at
1439 // nullptr even without the transformation.
1440 if (Group->getNumMembers() == Group->getFactor())
1441 continue;
1442
1443 // Case 2: If first and last members of the group don't wrap this implies
1444 // that all the pointers in the group don't wrap.
1445 // So we check only group member 0 (which is always guaranteed to exist),
1446 // and group member Factor - 1; If the latter doesn't exist we rely on
1447 // peeling (if it is a non-reversed accsess -- see Case 3).
1448 if (InvalidateGroupIfMemberMayWrap(Group, 0, std::string("first")))
1449 continue;
1450 if (Group->getMember(Group->getFactor() - 1))
1451 InvalidateGroupIfMemberMayWrap(Group, Group->getFactor() - 1,
1452 std::string("last"));
1453 else {
1454 // Case 3: A non-reversed interleaved load group with gaps: We need
1455 // to execute at least one scalar epilogue iteration. This will ensure
1456 // we don't speculatively access memory out-of-bounds. We only need
1457 // to look for a member at index factor - 1, since every group must have
1458 // a member at index zero.
1459 if (Group->isReverse()) {
1460 LLVM_DEBUG(
1461 dbgs() << "LV: Invalidate candidate interleaved group due to "
1462 "a reverse access with gaps.\n");
1463 releaseGroup(Group);
1464 continue;
1465 }
1466 LLVM_DEBUG(
1467 dbgs() << "LV: Interleaved group requires epilogue iteration.\n");
1468 RequiresScalarEpilogue = true;
1469 }
1470 }
1471
1472 for (auto *Group : StoreGroups) {
1473 // Case 1: A full group. Can Skip the checks; For full groups, if the wide
1474 // store would wrap around the address space we would do a memory access at
1475 // nullptr even without the transformation.
1476 if (Group->getNumMembers() == Group->getFactor())
1477 continue;
1478
1479 // Interleave-store-group with gaps is implemented using masked wide store.
1480 // Remove interleaved store groups with gaps if
1481 // masked-interleaved-accesses are not enabled by the target.
1482 if (!EnablePredicatedInterleavedMemAccesses) {
1483 LLVM_DEBUG(
1484 dbgs() << "LV: Invalidate candidate interleaved store group due "
1485 "to gaps.\n");
1486 releaseGroup(Group);
1487 continue;
1488 }
1489
1490 // Case 2: If first and last members of the group don't wrap this implies
1491 // that all the pointers in the group don't wrap.
1492 // So we check only group member 0 (which is always guaranteed to exist),
1493 // and the last group member. Case 3 (scalar epilog) is not relevant for
1494 // stores with gaps, which are implemented with masked-store (rather than
1495 // speculative access, as in loads).
1496 if (InvalidateGroupIfMemberMayWrap(Group, 0, std::string("first")))
1497 continue;
1498 for (int Index = Group->getFactor() - 1; Index > 0; Index--)
1499 if (Group->getMember(Index)) {
1500 InvalidateGroupIfMemberMayWrap(Group, Index, std::string("last"));
1501 break;
1502 }
1503 }
1504}
1505
1507 // If no group had triggered the requirement to create an epilogue loop,
1508 // there is nothing to do.
1510 return;
1511
1512 // Release groups requiring scalar epilogues. Note that this also removes them
1513 // from InterleaveGroups.
1514 bool ReleasedGroup = InterleaveGroups.remove_if([&](auto *Group) {
1515 if (!Group->requiresScalarEpilogue())
1516 return false;
1517 LLVM_DEBUG(
1518 dbgs()
1519 << "LV: Invalidate candidate interleaved group due to gaps that "
1520 "require a scalar epilogue (not allowed under optsize) and cannot "
1521 "be masked (not enabled). \n");
1522 releaseGroupWithoutRemovingFromSet(Group);
1523 return true;
1524 });
1525 assert(ReleasedGroup && "At least one group must be invalidated, as a "
1526 "scalar epilogue was required");
1527 (void)ReleasedGroup;
1528 RequiresScalarEpilogue = false;
1529}
1530
1531template <typename InstT>
1532void InterleaveGroup<InstT>::addMetadata(InstT *NewInst) const {
1533 llvm_unreachable("addMetadata can only be used for Instruction");
1534}
1535
1536namespace llvm {
1537template <>
1540 std::transform(Members.begin(), Members.end(), std::back_inserter(VL),
1541 [](std::pair<int, Instruction *> p) { return p.second; });
1542 propagateMetadata(NewInst, VL);
1543}
1544} // namespace llvm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
DenseMap< Block *, BlockRelaxAux > Blocks
Definition: ELF_riscv.cpp:507
Generic implementation of equivalence classes through the use Tarjan's efficient union-find algorithm...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
This file provides utility for Memory Model Relaxation Annotations (MMRAs).
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const NodeList & List
Definition: RDFGraph.cpp:201
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static unsigned getScalarSizeInBits(Type *Ty)
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This pass exposes codegen information to IR-level passes.
static Value * concatenateTwoVectors(IRBuilderBase &Builder, Value *V1, Value *V2)
A helper function for concatenating vectors.
static cl::opt< unsigned > MaxInterleaveGroupFactor("max-interleave-group-factor", cl::Hidden, cl::desc("Maximum factor for an interleaved access group (default = 8)"), cl::init(8))
Maximum factor for an interleaved memory access.
static void addToAccessGroupList(ListT &List, MDNode *AccGroups)
Add all access groups in AccGroups to List.
Class for arbitrary precision integers.
Definition: APInt.h:78
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:214
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1387
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1310
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
Definition: APInt.h:360
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1448
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
Definition: APInt.h:180
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1522
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:168
iterator end() const
Definition: ArrayRef.h:154
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
iterator begin() const
Definition: ArrayRef.h:153
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
LLVM Basic Block Representation.
Definition: BasicBlock.h:61
const DataLayout & getDataLayout() const
Get the data layout of the module this basic block belongs to.
Definition: BasicBlock.cpp:296
This class represents a function call, abstracting a target machine's calling convention.
static Constant * get(ArrayRef< Constant * > V)
Definition: Constants.cpp:1399
This is an important base class in LLVM.
Definition: Constant.h:42
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:151
EquivalenceClasses - This represents a collection of equivalence classes and supports three efficient...
const ElemTy & getOrInsertLeaderValue(const ElemTy &V)
getOrInsertLeaderValue - Return the leader for the specified value that is in the set.
member_iterator member_end() const
member_iterator member_begin(iterator I) const
member_iterator unionSets(const ElemTy &V1, const ElemTy &V2)
union - Merge the two equivalence sets for the specified values, inserting them if they do not alread...
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:91
ConstantInt * getInt1(bool V)
Get a constant value representing either true or false.
Definition: IRBuilder.h:458
Value * CreateShuffleVector(Value *V1, Value *V2, Value *Mask, const Twine &Name="")
Definition: IRBuilder.h:2502
This instruction inserts a single (scalar) element into a VectorType value.
bool mayReadOrWriteMemory() const
Return true if this instruction may read or write memory.
Definition: Instruction.h:754
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:381
void setMetadata(unsigned KindID, MDNode *Node)
Set the metadata of the specified kind to the specified node.
Definition: Metadata.cpp:1642
void getAllMetadataOtherThanDebugLoc(SmallVectorImpl< std::pair< unsigned, MDNode * > > &MDs) const
This does the same thing as getAllMetadata, except that it filters out the debug location.
Definition: Instruction.h:406
The group of interleaved loads/stores sharing the same stride and close to each other.
Definition: VectorUtils.h:470
uint32_t getFactor() const
Definition: VectorUtils.h:486
InstTy * getMember(uint32_t Index) const
Get the member with the given index Index.
Definition: VectorUtils.h:540
uint32_t getIndex(const InstTy *Instr) const
Get the index for the given member.
Definition: VectorUtils.h:547
void setInsertPos(InstTy *Inst)
Definition: VectorUtils.h:557
bool isReverse() const
Definition: VectorUtils.h:485
void addMetadata(InstTy *NewInst) const
Add metadata (e.g.
bool insertMember(InstTy *Instr, int32_t Index, Align NewAlign)
Try to insert a new member Instr with index Index and alignment NewAlign.
Definition: VectorUtils.h:495
uint32_t getNumMembers() const
Definition: VectorUtils.h:488
InterleaveGroup< Instruction > * getInterleaveGroup(const Instruction *Instr) const
Get the interleave group that Instr belongs to.
Definition: VectorUtils.h:657
bool requiresScalarEpilogue() const
Returns true if an interleaved group that may access memory out-of-bounds requires a scalar epilogue ...
Definition: VectorUtils.h:668
bool isInterleaved(Instruction *Instr) const
Check if Instr belongs to any interleave group.
Definition: VectorUtils.h:649
void analyzeInterleaving(bool EnableMaskedInterleavedGroup)
Analyze the interleaved accesses and collect them in interleave groups.
void invalidateGroupsRequiringScalarEpilogue()
Invalidate groups that require a scalar epilogue (due to gaps).
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
const DenseMap< Value *, const SCEV * > & getSymbolicStrides() const
If an access has a symbolic strides, this maps the pointer value to the stride symbol.
BlockT * getHeader() const
Store the result of a depth first search within basic blocks contained by a single loop.
Definition: LoopIterator.h:97
Metadata node.
Definition: Metadata.h:1069
static MDNode * getMostGenericAliasScope(MDNode *A, MDNode *B)
Definition: Metadata.cpp:1141
static MDNode * getMostGenericTBAA(MDNode *A, MDNode *B)
ArrayRef< MDOperand > operands() const
Definition: Metadata.h:1428
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1542
static MDNode * getMostGenericFPMath(MDNode *A, MDNode *B)
Definition: Metadata.cpp:1173
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1436
static MDNode * intersect(MDNode *A, MDNode *B)
Definition: Metadata.cpp:1128
LLVMContext & getContext() const
Definition: Metadata.h:1233
Tracking metadata reference owned by Metadata.
Definition: Metadata.h:891
static MDNode * combine(LLVMContext &Ctx, const MMRAMetadata &A, const MMRAMetadata &B)
Combines A and B according to MMRA semantics.
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:36
reverse_iterator rend()
Definition: MapVector.h:76
iterator find(const KeyT &Key)
Definition: MapVector.h:167
bool empty() const
Definition: MapVector.h:79
reverse_iterator rbegin()
Definition: MapVector.h:74
Root of the metadata hierarchy.
Definition: Metadata.h:62
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
Definition: Constants.cpp:1852
ScalarEvolution * getSE() const
Returns the ScalarEvolution analysis used.
This class represents a constant integer value.
const APInt & getAPInt() const
This class represents an analyzed expression in the program.
const SCEV * getMinusSCEV(const SCEV *LHS, const SCEV *RHS, SCEV::NoWrapFlags Flags=SCEV::FlagAnyWrap, unsigned Depth=0)
Return LHS-RHS.
bool remove(const value_type &X)
Remove an item from the set vector.
Definition: SetVector.h:188
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:162
bool contains(const key_type &key) const
Check if the SetVector contains the given key.
Definition: SetVector.h:254
This instruction constructs a fixed permutation of two input vectors.
int getMaskValue(unsigned Elt) const
Return the shuffle mask value of this instruction for the given element index.
VectorType * getType() const
Overload to return most specific vector type.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:436
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
bool contains(ConstPtrType Ptr) const
Definition: SmallPtrSet.h:442
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:503
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:370
bool empty() const
Definition: SmallVector.h:95
size_t size() const
Definition: SmallVector.h:92
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
void assign(size_type NumElts, ValueParamT Elt)
Definition: SmallVector.h:718
void reserve(size_type N)
Definition: SmallVector.h:677
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:697
void push_back(const T &Elt)
Definition: SmallVector.h:427
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
Provides information about what library functions are available for the current target.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
Value * getOperand(unsigned i) const
Definition: User.h:169
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:1075
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
Type * getElementType() const
Definition: DerivedTypes.h:436
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:100
class_match< Constant > m_Constant()
Match an arbitrary Constant and ignore it.
Definition: PatternMatch.h:165
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
ThreeOps_match< Cond, LHS, RHS, Instruction::Select > m_Select(const Cond &C, const LHS &L, const RHS &R)
Matches SelectInst.
cst_pred_ty< is_zero_int > m_ZeroInt()
Match an integer 0 or a vector with all elements equal to 0.
Definition: PatternMatch.h:599
TwoOps_match< V1_t, V2_t, Instruction::ShuffleVector > m_Shuffle(const V1_t &v1, const V2_t &v2)
Matches ShuffleVectorInst independently of mask value.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:92
ThreeOps_match< Val_t, Elt_t, Idx_t, Instruction::InsertElement > m_InsertElt(const Val_t &Val, const Elt_t &Elt, const Idx_t &Idx)
Matches InsertElementInst.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1722
unsigned getLoadStoreAddressSpace(const Value *I)
A helper function that returns the address space of the pointer operand of load or store instruction.
Intrinsic::ID getVectorIntrinsicIDForCall(const CallInst *CI, const TargetLibraryInfo *TLI)
Returns intrinsic ID for call.
APInt possiblyDemandedEltsInMask(Value *Mask)
Given a mask vector of the form <Y x i1>, return an APInt (of bitwidth Y) for each lane which may be ...
bool isVectorIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx)
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
const Value * getLoadStorePointerOperand(const Value *V)
A helper function that returns the pointer operand of a load or store instruction.
llvm::SmallVector< int, 16 > createUnaryMask(ArrayRef< int > Mask, unsigned NumElts)
Given a shuffle mask for a binary shuffle, create the equivalent shuffle mask assuming both operands ...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
Definition: bit.h:317
Value * concatenateVectors(IRBuilderBase &Builder, ArrayRef< Value * > Vecs)
Concatenate a list of vectors.
Align getLoadStoreAlignment(const Value *I)
A helper function that returns the alignment of load or store instruction.
bool widenShuffleMaskElts(int Scale, ArrayRef< int > Mask, SmallVectorImpl< int > &ScaledMask)
Try to transform a shuffle mask by replacing elements with the scaled index for an equivalent mask of...
Instruction * propagateMetadata(Instruction *I, ArrayRef< Value * > VL)
Specifically, let Kinds = [MD_tbaa, MD_alias_scope, MD_noalias, MD_fpmath, MD_nontemporal,...
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
Definition: bit.h:342
MDNode * intersectAccessGroups(const Instruction *Inst1, const Instruction *Inst2)
Compute the access-group list of access groups that Inst1 and Inst2 are both in.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
bool isSplatValue(const Value *V, int Index=-1, unsigned Depth=0)
Return true if each element of the vector value V is poisoned or equal to every other non-poisoned el...
Constant * createBitMaskForGaps(IRBuilderBase &Builder, unsigned VF, const InterleaveGroup< Instruction > &Group)
Create a mask that filters the members of an interleave group where there are gaps.
constexpr unsigned MaxAnalysisRecursionDepth
Definition: ValueTracking.h:48
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
void getHorizDemandedEltsForFirstOperand(unsigned VectorBitWidth, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS)
Compute the demanded elements mask of horizontal binary operations.
llvm::SmallVector< int, 16 > createReplicatedMask(unsigned ReplicationFactor, unsigned VF)
Create a mask with replicated elements.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
std::optional< int64_t > getPtrStride(PredicatedScalarEvolution &PSE, Type *AccessTy, Value *Ptr, const Loop *Lp, const DenseMap< Value *, const SCEV * > &StridesMap=DenseMap< Value *, const SCEV * >(), bool Assume=false, bool ShouldCheckWrap=true)
If the pointer has a constant stride return it in units of the access type size.
bool maskIsAllOneOrUndef(Value *Mask)
Given a mask vector of i1, Return true if all of the elements of this predicate mask are known to be ...
constexpr int PoisonMaskElem
bool isValidAsAccessGroup(MDNode *AccGroup)
Return whether an MDNode might represent an access group.
Definition: LoopInfo.cpp:1154
Intrinsic::ID getIntrinsicForCallSite(const CallBase &CB, const TargetLibraryInfo *TLI)
Map a call instruction to an intrinsic ID.
void processShuffleMasks(ArrayRef< int > Mask, unsigned NumOfSrcRegs, unsigned NumOfDestRegs, unsigned NumOfUsedRegs, function_ref< void()> NoInputAction, function_ref< void(ArrayRef< int >, unsigned, unsigned)> SingleInputAction, function_ref< void(ArrayRef< int >, unsigned, unsigned)> ManyInputsAction)
Splits and processes shuffle mask depending on the number of input and output registers.
void narrowShuffleMaskElts(int Scale, ArrayRef< int > Mask, SmallVectorImpl< int > &ScaledMask)
Replace each shuffle mask index with the scaled sequential indices for an equivalent mask of narrowed...
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
const SCEV * replaceSymbolicStrideSCEV(PredicatedScalarEvolution &PSE, const DenseMap< Value *, const SCEV * > &PtrToStride, Value *Ptr)
Return the SCEV corresponding to a pointer with the symbolic stride replaced with constant one,...
Value * findScalarElement(Value *V, unsigned EltNo)
Given a vector and an element number, see if the scalar value is already around as a register,...
MDNode * uniteAccessGroups(MDNode *AccGroups1, MDNode *AccGroups2)
Compute the union of two access-group lists.
auto count_if(R &&Range, UnaryPredicate P)
Wrapper function around std::count_if to count the number of times an element satisfying a given pred...
Definition: STLExtras.h:1921
bool maskIsAllZeroOrUndef(Value *Mask)
Given a mask vector of i1, Return true if all of the elements of this predicate mask are known to be ...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1749
void getShuffleMaskWithWidestElts(ArrayRef< int > Mask, SmallVectorImpl< int > &ScaledMask)
Repetitively apply widenShuffleMaskElts() for as long as it succeeds, to get the shuffle mask with wi...
Type * getLoadStoreType(const Value *I)
A helper function that returns the type of a load or store instruction.
bool isVectorIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx)
Identifies if the vector form of the intrinsic has a scalar operand.
bool all_equal(std::initializer_list< T > Values)
Returns true if all Values in the initializer lists are equal or the list.
Definition: STLExtras.h:2045
bool maskContainsAllOneOrUndef(Value *Mask)
Given a mask vector of i1, Return true if any of the elements of this predicate mask are known to be ...
bool isTriviallyVectorizable(Intrinsic::ID ID)
Identify if the intrinsic is trivially vectorizable.
Definition: VectorUtils.cpp:46
llvm::SmallVector< int, 16 > createSequentialMask(unsigned Start, unsigned NumInts, unsigned NumUndefs)
Create a sequential shuffle mask.
MapVector< Instruction *, uint64_t > computeMinimumValueSizes(ArrayRef< BasicBlock * > Blocks, DemandedBits &DB, const TargetTransformInfo *TTI=nullptr)
Compute a map of integer instructions to their minimum legal type size.
bool scaleShuffleMaskElts(unsigned NumDstElts, ArrayRef< int > Mask, SmallVectorImpl< int > &ScaledMask)
Attempt to narrow/widen the Mask shuffle mask to the NumDstElts target width.
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860