LLVM  13.0.0git
WebAssemblyISelLowering.h
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1 //- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that WebAssembly uses to lower LLVM
11 /// code into a selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
17 
19 
20 namespace llvm {
21 
22 namespace WebAssemblyISD {
23 
24 enum NodeType : unsigned {
26 #define HANDLE_NODETYPE(NODE) NODE,
27 #define HANDLE_MEM_NODETYPE(NODE)
28 #include "WebAssemblyISD.def"
30 #undef HANDLE_NODETYPE
31 #undef HANDLE_MEM_NODETYPE
32 #define HANDLE_NODETYPE(NODE)
33 #define HANDLE_MEM_NODETYPE(NODE) NODE,
34 #include "WebAssemblyISD.def"
35 #undef HANDLE_NODETYPE
36 #undef HANDLE_MEM_NODETYPE
37 };
38 
39 } // end namespace WebAssemblyISD
40 
41 class WebAssemblySubtarget;
42 
44 public:
46  const WebAssemblySubtarget &STI);
47 
48 private:
49  /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
50  /// right decision when generating code for different targets.
51  const WebAssemblySubtarget *Subtarget;
52 
53  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
54  FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
55  const TargetLibraryInfo *LibInfo) const override;
56  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
58  EmitInstrWithCustomInserter(MachineInstr &MI,
59  MachineBasicBlock *MBB) const override;
60  const char *getTargetNodeName(unsigned Opcode) const override;
61  std::pair<unsigned, const TargetRegisterClass *>
62  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
63  StringRef Constraint, MVT VT) const override;
64  bool isCheapToSpeculateCttz() const override;
65  bool isCheapToSpeculateCtlz() const override;
66  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
67  unsigned AS,
68  Instruction *I = nullptr) const override;
69  bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
71  bool *Fast) const override;
72  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
73  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
74  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
75  EVT VT) const override;
76  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
77  MachineFunction &MF,
78  unsigned Intrinsic) const override;
79 
80  SDValue LowerCall(CallLoweringInfo &CLI,
81  SmallVectorImpl<SDValue> &InVals) const override;
82  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
83  bool isVarArg,
85  LLVMContext &Context) const override;
86  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
88  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
89  SelectionDAG &DAG) const override;
90  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
91  bool IsVarArg,
93  const SDLoc &DL, SelectionDAG &DAG,
94  SmallVectorImpl<SDValue> &InVals) const override;
95 
96  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
97  SelectionDAG &DAG) const override;
98 
99  const char *getClearCacheBuiltinName() const override {
100  report_fatal_error("llvm.clear_cache is not supported on wasm");
101  }
102 
103  // Custom lowering hooks.
104  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
105  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
106  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
107  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
108  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
110  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
111  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
112  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
113  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
114  SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
115  SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
116  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
117  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
118  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
119  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
120  SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
121  SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
122  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
123 
124  // Custom DAG combine hooks
125  SDValue
126  PerformDAGCombine(SDNode *N,
127  TargetLowering::DAGCombinerInfo &DCI) const override;
128 };
129 
130 namespace WebAssembly {
132  const TargetLibraryInfo *libInfo);
133 } // end namespace WebAssembly
134 
135 } // end namespace llvm
136 
137 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::WebAssemblyISD::NodeType
NodeType
Definition: WebAssemblyISelLowering.h:24
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::AttributeList
Definition: Attributes.h:385
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:851
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering
WebAssemblyTargetLowering(const TargetMachine &TM, const WebAssemblySubtarget &STI)
Definition: WebAssemblyISelLowering.cpp:42
llvm::WebAssemblyTargetLowering
Definition: WebAssemblyISelLowering.h:43
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
TargetLowering.h
llvm::WebAssembly::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: WebAssemblyFastISel.cpp:1426
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3491
llvm::Instruction
Definition: Instruction.h:45
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::WebAssemblyISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: WebAssemblyISelLowering.h:25
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3694
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:975
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:247
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1247
N
#define N
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2322
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::WebAssemblyISD::FIRST_MEM_OPCODE
@ FIRST_MEM_OPCODE
Definition: WebAssemblyISelLowering.h:29