34#include "llvm/IR/IntrinsicsWebAssembly.h"
43#define DEBUG_TYPE "wasm-lower"
58 Subtarget->
hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
306 if (
MVT(
T) != MemT) {
344 setLibcallName(RTLIB::RETURN_ADDRESS,
"emscripten_return_address");
371WebAssemblyTargetLowering::shouldExpandAtomicRMWInIR(
AtomicRMWInst *AI)
const {
387bool WebAssemblyTargetLowering::shouldScalarizeBinop(
SDValue VecOp)
const {
407FastISel *WebAssemblyTargetLowering::createFastISel(
412MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(
const DataLayout & ,
423 "32-bit shift counts ought to be enough for anyone");
428 "Unable to represent scalar shift amount type");
438 bool IsUnsigned,
bool Int64,
439 bool Float64,
unsigned LoweredOpcode) {
445 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
446 unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
447 unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
448 unsigned GE = Float64 ? WebAssembly::GE_F64 : WebAssembly::GE_F32;
449 unsigned IConst =
Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
450 unsigned Eqz = WebAssembly::EQZ_I32;
451 unsigned And = WebAssembly::AND_I32;
453 int64_t Substitute = IsUnsigned ? 0 : Limit;
454 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(
double)Limit;
465 F->insert(It, FalseMBB);
466 F->insert(It, TrueMBB);
467 F->insert(It, DoneMBB);
470 DoneMBB->
splice(DoneMBB->
begin(), BB, std::next(
MI.getIterator()), BB->
end());
478 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
479 Tmp0 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
480 Tmp1 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
481 CmpReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
482 EqzReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
483 FalseReg =
MRI.createVirtualRegister(
MRI.getRegClass(OutReg));
484 TrueReg =
MRI.createVirtualRegister(
MRI.getRegClass(OutReg));
486 MI.eraseFromParent();
500 Tmp1 =
MRI.createVirtualRegister(
MRI.getRegClass(InReg));
502 MRI.createVirtualRegister(&WebAssembly::I32RegClass);
503 Register AndReg =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
535 CallResults.
getOpcode() == WebAssembly::RET_CALL_RESULTS);
538 bool IsRetCall = CallResults.
getOpcode() == WebAssembly::RET_CALL_RESULTS;
540 bool IsFuncrefCall =
false;
546 IsFuncrefCall = (TRC == &WebAssembly::FUNCREFRegClass);
551 if (IsIndirect && IsRetCall) {
552 CallOp = WebAssembly::RET_CALL_INDIRECT;
553 }
else if (IsIndirect) {
554 CallOp = WebAssembly::CALL_INDIRECT;
555 }
else if (IsRetCall) {
556 CallOp = WebAssembly::RET_CALL;
558 CallOp = WebAssembly::CALL;
574 TII.get(WebAssembly::I32_WRAP_I64), Reg32)
601 for (
auto Def : CallResults.
defs())
624 for (
auto Use : CallParams.
uses())
640 if (IsIndirect && IsFuncrefCall) {
652 BuildMI(MF,
DL,
TII.get(WebAssembly::REF_NULL_FUNCREF), RegFuncref);
656 BuildMI(MF,
DL,
TII.get(WebAssembly::TABLE_SET_FUNCREF))
671 switch (
MI.getOpcode()) {
674 case WebAssembly::FP_TO_SINT_I32_F32:
676 WebAssembly::I32_TRUNC_S_F32);
677 case WebAssembly::FP_TO_UINT_I32_F32:
679 WebAssembly::I32_TRUNC_U_F32);
680 case WebAssembly::FP_TO_SINT_I64_F32:
682 WebAssembly::I64_TRUNC_S_F32);
683 case WebAssembly::FP_TO_UINT_I64_F32:
685 WebAssembly::I64_TRUNC_U_F32);
686 case WebAssembly::FP_TO_SINT_I32_F64:
688 WebAssembly::I32_TRUNC_S_F64);
689 case WebAssembly::FP_TO_UINT_I32_F64:
691 WebAssembly::I32_TRUNC_U_F64);
692 case WebAssembly::FP_TO_SINT_I64_F64:
694 WebAssembly::I64_TRUNC_S_F64);
695 case WebAssembly::FP_TO_UINT_I64_F64:
697 WebAssembly::I64_TRUNC_U_F64);
698 case WebAssembly::CALL_RESULTS:
699 case WebAssembly::RET_CALL_RESULTS:
705WebAssemblyTargetLowering::getTargetNodeName(
unsigned Opcode)
const {
710#define HANDLE_NODETYPE(NODE) \
711 case WebAssemblyISD::NODE: \
712 return "WebAssemblyISD::" #NODE;
713#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE)
714#include "WebAssemblyISD.def"
715#undef HANDLE_MEM_NODETYPE
716#undef HANDLE_NODETYPE
721std::pair<unsigned, const TargetRegisterClass *>
722WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
726 if (Constraint.
size() == 1) {
727 switch (Constraint[0]) {
732 return std::make_pair(0U, &WebAssembly::V128RegClass);
736 return std::make_pair(0U, &WebAssembly::I32RegClass);
738 return std::make_pair(0U, &WebAssembly::I64RegClass);
743 return std::make_pair(0U, &WebAssembly::F32RegClass);
745 return std::make_pair(0U, &WebAssembly::F64RegClass);
759bool WebAssemblyTargetLowering::isCheapToSpeculateCttz(
Type *Ty)
const {
764bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz(
Type *Ty)
const {
769bool WebAssemblyTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
771 Type *Ty,
unsigned AS,
787bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
801bool WebAssemblyTargetLowering::isIntDivCheap(
EVT VT,
808bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(
SDValue ExtVal)
const {
810 EVT MemT = cast<LoadSDNode>(ExtVal->
getOperand(0))->getValueType(0);
816bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
836bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
839 unsigned Intrinsic)
const {
841 case Intrinsic::wasm_memory_atomic_notify:
844 Info.ptrVal =
I.getArgOperand(0);
855 case Intrinsic::wasm_memory_atomic_wait32:
858 Info.ptrVal =
I.getArgOperand(0);
863 case Intrinsic::wasm_memory_atomic_wait64:
866 Info.ptrVal =
I.getArgOperand(0);
876void WebAssemblyTargetLowering::computeKnownBitsForTargetNode(
879 switch (
Op.getOpcode()) {
883 unsigned IntNo =
Op.getConstantOperandVal(0);
887 case Intrinsic::wasm_bitmask: {
889 EVT VT =
Op.getOperand(1).getSimpleValueType();
892 Known.
Zero |= ZeroMask;
901WebAssemblyTargetLowering::getPreferredVectorAction(
MVT VT)
const {
915bool WebAssemblyTargetLowering::shouldSimplifyDemandedVectorElts(
916 SDValue Op,
const TargetLoweringOpt &TLO)
const {
969WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
981 "WebAssembly doesn't support language-specific or target-specific "
982 "calling conventions yet");
983 if (CLI.IsPatchPoint)
984 fail(
DL, DAG,
"WebAssembly doesn't support patch point yet");
986 if (CLI.IsTailCall) {
987 auto NoTail = [&](
const char *
Msg) {
988 if (CLI.CB && CLI.CB->isMustTailCall())
990 CLI.IsTailCall =
false;
994 NoTail(
"WebAssembly 'tail-call' feature not enabled");
998 NoTail(
"WebAssembly does not support varargs tail calls");
1008 bool TypesMatch = CallerRetTys.
size() == CalleeRetTys.
size() &&
1009 std::equal(CallerRetTys.
begin(), CallerRetTys.
end(),
1010 CalleeRetTys.
begin());
1012 NoTail(
"WebAssembly tail call requires caller and callee return types to "
1017 for (
auto &
Arg : CLI.CB->args()) {
1022 if (
auto *
GEP = dyn_cast<GetElementPtrInst>(Src))
1023 Src =
GEP->getPointerOperand();
1028 if (isa<AllocaInst>(Val)) {
1030 "WebAssembly does not support tail calling with stack arguments");
1045 Outs[0].Flags.isSRet()) {
1050 bool HasSwiftSelfArg =
false;
1051 bool HasSwiftErrorArg =
false;
1053 for (
unsigned I = 0;
I < Outs.
size(); ++
I) {
1059 fail(
DL, DAG,
"WebAssembly hasn't implemented nest arguments");
1061 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca arguments");
1063 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs arguments");
1065 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last arguments");
1084 bool IsVarArg = CLI.IsVarArg;
1092 if (!HasSwiftSelfArg) {
1095 Arg.Flags.setSwiftSelf();
1096 CLI.Outs.push_back(
Arg);
1098 CLI.OutVals.push_back(ArgVal);
1100 if (!HasSwiftErrorArg) {
1103 Arg.Flags.setSwiftError();
1104 CLI.Outs.push_back(
Arg);
1106 CLI.OutVals.push_back(ArgVal);
1120 EVT VT =
Arg.getValueType();
1126 CCInfo.AllocateStack(Layout.getTypeAllocSize(Ty), Alignment);
1133 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
1136 if (IsVarArg && NumBytes) {
1140 Layout.getStackAlignment(),
1145 assert(ArgLocs[ValNo].getValNo() == ValNo &&
1146 "ArgLocs should remain in order and only hold varargs args");
1147 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
1155 if (!Chains.
empty())
1157 }
else if (IsVarArg) {
1187 for (
const auto &In : Ins) {
1188 assert(!
In.Flags.isByVal() &&
"byval is not valid for return values");
1189 assert(!
In.Flags.isNest() &&
"nest is not valid for return values");
1190 if (
In.Flags.isInAlloca())
1191 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca return values");
1192 if (
In.Flags.isInConsecutiveRegs())
1193 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs return values");
1194 if (
In.Flags.isInConsecutiveRegsLast())
1196 "WebAssembly hasn't implemented cons regs last return values");
1225 CLI.CB->getCalledOperand()->getPointerAlignment(DAG.
getDataLayout()),
1231 if (CLI.IsTailCall) {
1234 return DAG.
getNode(WebAssemblyISD::RET_CALL,
DL, NodeTys, Ops);
1241 for (
size_t I = 0;
I <
Ins.size(); ++
I)
1248bool WebAssemblyTargetLowering::CanLowerReturn(
1256SDValue WebAssemblyTargetLowering::LowerReturn(
1262 "MVP WebAssembly can only return up to one value");
1264 fail(
DL, DAG,
"WebAssembly doesn't support non-C calling conventions");
1267 RetOps.append(OutVals.
begin(), OutVals.
end());
1274 assert(Out.
IsFixed &&
"non-fixed return value is not valid");
1276 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca results");
1278 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs results");
1280 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last results");
1286SDValue WebAssemblyTargetLowering::LowerFormalArguments(
1291 fail(
DL, DAG,
"WebAssembly doesn't support non-C calling conventions");
1300 bool HasSwiftErrorArg =
false;
1301 bool HasSwiftSelfArg =
false;
1303 HasSwiftSelfArg |=
In.Flags.isSwiftSelf();
1304 HasSwiftErrorArg |=
In.Flags.isSwiftError();
1305 if (
In.Flags.isInAlloca())
1306 fail(
DL, DAG,
"WebAssembly hasn't implemented inalloca arguments");
1307 if (
In.Flags.isNest())
1308 fail(
DL, DAG,
"WebAssembly hasn't implemented nest arguments");
1309 if (
In.Flags.isInConsecutiveRegs())
1310 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs arguments");
1311 if (
In.Flags.isInConsecutiveRegsLast())
1312 fail(
DL, DAG,
"WebAssembly hasn't implemented cons regs last arguments");
1321 MFI->addParam(
In.VT);
1330 if (!HasSwiftSelfArg) {
1331 MFI->addParam(PtrVT);
1333 if (!HasSwiftErrorArg) {
1334 MFI->addParam(PtrVT);
1343 MFI->setVarargBufferVreg(VarargVreg);
1345 Chain,
DL, VarargVreg,
1346 DAG.
getNode(WebAssemblyISD::ARGUMENT,
DL, PtrVT,
1348 MFI->addParam(PtrVT);
1360 assert(MFI->getParams().size() == Params.
size() &&
1361 std::equal(MFI->getParams().begin(), MFI->getParams().end(),
1367void WebAssemblyTargetLowering::ReplaceNodeResults(
1369 switch (
N->getOpcode()) {
1378 "ReplaceNodeResults not implemented for this op for WebAssembly!");
1389 switch (
Op.getOpcode()) {
1394 return LowerFrameIndex(Op, DAG);
1396 return LowerGlobalAddress(Op, DAG);
1398 return LowerGlobalTLSAddress(Op, DAG);
1400 return LowerExternalSymbol(Op, DAG);
1402 return LowerJumpTable(Op, DAG);
1404 return LowerBR_JT(Op, DAG);
1406 return LowerVASTART(Op, DAG);
1409 fail(
DL, DAG,
"WebAssembly hasn't implemented computed gotos");
1412 return LowerRETURNADDR(Op, DAG);
1414 return LowerFRAMEADDR(Op, DAG);
1416 return LowerCopyToReg(Op, DAG);
1419 return LowerAccessVectorElement(Op, DAG);
1423 return LowerIntrinsic(Op, DAG);
1425 return LowerSIGN_EXTEND_INREG(Op, DAG);
1427 return LowerBUILD_VECTOR(Op, DAG);
1429 return LowerVECTOR_SHUFFLE(Op, DAG);
1431 return LowerSETCC(Op, DAG);
1435 return LowerShift(Op, DAG);
1438 return LowerFP_TO_INT_SAT(Op, DAG);
1440 return LowerLoad(Op, DAG);
1442 return LowerStore(Op, DAG);
1461 return std::nullopt;
1494 return DAG.
getNode(WebAssemblyISD::LOCAL_SET,
DL, Tys, Ops);
1499 "Encountered an unlowerable store to the wasm_var address space",
1515 "unexpected offset when loading from webassembly global",
false);
1526 "unexpected offset when loading from webassembly local",
false);
1533 assert(
Result->getNumValues() == 2 &&
"Loads must carry a chain!");
1539 "Encountered an unlowerable load from the wasm_var address space",
1548 if (isa<FrameIndexSDNode>(Src.getNode())) {
1556 Register Reg = cast<RegisterSDNode>(
Op.getOperand(1))->getReg();
1557 EVT VT = Src.getValueType();
1559 : WebAssembly::COPY_I64,
1562 return Op.getNode()->getNumValues() == 1
1565 Op.getNumOperands() == 4 ?
Op.getOperand(3)
1573 int FI = cast<FrameIndexSDNode>(Op)->getIndex();
1583 "Non-Emscripten WebAssembly hasn't implemented "
1584 "__builtin_return_address");
1591 unsigned Depth =
Op.getConstantOperandVal(0);
1592 MakeLibCallOptions CallOptions;
1593 return makeLibCall(DAG, RTLIB::RETURN_ADDRESS,
Op.getValueType(),
1594 {DAG.getConstant(Depth, DL, MVT::i32)}, CallOptions,
DL)
1603 if (
Op.getConstantOperandVal(0) > 0)
1607 EVT VT =
Op.getValueType();
1614WebAssemblyTargetLowering::LowerGlobalTLSAddress(
SDValue Op,
1617 const auto *GA = cast<GlobalAddressSDNode>(Op);
1644 auto GlobalGet = PtrVT ==
MVT::i64 ? WebAssembly::GLOBAL_GET_I64
1645 : WebAssembly::GLOBAL_GET_I32;
1656 DAG.
getNode(WebAssemblyISD::WrapperREL,
DL, PtrVT, TLSOffset);
1663 EVT VT =
Op.getValueType();
1664 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1673 const auto *GA = cast<GlobalAddressSDNode>(Op);
1674 EVT VT =
Op.getValueType();
1676 "Unexpected target flags on generic GlobalAddressSDNode");
1678 fail(
DL, DAG,
"Invalid address space for WebAssembly target");
1686 const char *BaseName;
1695 DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
1699 WebAssemblyISD::WrapperREL,
DL, VT,
1708 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1714WebAssemblyTargetLowering::LowerExternalSymbol(
SDValue Op,
1717 const auto *ES = cast<ExternalSymbolSDNode>(Op);
1718 EVT VT =
Op.getValueType();
1719 assert(ES->getTargetFlags() == 0 &&
1720 "Unexpected target flags on generic ExternalSymbolSDNode");
1721 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, VT,
1732 JT->getTargetFlags());
1739 const auto *
JT = cast<JumpTableSDNode>(
Op.getOperand(1));
1741 assert(
JT->getTargetFlags() == 0 &&
"WebAssembly doesn't set target flags");
1751 for (
auto *
MBB : MBBs)
1767 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1770 MFI->getVarargBufferVreg(), PtrVT);
1771 return DAG.
getStore(
Op.getOperand(0),
DL, ArgN,
Op.getOperand(1),
1779 switch (
Op.getOpcode()) {
1782 IntNo =
Op.getConstantOperandVal(1);
1785 IntNo =
Op.getConstantOperandVal(0);
1796 case Intrinsic::wasm_lsda: {
1805 DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
1812 return DAG.
getNode(WebAssemblyISD::Wrapper,
DL, PtrVT,
Node);
1815 case Intrinsic::wasm_shuffle: {
1819 Ops[OpIdx++] =
Op.getOperand(1);
1820 Ops[OpIdx++] =
Op.getOperand(2);
1821 while (OpIdx < 18) {
1822 const SDValue &MaskIdx =
Op.getOperand(OpIdx + 1);
1824 cast<ConstantSDNode>(MaskIdx.
getNode())->getZExtValue() >= 32) {
1827 Ops[OpIdx++] = MaskIdx;
1830 return DAG.
getNode(WebAssemblyISD::SHUFFLE,
DL,
Op.getValueType(), Ops);
1836WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(
SDValue Op,
1850 const SDValue &Extract =
Op.getOperand(0);
1854 MVT ExtractedLaneT =
1855 cast<VTSDNode>(
Op.getOperand(1).getNode())->
getVT().getSimpleVT();
1858 if (ExtractedVecT == VecT)
1863 if (!isa<ConstantSDNode>(
Index))
1865 unsigned IndexVal = cast<ConstantSDNode>(
Index)->getZExtValue();
1883 auto GetConvertedLane = [](
SDValue Op,
unsigned &Opcode,
SDValue &SrcVec,
1884 unsigned &
Index) ->
bool {
1885 switch (Op.getOpcode()) {
1887 Opcode = WebAssemblyISD::CONVERT_LOW_S;
1890 Opcode = WebAssemblyISD::CONVERT_LOW_U;
1893 Opcode = WebAssemblyISD::PROMOTE_LOW;
1899 auto ExtractVector = Op.getOperand(0);
1903 if (!isa<ConstantSDNode>(ExtractVector.getOperand(1).getNode()))
1906 SrcVec = ExtractVector.getOperand(0);
1907 Index = ExtractVector.getConstantOperandVal(1);
1911 unsigned LHSOpcode, RHSOpcode, LHSIndex, RHSIndex;
1913 if (!GetConvertedLane(Op.getOperand(0), LHSOpcode, LHSSrcVec, LHSIndex) ||
1914 !GetConvertedLane(Op.getOperand(1), RHSOpcode, RHSSrcVec, RHSIndex))
1917 if (LHSOpcode != RHSOpcode)
1921 switch (LHSOpcode) {
1922 case WebAssemblyISD::CONVERT_LOW_S:
1923 case WebAssemblyISD::CONVERT_LOW_U:
1926 case WebAssemblyISD::PROMOTE_LOW:
1933 auto Src = LHSSrcVec;
1934 if (LHSIndex != 0 || RHSIndex != 1 || LHSSrcVec != RHSSrcVec) {
1937 ExpectedSrcVT,
DL, LHSSrcVec, RHSSrcVec,
1938 {
static_cast<int>(LHSIndex),
static_cast<int>(RHSIndex) + 4, -1, -1});
1949 const EVT VecT =
Op.getValueType();
1950 const EVT LaneT =
Op.getOperand(0).getValueType();
1951 const size_t Lanes =
Op.getNumOperands();
1973 auto GetSwizzleSrcs = [](
size_t I,
const SDValue &Lane) {
1988 Index->getConstantOperandVal(1) !=
I)
1990 return std::make_pair(SwizzleSrc, SwizzleIndices);
1997 auto GetShuffleSrc = [&](
const SDValue &Lane) {
2000 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode()))
2002 if (Lane->getOperand(0).getValueType().getVectorNumElements() >
2008 using ValueEntry = std::pair<SDValue, size_t>;
2011 using SwizzleEntry = std::pair<std::pair<SDValue, SDValue>,
size_t>;
2014 using ShuffleEntry = std::pair<SDValue, size_t>;
2017 auto AddCount = [](
auto &Counts,
const auto &Val) {
2020 if (CountIt == Counts.end()) {
2021 Counts.emplace_back(Val, 1);
2027 auto GetMostCommon = [](
auto &Counts) {
2030 assert(CommonIt != Counts.end() &&
"Unexpected all-undef build_vector");
2034 size_t NumConstantLanes = 0;
2037 for (
size_t I = 0;
I < Lanes; ++
I) {
2042 AddCount(SplatValueCounts, Lane);
2046 if (
auto ShuffleSrc = GetShuffleSrc(Lane))
2047 AddCount(ShuffleCounts, ShuffleSrc);
2049 auto SwizzleSrcs = GetSwizzleSrcs(
I, Lane);
2050 if (SwizzleSrcs.first)
2051 AddCount(SwizzleCounts, SwizzleSrcs);
2056 size_t NumSplatLanes;
2057 std::tie(SplatValue, NumSplatLanes) = GetMostCommon(SplatValueCounts);
2061 size_t NumSwizzleLanes = 0;
2062 if (SwizzleCounts.
size())
2063 std::forward_as_tuple(std::tie(SwizzleSrc, SwizzleIndices),
2064 NumSwizzleLanes) = GetMostCommon(SwizzleCounts);
2068 SDValue ShuffleSrc1, ShuffleSrc2;
2069 size_t NumShuffleLanes = 0;
2070 if (ShuffleCounts.
size()) {
2071 std::tie(ShuffleSrc1, NumShuffleLanes) = GetMostCommon(ShuffleCounts);
2073 [&](
const auto &Pair) {
return Pair.first == ShuffleSrc1; });
2075 if (ShuffleCounts.
size()) {
2076 size_t AdditionalShuffleLanes;
2077 std::tie(ShuffleSrc2, AdditionalShuffleLanes) =
2078 GetMostCommon(ShuffleCounts);
2079 NumShuffleLanes += AdditionalShuffleLanes;
2084 std::function<
bool(
size_t,
const SDValue &)> IsLaneConstructed;
2087 if (NumSwizzleLanes >= NumShuffleLanes &&
2088 NumSwizzleLanes >= NumConstantLanes && NumSwizzleLanes >= NumSplatLanes) {
2091 auto Swizzled = std::make_pair(SwizzleSrc, SwizzleIndices);
2092 IsLaneConstructed = [&, Swizzled](
size_t I,
const SDValue &Lane) {
2093 return Swizzled == GetSwizzleSrcs(
I, Lane);
2095 }
else if (NumShuffleLanes >= NumConstantLanes &&
2096 NumShuffleLanes >= NumSplatLanes) {
2106 assert(LaneSize > DestLaneSize);
2107 Scale1 = LaneSize / DestLaneSize;
2113 assert(LaneSize > DestLaneSize);
2114 Scale2 = LaneSize / DestLaneSize;
2119 assert(DestLaneCount <= 16);
2120 for (
size_t I = 0;
I < DestLaneCount; ++
I) {
2122 SDValue Src = GetShuffleSrc(Lane);
2123 if (Src == ShuffleSrc1) {
2125 }
else if (Src && Src == ShuffleSrc2) {
2133 IsLaneConstructed = [&](size_t,
const SDValue &Lane) {
2134 auto Src = GetShuffleSrc(Lane);
2135 return Src == ShuffleSrc1 || (Src && Src == ShuffleSrc2);
2137 }
else if (NumConstantLanes >= NumSplatLanes) {
2139 for (
const SDValue &Lane :
Op->op_values()) {
2147 auto *
Const = dyn_cast<ConstantSDNode>(Lane.
getNode());
2148 int64_t Val =
Const ?
Const->getSExtValue() : 0;
2150 assert((LaneBits == 64 || Val >= -(1ll << (LaneBits - 1))) &&
2151 "Unexpected out of bounds negative value");
2152 if (Const && LaneBits != 64 && Val > (1ll << (LaneBits - 1)) - 1) {
2153 auto NewVal = ((
uint64_t)Val % (1ll << LaneBits)) - (1ll << LaneBits);
2171 IsLaneConstructed = [&SplatValue](
size_t _,
const SDValue &Lane) {
2172 return Lane == SplatValue;
2177 assert(IsLaneConstructed);
2180 for (
size_t I = 0;
I < Lanes; ++
I) {
2182 if (!Lane.
isUndef() && !IsLaneConstructed(
I, Lane))
2191WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(
SDValue Op,
2196 assert(
VecType.is128BitVector() &&
"Unexpected shuffle vector type");
2197 size_t LaneBytes =
VecType.getVectorElementType().getSizeInBits() / 8;
2202 Ops[OpIdx++] =
Op.getOperand(0);
2203 Ops[OpIdx++] =
Op.getOperand(1);
2206 for (
int M : Mask) {
2207 for (
size_t J = 0; J < LaneBytes; ++J) {
2216 return DAG.
getNode(WebAssemblyISD::SHUFFLE,
DL,
Op.getValueType(), Ops);
2229 auto MakeLane = [&](
unsigned I) {
2235 {MakeLane(0), MakeLane(1)});
2239WebAssemblyTargetLowering::LowerAccessVectorElement(
SDValue Op,
2242 SDNode *IdxNode =
Op.getOperand(
Op.getNumOperands() - 1).getNode();
2243 if (isa<ConstantSDNode>(IdxNode) || IdxNode->
isUndef()) {
2245 uint64_t Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
2247 Ops[
Op.getNumOperands() - 1] =
2256 EVT LaneT = Op.getSimpleValueType().getVectorElementType();
2262 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements();
2264 unsigned ShiftOpcode = Op.getOpcode();
2270 for (
size_t i = 0; i < NumLanes; ++i) {
2273 SDValue ShiftedValue = ShiftedElements[i];
2288 assert(
Op.getSimpleValueType().isVector());
2290 uint64_t LaneBits =
Op.getValueType().getScalarSizeInBits();
2291 auto ShiftVal =
Op.getOperand(1);
2305 MaskVal == MaskBits)
2308 if (!isa<ConstantSDNode>(
RHS.getNode()))
2311 auto ConstantRHS = dyn_cast<ConstantSDNode>(
RHS.getNode());
2312 if (ConstantRHS && ConstantRHS->getAPIntValue() == MaskBits)
2320 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2326 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2331 switch (
Op.getOpcode()) {
2333 Opcode = WebAssemblyISD::VEC_SHL;
2336 Opcode = WebAssemblyISD::VEC_SHR_S;
2339 Opcode = WebAssemblyISD::VEC_SHR_U;
2345 return DAG.
getNode(Opcode,
DL,
Op.getValueType(),
Op.getOperand(0), ShiftVal);
2351 EVT ResT =
Op.getValueType();
2352 EVT SatVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
2369 auto &DAG = DCI.
DAG;
2370 auto Shuffle = cast<ShuffleVectorSDNode>(
N);
2376 SDValue Bitcast =
N->getOperand(0);
2379 if (!
N->getOperand(1).isUndef())
2381 SDValue CastOp = Bitcast.getOperand(0);
2383 MVT DstType = Bitcast.getSimpleValueType();
2398 auto &DAG = DCI.
DAG;
2402 EVT InVT =
N->getOperand(0)->getValueType(0);
2403 EVT ResVT =
N->getValueType(0);
2420 auto &DAG = DCI.
DAG;
2426 auto Extract =
N->getOperand(0);
2430 auto *IndexNode = dyn_cast<ConstantSDNode>(Extract.
getOperand(1));
2431 if (IndexNode ==
nullptr)
2433 auto Index = IndexNode->getZExtValue();
2437 EVT ResVT =
N->getValueType(0);
2455 bool IsLow =
Index == 0;
2457 unsigned Op = IsSext ? (IsLow ? WebAssemblyISD::EXTEND_LOW_S
2458 : WebAssemblyISD::EXTEND_HIGH_S)
2459 : (IsLow ? WebAssemblyISD::EXTEND_LOW_U
2460 : WebAssemblyISD::EXTEND_HIGH_U);
2467 auto &DAG = DCI.
DAG;
2469 auto GetWasmConversionOp = [](
unsigned Op) {
2472 return WebAssemblyISD::TRUNC_SAT_ZERO_S;
2474 return WebAssemblyISD::TRUNC_SAT_ZERO_U;
2476 return WebAssemblyISD::DEMOTE_ZERO;
2481 auto IsZeroSplat = [](
SDValue SplatVal) {
2482 auto *Splat = dyn_cast<BuildVectorSDNode>(SplatVal.getNode());
2483 APInt SplatValue, SplatUndef;
2484 unsigned SplatBitSize;
2487 Splat->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2505 EVT ExpectedConversionType;
2508 switch (ConversionOp) {
2522 if (
N->getValueType(0) != ResVT)
2525 if (
Conversion.getValueType() != ExpectedConversionType)
2532 if (!IsZeroSplat(
N->getOperand(1)) ||
2533 N->getOperand(1).getValueType() != ExpectedConversionType)
2536 unsigned Op = GetWasmConversionOp(ConversionOp);
2552 auto ConversionOp =
N->getOpcode();
2553 switch (ConversionOp) {
2565 if (
N->getValueType(0) != ResVT)
2568 auto Concat =
N->getOperand(0);
2572 auto Source =
Concat.getOperand(0);
2576 if (!IsZeroSplat(
Concat.getOperand(1)) ||
2580 unsigned Op = GetWasmConversionOp(ConversionOp);
2586 const SDLoc &
DL,
unsigned VectorWidth) {
2594 unsigned ElemsPerChunk = VectorWidth / ElVT.
getSizeInBits();
2599 IdxVal &= ~(ElemsPerChunk - 1);
2604 Vec->
ops().slice(IdxVal, ElemsPerChunk));
2616 EVT SrcVT = In.getValueType();
2639 unsigned SubSizeInBits = SrcSizeInBits / 2;
2641 OutVT =
EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits());
2667 auto &DAG = DCI.
DAG;
2670 EVT InVT = In.getValueType();
2674 EVT OutVT =
N->getValueType(0);
2693WebAssemblyTargetLowering::PerformDAGCombine(
SDNode *
N,
2694 DAGCombinerInfo &DCI)
const {
2695 switch (
N->getOpcode()) {
unsigned const MachineRegisterInfo * MRI
static SDValue performTruncateCombine(SDNode *N, SelectionDAG &DAG)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Function Alias Analysis Results
static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
static unsigned NumFixedArgs
unsigned const TargetRegisterInfo * TRI
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::FuncInfo FuncInfo
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachineBasicBlock * LowerFPToInt(MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode)
static bool callingConvSupported(CallingConv::ID CallConv)
static std::optional< unsigned > IsWebAssemblyLocal(SDValue Op, SelectionDAG &DAG)
static SDValue performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue unrollVectorShift(SDValue Op, SelectionDAG &DAG)
static MachineBasicBlock * LowerCallResults(MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB, const WebAssemblySubtarget *Subtarget, const TargetInstrInfo &TII)
static SDValue performVECTOR_SHUFFLECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue performVectorTruncZeroCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool IsWebAssemblyGlobal(SDValue Op)
static SDValue performVectorExtendToFPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instr...
static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG)
static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &DL, unsigned VectorWidth)
static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG)
This file defines the interfaces that WebAssembly uses to lower LLVM code into a selection DAG.
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file declares the WebAssembly-specific subclass of TargetMachine.
This file contains the declaration of the WebAssembly-specific type parsing utility functions.
This file contains the declaration of the WebAssembly-specific utility functions.
static constexpr int Concat[]
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
This class represents a function call, abstracting a target machine's calling convention.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
A parsed version of the target data layout string in and methods for querying it.
Diagnostic information for unsupported feature in backend.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
FunctionType * getFunctionType() const
Returns the FunctionType for me.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
ThreadLocalMode getThreadLocalMode() const
Module * getParent()
Get the module that this global value is contained inside of...
Type * getValueType() const
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
Describe properties that are true of each instruction in the target description file.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
static auto integer_fixedlen_vector_valuetypes()
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
bool isFixedLengthVector() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const SDValue & getOperand(unsigned Num) const
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isOSEmscripten() const
Tests whether the OS is Emscripten.
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getDoubleTy(LLVMContext &C)
bool isFunctionTy() const
True if this is an instance of FunctionType.
static Type * getFloatTy(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
const Value * stripPointerCastsAndAliases() const
Strip off pointer casts, all-zero GEPs, address space casts, and aliases.
static std::optional< unsigned > getLocalForStackObject(MachineFunction &MF, int FrameIndex)
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Register getFrameRegister(const MachineFunction &MF) const override
const Triple & getTargetTriple() const
const WebAssemblyInstrInfo * getInstrInfo() const override
bool hasBulkMemory() const
const WebAssemblyRegisterInfo * getRegisterInfo() const override
bool hasMultivalue() const
bool hasReferenceTypes() const
bool hasNontrappingFPToInt() const
WebAssemblyTargetLowering(const TargetMachine &TM, const WebAssemblySubtarget &STI)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const override
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Swift
Calling convention for Swift.
@ PreserveMost
Used for runtime calls that preserves most registers.
@ CXX_FAST_TLS
Used for access functions.
@ WASM_EmscriptenInvoke
For emscripten __invoke_* functions.
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
MCSymbolWasm * getOrCreateFunctionTableSymbol(MCContext &Ctx, const WebAssemblySubtarget *Subtarget)
Returns the __indirect_function_table, for use in call_indirect and in function bitcasts.
@ WASM_ADDRESS_SPACE_EXTERNREF
@ WASM_ADDRESS_SPACE_FUNCREF
MCSymbolWasm * getOrCreateFuncrefCallTableSymbol(MCContext &Ctx, const WebAssemblySubtarget *Subtarget)
Returns the __funcref_call_table, for use in funcref calls when lowered to table.set + call_indirect.
bool isFuncrefType(const Type *Ty)
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isValidAddressSpace(unsigned AS)
bool isWasmVarAddressSpace(unsigned AS)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
void computeSignatureVTs(const FunctionType *Ty, const Function *TargetFunc, const Function &ContextFunc, const TargetMachine &TM, SmallVectorImpl< MVT > &Params, SmallVectorImpl< MVT > &Results)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ And
Bitwise or logical AND of integers.
constexpr unsigned BitWidth
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
void computeLegalValueVTs(const WebAssemblyTargetLowering &TLI, LLVMContext &Ctx, const DataLayout &DL, Type *Ty, SmallVectorImpl< MVT > &ValueVTs)
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool is256BitVector() const
Return true if this is a 256-bit vector type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInConsecutiveRegs() const
Align getNonZeroOrigAlign() const
bool isSwiftError() const
unsigned getByValSize() const
bool isInConsecutiveRegsLast() const
Align getNonZeroByValAlign() const
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
bool IsFixed
IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
unsigned getBitWidth() const
Get the bit width of this value.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Function object to check whether the second component of a container supported by std::get (like std:...