LLVM  14.0.0git
Macros | Functions | Variables
X86FlagsCopyLowering.cpp File Reference
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86InstrInfo.h"
#include "X86Subtarget.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <iterator>
#include <utility>
Include dependency graph for X86FlagsCopyLowering.cpp:

Go to the source code of this file.

Macros

#define PASS_KEY   "x86-flags-copy-lowering"
 
#define DEBUG_TYPE   PASS_KEY
 
#define LLVM_EXPAND_INSTR_SIZES(MNEMONIC, SUFFIX)
 
#define LLVM_EXPAND_ADC_SBB_INSTR(MNEMONIC)
 

Functions

 STATISTIC (NumCopiesEliminated, "Number of copies of EFLAGS eliminated")
 
 STATISTIC (NumSetCCsInserted, "Number of setCC instructions inserted")
 
 STATISTIC (NumTestsInserted, "Number of test instructions inserted")
 
 STATISTIC (NumAddsInserted, "Number of adds instructions inserted")
 
 INITIALIZE_PASS_BEGIN (X86FlagsCopyLoweringPass, DEBUG_TYPE, "X86 EFLAGS copy lowering", false, false) INITIALIZE_PASS_END(X86FlagsCopyLoweringPass
 
static FlagArithMnemonic getMnemonicFromOpcode (unsigned Opcode)
 
static MachineBasicBlocksplitBlock (MachineBasicBlock &MBB, MachineInstr &SplitI, const X86InstrInfo &TII)
 
static X86::CondCode getCondFromFCMOV (unsigned Opcode)
 

Variables

 DEBUG_TYPE
 
X86 EFLAGS copy lowering
 
X86 EFLAGS copy false
 

Detailed Description

Lowers COPY nodes of EFLAGS by directly extracting and preserving individual flag bits.

We have to do this by carefully analyzing and rewriting the usage of the copied EFLAGS register because there is no general way to rematerialize the entire EFLAGS register safely and efficiently. Using popf both forces dynamic stack adjustment and can create correctness issues due to IF, TF, and other non-status flags being overwritten. Using sequences involving SAHF don't work on all x86 processors and are often quite slow compared to directly testing a single status preserved in its own GPR.

Definition in file X86FlagsCopyLowering.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   PASS_KEY

Definition at line 66 of file X86FlagsCopyLowering.cpp.

◆ LLVM_EXPAND_ADC_SBB_INSTR

#define LLVM_EXPAND_ADC_SBB_INSTR (   MNEMONIC)
Value:
LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rr) \
LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rr_REV) \
LLVM_EXPAND_INSTR_SIZES(MNEMONIC, rm) \
LLVM_EXPAND_INSTR_SIZES(MNEMONIC, mr) \
case X86::MNEMONIC##8ri: \
case X86::MNEMONIC##16ri8: \
case X86::MNEMONIC##32ri8: \
case X86::MNEMONIC##64ri8: \
case X86::MNEMONIC##16ri: \
case X86::MNEMONIC##32ri: \
case X86::MNEMONIC##64ri32: \
case X86::MNEMONIC##8mi: \
case X86::MNEMONIC##16mi8: \
case X86::MNEMONIC##32mi8: \
case X86::MNEMONIC##64mi8: \
case X86::MNEMONIC##16mi: \
case X86::MNEMONIC##32mi: \
case X86::MNEMONIC##64mi32: \
case X86::MNEMONIC##8i8: \
case X86::MNEMONIC##16i16: \
case X86::MNEMONIC##32i32: \
case X86::MNEMONIC##64i32:

◆ LLVM_EXPAND_INSTR_SIZES

#define LLVM_EXPAND_INSTR_SIZES (   MNEMONIC,
  SUFFIX 
)
Value:
case X86::MNEMONIC##8##SUFFIX: \
case X86::MNEMONIC##16##SUFFIX: \
case X86::MNEMONIC##32##SUFFIX: \
case X86::MNEMONIC##64##SUFFIX:

◆ PASS_KEY

#define PASS_KEY   "x86-flags-copy-lowering"

Definition at line 65 of file X86FlagsCopyLowering.cpp.

Function Documentation

◆ getCondFromFCMOV()

static X86::CondCode getCondFromFCMOV ( unsigned  Opcode)
static

◆ getMnemonicFromOpcode()

static FlagArithMnemonic getMnemonicFromOpcode ( unsigned  Opcode)
static

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( X86FlagsCopyLoweringPass  ,
DEBUG_TYPE  ,
"X86 EFLAGS copy lowering ,
false  ,
false   
)

◆ splitBlock()

static MachineBasicBlock& splitBlock ( MachineBasicBlock MBB,
MachineInstr SplitI,
const X86InstrInfo TII 
)
static

◆ STATISTIC() [1/4]

STATISTIC ( NumAddsInserted  ,
"Number of adds instructions inserted"   
)

◆ STATISTIC() [2/4]

STATISTIC ( NumCopiesEliminated  ,
"Number of copies of EFLAGS eliminated"   
)

◆ STATISTIC() [3/4]

STATISTIC ( NumSetCCsInserted  ,
"Number of setCC instructions inserted"   
)

◆ STATISTIC() [4/4]

STATISTIC ( NumTestsInserted  ,
"Number of test instructions inserted"   
)

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 137 of file X86FlagsCopyLowering.cpp.

◆ false

X86 EFLAGS copy false

Definition at line 138 of file X86FlagsCopyLowering.cpp.

◆ lowering

X86 EFLAGS copy lowering

Definition at line 138 of file X86FlagsCopyLowering.cpp.

i8
Clang compiles this i8
Definition: README.txt:504
LLVM_EXPAND_INSTR_SIZES
#define LLVM_EXPAND_INSTR_SIZES(MNEMONIC, SUFFIX)
i32
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32
Definition: README.txt:122
i16
< i32 > ret i32 conv5 And the following x86 eax movsbl ecx cmpl ecx sete al movzbl eax ret It should be possible to eliminate the sign extensions LLVM misses a load store narrowing opportunity in this i16
Definition: README.txt:1493