LLVM 22.0.0git
Macros | Functions | Variables
SIFixSGPRCopies.cpp File Reference

Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this: More...

#include "SIFixSGPRCopies.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/InitializePasses.h"
#include "llvm/Target/TargetMachine.h"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "si-fix-sgpr-copies"

Functions

 INITIALIZE_PASS_BEGIN (SIFixSGPRCopiesLegacy, DEBUG_TYPE, "SI Fix SGPR copies", false, false) INITIALIZE_PASS_END(SIFixSGPRCopiesLegacy
static std::pair< const TargetRegisterClass *, const TargetRegisterClass * > getCopyRegClasses (const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI)
static bool isVGPRToSGPRCopy (const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI)
static bool isSGPRToVGPRCopy (const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI)
static bool tryChangeVGPRtoSGPRinCopy (MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII)
static bool foldVGPRCopyIntoRegSequence (MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI)
static bool isSafeToFoldImmIntoCopy (const MachineInstr *Copy, const MachineInstr *MoveImm, const SIInstrInfo *TII, unsigned &SMovOp, int64_t &Imm)
template<class UnaryPredicate>
bool searchPredecessors (const MachineBasicBlock *MBB, const MachineBasicBlock *CutOff, UnaryPredicate Predicate)
static bool isReachable (const MachineInstr *From, const MachineInstr *To, const MachineBasicBlock *CutOff, MachineDominatorTree &MDT)
static MachineBasicBlock::iterator getFirstNonPrologue (MachineBasicBlock *MBB, const TargetInstrInfo *TII)
static bool hoistAndMergeSGPRInits (unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo *TRI, MachineDominatorTree &MDT, const TargetInstrInfo *TII)

Variables

static cl::opt< bool > EnableM0Merge ("amdgpu-enable-merge-m0", cl::desc("Merge and hoist M0 initializations"), cl::init(true))
 DEBUG_TYPE
SI Fix SGPR copies
SI Fix SGPR false

Detailed Description

Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:

Register Class <vsrc> is the union of <vgpr> and <sgpr>

BB0: %0 <sgpr> = SCALAR_INST %1 <vsrc> = COPY %0 <sgpr> ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <vsrc> = COPY %2 <vgpr> BB2: %4 <vsrc> = PHI %1 <vsrc>, <bb.0>, %3 <vrsc>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <vsrc>

The coalescer will begin at BB0 and eliminate its copy, then the resulting code will look like this:

BB0: %0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <vsrc> = COPY %2 <vgpr> BB2: %4 <sgpr> = PHI %0 <sgpr>, <bb.0>, %3 <vsrc>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <sgpr>

Now that the result of the PHI instruction is an SGPR, the register allocator is now forced to constrain the register class of %3 to <sgpr> so we end up with final code like this:

BB0: %0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: %2 <vgpr> = VECTOR_INST %3 <sgpr> = COPY %2 <vgpr> BB2: %4 <sgpr> = PHI %0 <sgpr>, <bb.0>, %3 <sgpr>, <bb.1> %5 <vgpr> = VECTOR_INST %4 <sgpr>

Now this code contains an illegal copy from a VGPR to an SGPR.

In order to avoid this problem, this pass searches for PHI instructions which define a <vsrc> register and constrains its definition class to <vgpr> if the user of the PHI's definition register is a vector instruction. If the PHI's definition class is constrained to <vgpr> then the coalescer will be unable to perform the COPY removal from the above example which ultimately led to the creation of an illegal COPY.

Definition in file SIFixSGPRCopies.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "si-fix-sgpr-copies"

Definition at line 77 of file SIFixSGPRCopies.cpp.

Function Documentation

◆ foldVGPRCopyIntoRegSequence()

bool foldVGPRCopyIntoRegSequence ( MachineInstr & MI,
const SIRegisterInfo * TRI,
const SIInstrInfo * TII,
MachineRegisterInfo & MRI )
static

Definition at line 278 of file SIFixSGPRCopies.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineInstr::eraseFromParent(), getCopyRegClasses(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), I, llvm::MachineInstr::isCopy(), llvm::Register::isPhysical(), isSGPRToVGPRCopy(), llvm::RegState::Kill, MI, MRI, N, Opc, SubReg, TII, TRI, and tryChangeVGPRtoSGPRinCopy().

◆ getCopyRegClasses()

std::pair< const TargetRegisterClass *, const TargetRegisterClass * > getCopyRegClasses ( const MachineInstr & Copy,
const SIRegisterInfo & TRI,
const MachineRegisterInfo & MRI )
static

Definition at line 203 of file SIFixSGPRCopies.cpp.

References llvm::Register::isVirtual(), MRI, and TRI.

Referenced by foldVGPRCopyIntoRegSequence().

◆ getFirstNonPrologue()

MachineBasicBlock::iterator getFirstNonPrologue ( MachineBasicBlock * MBB,
const TargetInstrInfo * TII )
static

Definition at line 440 of file SIFixSGPRCopies.cpp.

References I, MBB, and TII.

Referenced by hoistAndMergeSGPRInits().

◆ hoistAndMergeSGPRInits()

bool hoistAndMergeSGPRInits ( unsigned Reg,
const MachineRegisterInfo & MRI,
const TargetRegisterInfo * TRI,
MachineDominatorTree & MDT,
const TargetInstrInfo * TII )
static

Definition at line 452 of file SIFixSGPRCopies.cpp.

References llvm::any_of(), assert(), B(), llvm::CallingConv::C, Changed, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::dbgs(), llvm::MachineDominatorTree::dominates(), E(), llvm::DominatorTreeBase< NodeT, IsPostDom >::findNearestCommonDominator(), getFirstNonPrologue(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), isReachable(), LLVM_DEBUG, MBB, MI, MRI, llvm::printMBBReference(), llvm::DominatorTreeBase< NodeT, IsPostDom >::properlyDominates(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, TII, and TRI.

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( SIFixSGPRCopiesLegacy ,
DEBUG_TYPE ,
"SI Fix SGPR copies" ,
false ,
false  )

References DEBUG_TYPE, and INITIALIZE_PASS_DEPENDENCY.

◆ isReachable()

bool isReachable ( const MachineInstr * From,
const MachineInstr * To,
const MachineBasicBlock * CutOff,
MachineDominatorTree & MDT )
static

Definition at line 421 of file SIFixSGPRCopies.cpp.

References llvm::MachineDominatorTree::dominates(), llvm::MachineInstr::getParent(), MBB, and searchPredecessors().

Referenced by hoistAndMergeSGPRInits().

◆ isSafeToFoldImmIntoCopy()

bool isSafeToFoldImmIntoCopy ( const MachineInstr * Copy,
const MachineInstr * MoveImm,
const SIInstrInfo * TII,
unsigned & SMovOp,
int64_t & Imm )
static

Definition at line 357 of file SIFixSGPRCopies.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and TII.

◆ isSGPRToVGPRCopy()

bool isSGPRToVGPRCopy ( const TargetRegisterClass * SrcRC,
const TargetRegisterClass * DstRC,
const SIRegisterInfo & TRI )
static

Definition at line 230 of file SIFixSGPRCopies.cpp.

References TRI.

Referenced by foldVGPRCopyIntoRegSequence().

◆ isVGPRToSGPRCopy()

bool isVGPRToSGPRCopy ( const TargetRegisterClass * SrcRC,
const TargetRegisterClass * DstRC,
const SIRegisterInfo & TRI )
static

Definition at line 223 of file SIFixSGPRCopies.cpp.

References TRI.

◆ searchPredecessors()

template<class UnaryPredicate>
bool searchPredecessors ( const MachineBasicBlock * MBB,
const MachineBasicBlock * CutOff,
UnaryPredicate Predicate )

Definition at line 393 of file SIFixSGPRCopies.cpp.

References llvm::SmallVectorImpl< T >::append(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), MBB, and llvm::SmallVectorImpl< T >::pop_back_val().

Referenced by isReachable().

◆ tryChangeVGPRtoSGPRinCopy()

bool tryChangeVGPRtoSGPRinCopy ( MachineInstr & MI,
const SIRegisterInfo * TRI,
const SIInstrInfo * TII )
static

Definition at line 237 of file SIFixSGPRCopies.cpp.

References llvm::Register::isVirtual(), MI, MRI, OpIdx, TII, TRI, and UseMI.

Referenced by foldVGPRCopyIntoRegSequence().

Variable Documentation

◆ copies

SI Fix SGPR copies

Definition at line 191 of file SIFixSGPRCopies.cpp.

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 191 of file SIFixSGPRCopies.cpp.

◆ EnableM0Merge

cl::opt< bool > EnableM0Merge("amdgpu-enable-merge-m0", cl::desc("Merge and hoist M0 initializations"), cl::init(true)) ( "amdgpu-enable-merge-m0" ,
cl::desc("Merge and hoist M0 initializations") ,
cl::init(true)  )
static

◆ false

SI Fix SGPR false

Definition at line 192 of file SIFixSGPRCopies.cpp.

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