19#define DEBUG_TYPE "ppc-reg-bank-info"
21#define GET_TARGET_REGBANK_IMPL
22#include "PPCGenRegisterBank.inc"
25#include "PPCGenRegisterBankInfo.def"
35 case PPC::G8RCRegClassID:
36 case PPC::G8RC_NOX0RegClassID:
37 case PPC::G8RC_and_G8RC_NOX0RegClassID:
38 case PPC::GPRCRegClassID:
39 case PPC::GPRC_NOR0RegClassID:
40 case PPC::GPRC_and_GPRC_NOR0RegClassID:
42 case PPC::VSFRCRegClassID:
43 case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
44 case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
45 case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
46 case PPC::F8RCRegClassID:
47 case PPC::VFRCRegClassID:
48 case PPC::VSSRCRegClassID:
49 case PPC::F4RCRegClassID:
51 case PPC::VSRCRegClassID:
52 case PPC::VRRCRegClassID:
53 case PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
54 case PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
55 case PPC::SPILLTOVSRRCRegClassID:
56 case PPC::VSLRCRegClassID:
57 case PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
59 case PPC::CRRCRegClassID:
60 case PPC::CRBITRCRegClassID:
69 const unsigned Opc =
MI.getOpcode();
85 unsigned NumOperands =
MI.getNumOperands();
92 case TargetOpcode::G_ADD:
93 case TargetOpcode::G_SUB:
95 case TargetOpcode::G_AND:
96 case TargetOpcode::G_OR:
97 case TargetOpcode::G_XOR:
99 case TargetOpcode::G_SEXT:
100 case TargetOpcode::G_ZEXT:
101 case TargetOpcode::G_ANYEXT: {
102 assert(NumOperands <= 3 &&
103 "This code is for instructions with 3 or less operands");
104 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
116 case TargetOpcode::G_FADD:
117 case TargetOpcode::G_FSUB:
118 case TargetOpcode::G_FMUL:
119 case TargetOpcode::G_FDIV: {
124 "Unsupported floating point types!\n");
138 case TargetOpcode::G_FCMP: {
139 unsigned CmpSize =
MRI.getType(
MI.getOperand(2).getReg()).getSizeInBits();
147 case TargetOpcode::G_CONSTANT:
150 case TargetOpcode::G_CONSTANT_POOL:
153 case TargetOpcode::G_FPTOUI:
154 case TargetOpcode::G_FPTOSI: {
163 case TargetOpcode::G_UITOFP:
164 case TargetOpcode::G_SITOFP: {
173 case TargetOpcode::G_LOAD: {
176 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
185 return onlyUsesFP(UseMI, MRI, TRI);
196 case TargetOpcode::G_STORE: {
210 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
217 case TargetOpcode::G_BITCAST: {
218 LLT DstTy =
MRI.getType(
MI.getOperand(0).getReg());
219 LLT SrcTy =
MRI.getType(
MI.getOperand(1).getReg());
227 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank;
228 const RegisterBank &SrcRB = SrcIsGPR ? PPC::GPRRegBank : PPC::VECRegBank;
247 case TargetOpcode::G_FADD:
248 case TargetOpcode::G_FSUB:
249 case TargetOpcode::G_FMUL:
250 case TargetOpcode::G_FMA:
251 case TargetOpcode::G_FDIV:
252 case TargetOpcode::G_FCONSTANT:
253 case TargetOpcode::G_FPEXT:
254 case TargetOpcode::G_FPTRUNC:
255 case TargetOpcode::G_FCEIL:
256 case TargetOpcode::G_FFLOOR:
257 case TargetOpcode::G_FNEARBYINT:
258 case TargetOpcode::G_FNEG:
259 case TargetOpcode::G_FCOS:
260 case TargetOpcode::G_FSIN:
261 case TargetOpcode::G_FLOG10:
262 case TargetOpcode::G_FLOG:
263 case TargetOpcode::G_FLOG2:
264 case TargetOpcode::G_FSQRT:
265 case TargetOpcode::G_FABS:
266 case TargetOpcode::G_FEXP:
267 case TargetOpcode::G_FRINT:
268 case TargetOpcode::G_INTRINSIC_TRUNC:
269 case TargetOpcode::G_INTRINSIC_ROUND:
270 case TargetOpcode::G_FMAXNUM:
271 case TargetOpcode::G_FMINNUM:
272 case TargetOpcode::G_FMAXIMUM:
273 case TargetOpcode::G_FMINIMUM:
290 unsigned Depth)
const {
291 unsigned Op =
MI.getOpcode();
292 if (Op == TargetOpcode::G_INTRINSIC &&
isFPIntrinsic(
MI.getIntrinsicID()))
301 if (Op != TargetOpcode::COPY && !
MI.isPHI() &&
307 if (RB == &PPC::FPRRegBank)
309 if (RB == &PPC::GPRRegBank)
316 if (!
MI.isPHI() ||
Depth > MaxFPRSearchDepth)
321 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
330 unsigned Depth)
const {
331 switch (
MI.getOpcode()) {
332 case TargetOpcode::G_FPTOSI:
333 case TargetOpcode::G_FPTOUI:
334 case TargetOpcode::G_FCMP:
335 case TargetOpcode::G_LROUND:
336 case TargetOpcode::G_LLROUND:
349 unsigned Depth)
const {
350 switch (
MI.getOpcode()) {
351 case TargetOpcode::G_SITOFP:
352 case TargetOpcode::G_UITOFP:
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isFPIntrinsic(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
unsigned const TargetRegisterInfo * TRI
This file declares the targeting of the RegisterBankInfo class for PowerPC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static const RegisterBankInfo::ValueMapping * getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size)
Get the pointer to the ValueMapping of the operands of a copy instruction from the SrcBankID register...
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx RBIdx)
Get the pointer to the ValueMapping representing the RegisterBank at RBIdx.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
PPCRegisterBankInfo(const TargetRegisterInfo &TRI)
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Helper struct that represents how a value is mapped through different register banks.