LLVM 19.0.0git
ARMAsmParser.cpp
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1//===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARMBaseInstrInfo.h"
10#include "ARMFeatures.h"
17#include "Utils/ARMBaseInfo.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/SmallSet.h"
24#include "llvm/ADT/StringMap.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSet.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCInstrDesc.h"
33#include "llvm/MC/MCInstrInfo.h"
41#include "llvm/MC/MCSection.h"
42#include "llvm/MC/MCStreamer.h"
44#include "llvm/MC/MCSymbol.h"
51#include "llvm/Support/Debug.h"
54#include "llvm/Support/SMLoc.h"
59#include <algorithm>
60#include <cassert>
61#include <cstddef>
62#include <cstdint>
63#include <iterator>
64#include <limits>
65#include <memory>
66#include <optional>
67#include <string>
68#include <utility>
69#include <vector>
70
71#define DEBUG_TYPE "asm-parser"
72
73using namespace llvm;
74
75namespace {
76class ARMOperand;
77
78enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
79
80static cl::opt<ImplicitItModeTy> ImplicitItMode(
81 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
82 cl::desc("Allow conditional instructions outdside of an IT block"),
83 cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
84 "Accept in both ISAs, emit implicit ITs in Thumb"),
85 clEnumValN(ImplicitItModeTy::Never, "never",
86 "Warn in ARM, reject in Thumb"),
87 clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
88 "Accept in ARM, reject in Thumb"),
89 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
90 "Warn in ARM, emit implicit ITs in Thumb")));
91
92static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
93 cl::init(false));
94
95enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
96
97static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
98 // Position==0 means we're not in an IT block at all. Position==1
99 // means we want the first state bit, which is always 0 (Then).
100 // Position==2 means we want the second state bit, stored at bit 3
101 // of Mask, and so on downwards. So (5 - Position) will shift the
102 // right bit down to bit 0, including the always-0 bit at bit 4 for
103 // the mandatory initial Then.
104 return (Mask >> (5 - Position) & 1);
105}
106
107class UnwindContext {
108 using Locs = SmallVector<SMLoc, 4>;
109
110 MCAsmParser &Parser;
111 Locs FnStartLocs;
112 Locs CantUnwindLocs;
113 Locs PersonalityLocs;
114 Locs PersonalityIndexLocs;
115 Locs HandlerDataLocs;
116 int FPReg;
117
118public:
119 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
120
121 bool hasFnStart() const { return !FnStartLocs.empty(); }
122 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
123 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
124
125 bool hasPersonality() const {
126 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
127 }
128
129 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
130 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
131 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
132 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
133 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
134
135 void saveFPReg(int Reg) { FPReg = Reg; }
136 int getFPReg() const { return FPReg; }
137
138 void emitFnStartLocNotes() const {
139 for (const SMLoc &Loc : FnStartLocs)
140 Parser.Note(Loc, ".fnstart was specified here");
141 }
142
143 void emitCantUnwindLocNotes() const {
144 for (const SMLoc &Loc : CantUnwindLocs)
145 Parser.Note(Loc, ".cantunwind was specified here");
146 }
147
148 void emitHandlerDataLocNotes() const {
149 for (const SMLoc &Loc : HandlerDataLocs)
150 Parser.Note(Loc, ".handlerdata was specified here");
151 }
152
153 void emitPersonalityLocNotes() const {
154 for (Locs::const_iterator PI = PersonalityLocs.begin(),
155 PE = PersonalityLocs.end(),
156 PII = PersonalityIndexLocs.begin(),
157 PIE = PersonalityIndexLocs.end();
158 PI != PE || PII != PIE;) {
159 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
160 Parser.Note(*PI++, ".personality was specified here");
161 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
162 Parser.Note(*PII++, ".personalityindex was specified here");
163 else
164 llvm_unreachable(".personality and .personalityindex cannot be "
165 "at the same location");
166 }
167 }
168
169 void reset() {
170 FnStartLocs = Locs();
171 CantUnwindLocs = Locs();
172 PersonalityLocs = Locs();
173 HandlerDataLocs = Locs();
174 PersonalityIndexLocs = Locs();
175 FPReg = ARM::SP;
176 }
177};
178
179// Various sets of ARM instruction mnemonics which are used by the asm parser
180class ARMMnemonicSets {
181 StringSet<> CDE;
182 StringSet<> CDEWithVPTSuffix;
183public:
184 ARMMnemonicSets(const MCSubtargetInfo &STI);
185
186 /// Returns true iff a given mnemonic is a CDE instruction
187 bool isCDEInstr(StringRef Mnemonic) {
188 // Quick check before searching the set
189 if (!Mnemonic.starts_with("cx") && !Mnemonic.starts_with("vcx"))
190 return false;
191 return CDE.count(Mnemonic);
192 }
193
194 /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction
195 /// (possibly with a predication suffix "e" or "t")
196 bool isVPTPredicableCDEInstr(StringRef Mnemonic) {
197 if (!Mnemonic.starts_with("vcx"))
198 return false;
199 return CDEWithVPTSuffix.count(Mnemonic);
200 }
201
202 /// Returns true iff a given mnemonic is an IT-predicable CDE instruction
203 /// (possibly with a condition suffix)
204 bool isITPredicableCDEInstr(StringRef Mnemonic) {
205 if (!Mnemonic.starts_with("cx"))
206 return false;
207 return Mnemonic.starts_with("cx1a") || Mnemonic.starts_with("cx1da") ||
208 Mnemonic.starts_with("cx2a") || Mnemonic.starts_with("cx2da") ||
209 Mnemonic.starts_with("cx3a") || Mnemonic.starts_with("cx3da");
210 }
211
212 /// Return true iff a given mnemonic is an integer CDE instruction with
213 /// dual-register destination
214 bool isCDEDualRegInstr(StringRef Mnemonic) {
215 if (!Mnemonic.starts_with("cx"))
216 return false;
217 return Mnemonic == "cx1d" || Mnemonic == "cx1da" ||
218 Mnemonic == "cx2d" || Mnemonic == "cx2da" ||
219 Mnemonic == "cx3d" || Mnemonic == "cx3da";
220 }
221};
222
223ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) {
224 for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da",
225 "cx2", "cx2a", "cx2d", "cx2da",
226 "cx3", "cx3a", "cx3d", "cx3da", })
227 CDE.insert(Mnemonic);
228 for (StringRef Mnemonic :
229 {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) {
230 CDE.insert(Mnemonic);
231 CDEWithVPTSuffix.insert(Mnemonic);
232 CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t");
233 CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e");
234 }
235}
236
237class ARMAsmParser : public MCTargetAsmParser {
238 const MCRegisterInfo *MRI;
239 UnwindContext UC;
240 ARMMnemonicSets MS;
241
242 ARMTargetStreamer &getTargetStreamer() {
243 assert(getParser().getStreamer().getTargetStreamer() &&
244 "do not have a target streamer");
246 return static_cast<ARMTargetStreamer &>(TS);
247 }
248
249 // Map of register aliases registers via the .req directive.
250 StringMap<unsigned> RegisterReqs;
251
252 bool NextSymbolIsThumb;
253
254 bool useImplicitITThumb() const {
255 return ImplicitItMode == ImplicitItModeTy::Always ||
256 ImplicitItMode == ImplicitItModeTy::ThumbOnly;
257 }
258
259 bool useImplicitITARM() const {
260 return ImplicitItMode == ImplicitItModeTy::Always ||
261 ImplicitItMode == ImplicitItModeTy::ARMOnly;
262 }
263
264 struct {
265 ARMCC::CondCodes Cond; // Condition for IT block.
266 unsigned Mask:4; // Condition mask for instructions.
267 // Starting at first 1 (from lsb).
268 // '1' condition as indicated in IT.
269 // '0' inverse of condition (else).
270 // Count of instructions in IT block is
271 // 4 - trailingzeroes(mask)
272 // Note that this does not have the same encoding
273 // as in the IT instruction, which also depends
274 // on the low bit of the condition code.
275
276 unsigned CurPosition; // Current position in parsing of IT
277 // block. In range [0,4], with 0 being the IT
278 // instruction itself. Initialized according to
279 // count of instructions in block. ~0U if no
280 // active IT block.
281
282 bool IsExplicit; // true - The IT instruction was present in the
283 // input, we should not modify it.
284 // false - The IT instruction was added
285 // implicitly, we can extend it if that
286 // would be legal.
287 } ITState;
288
289 SmallVector<MCInst, 4> PendingConditionalInsts;
290
291 void flushPendingInstructions(MCStreamer &Out) override {
292 if (!inImplicitITBlock()) {
293 assert(PendingConditionalInsts.size() == 0);
294 return;
295 }
296
297 // Emit the IT instruction
298 MCInst ITInst;
299 ITInst.setOpcode(ARM::t2IT);
300 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
301 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
302 Out.emitInstruction(ITInst, getSTI());
303
304 // Emit the conditional instructions
305 assert(PendingConditionalInsts.size() <= 4);
306 for (const MCInst &Inst : PendingConditionalInsts) {
307 Out.emitInstruction(Inst, getSTI());
308 }
309 PendingConditionalInsts.clear();
310
311 // Clear the IT state
312 ITState.Mask = 0;
313 ITState.CurPosition = ~0U;
314 }
315
316 bool inITBlock() { return ITState.CurPosition != ~0U; }
317 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
318 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
319
320 bool lastInITBlock() {
321 return ITState.CurPosition == 4 - (unsigned)llvm::countr_zero(ITState.Mask);
322 }
323
324 void forwardITPosition() {
325 if (!inITBlock()) return;
326 // Move to the next instruction in the IT block, if there is one. If not,
327 // mark the block as done, except for implicit IT blocks, which we leave
328 // open until we find an instruction that can't be added to it.
329 unsigned TZ = llvm::countr_zero(ITState.Mask);
330 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
331 ITState.CurPosition = ~0U; // Done with the IT block after this.
332 }
333
334 // Rewind the state of the current IT block, removing the last slot from it.
335 void rewindImplicitITPosition() {
336 assert(inImplicitITBlock());
337 assert(ITState.CurPosition > 1);
338 ITState.CurPosition--;
339 unsigned TZ = llvm::countr_zero(ITState.Mask);
340 unsigned NewMask = 0;
341 NewMask |= ITState.Mask & (0xC << TZ);
342 NewMask |= 0x2 << TZ;
343 ITState.Mask = NewMask;
344 }
345
346 // Rewind the state of the current IT block, removing the last slot from it.
347 // If we were at the first slot, this closes the IT block.
348 void discardImplicitITBlock() {
349 assert(inImplicitITBlock());
350 assert(ITState.CurPosition == 1);
351 ITState.CurPosition = ~0U;
352 }
353
354 // Get the condition code corresponding to the current IT block slot.
355 ARMCC::CondCodes currentITCond() {
356 unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
357 return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
358 }
359
360 // Invert the condition of the current IT block slot without changing any
361 // other slots in the same block.
362 void invertCurrentITCondition() {
363 if (ITState.CurPosition == 1) {
364 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
365 } else {
366 ITState.Mask ^= 1 << (5 - ITState.CurPosition);
367 }
368 }
369
370 // Returns true if the current IT block is full (all 4 slots used).
371 bool isITBlockFull() {
372 return inITBlock() && (ITState.Mask & 1);
373 }
374
375 // Extend the current implicit IT block to have one more slot with the given
376 // condition code.
377 void extendImplicitITBlock(ARMCC::CondCodes Cond) {
378 assert(inImplicitITBlock());
379 assert(!isITBlockFull());
380 assert(Cond == ITState.Cond ||
381 Cond == ARMCC::getOppositeCondition(ITState.Cond));
382 unsigned TZ = llvm::countr_zero(ITState.Mask);
383 unsigned NewMask = 0;
384 // Keep any existing condition bits.
385 NewMask |= ITState.Mask & (0xE << TZ);
386 // Insert the new condition bit.
387 NewMask |= (Cond != ITState.Cond) << TZ;
388 // Move the trailing 1 down one bit.
389 NewMask |= 1 << (TZ - 1);
390 ITState.Mask = NewMask;
391 }
392
393 // Create a new implicit IT block with a dummy condition code.
394 void startImplicitITBlock() {
395 assert(!inITBlock());
396 ITState.Cond = ARMCC::AL;
397 ITState.Mask = 8;
398 ITState.CurPosition = 1;
399 ITState.IsExplicit = false;
400 }
401
402 // Create a new explicit IT block with the given condition and mask.
403 // The mask should be in the format used in ARMOperand and
404 // MCOperand, with a 1 implying 'e', regardless of the low bit of
405 // the condition.
406 void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
407 assert(!inITBlock());
408 ITState.Cond = Cond;
409 ITState.Mask = Mask;
410 ITState.CurPosition = 0;
411 ITState.IsExplicit = true;
412 }
413
414 struct {
415 unsigned Mask : 4;
416 unsigned CurPosition;
417 } VPTState;
418 bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
419 void forwardVPTPosition() {
420 if (!inVPTBlock()) return;
421 unsigned TZ = llvm::countr_zero(VPTState.Mask);
422 if (++VPTState.CurPosition == 5 - TZ)
423 VPTState.CurPosition = ~0U;
424 }
425
426 void Note(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
427 return getParser().Note(L, Msg, Range);
428 }
429
430 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
431 return getParser().Warning(L, Msg, Range);
432 }
433
434 bool Error(SMLoc L, const Twine &Msg, SMRange Range = std::nullopt) {
435 return getParser().Error(L, Msg, Range);
436 }
437
438 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
439 unsigned MnemonicOpsEndInd, unsigned ListIndex,
440 bool IsARPop = false);
441 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
442 unsigned MnemonicOpsEndInd, unsigned ListIndex);
443
444 int tryParseRegister(bool AllowOutofBoundReg = false);
445 bool tryParseRegisterWithWriteBack(OperandVector &);
446 int tryParseShiftRegister(OperandVector &);
447 std::optional<ARM_AM::ShiftOpc> tryParseShiftToken();
448 bool parseRegisterList(OperandVector &, bool EnforceOrder = true,
449 bool AllowRAAC = false,
450 bool AllowOutOfBoundReg = false);
451 bool parseMemory(OperandVector &);
452 bool parseOperand(OperandVector &, StringRef Mnemonic);
453 bool parseImmExpr(int64_t &Out);
454 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
455 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
456 unsigned &ShiftAmount);
457 bool parseLiteralValues(unsigned Size, SMLoc L);
458 bool parseDirectiveThumb(SMLoc L);
459 bool parseDirectiveARM(SMLoc L);
460 bool parseDirectiveThumbFunc(SMLoc L);
461 bool parseDirectiveCode(SMLoc L);
462 bool parseDirectiveSyntax(SMLoc L);
463 bool parseDirectiveReq(StringRef Name, SMLoc L);
464 bool parseDirectiveUnreq(SMLoc L);
465 bool parseDirectiveArch(SMLoc L);
466 bool parseDirectiveEabiAttr(SMLoc L);
467 bool parseDirectiveCPU(SMLoc L);
468 bool parseDirectiveFPU(SMLoc L);
469 bool parseDirectiveFnStart(SMLoc L);
470 bool parseDirectiveFnEnd(SMLoc L);
471 bool parseDirectiveCantUnwind(SMLoc L);
472 bool parseDirectivePersonality(SMLoc L);
473 bool parseDirectiveHandlerData(SMLoc L);
474 bool parseDirectiveSetFP(SMLoc L);
475 bool parseDirectivePad(SMLoc L);
476 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
477 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
478 bool parseDirectiveLtorg(SMLoc L);
479 bool parseDirectiveEven(SMLoc L);
480 bool parseDirectivePersonalityIndex(SMLoc L);
481 bool parseDirectiveUnwindRaw(SMLoc L);
482 bool parseDirectiveTLSDescSeq(SMLoc L);
483 bool parseDirectiveMovSP(SMLoc L);
484 bool parseDirectiveObjectArch(SMLoc L);
485 bool parseDirectiveArchExtension(SMLoc L);
486 bool parseDirectiveAlign(SMLoc L);
487 bool parseDirectiveThumbSet(SMLoc L);
488
489 bool parseDirectiveSEHAllocStack(SMLoc L, bool Wide);
490 bool parseDirectiveSEHSaveRegs(SMLoc L, bool Wide);
491 bool parseDirectiveSEHSaveSP(SMLoc L);
492 bool parseDirectiveSEHSaveFRegs(SMLoc L);
493 bool parseDirectiveSEHSaveLR(SMLoc L);
494 bool parseDirectiveSEHPrologEnd(SMLoc L, bool Fragment);
495 bool parseDirectiveSEHNop(SMLoc L, bool Wide);
496 bool parseDirectiveSEHEpilogStart(SMLoc L, bool Condition);
497 bool parseDirectiveSEHEpilogEnd(SMLoc L);
498 bool parseDirectiveSEHCustom(SMLoc L);
499
500 std::unique_ptr<ARMOperand> defaultCondCodeOp();
501 std::unique_ptr<ARMOperand> defaultCCOutOp();
502 std::unique_ptr<ARMOperand> defaultVPTPredOp();
503
504 bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
505 StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
506 ARMCC::CondCodes &PredicationCode,
507 ARMVCC::VPTCodes &VPTPredicationCode,
508 bool &CarrySetting, unsigned &ProcessorIMod,
509 StringRef &ITMask);
510 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
511 StringRef FullInst, bool &CanAcceptCarrySet,
512 bool &CanAcceptPredicationCode,
513 bool &CanAcceptVPTPredicationCode);
514 bool enableArchExtFeature(StringRef Name, SMLoc &ExtLoc);
515
516 void tryConvertingToTwoOperandForm(StringRef Mnemonic,
517 ARMCC::CondCodes PredicationCode,
518 bool CarrySetting, OperandVector &Operands,
519 unsigned MnemonicOpsEndInd);
520
521 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands,
522 unsigned MnemonicOpsEndInd);
523
524 bool isThumb() const {
525 // FIXME: Can tablegen auto-generate this?
526 return getSTI().hasFeature(ARM::ModeThumb);
527 }
528
529 bool isThumbOne() const {
530 return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2);
531 }
532
533 bool isThumbTwo() const {
534 return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2);
535 }
536
537 bool hasThumb() const {
538 return getSTI().hasFeature(ARM::HasV4TOps);
539 }
540
541 bool hasThumb2() const {
542 return getSTI().hasFeature(ARM::FeatureThumb2);
543 }
544
545 bool hasV6Ops() const {
546 return getSTI().hasFeature(ARM::HasV6Ops);
547 }
548
549 bool hasV6T2Ops() const {
550 return getSTI().hasFeature(ARM::HasV6T2Ops);
551 }
552
553 bool hasV6MOps() const {
554 return getSTI().hasFeature(ARM::HasV6MOps);
555 }
556
557 bool hasV7Ops() const {
558 return getSTI().hasFeature(ARM::HasV7Ops);
559 }
560
561 bool hasV8Ops() const {
562 return getSTI().hasFeature(ARM::HasV8Ops);
563 }
564
565 bool hasV8MBaseline() const {
566 return getSTI().hasFeature(ARM::HasV8MBaselineOps);
567 }
568
569 bool hasV8MMainline() const {
570 return getSTI().hasFeature(ARM::HasV8MMainlineOps);
571 }
572 bool hasV8_1MMainline() const {
573 return getSTI().hasFeature(ARM::HasV8_1MMainlineOps);
574 }
575 bool hasMVEFloat() const {
576 return getSTI().hasFeature(ARM::HasMVEFloatOps);
577 }
578 bool hasCDE() const {
579 return getSTI().hasFeature(ARM::HasCDEOps);
580 }
581 bool has8MSecExt() const {
582 return getSTI().hasFeature(ARM::Feature8MSecExt);
583 }
584
585 bool hasARM() const {
586 return !getSTI().hasFeature(ARM::FeatureNoARM);
587 }
588
589 bool hasDSP() const {
590 return getSTI().hasFeature(ARM::FeatureDSP);
591 }
592
593 bool hasD32() const {
594 return getSTI().hasFeature(ARM::FeatureD32);
595 }
596
597 bool hasV8_1aOps() const {
598 return getSTI().hasFeature(ARM::HasV8_1aOps);
599 }
600
601 bool hasRAS() const {
602 return getSTI().hasFeature(ARM::FeatureRAS);
603 }
604
605 void SwitchMode() {
606 MCSubtargetInfo &STI = copySTI();
607 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
609 }
610
611 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
612
613 bool isMClass() const {
614 return getSTI().hasFeature(ARM::FeatureMClass);
615 }
616
617 /// @name Auto-generated Match Functions
618 /// {
619
620#define GET_ASSEMBLER_HEADER
621#include "ARMGenAsmMatcher.inc"
622
623 /// }
624
625 ParseStatus parseITCondCode(OperandVector &);
626 ParseStatus parseCoprocNumOperand(OperandVector &);
627 ParseStatus parseCoprocRegOperand(OperandVector &);
628 ParseStatus parseCoprocOptionOperand(OperandVector &);
629 ParseStatus parseMemBarrierOptOperand(OperandVector &);
630 ParseStatus parseTraceSyncBarrierOptOperand(OperandVector &);
631 ParseStatus parseInstSyncBarrierOptOperand(OperandVector &);
632 ParseStatus parseProcIFlagsOperand(OperandVector &);
633 ParseStatus parseMSRMaskOperand(OperandVector &);
634 ParseStatus parseBankedRegOperand(OperandVector &);
635 ParseStatus parsePKHImm(OperandVector &O, ARM_AM::ShiftOpc, int Low,
636 int High);
637 ParseStatus parsePKHLSLImm(OperandVector &O) {
638 return parsePKHImm(O, ARM_AM::lsl, 0, 31);
639 }
640 ParseStatus parsePKHASRImm(OperandVector &O) {
641 return parsePKHImm(O, ARM_AM::asr, 1, 32);
642 }
643 ParseStatus parseSetEndImm(OperandVector &);
644 ParseStatus parseShifterImm(OperandVector &);
645 ParseStatus parseRotImm(OperandVector &);
646 ParseStatus parseModImm(OperandVector &);
647 ParseStatus parseBitfield(OperandVector &);
648 ParseStatus parsePostIdxReg(OperandVector &);
649 ParseStatus parseAM3Offset(OperandVector &);
650 ParseStatus parseFPImm(OperandVector &);
651 ParseStatus parseVectorList(OperandVector &);
652 ParseStatus parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
653 SMLoc &EndLoc);
654
655 // Asm Match Converter Methods
656 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
657 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
658 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
659
660 bool validateInstruction(MCInst &Inst, const OperandVector &Ops,
661 unsigned MnemonicOpsEndInd);
662 bool processInstruction(MCInst &Inst, const OperandVector &Ops,
663 unsigned MnemonicOpsEndInd, MCStreamer &Out);
664 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic,
666 unsigned MnemonicOpsEndInd);
667 bool isITBlockTerminator(MCInst &Inst) const;
668
669 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands,
670 unsigned MnemonicOpsEndInd);
671 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, bool Load,
672 bool ARMMode, bool Writeback,
673 unsigned MnemonicOpsEndInd);
674
675public:
676 enum ARMMatchResultTy {
677 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
678 Match_RequiresNotITBlock,
679 Match_RequiresV6,
680 Match_RequiresThumb2,
681 Match_RequiresV8,
682 Match_RequiresFlagSetting,
683#define GET_OPERAND_DIAGNOSTIC_TYPES
684#include "ARMGenAsmMatcher.inc"
685
686 };
687
688 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
689 const MCInstrInfo &MII, const MCTargetOptions &Options)
690 : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) {
692
693 // Cache the MCRegisterInfo.
695
696 // Initialize the set of available features.
697 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
698
699 // Add build attributes based on the selected target.
701 getTargetStreamer().emitTargetAttributes(STI);
702
703 // Not in an ITBlock to start with.
704 ITState.CurPosition = ~0U;
705
706 VPTState.CurPosition = ~0U;
707
708 NextSymbolIsThumb = false;
709 }
710
711 // Implementation of the MCTargetAsmParser interface:
712 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
714 SMLoc &EndLoc) override;
716 SMLoc NameLoc, OperandVector &Operands) override;
717 bool ParseDirective(AsmToken DirectiveID) override;
718
720 unsigned Kind) override;
721 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
722 unsigned
724 const OperandVector &Operands) override;
725
726 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
729 bool MatchingInlineAsm) override;
730 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
732 bool MatchingInlineAsm, bool &EmitInITBlock,
733 MCStreamer &Out);
734
735 struct NearMissMessage {
736 SMLoc Loc;
737 SmallString<128> Message;
738 };
739
740 const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
741
742 void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
745 void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
747
749 getVariantKindForName(StringRef Name) const override;
750
751 void doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc) override;
752
753 void onLabelParsed(MCSymbol *Symbol) override;
754
755 const MCInstrDesc &getInstrDesc(unsigned int Opcode) const {
756 return MII.get(Opcode);
757 }
758
759 bool hasMVE() const { return getSTI().hasFeature(ARM::HasMVEIntegerOps); }
760
761 // Return the low-subreg of a given Q register.
762 unsigned getDRegFromQReg(unsigned QReg) const {
763 return MRI->getSubReg(QReg, ARM::dsub_0);
764 }
765
766 const MCRegisterInfo *getMRI() const { return MRI; }
767};
768
769/// ARMOperand - Instances of this class represent a parsed ARM machine
770/// operand.
771class ARMOperand : public MCParsedAsmOperand {
772 enum KindTy {
773 k_CondCode,
774 k_VPTPred,
775 k_CCOut,
776 k_ITCondMask,
777 k_CoprocNum,
778 k_CoprocReg,
779 k_CoprocOption,
780 k_Immediate,
781 k_MemBarrierOpt,
782 k_InstSyncBarrierOpt,
783 k_TraceSyncBarrierOpt,
784 k_Memory,
785 k_PostIndexRegister,
786 k_MSRMask,
787 k_BankedReg,
788 k_ProcIFlags,
789 k_VectorIndex,
790 k_Register,
791 k_RegisterList,
792 k_RegisterListWithAPSR,
793 k_DPRRegisterList,
794 k_SPRRegisterList,
795 k_FPSRegisterListWithVPR,
796 k_FPDRegisterListWithVPR,
797 k_VectorList,
798 k_VectorListAllLanes,
799 k_VectorListIndexed,
800 k_ShiftedRegister,
801 k_ShiftedImmediate,
802 k_ShifterImmediate,
803 k_RotateImmediate,
804 k_ModifiedImmediate,
805 k_ConstantPoolImmediate,
806 k_BitfieldDescriptor,
807 k_Token,
808 } Kind;
809
810 SMLoc StartLoc, EndLoc, AlignmentLoc;
812
813 ARMAsmParser *Parser;
814
815 struct CCOp {
817 };
818
819 struct VCCOp {
821 };
822
823 struct CopOp {
824 unsigned Val;
825 };
826
827 struct CoprocOptionOp {
828 unsigned Val;
829 };
830
831 struct ITMaskOp {
832 unsigned Mask:4;
833 };
834
835 struct MBOptOp {
836 ARM_MB::MemBOpt Val;
837 };
838
839 struct ISBOptOp {
841 };
842
843 struct TSBOptOp {
845 };
846
847 struct IFlagsOp {
849 };
850
851 struct MMaskOp {
852 unsigned Val;
853 };
854
855 struct BankedRegOp {
856 unsigned Val;
857 };
858
859 struct TokOp {
860 const char *Data;
861 unsigned Length;
862 };
863
864 struct RegOp {
865 unsigned RegNum;
866 };
867
868 // A vector register list is a sequential list of 1 to 4 registers.
869 struct VectorListOp {
870 unsigned RegNum;
871 unsigned Count;
872 unsigned LaneIndex;
873 bool isDoubleSpaced;
874 };
875
876 struct VectorIndexOp {
877 unsigned Val;
878 };
879
880 struct ImmOp {
881 const MCExpr *Val;
882 };
883
884 /// Combined record for all forms of ARM address expressions.
885 struct MemoryOp {
886 unsigned BaseRegNum;
887 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
888 // was specified.
889 const MCExpr *OffsetImm; // Offset immediate value
890 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
891 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
892 unsigned ShiftImm; // shift for OffsetReg.
893 unsigned Alignment; // 0 = no alignment specified
894 // n = alignment in bytes (2, 4, 8, 16, or 32)
895 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
896 };
897
898 struct PostIdxRegOp {
899 unsigned RegNum;
900 bool isAdd;
901 ARM_AM::ShiftOpc ShiftTy;
902 unsigned ShiftImm;
903 };
904
905 struct ShifterImmOp {
906 bool isASR;
907 unsigned Imm;
908 };
909
910 struct RegShiftedRegOp {
911 ARM_AM::ShiftOpc ShiftTy;
912 unsigned SrcReg;
913 unsigned ShiftReg;
914 unsigned ShiftImm;
915 };
916
917 struct RegShiftedImmOp {
918 ARM_AM::ShiftOpc ShiftTy;
919 unsigned SrcReg;
920 unsigned ShiftImm;
921 };
922
923 struct RotImmOp {
924 unsigned Imm;
925 };
926
927 struct ModImmOp {
928 unsigned Bits;
929 unsigned Rot;
930 };
931
932 struct BitfieldOp {
933 unsigned LSB;
934 unsigned Width;
935 };
936
937 union {
938 struct CCOp CC;
939 struct VCCOp VCC;
940 struct CopOp Cop;
941 struct CoprocOptionOp CoprocOption;
942 struct MBOptOp MBOpt;
943 struct ISBOptOp ISBOpt;
944 struct TSBOptOp TSBOpt;
945 struct ITMaskOp ITMask;
946 struct IFlagsOp IFlags;
947 struct MMaskOp MMask;
948 struct BankedRegOp BankedReg;
949 struct TokOp Tok;
950 struct RegOp Reg;
951 struct VectorListOp VectorList;
952 struct VectorIndexOp VectorIndex;
953 struct ImmOp Imm;
954 struct MemoryOp Memory;
955 struct PostIdxRegOp PostIdxReg;
956 struct ShifterImmOp ShifterImm;
957 struct RegShiftedRegOp RegShiftedReg;
958 struct RegShiftedImmOp RegShiftedImm;
959 struct RotImmOp RotImm;
960 struct ModImmOp ModImm;
961 struct BitfieldOp Bitfield;
962 };
963
964public:
965 ARMOperand(KindTy K, ARMAsmParser &Parser) : Kind(K), Parser(&Parser) {}
966
967 /// getStartLoc - Get the location of the first token of this operand.
968 SMLoc getStartLoc() const override { return StartLoc; }
969
970 /// getEndLoc - Get the location of the last token of this operand.
971 SMLoc getEndLoc() const override { return EndLoc; }
972
973 /// getLocRange - Get the range between the first and last token of this
974 /// operand.
975 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
976
977 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
978 SMLoc getAlignmentLoc() const {
979 assert(Kind == k_Memory && "Invalid access!");
980 return AlignmentLoc;
981 }
982
984 assert(Kind == k_CondCode && "Invalid access!");
985 return CC.Val;
986 }
987
988 ARMVCC::VPTCodes getVPTPred() const {
989 assert(isVPTPred() && "Invalid access!");
990 return VCC.Val;
991 }
992
993 unsigned getCoproc() const {
994 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
995 return Cop.Val;
996 }
997
998 StringRef getToken() const {
999 assert(Kind == k_Token && "Invalid access!");
1000 return StringRef(Tok.Data, Tok.Length);
1001 }
1002
1003 MCRegister getReg() const override {
1004 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
1005 return Reg.RegNum;
1006 }
1007
1008 const SmallVectorImpl<unsigned> &getRegList() const {
1009 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
1010 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
1011 Kind == k_FPSRegisterListWithVPR ||
1012 Kind == k_FPDRegisterListWithVPR) &&
1013 "Invalid access!");
1014 return Registers;
1015 }
1016
1017 const MCExpr *getImm() const {
1018 assert(isImm() && "Invalid access!");
1019 return Imm.Val;
1020 }
1021
1022 const MCExpr *getConstantPoolImm() const {
1023 assert(isConstantPoolImm() && "Invalid access!");
1024 return Imm.Val;
1025 }
1026
1027 unsigned getVectorIndex() const {
1028 assert(Kind == k_VectorIndex && "Invalid access!");
1029 return VectorIndex.Val;
1030 }
1031
1032 ARM_MB::MemBOpt getMemBarrierOpt() const {
1033 assert(Kind == k_MemBarrierOpt && "Invalid access!");
1034 return MBOpt.Val;
1035 }
1036
1037 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
1038 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
1039 return ISBOpt.Val;
1040 }
1041
1042 ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
1043 assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
1044 return TSBOpt.Val;
1045 }
1046
1047 ARM_PROC::IFlags getProcIFlags() const {
1048 assert(Kind == k_ProcIFlags && "Invalid access!");
1049 return IFlags.Val;
1050 }
1051
1052 unsigned getMSRMask() const {
1053 assert(Kind == k_MSRMask && "Invalid access!");
1054 return MMask.Val;
1055 }
1056
1057 unsigned getBankedReg() const {
1058 assert(Kind == k_BankedReg && "Invalid access!");
1059 return BankedReg.Val;
1060 }
1061
1062 bool isCoprocNum() const { return Kind == k_CoprocNum; }
1063 bool isCoprocReg() const { return Kind == k_CoprocReg; }
1064 bool isCoprocOption() const { return Kind == k_CoprocOption; }
1065 bool isCondCode() const { return Kind == k_CondCode; }
1066 bool isVPTPred() const { return Kind == k_VPTPred; }
1067 bool isCCOut() const { return Kind == k_CCOut; }
1068 bool isITMask() const { return Kind == k_ITCondMask; }
1069 bool isITCondCode() const { return Kind == k_CondCode; }
1070 bool isImm() const override {
1071 return Kind == k_Immediate;
1072 }
1073
1074 bool isARMBranchTarget() const {
1075 if (!isImm()) return false;
1076
1077 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1078 return CE->getValue() % 4 == 0;
1079 return true;
1080 }
1081
1082
1083 bool isThumbBranchTarget() const {
1084 if (!isImm()) return false;
1085
1086 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1087 return CE->getValue() % 2 == 0;
1088 return true;
1089 }
1090
1091 // checks whether this operand is an unsigned offset which fits is a field
1092 // of specified width and scaled by a specific number of bits
1093 template<unsigned width, unsigned scale>
1094 bool isUnsignedOffset() const {
1095 if (!isImm()) return false;
1096 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1097 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1098 int64_t Val = CE->getValue();
1099 int64_t Align = 1LL << scale;
1100 int64_t Max = Align * ((1LL << width) - 1);
1101 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
1102 }
1103 return false;
1104 }
1105
1106 // checks whether this operand is an signed offset which fits is a field
1107 // of specified width and scaled by a specific number of bits
1108 template<unsigned width, unsigned scale>
1109 bool isSignedOffset() const {
1110 if (!isImm()) return false;
1111 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1112 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1113 int64_t Val = CE->getValue();
1114 int64_t Align = 1LL << scale;
1115 int64_t Max = Align * ((1LL << (width-1)) - 1);
1116 int64_t Min = -Align * (1LL << (width-1));
1117 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1118 }
1119 return false;
1120 }
1121
1122 // checks whether this operand is an offset suitable for the LE /
1123 // LETP instructions in Arm v8.1M
1124 bool isLEOffset() const {
1125 if (!isImm()) return false;
1126 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1127 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1128 int64_t Val = CE->getValue();
1129 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1130 }
1131 return false;
1132 }
1133
1134 // checks whether this operand is a memory operand computed as an offset
1135 // applied to PC. the offset may have 8 bits of magnitude and is represented
1136 // with two bits of shift. textually it may be either [pc, #imm], #imm or
1137 // relocable expression...
1138 bool isThumbMemPC() const {
1139 int64_t Val = 0;
1140 if (isImm()) {
1141 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1143 if (!CE) return false;
1144 Val = CE->getValue();
1145 }
1146 else if (isGPRMem()) {
1147 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1148 if(Memory.BaseRegNum != ARM::PC) return false;
1149 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
1150 Val = CE->getValue();
1151 else
1152 return false;
1153 }
1154 else return false;
1155 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1156 }
1157
1158 bool isFPImm() const {
1159 if (!isImm()) return false;
1160 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1161 if (!CE) return false;
1162 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1163 return Val != -1;
1164 }
1165
1166 template<int64_t N, int64_t M>
1167 bool isImmediate() const {
1168 if (!isImm()) return false;
1169 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1170 if (!CE) return false;
1171 int64_t Value = CE->getValue();
1172 return Value >= N && Value <= M;
1173 }
1174
1175 template<int64_t N, int64_t M>
1176 bool isImmediateS4() const {
1177 if (!isImm()) return false;
1178 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1179 if (!CE) return false;
1180 int64_t Value = CE->getValue();
1181 return ((Value & 3) == 0) && Value >= N && Value <= M;
1182 }
1183 template<int64_t N, int64_t M>
1184 bool isImmediateS2() const {
1185 if (!isImm()) return false;
1186 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1187 if (!CE) return false;
1188 int64_t Value = CE->getValue();
1189 return ((Value & 1) == 0) && Value >= N && Value <= M;
1190 }
1191 bool isFBits16() const {
1192 return isImmediate<0, 17>();
1193 }
1194 bool isFBits32() const {
1195 return isImmediate<1, 33>();
1196 }
1197 bool isImm8s4() const {
1198 return isImmediateS4<-1020, 1020>();
1199 }
1200 bool isImm7s4() const {
1201 return isImmediateS4<-508, 508>();
1202 }
1203 bool isImm7Shift0() const {
1204 return isImmediate<-127, 127>();
1205 }
1206 bool isImm7Shift1() const {
1207 return isImmediateS2<-255, 255>();
1208 }
1209 bool isImm7Shift2() const {
1210 return isImmediateS4<-511, 511>();
1211 }
1212 bool isImm7() const {
1213 return isImmediate<-127, 127>();
1214 }
1215 bool isImm0_1020s4() const {
1216 return isImmediateS4<0, 1020>();
1217 }
1218 bool isImm0_508s4() const {
1219 return isImmediateS4<0, 508>();
1220 }
1221 bool isImm0_508s4Neg() const {
1222 if (!isImm()) return false;
1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Value = -CE->getValue();
1226 // explicitly exclude zero. we want that to use the normal 0_508 version.
1227 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1228 }
1229
1230 bool isImm0_4095Neg() const {
1231 if (!isImm()) return false;
1232 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1233 if (!CE) return false;
1234 // isImm0_4095Neg is used with 32-bit immediates only.
1235 // 32-bit immediates are zero extended to 64-bit when parsed,
1236 // thus simple -CE->getValue() results in a big negative number,
1237 // not a small positive number as intended
1238 if ((CE->getValue() >> 32) > 0) return false;
1239 uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1240 return Value > 0 && Value < 4096;
1241 }
1242
1243 bool isImm0_7() const {
1244 return isImmediate<0, 7>();
1245 }
1246
1247 bool isImm1_16() const {
1248 return isImmediate<1, 16>();
1249 }
1250
1251 bool isImm1_32() const {
1252 return isImmediate<1, 32>();
1253 }
1254
1255 bool isImm8_255() const {
1256 return isImmediate<8, 255>();
1257 }
1258
1259 bool isImm0_255Expr() const {
1260 if (!isImm())
1261 return false;
1262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1263 // If it's not a constant expression, it'll generate a fixup and be
1264 // handled later.
1265 if (!CE)
1266 return true;
1267 int64_t Value = CE->getValue();
1268 return isUInt<8>(Value);
1269 }
1270
1271 bool isImm256_65535Expr() const {
1272 if (!isImm()) return false;
1273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1274 // If it's not a constant expression, it'll generate a fixup and be
1275 // handled later.
1276 if (!CE) return true;
1277 int64_t Value = CE->getValue();
1278 return Value >= 256 && Value < 65536;
1279 }
1280
1281 bool isImm0_65535Expr() const {
1282 if (!isImm()) return false;
1283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1284 // If it's not a constant expression, it'll generate a fixup and be
1285 // handled later.
1286 if (!CE) return true;
1287 int64_t Value = CE->getValue();
1288 return Value >= 0 && Value < 65536;
1289 }
1290
1291 bool isImm24bit() const {
1292 return isImmediate<0, 0xffffff + 1>();
1293 }
1294
1295 bool isImmThumbSR() const {
1296 return isImmediate<1, 33>();
1297 }
1298
1299 bool isPKHLSLImm() const {
1300 return isImmediate<0, 32>();
1301 }
1302
1303 bool isPKHASRImm() const {
1304 return isImmediate<0, 33>();
1305 }
1306
1307 bool isAdrLabel() const {
1308 // If we have an immediate that's not a constant, treat it as a label
1309 // reference needing a fixup.
1310 if (isImm() && !isa<MCConstantExpr>(getImm()))
1311 return true;
1312
1313 // If it is a constant, it must fit into a modified immediate encoding.
1314 if (!isImm()) return false;
1315 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1316 if (!CE) return false;
1317 int64_t Value = CE->getValue();
1318 return (ARM_AM::getSOImmVal(Value) != -1 ||
1319 ARM_AM::getSOImmVal(-Value) != -1);
1320 }
1321
1322 bool isT2SOImm() const {
1323 // If we have an immediate that's not a constant, treat it as an expression
1324 // needing a fixup.
1325 if (isImm() && !isa<MCConstantExpr>(getImm())) {
1326 // We want to avoid matching :upper16: and :lower16: as we want these
1327 // expressions to match in isImm0_65535Expr()
1328 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1329 return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1330 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1331 }
1332 if (!isImm()) return false;
1333 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1334 if (!CE) return false;
1335 int64_t Value = CE->getValue();
1336 return ARM_AM::getT2SOImmVal(Value) != -1;
1337 }
1338
1339 bool isT2SOImmNot() const {
1340 if (!isImm()) return false;
1341 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1342 if (!CE) return false;
1343 int64_t Value = CE->getValue();
1344 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1346 }
1347
1348 bool isT2SOImmNeg() const {
1349 if (!isImm()) return false;
1350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351 if (!CE) return false;
1352 int64_t Value = CE->getValue();
1353 // Only use this when not representable as a plain so_imm.
1354 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1356 }
1357
1358 bool isSetEndImm() const {
1359 if (!isImm()) return false;
1360 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1361 if (!CE) return false;
1362 int64_t Value = CE->getValue();
1363 return Value == 1 || Value == 0;
1364 }
1365
1366 bool isReg() const override { return Kind == k_Register; }
1367 bool isRegList() const { return Kind == k_RegisterList; }
1368 bool isRegListWithAPSR() const {
1369 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1370 }
1371 bool isDReg() const {
1372 return isReg() &&
1373 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg.RegNum);
1374 }
1375 bool isQReg() const {
1376 return isReg() &&
1377 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg.RegNum);
1378 }
1379 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1380 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1381 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1382 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1383 bool isToken() const override { return Kind == k_Token; }
1384 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1385 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1386 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1387 bool isMem() const override {
1388 return isGPRMem() || isMVEMem();
1389 }
1390 bool isMVEMem() const {
1391 if (Kind != k_Memory)
1392 return false;
1393 if (Memory.BaseRegNum &&
1394 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1395 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1396 return false;
1397 if (Memory.OffsetRegNum &&
1398 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1399 Memory.OffsetRegNum))
1400 return false;
1401 return true;
1402 }
1403 bool isGPRMem() const {
1404 if (Kind != k_Memory)
1405 return false;
1406 if (Memory.BaseRegNum &&
1407 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1408 return false;
1409 if (Memory.OffsetRegNum &&
1410 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1411 return false;
1412 return true;
1413 }
1414 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1415 bool isRegShiftedReg() const {
1416 return Kind == k_ShiftedRegister &&
1417 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1418 RegShiftedReg.SrcReg) &&
1419 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1420 RegShiftedReg.ShiftReg);
1421 }
1422 bool isRegShiftedImm() const {
1423 return Kind == k_ShiftedImmediate &&
1424 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1425 RegShiftedImm.SrcReg);
1426 }
1427 bool isRotImm() const { return Kind == k_RotateImmediate; }
1428
1429 template<unsigned Min, unsigned Max>
1430 bool isPowerTwoInRange() const {
1431 if (!isImm()) return false;
1432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1433 if (!CE) return false;
1434 int64_t Value = CE->getValue();
1435 return Value > 0 && llvm::popcount((uint64_t)Value) == 1 && Value >= Min &&
1436 Value <= Max;
1437 }
1438 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1439
1440 bool isModImmNot() const {
1441 if (!isImm()) return false;
1442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1443 if (!CE) return false;
1444 int64_t Value = CE->getValue();
1445 return ARM_AM::getSOImmVal(~Value) != -1;
1446 }
1447
1448 bool isModImmNeg() const {
1449 if (!isImm()) return false;
1450 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1451 if (!CE) return false;
1452 int64_t Value = CE->getValue();
1453 return ARM_AM::getSOImmVal(Value) == -1 &&
1454 ARM_AM::getSOImmVal(-Value) != -1;
1455 }
1456
1457 bool isThumbModImmNeg1_7() const {
1458 if (!isImm()) return false;
1459 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1460 if (!CE) return false;
1461 int32_t Value = -(int32_t)CE->getValue();
1462 return 0 < Value && Value < 8;
1463 }
1464
1465 bool isThumbModImmNeg8_255() const {
1466 if (!isImm()) return false;
1467 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1468 if (!CE) return false;
1469 int32_t Value = -(int32_t)CE->getValue();
1470 return 7 < Value && Value < 256;
1471 }
1472
1473 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1474 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1475 bool isPostIdxRegShifted() const {
1476 return Kind == k_PostIndexRegister &&
1477 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1478 }
1479 bool isPostIdxReg() const {
1480 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1481 }
1482 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1483 if (!isGPRMem())
1484 return false;
1485 // No offset of any kind.
1486 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1487 (alignOK || Memory.Alignment == Alignment);
1488 }
1489 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1490 if (!isGPRMem())
1491 return false;
1492
1493 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1494 Memory.BaseRegNum))
1495 return false;
1496
1497 // No offset of any kind.
1498 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1499 (alignOK || Memory.Alignment == Alignment);
1500 }
1501 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1502 if (!isGPRMem())
1503 return false;
1504
1505 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1506 Memory.BaseRegNum))
1507 return false;
1508
1509 // No offset of any kind.
1510 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1511 (alignOK || Memory.Alignment == Alignment);
1512 }
1513 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1514 if (!isGPRMem())
1515 return false;
1516
1517 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1518 Memory.BaseRegNum))
1519 return false;
1520
1521 // No offset of any kind.
1522 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1523 (alignOK || Memory.Alignment == Alignment);
1524 }
1525 bool isMemPCRelImm12() const {
1526 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1527 return false;
1528 // Base register must be PC.
1529 if (Memory.BaseRegNum != ARM::PC)
1530 return false;
1531 // Immediate offset in range [-4095, 4095].
1532 if (!Memory.OffsetImm) return true;
1533 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1534 int64_t Val = CE->getValue();
1535 return (Val > -4096 && Val < 4096) ||
1536 (Val == std::numeric_limits<int32_t>::min());
1537 }
1538 return false;
1539 }
1540
1541 bool isAlignedMemory() const {
1542 return isMemNoOffset(true);
1543 }
1544
1545 bool isAlignedMemoryNone() const {
1546 return isMemNoOffset(false, 0);
1547 }
1548
1549 bool isDupAlignedMemoryNone() const {
1550 return isMemNoOffset(false, 0);
1551 }
1552
1553 bool isAlignedMemory16() const {
1554 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1555 return true;
1556 return isMemNoOffset(false, 0);
1557 }
1558
1559 bool isDupAlignedMemory16() const {
1560 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1561 return true;
1562 return isMemNoOffset(false, 0);
1563 }
1564
1565 bool isAlignedMemory32() const {
1566 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1567 return true;
1568 return isMemNoOffset(false, 0);
1569 }
1570
1571 bool isDupAlignedMemory32() const {
1572 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1573 return true;
1574 return isMemNoOffset(false, 0);
1575 }
1576
1577 bool isAlignedMemory64() const {
1578 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1579 return true;
1580 return isMemNoOffset(false, 0);
1581 }
1582
1583 bool isDupAlignedMemory64() const {
1584 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1585 return true;
1586 return isMemNoOffset(false, 0);
1587 }
1588
1589 bool isAlignedMemory64or128() const {
1590 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1591 return true;
1592 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1593 return true;
1594 return isMemNoOffset(false, 0);
1595 }
1596
1597 bool isDupAlignedMemory64or128() const {
1598 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1599 return true;
1600 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1601 return true;
1602 return isMemNoOffset(false, 0);
1603 }
1604
1605 bool isAlignedMemory64or128or256() const {
1606 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1607 return true;
1608 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1609 return true;
1610 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1611 return true;
1612 return isMemNoOffset(false, 0);
1613 }
1614
1615 bool isAddrMode2() const {
1616 if (!isGPRMem() || Memory.Alignment != 0) return false;
1617 // Check for register offset.
1618 if (Memory.OffsetRegNum) return true;
1619 // Immediate offset in range [-4095, 4095].
1620 if (!Memory.OffsetImm) return true;
1621 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1622 int64_t Val = CE->getValue();
1623 return Val > -4096 && Val < 4096;
1624 }
1625 return false;
1626 }
1627
1628 bool isAM2OffsetImm() const {
1629 if (!isImm()) return false;
1630 // Immediate offset in range [-4095, 4095].
1631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1632 if (!CE) return false;
1633 int64_t Val = CE->getValue();
1634 return (Val == std::numeric_limits<int32_t>::min()) ||
1635 (Val > -4096 && Val < 4096);
1636 }
1637
1638 bool isAddrMode3() const {
1639 // If we have an immediate that's not a constant, treat it as a label
1640 // reference needing a fixup. If it is a constant, it's something else
1641 // and we reject it.
1642 if (isImm() && !isa<MCConstantExpr>(getImm()))
1643 return true;
1644 if (!isGPRMem() || Memory.Alignment != 0) return false;
1645 // No shifts are legal for AM3.
1646 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1647 // Check for register offset.
1648 if (Memory.OffsetRegNum) return true;
1649 // Immediate offset in range [-255, 255].
1650 if (!Memory.OffsetImm) return true;
1651 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1652 int64_t Val = CE->getValue();
1653 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and
1654 // we have to check for this too.
1655 return (Val > -256 && Val < 256) ||
1656 Val == std::numeric_limits<int32_t>::min();
1657 }
1658 return false;
1659 }
1660
1661 bool isAM3Offset() const {
1662 if (isPostIdxReg())
1663 return true;
1664 if (!isImm())
1665 return false;
1666 // Immediate offset in range [-255, 255].
1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668 if (!CE) return false;
1669 int64_t Val = CE->getValue();
1670 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1671 return (Val > -256 && Val < 256) ||
1672 Val == std::numeric_limits<int32_t>::min();
1673 }
1674
1675 bool isAddrMode5() const {
1676 // If we have an immediate that's not a constant, treat it as a label
1677 // reference needing a fixup. If it is a constant, it's something else
1678 // and we reject it.
1679 if (isImm() && !isa<MCConstantExpr>(getImm()))
1680 return true;
1681 if (!isGPRMem() || Memory.Alignment != 0) return false;
1682 // Check for register offset.
1683 if (Memory.OffsetRegNum) return false;
1684 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1685 if (!Memory.OffsetImm) return true;
1686 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1687 int64_t Val = CE->getValue();
1688 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1689 Val == std::numeric_limits<int32_t>::min();
1690 }
1691 return false;
1692 }
1693
1694 bool isAddrMode5FP16() const {
1695 // If we have an immediate that's not a constant, treat it as a label
1696 // reference needing a fixup. If it is a constant, it's something else
1697 // and we reject it.
1698 if (isImm() && !isa<MCConstantExpr>(getImm()))
1699 return true;
1700 if (!isGPRMem() || Memory.Alignment != 0) return false;
1701 // Check for register offset.
1702 if (Memory.OffsetRegNum) return false;
1703 // Immediate offset in range [-510, 510] and a multiple of 2.
1704 if (!Memory.OffsetImm) return true;
1705 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1706 int64_t Val = CE->getValue();
1707 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1708 Val == std::numeric_limits<int32_t>::min();
1709 }
1710 return false;
1711 }
1712
1713 bool isMemTBB() const {
1714 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1715 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1716 return false;
1717 return true;
1718 }
1719
1720 bool isMemTBH() const {
1721 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1722 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1723 Memory.Alignment != 0 )
1724 return false;
1725 return true;
1726 }
1727
1728 bool isMemRegOffset() const {
1729 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1730 return false;
1731 return true;
1732 }
1733
1734 bool isT2MemRegOffset() const {
1735 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1736 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1737 return false;
1738 // Only lsl #{0, 1, 2, 3} allowed.
1739 if (Memory.ShiftType == ARM_AM::no_shift)
1740 return true;
1741 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1742 return false;
1743 return true;
1744 }
1745
1746 bool isMemThumbRR() const {
1747 // Thumb reg+reg addressing is simple. Just two registers, a base and
1748 // an offset. No shifts, negations or any other complicating factors.
1749 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1750 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1751 return false;
1752 return isARMLowRegister(Memory.BaseRegNum) &&
1753 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1754 }
1755
1756 bool isMemThumbRIs4() const {
1757 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1758 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1759 return false;
1760 // Immediate offset, multiple of 4 in range [0, 124].
1761 if (!Memory.OffsetImm) return true;
1762 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1763 int64_t Val = CE->getValue();
1764 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1765 }
1766 return false;
1767 }
1768
1769 bool isMemThumbRIs2() const {
1770 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1771 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1772 return false;
1773 // Immediate offset, multiple of 4 in range [0, 62].
1774 if (!Memory.OffsetImm) return true;
1775 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1776 int64_t Val = CE->getValue();
1777 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1778 }
1779 return false;
1780 }
1781
1782 bool isMemThumbRIs1() const {
1783 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1784 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1785 return false;
1786 // Immediate offset in range [0, 31].
1787 if (!Memory.OffsetImm) return true;
1788 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1789 int64_t Val = CE->getValue();
1790 return Val >= 0 && Val <= 31;
1791 }
1792 return false;
1793 }
1794
1795 bool isMemThumbSPI() const {
1796 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1797 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1798 return false;
1799 // Immediate offset, multiple of 4 in range [0, 1020].
1800 if (!Memory.OffsetImm) return true;
1801 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1802 int64_t Val = CE->getValue();
1803 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1804 }
1805 return false;
1806 }
1807
1808 bool isMemImm8s4Offset() const {
1809 // If we have an immediate that's not a constant, treat it as a label
1810 // reference needing a fixup. If it is a constant, it's something else
1811 // and we reject it.
1812 if (isImm() && !isa<MCConstantExpr>(getImm()))
1813 return true;
1814 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1815 return false;
1816 // Immediate offset a multiple of 4 in range [-1020, 1020].
1817 if (!Memory.OffsetImm) return true;
1818 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1819 int64_t Val = CE->getValue();
1820 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1821 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1822 Val == std::numeric_limits<int32_t>::min();
1823 }
1824 return false;
1825 }
1826
1827 bool isMemImm7s4Offset() const {
1828 // If we have an immediate that's not a constant, treat it as a label
1829 // reference needing a fixup. If it is a constant, it's something else
1830 // and we reject it.
1831 if (isImm() && !isa<MCConstantExpr>(getImm()))
1832 return true;
1833 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1834 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1835 Memory.BaseRegNum))
1836 return false;
1837 // Immediate offset a multiple of 4 in range [-508, 508].
1838 if (!Memory.OffsetImm) return true;
1839 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1840 int64_t Val = CE->getValue();
1841 // Special case, #-0 is INT32_MIN.
1842 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1843 }
1844 return false;
1845 }
1846
1847 bool isMemImm0_1020s4Offset() const {
1848 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1849 return false;
1850 // Immediate offset a multiple of 4 in range [0, 1020].
1851 if (!Memory.OffsetImm) return true;
1852 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1853 int64_t Val = CE->getValue();
1854 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1855 }
1856 return false;
1857 }
1858
1859 bool isMemImm8Offset() const {
1860 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1861 return false;
1862 // Base reg of PC isn't allowed for these encodings.
1863 if (Memory.BaseRegNum == ARM::PC) return false;
1864 // Immediate offset in range [-255, 255].
1865 if (!Memory.OffsetImm) return true;
1866 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1867 int64_t Val = CE->getValue();
1868 return (Val == std::numeric_limits<int32_t>::min()) ||
1869 (Val > -256 && Val < 256);
1870 }
1871 return false;
1872 }
1873
1874 template<unsigned Bits, unsigned RegClassID>
1875 bool isMemImm7ShiftedOffset() const {
1876 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1877 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1878 return false;
1879
1880 // Expect an immediate offset equal to an element of the range
1881 // [-127, 127], shifted left by Bits.
1882
1883 if (!Memory.OffsetImm) return true;
1884 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1885 int64_t Val = CE->getValue();
1886
1887 // INT32_MIN is a special-case value (indicating the encoding with
1888 // zero offset and the subtract bit set)
1889 if (Val == INT32_MIN)
1890 return true;
1891
1892 unsigned Divisor = 1U << Bits;
1893
1894 // Check that the low bits are zero
1895 if (Val % Divisor != 0)
1896 return false;
1897
1898 // Check that the remaining offset is within range.
1899 Val /= Divisor;
1900 return (Val >= -127 && Val <= 127);
1901 }
1902 return false;
1903 }
1904
1905 template <int shift> bool isMemRegRQOffset() const {
1906 if (!isMVEMem() || Memory.OffsetImm != nullptr || Memory.Alignment != 0)
1907 return false;
1908
1909 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1910 Memory.BaseRegNum))
1911 return false;
1912 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1913 Memory.OffsetRegNum))
1914 return false;
1915
1916 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1917 return false;
1918
1919 if (shift > 0 &&
1920 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1921 return false;
1922
1923 return true;
1924 }
1925
1926 template <int shift> bool isMemRegQOffset() const {
1927 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1928 return false;
1929
1930 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1931 Memory.BaseRegNum))
1932 return false;
1933
1934 if (!Memory.OffsetImm)
1935 return true;
1936 static_assert(shift < 56,
1937 "Such that we dont shift by a value higher than 62");
1938 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1939 int64_t Val = CE->getValue();
1940
1941 // The value must be a multiple of (1 << shift)
1942 if ((Val & ((1U << shift) - 1)) != 0)
1943 return false;
1944
1945 // And be in the right range, depending on the amount that it is shifted
1946 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1947 // separately.
1948 int64_t Range = (1U << (7 + shift)) - 1;
1949 return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1950 }
1951 return false;
1952 }
1953
1954 bool isMemPosImm8Offset() const {
1955 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1956 return false;
1957 // Immediate offset in range [0, 255].
1958 if (!Memory.OffsetImm) return true;
1959 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1960 int64_t Val = CE->getValue();
1961 return Val >= 0 && Val < 256;
1962 }
1963 return false;
1964 }
1965
1966 bool isMemNegImm8Offset() const {
1967 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1968 return false;
1969 // Base reg of PC isn't allowed for these encodings.
1970 if (Memory.BaseRegNum == ARM::PC) return false;
1971 // Immediate offset in range [-255, -1].
1972 if (!Memory.OffsetImm) return false;
1973 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1974 int64_t Val = CE->getValue();
1975 return (Val == std::numeric_limits<int32_t>::min()) ||
1976 (Val > -256 && Val < 0);
1977 }
1978 return false;
1979 }
1980
1981 bool isMemUImm12Offset() const {
1982 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1983 return false;
1984 // Immediate offset in range [0, 4095].
1985 if (!Memory.OffsetImm) return true;
1986 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
1987 int64_t Val = CE->getValue();
1988 return (Val >= 0 && Val < 4096);
1989 }
1990 return false;
1991 }
1992
1993 bool isMemImm12Offset() const {
1994 // If we have an immediate that's not a constant, treat it as a label
1995 // reference needing a fixup. If it is a constant, it's something else
1996 // and we reject it.
1997
1998 if (isImm() && !isa<MCConstantExpr>(getImm()))
1999 return true;
2000
2001 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
2002 return false;
2003 // Immediate offset in range [-4095, 4095].
2004 if (!Memory.OffsetImm) return true;
2005 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
2006 int64_t Val = CE->getValue();
2007 return (Val > -4096 && Val < 4096) ||
2008 (Val == std::numeric_limits<int32_t>::min());
2009 }
2010 // If we have an immediate that's not a constant, treat it as a
2011 // symbolic expression needing a fixup.
2012 return true;
2013 }
2014
2015 bool isConstPoolAsmImm() const {
2016 // Delay processing of Constant Pool Immediate, this will turn into
2017 // a constant. Match no other operand
2018 return (isConstantPoolImm());
2019 }
2020
2021 bool isPostIdxImm8() const {
2022 if (!isImm()) return false;
2023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2024 if (!CE) return false;
2025 int64_t Val = CE->getValue();
2026 return (Val > -256 && Val < 256) ||
2027 (Val == std::numeric_limits<int32_t>::min());
2028 }
2029
2030 bool isPostIdxImm8s4() const {
2031 if (!isImm()) return false;
2032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2033 if (!CE) return false;
2034 int64_t Val = CE->getValue();
2035 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
2036 (Val == std::numeric_limits<int32_t>::min());
2037 }
2038
2039 bool isMSRMask() const { return Kind == k_MSRMask; }
2040 bool isBankedReg() const { return Kind == k_BankedReg; }
2041 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
2042
2043 // NEON operands.
2044 bool isAnyVectorList() const {
2045 return Kind == k_VectorList || Kind == k_VectorListAllLanes ||
2046 Kind == k_VectorListIndexed;
2047 }
2048
2049 bool isVectorList() const { return Kind == k_VectorList; }
2050
2051 bool isSingleSpacedVectorList() const {
2052 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
2053 }
2054
2055 bool isDoubleSpacedVectorList() const {
2056 return Kind == k_VectorList && VectorList.isDoubleSpaced;
2057 }
2058
2059 bool isVecListOneD() const {
2060 // We convert a single D reg to a list containing a D reg
2061 if (isDReg() && !Parser->hasMVE())
2062 return true;
2063 if (!isSingleSpacedVectorList()) return false;
2064 return VectorList.Count == 1;
2065 }
2066
2067 bool isVecListTwoMQ() const {
2068 return isSingleSpacedVectorList() && VectorList.Count == 2 &&
2069 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2070 VectorList.RegNum);
2071 }
2072
2073 bool isVecListDPair() const {
2074 // We convert a single Q reg to a list with the two corresponding D
2075 // registers
2076 if (isQReg() && !Parser->hasMVE())
2077 return true;
2078 if (!isSingleSpacedVectorList()) return false;
2079 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2080 .contains(VectorList.RegNum));
2081 }
2082
2083 bool isVecListThreeD() const {
2084 if (!isSingleSpacedVectorList()) return false;
2085 return VectorList.Count == 3;
2086 }
2087
2088 bool isVecListFourD() const {
2089 if (!isSingleSpacedVectorList()) return false;
2090 return VectorList.Count == 4;
2091 }
2092
2093 bool isVecListDPairSpaced() const {
2094 if (Kind != k_VectorList) return false;
2095 if (isSingleSpacedVectorList()) return false;
2096 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
2097 .contains(VectorList.RegNum));
2098 }
2099
2100 bool isVecListThreeQ() const {
2101 if (!isDoubleSpacedVectorList()) return false;
2102 return VectorList.Count == 3;
2103 }
2104
2105 bool isVecListFourQ() const {
2106 if (!isDoubleSpacedVectorList()) return false;
2107 return VectorList.Count == 4;
2108 }
2109
2110 bool isVecListFourMQ() const {
2111 return isSingleSpacedVectorList() && VectorList.Count == 4 &&
2112 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2113 VectorList.RegNum);
2114 }
2115
2116 bool isSingleSpacedVectorAllLanes() const {
2117 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
2118 }
2119
2120 bool isDoubleSpacedVectorAllLanes() const {
2121 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
2122 }
2123
2124 bool isVecListOneDAllLanes() const {
2125 if (!isSingleSpacedVectorAllLanes()) return false;
2126 return VectorList.Count == 1;
2127 }
2128
2129 bool isVecListDPairAllLanes() const {
2130 if (!isSingleSpacedVectorAllLanes()) return false;
2131 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2132 .contains(VectorList.RegNum));
2133 }
2134
2135 bool isVecListDPairSpacedAllLanes() const {
2136 if (!isDoubleSpacedVectorAllLanes()) return false;
2137 return VectorList.Count == 2;
2138 }
2139
2140 bool isVecListThreeDAllLanes() const {
2141 if (!isSingleSpacedVectorAllLanes()) return false;
2142 return VectorList.Count == 3;
2143 }
2144
2145 bool isVecListThreeQAllLanes() const {
2146 if (!isDoubleSpacedVectorAllLanes()) return false;
2147 return VectorList.Count == 3;
2148 }
2149
2150 bool isVecListFourDAllLanes() const {
2151 if (!isSingleSpacedVectorAllLanes()) return false;
2152 return VectorList.Count == 4;
2153 }
2154
2155 bool isVecListFourQAllLanes() const {
2156 if (!isDoubleSpacedVectorAllLanes()) return false;
2157 return VectorList.Count == 4;
2158 }
2159
2160 bool isSingleSpacedVectorIndexed() const {
2161 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
2162 }
2163
2164 bool isDoubleSpacedVectorIndexed() const {
2165 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
2166 }
2167
2168 bool isVecListOneDByteIndexed() const {
2169 if (!isSingleSpacedVectorIndexed()) return false;
2170 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
2171 }
2172
2173 bool isVecListOneDHWordIndexed() const {
2174 if (!isSingleSpacedVectorIndexed()) return false;
2175 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2176 }
2177
2178 bool isVecListOneDWordIndexed() const {
2179 if (!isSingleSpacedVectorIndexed()) return false;
2180 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2181 }
2182
2183 bool isVecListTwoDByteIndexed() const {
2184 if (!isSingleSpacedVectorIndexed()) return false;
2185 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2186 }
2187
2188 bool isVecListTwoDHWordIndexed() const {
2189 if (!isSingleSpacedVectorIndexed()) return false;
2190 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2191 }
2192
2193 bool isVecListTwoQWordIndexed() const {
2194 if (!isDoubleSpacedVectorIndexed()) return false;
2195 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2196 }
2197
2198 bool isVecListTwoQHWordIndexed() const {
2199 if (!isDoubleSpacedVectorIndexed()) return false;
2200 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2201 }
2202
2203 bool isVecListTwoDWordIndexed() const {
2204 if (!isSingleSpacedVectorIndexed()) return false;
2205 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2206 }
2207
2208 bool isVecListThreeDByteIndexed() const {
2209 if (!isSingleSpacedVectorIndexed()) return false;
2210 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2211 }
2212
2213 bool isVecListThreeDHWordIndexed() const {
2214 if (!isSingleSpacedVectorIndexed()) return false;
2215 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2216 }
2217
2218 bool isVecListThreeQWordIndexed() const {
2219 if (!isDoubleSpacedVectorIndexed()) return false;
2220 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2221 }
2222
2223 bool isVecListThreeQHWordIndexed() const {
2224 if (!isDoubleSpacedVectorIndexed()) return false;
2225 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2226 }
2227
2228 bool isVecListThreeDWordIndexed() const {
2229 if (!isSingleSpacedVectorIndexed()) return false;
2230 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2231 }
2232
2233 bool isVecListFourDByteIndexed() const {
2234 if (!isSingleSpacedVectorIndexed()) return false;
2235 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2236 }
2237
2238 bool isVecListFourDHWordIndexed() const {
2239 if (!isSingleSpacedVectorIndexed()) return false;
2240 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2241 }
2242
2243 bool isVecListFourQWordIndexed() const {
2244 if (!isDoubleSpacedVectorIndexed()) return false;
2245 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2246 }
2247
2248 bool isVecListFourQHWordIndexed() const {
2249 if (!isDoubleSpacedVectorIndexed()) return false;
2250 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2251 }
2252
2253 bool isVecListFourDWordIndexed() const {
2254 if (!isSingleSpacedVectorIndexed()) return false;
2255 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2256 }
2257
2258 bool isVectorIndex() const { return Kind == k_VectorIndex; }
2259
2260 template <unsigned NumLanes>
2261 bool isVectorIndexInRange() const {
2262 if (Kind != k_VectorIndex) return false;
2263 return VectorIndex.Val < NumLanes;
2264 }
2265
2266 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
2267 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2268 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2269 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2270
2271 template<int PermittedValue, int OtherPermittedValue>
2272 bool isMVEPairVectorIndex() const {
2273 if (Kind != k_VectorIndex) return false;
2274 return VectorIndex.Val == PermittedValue ||
2275 VectorIndex.Val == OtherPermittedValue;
2276 }
2277
2278 bool isNEONi8splat() const {
2279 if (!isImm()) return false;
2280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2281 // Must be a constant.
2282 if (!CE) return false;
2283 int64_t Value = CE->getValue();
2284 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2285 // value.
2286 return Value >= 0 && Value < 256;
2287 }
2288
2289 bool isNEONi16splat() const {
2290 if (isNEONByteReplicate(2))
2291 return false; // Leave that for bytes replication and forbid by default.
2292 if (!isImm())
2293 return false;
2294 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2295 // Must be a constant.
2296 if (!CE) return false;
2297 unsigned Value = CE->getValue();
2299 }
2300
2301 bool isNEONi16splatNot() const {
2302 if (!isImm())
2303 return false;
2304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2305 // Must be a constant.
2306 if (!CE) return false;
2307 unsigned Value = CE->getValue();
2308 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2309 }
2310
2311 bool isNEONi32splat() const {
2312 if (isNEONByteReplicate(4))
2313 return false; // Leave that for bytes replication and forbid by default.
2314 if (!isImm())
2315 return false;
2316 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2317 // Must be a constant.
2318 if (!CE) return false;
2319 unsigned Value = CE->getValue();
2321 }
2322
2323 bool isNEONi32splatNot() const {
2324 if (!isImm())
2325 return false;
2326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2327 // Must be a constant.
2328 if (!CE) return false;
2329 unsigned Value = CE->getValue();
2331 }
2332
2333 static bool isValidNEONi32vmovImm(int64_t Value) {
2334 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2335 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2336 return ((Value & 0xffffffffffffff00) == 0) ||
2337 ((Value & 0xffffffffffff00ff) == 0) ||
2338 ((Value & 0xffffffffff00ffff) == 0) ||
2339 ((Value & 0xffffffff00ffffff) == 0) ||
2340 ((Value & 0xffffffffffff00ff) == 0xff) ||
2341 ((Value & 0xffffffffff00ffff) == 0xffff);
2342 }
2343
2344 bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2345 assert((Width == 8 || Width == 16 || Width == 32) &&
2346 "Invalid element width");
2347 assert(NumElems * Width <= 64 && "Invalid result width");
2348
2349 if (!isImm())
2350 return false;
2351 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2352 // Must be a constant.
2353 if (!CE)
2354 return false;
2355 int64_t Value = CE->getValue();
2356 if (!Value)
2357 return false; // Don't bother with zero.
2358 if (Inv)
2359 Value = ~Value;
2360
2361 uint64_t Mask = (1ull << Width) - 1;
2362 uint64_t Elem = Value & Mask;
2363 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2364 return false;
2365 if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2366 return false;
2367
2368 for (unsigned i = 1; i < NumElems; ++i) {
2369 Value >>= Width;
2370 if ((Value & Mask) != Elem)
2371 return false;
2372 }
2373 return true;
2374 }
2375
2376 bool isNEONByteReplicate(unsigned NumBytes) const {
2377 return isNEONReplicate(8, NumBytes, false);
2378 }
2379
2380 static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2381 assert((FromW == 8 || FromW == 16 || FromW == 32) &&
2382 "Invalid source width");
2383 assert((ToW == 16 || ToW == 32 || ToW == 64) &&
2384 "Invalid destination width");
2385 assert(FromW < ToW && "ToW is not less than FromW");
2386 }
2387
2388 template<unsigned FromW, unsigned ToW>
2389 bool isNEONmovReplicate() const {
2390 checkNeonReplicateArgs(FromW, ToW);
2391 if (ToW == 64 && isNEONi64splat())
2392 return false;
2393 return isNEONReplicate(FromW, ToW / FromW, false);
2394 }
2395
2396 template<unsigned FromW, unsigned ToW>
2397 bool isNEONinvReplicate() const {
2398 checkNeonReplicateArgs(FromW, ToW);
2399 return isNEONReplicate(FromW, ToW / FromW, true);
2400 }
2401
2402 bool isNEONi32vmov() const {
2403 if (isNEONByteReplicate(4))
2404 return false; // Let it to be classified as byte-replicate case.
2405 if (!isImm())
2406 return false;
2407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2408 // Must be a constant.
2409 if (!CE)
2410 return false;
2411 return isValidNEONi32vmovImm(CE->getValue());
2412 }
2413
2414 bool isNEONi32vmovNeg() const {
2415 if (!isImm()) return false;
2416 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2417 // Must be a constant.
2418 if (!CE) return false;
2419 return isValidNEONi32vmovImm(~CE->getValue());
2420 }
2421
2422 bool isNEONi64splat() const {
2423 if (!isImm()) return false;
2424 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2425 // Must be a constant.
2426 if (!CE) return false;
2427 uint64_t Value = CE->getValue();
2428 // i64 value with each byte being either 0 or 0xff.
2429 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2430 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2431 return true;
2432 }
2433
2434 template<int64_t Angle, int64_t Remainder>
2435 bool isComplexRotation() const {
2436 if (!isImm()) return false;
2437
2438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2439 if (!CE) return false;
2440 uint64_t Value = CE->getValue();
2441
2442 return (Value % Angle == Remainder && Value <= 270);
2443 }
2444
2445 bool isMVELongShift() const {
2446 if (!isImm()) return false;
2447 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2448 // Must be a constant.
2449 if (!CE) return false;
2450 uint64_t Value = CE->getValue();
2451 return Value >= 1 && Value <= 32;
2452 }
2453
2454 bool isMveSaturateOp() const {
2455 if (!isImm()) return false;
2456 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2457 if (!CE) return false;
2458 uint64_t Value = CE->getValue();
2459 return Value == 48 || Value == 64;
2460 }
2461
2462 bool isITCondCodeNoAL() const {
2463 if (!isITCondCode()) return false;
2465 return CC != ARMCC::AL;
2466 }
2467
2468 bool isITCondCodeRestrictedI() const {
2469 if (!isITCondCode())
2470 return false;
2472 return CC == ARMCC::EQ || CC == ARMCC::NE;
2473 }
2474
2475 bool isITCondCodeRestrictedS() const {
2476 if (!isITCondCode())
2477 return false;
2479 return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2480 CC == ARMCC::GE;
2481 }
2482
2483 bool isITCondCodeRestrictedU() const {
2484 if (!isITCondCode())
2485 return false;
2487 return CC == ARMCC::HS || CC == ARMCC::HI;
2488 }
2489
2490 bool isITCondCodeRestrictedFP() const {
2491 if (!isITCondCode())
2492 return false;
2494 return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2495 CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2496 }
2497
2498 void setVecListDPair(unsigned int DPair) {
2499 Kind = k_VectorList;
2500 VectorList.RegNum = DPair;
2501 VectorList.Count = 2;
2502 VectorList.isDoubleSpaced = false;
2503 }
2504
2505 void setVecListOneD(unsigned int DReg) {
2506 Kind = k_VectorList;
2507 VectorList.RegNum = DReg;
2508 VectorList.Count = 1;
2509 VectorList.isDoubleSpaced = false;
2510 }
2511
2512 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2513 // Add as immediates when possible. Null MCExpr = 0.
2514 if (!Expr)
2516 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2517 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2518 else
2520 }
2521
2522 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2523 assert(N == 1 && "Invalid number of operands!");
2524 addExpr(Inst, getImm());
2525 }
2526
2527 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2528 assert(N == 1 && "Invalid number of operands!");
2529 addExpr(Inst, getImm());
2530 }
2531
2532 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2533 assert(N == 2 && "Invalid number of operands!");
2534 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2535 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2536 Inst.addOperand(MCOperand::createReg(RegNum));
2537 }
2538
2539 void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2540 assert(N == 3 && "Invalid number of operands!");
2541 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2542 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2543 Inst.addOperand(MCOperand::createReg(RegNum));
2545 }
2546
2547 void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2548 assert(N == 4 && "Invalid number of operands!");
2549 addVPTPredNOperands(Inst, N-1);
2550 unsigned RegNum;
2551 if (getVPTPred() == ARMVCC::None) {
2552 RegNum = 0;
2553 } else {
2554 unsigned NextOpIndex = Inst.getNumOperands();
2555 auto &MCID = Parser->getInstrDesc(Inst.getOpcode());
2556 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2557 assert(TiedOp >= 0 &&
2558 "Inactive register in vpred_r is not tied to an output!");
2559 RegNum = Inst.getOperand(TiedOp).getReg();
2560 }
2561 Inst.addOperand(MCOperand::createReg(RegNum));
2562 }
2563
2564 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2565 assert(N == 1 && "Invalid number of operands!");
2566 Inst.addOperand(MCOperand::createImm(getCoproc()));
2567 }
2568
2569 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2570 assert(N == 1 && "Invalid number of operands!");
2571 Inst.addOperand(MCOperand::createImm(getCoproc()));
2572 }
2573
2574 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2575 assert(N == 1 && "Invalid number of operands!");
2576 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2577 }
2578
2579 void addITMaskOperands(MCInst &Inst, unsigned N) const {
2580 assert(N == 1 && "Invalid number of operands!");
2581 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2582 }
2583
2584 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2585 assert(N == 1 && "Invalid number of operands!");
2586 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2587 }
2588
2589 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2590 assert(N == 1 && "Invalid number of operands!");
2592 }
2593
2594 void addCCOutOperands(MCInst &Inst, unsigned N) const {
2595 assert(N == 1 && "Invalid number of operands!");
2597 }
2598
2599 void addRegOperands(MCInst &Inst, unsigned N) const {
2600 assert(N == 1 && "Invalid number of operands!");
2602 }
2603
2604 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2605 assert(N == 3 && "Invalid number of operands!");
2606 assert(isRegShiftedReg() &&
2607 "addRegShiftedRegOperands() on non-RegShiftedReg!");
2608 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2609 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2611 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2612 }
2613
2614 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2615 assert(N == 2 && "Invalid number of operands!");
2616 assert(isRegShiftedImm() &&
2617 "addRegShiftedImmOperands() on non-RegShiftedImm!");
2618 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2619 // Shift of #32 is encoded as 0 where permitted
2620 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2622 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2623 }
2624
2625 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2626 assert(N == 1 && "Invalid number of operands!");
2627 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2628 ShifterImm.Imm));
2629 }
2630
2631 void addRegListOperands(MCInst &Inst, unsigned N) const {
2632 assert(N == 1 && "Invalid number of operands!");
2633 const SmallVectorImpl<unsigned> &RegList = getRegList();
2634 for (unsigned Reg : RegList)
2636 }
2637
2638 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2639 assert(N == 1 && "Invalid number of operands!");
2640 const SmallVectorImpl<unsigned> &RegList = getRegList();
2641 for (unsigned Reg : RegList)
2643 }
2644
2645 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2646 addRegListOperands(Inst, N);
2647 }
2648
2649 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2650 addRegListOperands(Inst, N);
2651 }
2652
2653 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2654 addRegListOperands(Inst, N);
2655 }
2656
2657 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2658 addRegListOperands(Inst, N);
2659 }
2660
2661 void addRotImmOperands(MCInst &Inst, unsigned N) const {
2662 assert(N == 1 && "Invalid number of operands!");
2663 // Encoded as val>>3. The printer handles display as 8, 16, 24.
2664 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2665 }
2666
2667 void addModImmOperands(MCInst &Inst, unsigned N) const {
2668 assert(N == 1 && "Invalid number of operands!");
2669
2670 // Support for fixups (MCFixup)
2671 if (isImm())
2672 return addImmOperands(Inst, N);
2673
2674 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2675 }
2676
2677 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2678 assert(N == 1 && "Invalid number of operands!");
2679 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2680 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2682 }
2683
2684 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2685 assert(N == 1 && "Invalid number of operands!");
2686 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2687 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2689 }
2690
2691 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2692 assert(N == 1 && "Invalid number of operands!");
2693 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2694 uint32_t Val = -CE->getValue();
2696 }
2697
2698 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2699 assert(N == 1 && "Invalid number of operands!");
2700 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2701 uint32_t Val = -CE->getValue();
2703 }
2704
2705 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2706 assert(N == 1 && "Invalid number of operands!");
2707 // Munge the lsb/width into a bitfield mask.
2708 unsigned lsb = Bitfield.LSB;
2709 unsigned width = Bitfield.Width;
2710 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2711 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2712 (32 - (lsb + width)));
2713 Inst.addOperand(MCOperand::createImm(Mask));
2714 }
2715
2716 void addImmOperands(MCInst &Inst, unsigned N) const {
2717 assert(N == 1 && "Invalid number of operands!");
2718 addExpr(Inst, getImm());
2719 }
2720
2721 void addFBits16Operands(MCInst &Inst, unsigned N) const {
2722 assert(N == 1 && "Invalid number of operands!");
2723 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2724 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2725 }
2726
2727 void addFBits32Operands(MCInst &Inst, unsigned N) const {
2728 assert(N == 1 && "Invalid number of operands!");
2729 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2730 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2731 }
2732
2733 void addFPImmOperands(MCInst &Inst, unsigned N) const {
2734 assert(N == 1 && "Invalid number of operands!");
2735 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2736 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2738 }
2739
2740 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2741 assert(N == 1 && "Invalid number of operands!");
2742 // FIXME: We really want to scale the value here, but the LDRD/STRD
2743 // instruction don't encode operands that way yet.
2744 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2745 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2746 }
2747
2748 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2749 assert(N == 1 && "Invalid number of operands!");
2750 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2751 // instruction don't encode operands that way yet.
2752 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2753 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2754 }
2755
2756 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2757 assert(N == 1 && "Invalid number of operands!");
2758 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2759 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2760 }
2761
2762 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2763 assert(N == 1 && "Invalid number of operands!");
2764 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2765 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2766 }
2767
2768 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2769 assert(N == 1 && "Invalid number of operands!");
2770 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2771 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2772 }
2773
2774 void addImm7Operands(MCInst &Inst, unsigned N) const {
2775 assert(N == 1 && "Invalid number of operands!");
2776 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2777 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2778 }
2779
2780 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2781 assert(N == 1 && "Invalid number of operands!");
2782 // The immediate is scaled by four in the encoding and is stored
2783 // in the MCInst as such. Lop off the low two bits here.
2784 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2785 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2786 }
2787
2788 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2789 assert(N == 1 && "Invalid number of operands!");
2790 // The immediate is scaled by four in the encoding and is stored
2791 // in the MCInst as such. Lop off the low two bits here.
2792 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2793 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2794 }
2795
2796 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2797 assert(N == 1 && "Invalid number of operands!");
2798 // The immediate is scaled by four in the encoding and is stored
2799 // in the MCInst as such. Lop off the low two bits here.
2800 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2801 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2802 }
2803
2804 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2805 assert(N == 1 && "Invalid number of operands!");
2806 // The constant encodes as the immediate-1, and we store in the instruction
2807 // the bits as encoded, so subtract off one here.
2808 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2809 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2810 }
2811
2812 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2813 assert(N == 1 && "Invalid number of operands!");
2814 // The constant encodes as the immediate-1, and we store in the instruction
2815 // the bits as encoded, so subtract off one here.
2816 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2817 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2818 }
2819
2820 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2821 assert(N == 1 && "Invalid number of operands!");
2822 // The constant encodes as the immediate, except for 32, which encodes as
2823 // zero.
2824 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2825 unsigned Imm = CE->getValue();
2826 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2827 }
2828
2829 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2830 assert(N == 1 && "Invalid number of operands!");
2831 // An ASR value of 32 encodes as 0, so that's how we want to add it to
2832 // the instruction as well.
2833 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2834 int Val = CE->getValue();
2835 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2836 }
2837
2838 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2839 assert(N == 1 && "Invalid number of operands!");
2840 // The operand is actually a t2_so_imm, but we have its bitwise
2841 // negation in the assembly source, so twiddle it here.
2842 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2843 Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2844 }
2845
2846 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2847 assert(N == 1 && "Invalid number of operands!");
2848 // The operand is actually a t2_so_imm, but we have its
2849 // negation in the assembly source, so twiddle it here.
2850 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2851 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2852 }
2853
2854 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2855 assert(N == 1 && "Invalid number of operands!");
2856 // The operand is actually an imm0_4095, but we have its
2857 // negation in the assembly source, so twiddle it here.
2858 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2859 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2860 }
2861
2862 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2863 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2864 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2865 return;
2866 }
2867 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2869 }
2870
2871 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2872 assert(N == 1 && "Invalid number of operands!");
2873 if (isImm()) {
2874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2875 if (CE) {
2876 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2877 return;
2878 }
2879 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2881 return;
2882 }
2883
2884 assert(isGPRMem() && "Unknown value type!");
2885 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2886 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2887 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2888 else
2889 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2890 }
2891
2892 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2893 assert(N == 1 && "Invalid number of operands!");
2894 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2895 }
2896
2897 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2898 assert(N == 1 && "Invalid number of operands!");
2899 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2900 }
2901
2902 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2903 assert(N == 1 && "Invalid number of operands!");
2904 Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2905 }
2906
2907 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2908 assert(N == 1 && "Invalid number of operands!");
2909 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2910 }
2911
2912 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2913 assert(N == 1 && "Invalid number of operands!");
2914 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2915 }
2916
2917 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2918 assert(N == 1 && "Invalid number of operands!");
2919 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2920 }
2921
2922 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2923 assert(N == 1 && "Invalid number of operands!");
2924 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2925 }
2926
2927 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2928 assert(N == 1 && "Invalid number of operands!");
2929 if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
2930 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2931 else
2932 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
2933 }
2934
2935 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2936 assert(N == 1 && "Invalid number of operands!");
2937 assert(isImm() && "Not an immediate!");
2938
2939 // If we have an immediate that's not a constant, treat it as a label
2940 // reference needing a fixup.
2941 if (!isa<MCConstantExpr>(getImm())) {
2942 Inst.addOperand(MCOperand::createExpr(getImm()));
2943 return;
2944 }
2945
2946 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2947 int Val = CE->getValue();
2949 }
2950
2951 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2952 assert(N == 2 && "Invalid number of operands!");
2953 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2954 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2955 }
2956
2957 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2958 addAlignedMemoryOperands(Inst, N);
2959 }
2960
2961 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2962 addAlignedMemoryOperands(Inst, N);
2963 }
2964
2965 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2966 addAlignedMemoryOperands(Inst, N);
2967 }
2968
2969 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2970 addAlignedMemoryOperands(Inst, N);
2971 }
2972
2973 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2974 addAlignedMemoryOperands(Inst, N);
2975 }
2976
2977 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2978 addAlignedMemoryOperands(Inst, N);
2979 }
2980
2981 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2982 addAlignedMemoryOperands(Inst, N);
2983 }
2984
2985 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2986 addAlignedMemoryOperands(Inst, N);
2987 }
2988
2989 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2990 addAlignedMemoryOperands(Inst, N);
2991 }
2992
2993 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2994 addAlignedMemoryOperands(Inst, N);
2995 }
2996
2997 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2998 addAlignedMemoryOperands(Inst, N);
2999 }
3000
3001 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
3002 assert(N == 3 && "Invalid number of operands!");
3003 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3004 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3005 if (!Memory.OffsetRegNum) {
3006 if (!Memory.OffsetImm)
3008 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3009 int32_t Val = CE->getValue();
3011 // Special case for #-0
3012 if (Val == std::numeric_limits<int32_t>::min())
3013 Val = 0;
3014 if (Val < 0)
3015 Val = -Val;
3016 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
3018 } else
3019 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3020 } else {
3021 // For register offset, we encode the shift type and negation flag
3022 // here.
3023 int32_t Val =
3025 Memory.ShiftImm, Memory.ShiftType);
3027 }
3028 }
3029
3030 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
3031 assert(N == 2 && "Invalid number of operands!");
3032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3033 assert(CE && "non-constant AM2OffsetImm operand!");
3034 int32_t Val = CE->getValue();
3036 // Special case for #-0
3037 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3038 if (Val < 0) Val = -Val;
3039 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
3042 }
3043
3044 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
3045 assert(N == 3 && "Invalid number of operands!");
3046 // If we have an immediate that's not a constant, treat it as a label
3047 // reference needing a fixup. If it is a constant, it's something else
3048 // and we reject it.
3049 if (isImm()) {
3050 Inst.addOperand(MCOperand::createExpr(getImm()));
3053 return;
3054 }
3055
3056 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3057 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3058 if (!Memory.OffsetRegNum) {
3059 if (!Memory.OffsetImm)
3061 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3062 int32_t Val = CE->getValue();
3064 // Special case for #-0
3065 if (Val == std::numeric_limits<int32_t>::min())
3066 Val = 0;
3067 if (Val < 0)
3068 Val = -Val;
3069 Val = ARM_AM::getAM3Opc(AddSub, Val);
3071 } else
3072 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3073 } else {
3074 // For register offset, we encode the shift type and negation flag
3075 // here.
3076 int32_t Val =
3079 }
3080 }
3081
3082 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
3083 assert(N == 2 && "Invalid number of operands!");
3084 if (Kind == k_PostIndexRegister) {
3085 int32_t Val =
3086 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
3087 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3089 return;
3090 }
3091
3092 // Constant offset.
3093 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
3094 int32_t Val = CE->getValue();
3096 // Special case for #-0
3097 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
3098 if (Val < 0) Val = -Val;
3099 Val = ARM_AM::getAM3Opc(AddSub, Val);
3102 }
3103
3104 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
3105 assert(N == 2 && "Invalid number of operands!");
3106 // If we have an immediate that's not a constant, treat it as a label
3107 // reference needing a fixup. If it is a constant, it's something else
3108 // and we reject it.
3109 if (isImm()) {
3110 Inst.addOperand(MCOperand::createExpr(getImm()));
3112 return;
3113 }
3114
3115 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3116 if (!Memory.OffsetImm)
3118 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3119 // The lower two bits are always zero and as such are not encoded.
3120 int32_t Val = CE->getValue() / 4;
3122 // Special case for #-0
3123 if (Val == std::numeric_limits<int32_t>::min())
3124 Val = 0;
3125 if (Val < 0)
3126 Val = -Val;
3127 Val = ARM_AM::getAM5Opc(AddSub, Val);
3129 } else
3130 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3131 }
3132
3133 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
3134 assert(N == 2 && "Invalid number of operands!");
3135 // If we have an immediate that's not a constant, treat it as a label
3136 // reference needing a fixup. If it is a constant, it's something else
3137 // and we reject it.
3138 if (isImm()) {
3139 Inst.addOperand(MCOperand::createExpr(getImm()));
3141 return;
3142 }
3143
3144 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3145 // The lower bit is always zero and as such is not encoded.
3146 if (!Memory.OffsetImm)
3148 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm)) {
3149 int32_t Val = CE->getValue() / 2;
3151 // Special case for #-0
3152 if (Val == std::numeric_limits<int32_t>::min())
3153 Val = 0;
3154 if (Val < 0)
3155 Val = -Val;
3156 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
3158 } else
3159 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3160 }
3161
3162 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
3163 assert(N == 2 && "Invalid number of operands!");
3164 // If we have an immediate that's not a constant, treat it as a label
3165 // reference needing a fixup. If it is a constant, it's something else
3166 // and we reject it.
3167 if (isImm()) {
3168 Inst.addOperand(MCOperand::createExpr(getImm()));
3170 return;
3171 }
3172
3173 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3174 addExpr(Inst, Memory.OffsetImm);
3175 }
3176
3177 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
3178 assert(N == 2 && "Invalid number of operands!");
3179 // If we have an immediate that's not a constant, treat it as a label
3180 // reference needing a fixup. If it is a constant, it's something else
3181 // and we reject it.
3182 if (isImm()) {
3183 Inst.addOperand(MCOperand::createExpr(getImm()));
3185 return;
3186 }
3187
3188 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3189 addExpr(Inst, Memory.OffsetImm);
3190 }
3191
3192 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
3193 assert(N == 2 && "Invalid number of operands!");
3194 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3195 if (!Memory.OffsetImm)
3197 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3198 // The lower two bits are always zero and as such are not encoded.
3199 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3200 else
3201 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3202 }
3203
3204 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
3205 assert(N == 2 && "Invalid number of operands!");
3206 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3207 addExpr(Inst, Memory.OffsetImm);
3208 }
3209
3210 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
3211 assert(N == 2 && "Invalid number of operands!");
3212 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3213 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3214 }
3215
3216 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3217 assert(N == 2 && "Invalid number of operands!");
3218 // If this is an immediate, it's a label reference.
3219 if (isImm()) {
3220 addExpr(Inst, getImm());
3222 return;
3223 }
3224
3225 // Otherwise, it's a normal memory reg+offset.
3226 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3227 addExpr(Inst, Memory.OffsetImm);
3228 }
3229
3230 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3231 assert(N == 2 && "Invalid number of operands!");
3232 // If this is an immediate, it's a label reference.
3233 if (isImm()) {
3234 addExpr(Inst, getImm());
3236 return;
3237 }
3238
3239 // Otherwise, it's a normal memory reg+offset.
3240 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3241 addExpr(Inst, Memory.OffsetImm);
3242 }
3243
3244 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3245 assert(N == 1 && "Invalid number of operands!");
3246 // This is container for the immediate that we will create the constant
3247 // pool from
3248 addExpr(Inst, getConstantPoolImm());
3249 }
3250
3251 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3252 assert(N == 2 && "Invalid number of operands!");
3253 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3254 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3255 }
3256
3257 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3258 assert(N == 2 && "Invalid number of operands!");
3259 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3260 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3261 }
3262
3263 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3264 assert(N == 3 && "Invalid number of operands!");
3265 unsigned Val =
3267 Memory.ShiftImm, Memory.ShiftType);
3268 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3269 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3271 }
3272
3273 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3274 assert(N == 3 && "Invalid number of operands!");
3275 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3276 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3277 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3278 }
3279
3280 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3281 assert(N == 2 && "Invalid number of operands!");
3282 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3283 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3284 }
3285
3286 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3287 assert(N == 2 && "Invalid number of operands!");
3288 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3289 if (!Memory.OffsetImm)
3291 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3292 // The lower two bits are always zero and as such are not encoded.
3293 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3294 else
3295 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3296 }
3297
3298 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3299 assert(N == 2 && "Invalid number of operands!");
3300 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3301 if (!Memory.OffsetImm)
3303 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3304 Inst.addOperand(MCOperand::createImm(CE->getValue() / 2));
3305 else
3306 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3307 }
3308
3309 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3310 assert(N == 2 && "Invalid number of operands!");
3311 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3312 addExpr(Inst, Memory.OffsetImm);
3313 }
3314
3315 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3316 assert(N == 2 && "Invalid number of operands!");
3317 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3318 if (!Memory.OffsetImm)
3320 else if (const auto *CE = dyn_cast<MCConstantExpr>(Memory.OffsetImm))
3321 // The lower two bits are always zero and as such are not encoded.
3322 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
3323 else
3324 Inst.addOperand(MCOperand::createExpr(Memory.OffsetImm));
3325 }
3326
3327 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3328 assert(N == 1 && "Invalid number of operands!");
3329 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3330 assert(CE && "non-constant post-idx-imm8 operand!");
3331 int Imm = CE->getValue();
3332 bool isAdd = Imm >= 0;
3333 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3334 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3336 }
3337
3338 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3339 assert(N == 1 && "Invalid number of operands!");
3340 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3341 assert(CE && "non-constant post-idx-imm8s4 operand!");
3342 int Imm = CE->getValue();
3343 bool isAdd = Imm >= 0;
3344 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3345 // Immediate is scaled by 4.
3346 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3348 }
3349
3350 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3351 assert(N == 2 && "Invalid number of operands!");
3352 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3353 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3354 }
3355
3356 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3357 assert(N == 2 && "Invalid number of operands!");
3358 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3359 // The sign, shift type, and shift amount are encoded in a single operand
3360 // using the AM2 encoding helpers.
3361 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3362 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3363 PostIdxReg.ShiftTy);
3365 }
3366
3367 void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3368 assert(N == 1 && "Invalid number of operands!");
3369 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3370 Inst.addOperand(MCOperand::createImm(CE->getValue()));
3371 }
3372
3373 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3374 assert(N == 1 && "Invalid number of operands!");
3375 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3376 }
3377
3378 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3379 assert(N == 1 && "Invalid number of operands!");
3380 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3381 }
3382
3383 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3384 assert(N == 1 && "Invalid number of operands!");
3385 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3386 }
3387
3388 void addVecListOperands(MCInst &Inst, unsigned N) const {
3389 assert(N == 1 && "Invalid number of operands!");
3390
3391 if (isAnyVectorList())
3392 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3393 else if (isDReg() && !Parser->hasMVE()) {
3394 Inst.addOperand(MCOperand::createReg(Reg.RegNum));
3395 } else if (isQReg() && !Parser->hasMVE()) {
3396 auto DPair = Parser->getDRegFromQReg(Reg.RegNum);
3397 DPair = Parser->getMRI()->getMatchingSuperReg(
3398 DPair, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3399 Inst.addOperand(MCOperand::createReg(DPair));
3400 } else {
3401 LLVM_DEBUG(dbgs() << "TYPE: " << Kind << "\n");
3403 "attempted to add a vector list register with wrong type!");
3404 }
3405 }
3406
3407 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3408 assert(N == 1 && "Invalid number of operands!");
3409
3410 // When we come here, the VectorList field will identify a range
3411 // of q-registers by its base register and length, and it will
3412 // have already been error-checked to be the expected length of
3413 // range and contain only q-regs in the range q0-q7. So we can
3414 // count on the base register being in the range q0-q6 (for 2
3415 // regs) or q0-q4 (for 4)
3416 //
3417 // The MVE instructions taking a register range of this kind will
3418 // need an operand in the MQQPR or MQQQQPR class, representing the
3419 // entire range as a unit. So we must translate into that class,
3420 // by finding the index of the base register in the MQPR reg
3421 // class, and returning the super-register at the corresponding
3422 // index in the target class.
3423
3424 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3425 const MCRegisterClass *RC_out =
3426 (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::MQQPRRegClassID]
3427 : &ARMMCRegisterClasses[ARM::MQQQQPRRegClassID];
3428
3429 unsigned I, E = RC_out->getNumRegs();
3430 for (I = 0; I < E; I++)
3431 if (RC_in->getRegister(I) == VectorList.RegNum)
3432 break;
3433 assert(I < E && "Invalid vector list start register!");
3434
3436 }
3437
3438 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3439 assert(N == 2 && "Invalid number of operands!");
3440 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3441 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3442 }
3443
3444 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3445 assert(N == 1 && "Invalid number of operands!");
3446 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3447 }
3448
3449 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3450 assert(N == 1 && "Invalid number of operands!");
3451 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3452 }
3453
3454 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3455 assert(N == 1 && "Invalid number of operands!");
3456 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3457 }
3458
3459 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3460 assert(N == 1 && "Invalid number of operands!");
3461 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3462 }
3463
3464 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3465 assert(N == 1 && "Invalid number of operands!");
3466 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3467 }
3468
3469 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3470 assert(N == 1 && "Invalid number of operands!");
3471 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3472 }
3473
3474 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3475 assert(N == 1 && "Invalid number of operands!");
3476 // The immediate encodes the type of constant as well as the value.
3477 // Mask in that this is an i8 splat.
3478 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3479 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3480 }
3481
3482 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3483 assert(N == 1 && "Invalid number of operands!");
3484 // The immediate encodes the type of constant as well as the value.
3485 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3486 unsigned Value = CE->getValue();
3489 }
3490
3491 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3492 assert(N == 1 && "Invalid number of operands!");
3493 // The immediate encodes the type of constant as well as the value.
3494 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3495 unsigned Value = CE->getValue();
3498 }
3499
3500 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3501 assert(N == 1 && "Invalid number of operands!");
3502 // The immediate encodes the type of constant as well as the value.
3503 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3504 unsigned Value = CE->getValue();
3507 }
3508
3509 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3510 assert(N == 1 && "Invalid number of operands!");
3511 // The immediate encodes the type of constant as well as the value.
3512 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3513 unsigned Value = CE->getValue();
3516 }
3517
3518 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3519 // The immediate encodes the type of constant as well as the value.
3520 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3521 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3522 Inst.getOpcode() == ARM::VMOVv16i8) &&
3523 "All instructions that wants to replicate non-zero byte "
3524 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
3525 unsigned Value = CE->getValue();
3526 if (Inv)
3527 Value = ~Value;
3528 unsigned B = Value & 0xff;
3529 B |= 0xe00; // cmode = 0b1110
3531 }
3532
3533 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3534 assert(N == 1 && "Invalid number of operands!");
3535 addNEONi8ReplicateOperands(Inst, true);
3536 }
3537
3538 static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3539 if (Value >= 256 && Value <= 0xffff)
3540 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3541 else if (Value > 0xffff && Value <= 0xffffff)
3542 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3543 else if (Value > 0xffffff)
3544 Value = (Value >> 24) | 0x600;
3545 return Value;
3546 }
3547
3548 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3549 assert(N == 1 && "Invalid number of operands!");
3550 // The immediate encodes the type of constant as well as the value.
3551 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3552 unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3554 }
3555
3556 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3557 assert(N == 1 && "Invalid number of operands!");
3558 addNEONi8ReplicateOperands(Inst, false);
3559 }
3560
3561 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3562 assert(N == 1 && "Invalid number of operands!");
3563 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3564 assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3565 Inst.getOpcode() == ARM::VMOVv8i16 ||
3566 Inst.getOpcode() == ARM::VMVNv4i16 ||
3567 Inst.getOpcode() == ARM::VMVNv8i16) &&
3568 "All instructions that want to replicate non-zero half-word "
3569 "always must be replaced with V{MOV,MVN}v{4,8}i16.");
3570 uint64_t Value = CE->getValue();
3571 unsigned Elem = Value & 0xffff;
3572 if (Elem >= 256)
3573 Elem = (Elem >> 8) | 0x200;
3574 Inst.addOperand(MCOperand::createImm(Elem));
3575 }
3576
3577 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3578 assert(N == 1 && "Invalid number of operands!");
3579 // The immediate encodes the type of constant as well as the value.
3580 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3581 unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3583 }
3584
3585 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3586 assert(N == 1 && "Invalid number of operands!");
3587 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3588 assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3589 Inst.getOpcode() == ARM::VMOVv4i32 ||
3590 Inst.getOpcode() == ARM::VMVNv2i32 ||
3591 Inst.getOpcode() == ARM::VMVNv4i32) &&
3592 "All instructions that want to replicate non-zero word "
3593 "always must be replaced with V{MOV,MVN}v{2,4}i32.");
3594 uint64_t Value = CE->getValue();
3595 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3596 Inst.addOperand(MCOperand::createImm(Elem));
3597 }
3598
3599 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3600 assert(N == 1 && "Invalid number of operands!");
3601 // The immediate encodes the type of constant as well as the value.
3602 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3603 uint64_t Value = CE->getValue();
3604 unsigned Imm = 0;
3605 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3606 Imm |= (Value & 1) << i;
3607 }
3608 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3609 }
3610
3611 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3612 assert(N == 1 && "Invalid number of operands!");
3613 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3614 Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3615 }
3616
3617 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3618 assert(N == 1 && "Invalid number of operands!");
3619 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3620 Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3621 }
3622
3623 void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3624 assert(N == 1 && "Invalid number of operands!");
3625 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3626 unsigned Imm = CE->getValue();
3627 assert((Imm == 48 || Imm == 64) && "Invalid saturate operand");
3628 Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3629 }
3630
3631 void print(raw_ostream &OS) const override;
3632
3633 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S,
3634 ARMAsmParser &Parser) {
3635 auto Op = std::make_unique<ARMOperand>(k_ITCondMask, Parser);
3636 Op->ITMask.Mask = Mask;
3637 Op->StartLoc = S;
3638 Op->EndLoc = S;
3639 return Op;
3640 }
3641
3642 static std::unique_ptr<ARMOperand>
3643 CreateCondCode(ARMCC::CondCodes CC, SMLoc S, ARMAsmParser &Parser) {
3644 auto Op = std::make_unique<ARMOperand>(k_CondCode, Parser);
3645 Op->CC.Val = CC;
3646 Op->StartLoc = S;
3647 Op->EndLoc = S;
3648 return Op;
3649 }
3650
3651 static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC, SMLoc S,
3652 ARMAsmParser &Parser) {
3653 auto Op = std::make_unique<ARMOperand>(k_VPTPred, Parser);
3654 Op->VCC.Val = CC;
3655 Op->StartLoc = S;
3656 Op->EndLoc = S;
3657 return Op;
3658 }
3659
3660 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S,
3661 ARMAsmParser &Parser) {
3662 auto Op = std::make_unique<ARMOperand>(k_CoprocNum, Parser);
3663 Op->Cop.Val = CopVal;
3664 Op->StartLoc = S;
3665 Op->EndLoc = S;
3666 return Op;
3667 }
3668
3669 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S,
3670 ARMAsmParser &Parser) {
3671 auto Op = std::make_unique<ARMOperand>(k_CoprocReg, Parser);
3672 Op->Cop.Val = CopVal;
3673 Op->StartLoc = S;
3674 Op->EndLoc = S;
3675 return Op;
3676 }
3677
3678 static std::unique_ptr<ARMOperand>
3679 CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3680 auto Op = std::make_unique<ARMOperand>(k_CoprocOption, Parser);
3681 Op->Cop.Val = Val;
3682 Op->StartLoc = S;
3683 Op->EndLoc = E;
3684 return Op;
3685 }
3686
3687 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S,
3688 ARMAsmParser &Parser) {
3689 auto Op = std::make_unique<ARMOperand>(k_CCOut, Parser);
3690 Op->Reg.RegNum = RegNum;
3691 Op->StartLoc = S;
3692 Op->EndLoc = S;
3693 return Op;
3694 }
3695
3696 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S,
3697 ARMAsmParser &Parser) {
3698 auto Op = std::make_unique<ARMOperand>(k_Token, Parser);
3699 Op->Tok.Data = Str.data();
3700 Op->Tok.Length = Str.size();
3701 Op->StartLoc = S;
3702 Op->EndLoc = S;
3703 return Op;
3704 }
3705
3706 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3707 SMLoc E, ARMAsmParser &Parser) {
3708 auto Op = std::make_unique<ARMOperand>(k_Register, Parser);
3709 Op->Reg.RegNum = RegNum;
3710 Op->StartLoc = S;
3711 Op->EndLoc = E;
3712 return Op;
3713 }
3714
3715 static std::unique_ptr<ARMOperand>
3716 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3717 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E,
3718 ARMAsmParser &Parser) {
3719 auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister, Parser);
3720 Op->RegShiftedReg.ShiftTy = ShTy;
3721 Op->RegShiftedReg.SrcReg = SrcReg;
3722 Op->RegShiftedReg.ShiftReg = ShiftReg;
3723 Op->RegShiftedReg.ShiftImm = ShiftImm;
3724 Op->StartLoc = S;
3725 Op->EndLoc = E;
3726 return Op;
3727 }
3728
3729 static std::unique_ptr<ARMOperand>
3730 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3731 unsigned ShiftImm, SMLoc S, SMLoc E,
3732 ARMAsmParser &Parser) {
3733 auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate, Parser);
3734 Op->RegShiftedImm.ShiftTy = ShTy;
3735 Op->RegShiftedImm.SrcReg = SrcReg;
3736 Op->RegShiftedImm.ShiftImm = ShiftImm;
3737 Op->StartLoc = S;
3738 Op->EndLoc = E;
3739 return Op;
3740 }
3741
3742 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3743 SMLoc S, SMLoc E,
3744 ARMAsmParser &Parser) {
3745 auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate, Parser);
3746 Op->ShifterImm.isASR = isASR;
3747 Op->ShifterImm.Imm = Imm;
3748 Op->StartLoc = S;
3749 Op->EndLoc = E;
3750 return Op;
3751 }
3752
3753 static std::unique_ptr<ARMOperand>
3754 CreateRotImm(unsigned Imm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3755 auto Op = std::make_unique<ARMOperand>(k_RotateImmediate, Parser);
3756 Op->RotImm.Imm = Imm;
3757 Op->StartLoc = S;
3758 Op->EndLoc = E;
3759 return Op;
3760 }
3761
3762 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3763 SMLoc S, SMLoc E,
3764 ARMAsmParser &Parser) {
3765 auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate, Parser);
3766 Op->ModImm.Bits = Bits;
3767 Op->ModImm.Rot = Rot;
3768 Op->StartLoc = S;
3769 Op->EndLoc = E;
3770 return Op;
3771 }
3772
3773 static std::unique_ptr<ARMOperand>
3774 CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E,
3775 ARMAsmParser &Parser) {
3776 auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate, Parser);
3777 Op->Imm.Val = Val;
3778 Op->StartLoc = S;
3779 Op->EndLoc = E;
3780 return Op;
3781 }
3782
3783 static std::unique_ptr<ARMOperand> CreateBitfield(unsigned LSB,
3784 unsigned Width, SMLoc S,
3785 SMLoc E,
3786 ARMAsmParser &Parser) {
3787 auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor, Parser);
3788 Op->Bitfield.LSB = LSB;
3789 Op->Bitfield.Width = Width;
3790 Op->StartLoc = S;
3791 Op->EndLoc = E;
3792 return Op;
3793 }
3794
3795 static std::unique_ptr<ARMOperand>
3796 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3797 SMLoc StartLoc, SMLoc EndLoc, ARMAsmParser &Parser) {
3798 assert(Regs.size() > 0 && "RegList contains no registers?");
3799 KindTy Kind = k_RegisterList;
3800
3801 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3802 Regs.front().second)) {
3803 if (Regs.back().second == ARM::VPR)
3804 Kind = k_FPDRegisterListWithVPR;
3805 else
3806 Kind = k_DPRRegisterList;
3807 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3808 Regs.front().second)) {
3809 if (Regs.back().second == ARM::VPR)
3810 Kind = k_FPSRegisterListWithVPR;
3811 else
3812 Kind = k_SPRRegisterList;
3813 }
3814
3815 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3816 Kind = k_RegisterListWithAPSR;
3817
3818 assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding");
3819
3820 auto Op = std::make_unique<ARMOperand>(Kind, Parser);
3821 for (const auto &P : Regs)
3822 Op->Registers.push_back(P.second);
3823
3824 Op->StartLoc = StartLoc;
3825 Op->EndLoc = EndLoc;
3826 return Op;
3827 }
3828
3829 static std::unique_ptr<ARMOperand>
3830 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3831 SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3832 auto Op = std::make_unique<ARMOperand>(k_VectorList, Parser);
3833 Op->VectorList.RegNum = RegNum;
3834 Op->VectorList.Count = Count;
3835 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3836 Op->StartLoc = S;
3837 Op->EndLoc = E;
3838 return Op;
3839 }
3840
3841 static std::unique_ptr<ARMOperand>
3842 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3843 SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3844 auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes, Parser);
3845 Op->VectorList.RegNum = RegNum;
3846 Op->VectorList.Count = Count;
3847 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3848 Op->StartLoc = S;
3849 Op->EndLoc = E;
3850 return Op;
3851 }
3852
3853 static std::unique_ptr<ARMOperand>
3854 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3855 bool isDoubleSpaced, SMLoc S, SMLoc E,
3856 ARMAsmParser &Parser) {
3857 auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed, Parser);
3858 Op->VectorList.RegNum = RegNum;
3859 Op->VectorList.Count = Count;
3860 Op->VectorList.LaneIndex = Index;
3861 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3862 Op->StartLoc = S;
3863 Op->EndLoc = E;
3864 return Op;
3865 }
3866
3867 static std::unique_ptr<ARMOperand> CreateVectorIndex(unsigned Idx, SMLoc S,
3868 SMLoc E, MCContext &Ctx,
3869 ARMAsmParser &Parser) {
3870 auto Op = std::make_unique<ARMOperand>(k_VectorIndex, Parser);
3871 Op->VectorIndex.Val = Idx;
3872 Op->StartLoc = S;
3873 Op->EndLoc = E;
3874 return Op;
3875 }
3876
3877 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3878 SMLoc E, ARMAsmParser &Parser) {
3879 auto Op = std::make_unique<ARMOperand>(k_Immediate, Parser);
3880 Op->Imm.Val = Val;
3881 Op->StartLoc = S;
3882 Op->EndLoc = E;
3883 return Op;
3884 }
3885
3886 static std::unique_ptr<ARMOperand>
3887 CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum,
3888 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3889 bool isNegative, SMLoc S, SMLoc E, ARMAsmParser &Parser,
3890 SMLoc AlignmentLoc = SMLoc()) {
3891 auto Op = std::make_unique<ARMOperand>(k_Memory, Parser);
3892 Op->Memory.BaseRegNum = BaseRegNum;
3893 Op->Memory.OffsetImm = OffsetImm;
3894 Op->Memory.OffsetRegNum = OffsetRegNum;
3895 Op->Memory.ShiftType = ShiftType;
3896 Op->Memory.ShiftImm = ShiftImm;
3897 Op->Memory.Alignment = Alignment;
3898 Op->Memory.isNegative = isNegative;
3899 Op->StartLoc = S;
3900 Op->EndLoc = E;
3901 Op->AlignmentLoc = AlignmentLoc;
3902 return Op;
3903 }
3904
3905 static std::unique_ptr<ARMOperand>
3906 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3907 unsigned ShiftImm, SMLoc S, SMLoc E, ARMAsmParser &Parser) {
3908 auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister, Parser);
3909 Op->PostIdxReg.RegNum = RegNum;
3910 Op->PostIdxReg.isAdd = isAdd;
3911 Op->PostIdxReg.ShiftTy = ShiftTy;
3912 Op->PostIdxReg.ShiftImm = ShiftImm;
3913 Op->StartLoc = S;
3914 Op->EndLoc = E;
3915 return Op;
3916 }
3917
3918 static std::unique_ptr<ARMOperand>
3919 CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S, ARMAsmParser &Parser) {
3920 auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt, Parser);
3921 Op->MBOpt.Val = Opt;
3922 Op->StartLoc = S;
3923 Op->EndLoc = S;
3924 return Op;
3925 }
3926
3927 static std::unique_ptr<ARMOperand>
3928 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S,
3929 ARMAsmParser &Parser) {
3930 auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt, Parser);
3931 Op->ISBOpt.Val = Opt;
3932 Op->StartLoc = S;
3933 Op->EndLoc = S;
3934 return Op;
3935 }
3936
3937 static std::unique_ptr<ARMOperand>
3938 CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S,
3939 ARMAsmParser &Parser) {
3940 auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt, Parser);
3941 Op->TSBOpt.Val = Opt;
3942 Op->StartLoc = S;
3943 Op->EndLoc = S;
3944 return Op;
3945 }
3946
3947 static std::unique_ptr<ARMOperand>
3948 CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S, ARMAsmParser &Parser) {
3949 auto Op = std::make_unique<ARMOperand>(k_ProcIFlags, Parser);
3950 Op->IFlags.Val = IFlags;
3951 Op->StartLoc = S;
3952 Op->EndLoc = S;
3953 return Op;
3954 }
3955
3956 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S,
3957 ARMAsmParser &Parser) {
3958 auto Op = std::make_unique<ARMOperand>(k_MSRMask, Parser);
3959 Op->MMask.Val = MMask;
3960 Op->StartLoc = S;
3961 Op->EndLoc = S;
3962 return Op;
3963 }
3964
3965 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S,
3966 ARMAsmParser &Parser) {
3967 auto Op = std::make_unique<ARMOperand>(k_BankedReg, Parser);
3968 Op->BankedReg.Val = Reg;
3969 Op->StartLoc = S;
3970 Op->EndLoc = S;
3971 return Op;
3972 }
3973};
3974
3975} // end anonymous namespace.
3976
3977void ARMOperand::print(raw_ostream &OS) const {
3978 auto RegName = [](MCRegister Reg) {
3979 if (Reg)
3981 else
3982 return "noreg";
3983 };
3984
3985 switch (Kind) {
3986 case k_CondCode:
3987 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3988 break;
3989 case k_VPTPred:
3990 OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3991 break;
3992 case k_CCOut:
3993 OS << "<ccout " << RegName(getReg()) << ">";
3994 break;
3995 case k_ITCondMask: {
3996 static const char *const MaskStr[] = {
3997 "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3998 "(tt)", "(ttet)", "(tte)", "(ttee)",
3999 "(t)", "(tett)", "(tet)", "(tete)",
4000 "(te)", "(teet)", "(tee)", "(teee)",
4001 };
4002 assert((ITMask.Mask & 0xf) == ITMask.Mask);
4003 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
4004 break;
4005 }
4006 case k_CoprocNum:
4007 OS << "<coprocessor number: " << getCoproc() << ">";
4008 break;
4009 case k_CoprocReg:
4010 OS << "<coprocessor register: " << getCoproc() << ">";
4011 break;
4012 case k_CoprocOption:
4013 OS << "<coprocessor option: " << CoprocOption.Val << ">";
4014 break;
4015 case k_MSRMask:
4016 OS << "<mask: " << getMSRMask() << ">";
4017 break;
4018 case k_BankedReg:
4019 OS << "<banked reg: " << getBankedReg() << ">";
4020 break;
4021 case k_Immediate:
4022 OS << *getImm();
4023 break;
4024 case k_MemBarrierOpt:
4025 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
4026 break;
4027 case k_InstSyncBarrierOpt:
4028 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
4029 break;
4030 case k_TraceSyncBarrierOpt:
4031 OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
4032 break;
4033 case k_Memory:
4034 OS << "<memory";
4035 if (Memory.BaseRegNum)
4036 OS << " base:" << RegName(Memory.BaseRegNum);
4037 if (Memory.OffsetImm)
4038 OS << " offset-imm:" << *Memory.OffsetImm;
4039 if (Memory.OffsetRegNum)
4040 OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
4041 << RegName(Memory.OffsetRegNum);
4042 if (Memory.ShiftType != ARM_AM::no_shift) {
4043 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
4044 OS << " shift-imm:" << Memory.ShiftImm;
4045 }
4046 if (Memory.Alignment)
4047 OS << " alignment:" << Memory.Alignment;
4048 OS << ">";
4049 break;
4050 case k_PostIndexRegister:
4051 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
4052 << RegName(PostIdxReg.RegNum);
4053 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
4054 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
4055 << PostIdxReg.ShiftImm;
4056 OS << ">";
4057 break;
4058 case k_ProcIFlags: {
4059 OS << "<ARM_PROC::";
4060 unsigned IFlags = getProcIFlags();
4061 for (int i=2; i >= 0; --i)
4062 if (IFlags & (1 << i))
4063 OS << ARM_PROC::IFlagsToString(1 << i);
4064 OS << ">";
4065 break;
4066 }
4067 case k_Register:
4068 OS << "<register " << RegName(getReg()) << ">";
4069 break;
4070 case k_ShifterImmediate:
4071 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
4072 << " #" << ShifterImm.Imm << ">";
4073 break;
4074 case k_ShiftedRegister:
4075 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
4076 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
4077 << RegName(RegShiftedReg.ShiftReg) << ">";
4078 break;
4079 case k_ShiftedImmediate:
4080 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
4081 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4082 << RegShiftedImm.ShiftImm << ">";
4083 break;
4084 case k_RotateImmediate:
4085 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
4086 break;
4087 case k_ModifiedImmediate:
4088 OS << "<mod_imm #" << ModImm.Bits << ", #"
4089 << ModImm.Rot << ")>";
4090 break;
4091 case k_ConstantPoolImmediate:
4092 OS << "<constant_pool_imm #" << *getConstantPoolImm();
4093 break;
4094 case k_BitfieldDescriptor:
4095 OS << "<bitfield " << "lsb: " << Bitfield.LSB
4096 << ", width: " << Bitfield.Width << ">";
4097 break;
4098 case k_RegisterList:
4099 case k_RegisterListWithAPSR:
4100 case k_DPRRegisterList:
4101 case k_SPRRegisterList:
4102 case k_FPSRegisterListWithVPR:
4103 case k_FPDRegisterListWithVPR: {
4104 OS << "<register_list ";
4105
4106 const SmallVectorImpl<unsigned> &RegList = getRegList();
4108 I = RegList.begin(), E = RegList.end(); I != E; ) {
4109 OS << RegName(*I);
4110 if (++I < E) OS << ", ";
4111 }
4112
4113 OS << ">";
4114 break;
4115 }
4116 case k_VectorList:
4117 OS << "<vector_list " << VectorList.Count << " * "
4118 << RegName(VectorList.RegNum) << ">";
4119 break;
4120 case k_VectorListAllLanes:
4121 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
4122 << RegName(VectorList.RegNum) << ">";
4123 break;
4124 case k_VectorListIndexed:
4125 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
4126 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
4127 break;
4128 case k_Token:
4129 OS << "'" << getToken() << "'";
4130 break;
4131 case k_VectorIndex:
4132 OS << "<vectorindex " << getVectorIndex() << ">";
4133 break;
4134 }
4135}
4136
4137/// @name Auto-generated Match Functions
4138/// {
4139
4141
4142/// }
4143
4144static bool isDataTypeToken(StringRef Tok) {
4145 static const DenseSet<StringRef> DataTypes{
4146 ".8", ".16", ".32", ".64", ".i8", ".i16", ".i32", ".i64",
4147 ".u8", ".u16", ".u32", ".u64", ".s8", ".s16", ".s32", ".s64",
4148 ".p8", ".p16", ".f32", ".f64", ".f", ".d"};
4149 return DataTypes.contains(Tok);
4150}
4151
4153 unsigned MnemonicOpsEndInd = 1;
4154 // Special case for CPS which has a Mnemonic side token for possibly storing
4155 // ie/id variant
4156 if (Operands[0]->isToken() &&
4157 static_cast<ARMOperand &>(*Operands[0]).getToken() == "cps") {
4158 if (Operands.size() > 1 && Operands[1]->isImm() &&
4159 static_cast<ARMOperand &>(*Operands[1]).getImm()->getKind() ==
4161 (dyn_cast<MCConstantExpr>(
4162 static_cast<ARMOperand &>(*Operands[1]).getImm())
4163 ->getValue() == ARM_PROC::IE ||
4164 dyn_cast<MCConstantExpr>(
4165 static_cast<ARMOperand &>(*Operands[1]).getImm())
4166 ->getValue() == ARM_PROC::ID))
4167 ++MnemonicOpsEndInd;
4168 }
4169
4170 // In some circumstances the condition code moves to the right
4171 bool RHSCondCode = false;
4172 while (MnemonicOpsEndInd < Operands.size()) {
4173 auto Op = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]);
4174 // Special case for it instructions which have a condition code on the RHS
4175 if (Op.isITMask()) {
4176 RHSCondCode = true;
4177 MnemonicOpsEndInd++;
4178 } else if (Op.isToken() &&
4179 (
4180 // There are several special cases not covered by
4181 // isDataTypeToken
4182 Op.getToken() == ".w" || Op.getToken() == ".bf16" ||
4183 Op.getToken() == ".p64" || Op.getToken() == ".f16" ||
4184 isDataTypeToken(Op.getToken()))) {
4185 // In the mnemonic operators the cond code must always precede the data
4186 // type. So we can now safely assume any subsequent cond code is on the
4187 // RHS. As is the case for VCMP and VPT.
4188 RHSCondCode = true;
4189 MnemonicOpsEndInd++;
4190 }
4191 // Skip all mnemonic operator types
4192 else if (Op.isCCOut() || (Op.isCondCode() && !RHSCondCode) ||
4193 Op.isVPTPred() || (Op.isToken() && Op.getToken() == ".w"))
4194 MnemonicOpsEndInd++;
4195 else
4196 break;
4197 }
4198 return MnemonicOpsEndInd;
4199}
4200
4201bool ARMAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
4202 SMLoc &EndLoc) {
4203 const AsmToken &Tok = getParser().getTok();
4204 StartLoc = Tok.getLoc();
4205 EndLoc = Tok.getEndLoc();
4206 Reg = tryParseRegister();
4207
4208 return Reg == (unsigned)-1;
4209}
4210
4211ParseStatus ARMAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
4212 SMLoc &EndLoc) {
4213 if (parseRegister(Reg, StartLoc, EndLoc))
4214 return ParseStatus::NoMatch;
4215 return ParseStatus::Success;
4216}
4217
4218/// Try to parse a register name. The token must be an Identifier when called,
4219/// and if it is a register name the token is eaten and the register number is
4220/// returned. Otherwise return -1.
4221int ARMAsmParser::tryParseRegister(bool AllowOutOfBoundReg) {
4222 MCAsmParser &Parser = getParser();
4223 const AsmToken &Tok = Parser.getTok();
4224 if (Tok.isNot(AsmToken::Identifier)) return -1;
4225
4226 std::string lowerCase = Tok.getString().lower();
4227 unsigned RegNum = MatchRegisterName(lowerCase);
4228 if (!RegNum) {
4229 RegNum = StringSwitch<unsigned>(lowerCase)
4230 .Case("r13", ARM::SP)
4231 .Case("r14", ARM::LR)
4232 .Case("r15", ARM::PC)
4233 .Case("ip", ARM::R12)
4234 // Additional register name aliases for 'gas' compatibility.
4235 .Case("a1", ARM::R0)
4236 .Case("a2", ARM::R1)
4237 .Case("a3", ARM::R2)
4238 .Case("a4", ARM::R3)
4239 .Case("v1", ARM::R4)
4240 .Case("v2", ARM::R5)
4241 .Case("v3", ARM::R6)
4242 .Case("v4", ARM::R7)
4243 .Case("v5", ARM::R8)
4244 .Case("v6", ARM::R9)
4245 .Case("v7", ARM::R10)
4246 .Case("v8", ARM::R11)
4247 .Case("sb", ARM::R9)
4248 .Case("sl", ARM::R10)
4249 .Case("fp", ARM::R11)
4250 .Default(0);
4251 }
4252 if (!RegNum) {
4253 // Check for aliases registered via .req. Canonicalize to lower case.
4254 // That's more consistent since register names are case insensitive, and
4255 // it's how the original entry was passed in from MC/MCParser/AsmParser.
4256 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
4257 // If no match, return failure.
4258 if (Entry == RegisterReqs.end())
4259 return -1;
4260 Parser.Lex(); // Eat identifier token.
4261 return Entry->getValue();
4262 }
4263
4264 // Some FPUs only have 16 D registers, so D16-D31 are invalid
4265 if (!AllowOutOfBoundReg && !hasD32() && RegNum >= ARM::D16 &&
4266 RegNum <= ARM::D31)
4267 return -1;
4268
4269 Parser.Lex(); // Eat identifier token.
4270
4271 return RegNum;
4272}
4273
4274std::optional<ARM_AM::ShiftOpc> ARMAsmParser::tryParseShiftToken() {
4275 MCAsmParser &Parser = getParser();
4276 const AsmToken &Tok = Parser.getTok();
4277 if (Tok.isNot(AsmToken::Identifier))
4278 return std::nullopt;
4279
4280 std::string lowerCase = Tok.getString().lower();
4282 .Case("asl", ARM_AM::lsl)
4283 .Case("lsl", ARM_AM::lsl)
4284 .Case("lsr", ARM_AM::lsr)
4285 .Case("asr", ARM_AM::asr)
4286 .Case("ror", ARM_AM::ror)
4287 .Case("rrx", ARM_AM::rrx)
4288 .Default(std::nullopt);
4289}
4290
4291// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
4292// If a recoverable error occurs, return 1. If an irrecoverable error
4293// occurs, return -1. An irrecoverable error is one where tokens have been
4294// consumed in the process of trying to parse the shifter (i.e., when it is
4295// indeed a shifter operand, but malformed).
4296int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4297 MCAsmParser &Parser = getParser();
4298 SMLoc S = Parser.getTok().getLoc();
4299
4300 auto ShiftTyOpt = tryParseShiftToken();
4301 if (ShiftTyOpt == std::nullopt)
4302 return 1;
4303 auto ShiftTy = ShiftTyOpt.value();
4304
4305 Parser.Lex(); // Eat the operator.
4306
4307 // The source register for the shift has already been added to the
4308 // operand list, so we need to pop it off and combine it into the shifted
4309 // register operand instead.
4310 std::unique_ptr<ARMOperand> PrevOp(
4311 (ARMOperand *)Operands.pop_back_val().release());
4312 if (!PrevOp->isReg())
4313 return Error(PrevOp->getStartLoc(), "shift must be of a register");
4314 int SrcReg = PrevOp->getReg();
4315
4316 SMLoc EndLoc;
4317 int64_t Imm = 0;
4318 int ShiftReg = 0;
4319 if (ShiftTy == ARM_AM::rrx) {
4320 // RRX Doesn't have an explicit shift amount. The encoder expects
4321 // the shift register to be the same as the source register. Seems odd,
4322 // but OK.
4323 ShiftReg = SrcReg;
4324 } else {
4325 // Figure out if this is shifted by a constant or a register (for non-RRX).
4326 if (Parser.getTok().is(AsmToken::Hash) ||
4327 Parser.getTok().is(AsmToken::Dollar)) {
4328 Parser.Lex(); // Eat hash.
4329 SMLoc ImmLoc = Parser.getTok().getLoc();
4330 const MCExpr *ShiftExpr = nullptr;
4331 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
4332 Error(ImmLoc, "invalid immediate shift value");
4333 return -1;
4334 }
4335 // The expression must be evaluatable as an immediate.
4336 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4337 if (!CE) {
4338 Error(ImmLoc, "invalid immediate shift value");
4339 return -1;
4340 }
4341 // Range check the immediate.
4342 // lsl, ror: 0 <= imm <= 31
4343 // lsr, asr: 0 <= imm <= 32
4344 Imm = CE->getValue();
4345 if (Imm < 0 ||
4346 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4347 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4348 Error(ImmLoc, "immediate shift value out of range");
4349 return -1;
4350 }
4351 // shift by zero is a nop. Always send it through as lsl.
4352 // ('as' compatibility)
4353 if (Imm == 0)
4354 ShiftTy = ARM_AM::lsl;
4355 } else if (Parser.getTok().is(AsmToken::Identifier)) {
4356 SMLoc L = Parser.getTok().getLoc();
4357 EndLoc = Parser.getTok().getEndLoc();
4358 ShiftReg = tryParseRegister();
4359 if (ShiftReg == -1) {
4360 Error(L, "expected immediate or register in shift operand");
4361 return -1;
4362 }
4363 } else {
4364 Error(Parser.getTok().getLoc(),
4365 "expected immediate or register in shift operand");
4366 return -1;
4367 }
4368 }
4369
4370 if (ShiftReg && ShiftTy != ARM_AM::rrx)
4371 Operands.push_back(ARMOperand::CreateShiftedRegister(
4372 ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc, *this));
4373 else
4374 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4375 S, EndLoc, *this));
4376
4377 return 0;
4378}
4379
4380/// Try to parse a register name. The token must be an Identifier when called.
4381/// If it's a register, an AsmOperand is created. Another AsmOperand is created
4382/// if there is a "writeback". 'true' if it's not a register.
4383///
4384/// TODO this is likely to change to allow different register types and or to
4385/// parse for a specific register type.
4386bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4387 MCAsmParser &Parser = getParser();
4388 SMLoc RegStartLoc = Parser.getTok().getLoc();
4389 SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4390 int RegNo = tryParseRegister();
4391 if (RegNo == -1)
4392 return true;
4393
4394 Operands.push_back(
4395 ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc, *this));
4396
4397 const AsmToken &ExclaimTok = Parser.getTok();
4398 if (ExclaimTok.is(AsmToken::Exclaim)) {
4399 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4400 ExclaimTok.getLoc(), *this));
4401 Parser.Lex(); // Eat exclaim token
4402 return false;
4403 }
4404
4405 // Also check for an index operand. This is only legal for vector registers,
4406 // but that'll get caught OK in operand matching, so we don't need to
4407 // explicitly filter everything else out here.
4408 if (Parser.getTok().is(AsmToken::LBrac)) {
4409 SMLoc SIdx = Parser.getTok().getLoc();
4410 Parser.Lex(); // Eat left bracket token.
4411
4412 const MCExpr *ImmVal;
4413 if (getParser().parseExpression(ImmVal))
4414 return true;
4415 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4416 if (!MCE)
4417 return TokError("immediate value expected for vector index");
4418
4419 if (Parser.getTok().isNot(AsmToken::RBrac))
4420 return Error(Parser.getTok().getLoc(), "']' expected");
4421
4422 SMLoc E = Parser.getTok().getEndLoc();
4423 Parser.Lex(); // Eat right bracket token.
4424
4425 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), SIdx, E,
4426 getContext(), *this));
4427 }
4428
4429 return false;
4430}
4431
4432/// MatchCoprocessorOperandName - Try to parse an coprocessor related
4433/// instruction with a symbolic operand name.
4434/// We accept "crN" syntax for GAS compatibility.
4435/// <operand-name> ::= <prefix><number>
4436/// If CoprocOp is 'c', then:
4437/// <prefix> ::= c | cr
4438/// If CoprocOp is 'p', then :
4439/// <prefix> ::= p
4440/// <number> ::= integer in range [0, 15]
4441static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4442 // Use the same layout as the tablegen'erated register name matcher. Ugly,
4443 // but efficient.
4444 if (Name.size() < 2 || Name[0] != CoprocOp)
4445 return -1;
4446 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4447
4448 switch (Name.size()) {
4449 default: return -1;
4450 case 1:
4451 switch (Name[0]) {
4452 default: return -1;
4453 case '0': return 0;
4454 case '1': return 1;
4455 case '2': return 2;
4456 case '3': return 3;
4457 case '4': return 4;
4458 case '5': return 5;
4459 case '6': return 6;
4460 case '7': return 7;
4461 case '8': return 8;
4462 case '9': return 9;
4463 }
4464 case 2:
4465 if (Name[0] != '1')
4466 return -1;
4467 switch (Name[1]) {
4468 default: return -1;
4469 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4470 // However, old cores (v5/v6) did use them in that way.
4471 case '0': return 10;
4472 case '1': return 11;
4473 case '2': return 12;
4474 case '3': return 13;
4475 case '4': return 14;
4476 case '5': return 15;
4477 }
4478 }
4479}
4480
4481/// parseITCondCode - Try to parse a condition code for an IT instruction.
4482ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4483 MCAsmParser &Parser = getParser();
4484 SMLoc S = Parser.getTok().getLoc();
4485 const AsmToken &Tok = Parser.getTok();
4486 if (!Tok.is(AsmToken::Identifier))
4487 return ParseStatus::NoMatch;
4488 unsigned CC = ARMCondCodeFromString(Tok.getString());
4489 if (CC == ~0U)
4490 return ParseStatus::NoMatch;
4491 Parser.Lex(); // Eat the token.
4492
4493 Operands.push_back(
4494 ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S, *this));
4495
4496 return ParseStatus::Success;
4497}
4498
4499/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4500/// token must be an Identifier when called, and if it is a coprocessor
4501/// number, the token is eaten and the operand is added to the operand list.
4502ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4503 MCAsmParser &Parser = getParser();
4504 SMLoc S = Parser.getTok().getLoc();
4505 const AsmToken &Tok = Parser.getTok();
4506 if (Tok.isNot(AsmToken::Identifier))
4507 return ParseStatus::NoMatch;
4508
4509 int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4510 if (Num == -1)
4511 return ParseStatus::NoMatch;
4512 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4513 return ParseStatus::NoMatch;
4514
4515 Parser.Lex(); // Eat identifier token.
4516 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S, *this));
4517 return ParseStatus::Success;
4518}
4519
4520/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4521/// token must be an Identifier when called, and if it is a coprocessor
4522/// number, the token is eaten and the operand is added to the operand list.
4523ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4524 MCAsmParser &Parser = getParser();
4525 SMLoc S = Parser.getTok().getLoc();
4526 const AsmToken &Tok = Parser.getTok();
4527 if (Tok.isNot(AsmToken::Identifier))
4528 return ParseStatus::NoMatch;
4529
4530 int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4531 if (Reg == -1)
4532 return ParseStatus::NoMatch;
4533
4534 Parser.Lex(); // Eat identifier token.
4535 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S, *this));
4536 return ParseStatus::Success;
4537}
4538
4539/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4540/// coproc_option : '{' imm0_255 '}'
4541ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4542 MCAsmParser &Parser = getParser();
4543 SMLoc S = Parser.getTok().getLoc();
4544
4545 // If this isn't a '{', this isn't a coprocessor immediate operand.
4546 if (Parser.getTok().isNot(AsmToken::LCurly))
4547 return ParseStatus::NoMatch;
4548 Parser.Lex(); // Eat the '{'
4549
4550 const MCExpr *Expr;
4551 SMLoc Loc = Parser.getTok().getLoc();
4552 if (getParser().parseExpression(Expr))
4553 return Error(Loc, "illegal expression");
4554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4555 if (!CE || CE->getValue() < 0 || CE->getValue() > 255)
4556 return Error(Loc,
4557 "coprocessor option must be an immediate in range [0, 255]");
4558 int Val = CE->getValue();
4559
4560 // Check for and consume the closing '}'
4561 if (Parser.getTok().isNot(AsmToken::RCurly))
4562 return ParseStatus::Failure;
4563 SMLoc E = Parser.getTok().getEndLoc();
4564 Parser.Lex(); // Eat the '}'
4565
4566 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E, *this));
4567 return ParseStatus::Success;
4568}
4569
4570// For register list parsing, we need to map from raw GPR register numbering
4571// to the enumeration values. The enumeration values aren't sorted by
4572// register number due to our using "sp", "lr" and "pc" as canonical names.
4573static unsigned getNextRegister(unsigned Reg) {
4574 // If this is a GPR, we need to do it manually, otherwise we can rely
4575 // on the sort ordering of the enumeration since the other reg-classes
4576 // are sane.
4577 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4578 return Reg + 1;
4579 switch(Reg) {
4580 default: llvm_unreachable("Invalid GPR number!");
4581 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4582 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4583 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
4584 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
4585 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
4586 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4587 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4588 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
4589 }
4590}
4591
4592// Insert an <Encoding, Register> pair in an ordered vector. Return true on
4593// success, or false, if duplicate encoding found.
4594static bool
4595insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4596 unsigned Enc, unsigned Reg) {
4597 Regs.emplace_back(Enc, Reg);
4598 for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4599 if (J->first == Enc) {
4600 Regs.erase(J.base());
4601 return false;
4602 }
4603 if (J->first < Enc)
4604 break;
4605 std::swap(*I, *J);
4606 }
4607 return true;
4608}
4609
4610/// Parse a register list.
4611bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
4612 bool AllowRAAC, bool AllowOutOfBoundReg) {
4613 MCAsmParser &Parser = getParser();
4614 if (Parser.getTok().isNot(AsmToken::LCurly))
4615 return TokError("Token is not a Left Curly Brace");
4616 SMLoc S = Parser.getTok().getLoc();
4617 Parser.Lex(); // Eat '{' token.
4618 SMLoc RegLoc = Parser.getTok().getLoc();
4619
4620 // Check the first register in the list to see what register class
4621 // this is a list of.
4622 int Reg = tryParseRegister();
4623 if (Reg == -1)
4624 return Error(RegLoc, "register expected");
4625 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4626 return Error(RegLoc, "pseudo-register not allowed");
4627 // The reglist instructions have at most 16 registers, so reserve
4628 // space for that many.
4629 int EReg = 0;
4631
4632 // Allow Q regs and just interpret them as the two D sub-registers.
4633 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4634 Reg = getDRegFromQReg(Reg);
4635 EReg = MRI->getEncodingValue(Reg);
4636 Registers.emplace_back(EReg, Reg);
4637 ++Reg;
4638 }
4639 const MCRegisterClass *RC;
4640 if (Reg == ARM::RA_AUTH_CODE ||
4641 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4642 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4643 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4644 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4645 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4646 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4647 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4648 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4649 else
4650 return Error(RegLoc, "invalid register in register list");
4651
4652 // Store the register.
4653 EReg = MRI->getEncodingValue(Reg);
4654 Registers.emplace_back(EReg, Reg);
4655
4656 // This starts immediately after the first register token in the list,
4657 // so we can see either a comma or a minus (range separator) as a legal
4658 // next token.
4659 while (Parser.getTok().is(AsmToken::Comma) ||
4660 Parser.getTok().is(AsmToken::Minus)) {
4661 if (Parser.getTok().is(AsmToken::Minus)) {
4662 if (Reg == ARM::RA_AUTH_CODE)
4663 return Error(RegLoc, "pseudo-register not allowed");
4664 Parser.Lex(); // Eat the minus.
4665 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4666 int EndReg = tryParseRegister(AllowOutOfBoundReg);
4667 if (EndReg == -1)
4668 return Error(AfterMinusLoc, "register expected");
4669 if (EndReg == ARM::RA_AUTH_CODE)
4670 return Error(AfterMinusLoc, "pseudo-register not allowed");
4671 // Allow Q regs and just interpret them as the two D sub-registers.
4672 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4673 EndReg = getDRegFromQReg(EndReg) + 1;
4674 // If the register is the same as the start reg, there's nothing
4675 // more to do.
4676 if (Reg == EndReg)
4677 continue;
4678 // The register must be in the same register class as the first.
4679 if (!RC->contains(Reg))
4680 return Error(AfterMinusLoc, "invalid register in register list");
4681 // Ranges must go from low to high.
4682 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4683 return Error(AfterMinusLoc, "bad range in register list");
4684
4685 // Add all the registers in the range to the register list.
4686 while (Reg != EndReg) {
4688 EReg = MRI->getEncodingValue(Reg);
4689 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4690 Warning(AfterMinusLoc, StringRef("duplicated register (") +
4692 ") in register list");
4693 }
4694 }
4695 continue;
4696 }
4697 Parser.Lex(); // Eat the comma.
4698 RegLoc = Parser.getTok().getLoc();
4699 int OldReg = Reg;
4700 const AsmToken RegTok = Parser.getTok();
4701 Reg = tryParseRegister(AllowOutOfBoundReg);
4702 if (Reg == -1)
4703 return Error(RegLoc, "register expected");
4704 if (!AllowRAAC && Reg == ARM::RA_AUTH_CODE)
4705 return Error(RegLoc, "pseudo-register not allowed");
4706 // Allow Q regs and just interpret them as the two D sub-registers.
4707 bool isQReg = false;
4708 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4709 Reg = getDRegFromQReg(Reg);
4710 isQReg = true;
4711 }
4712 if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) &&
4713 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4714 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4715 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4716 // subset of GPRRegClassId except it contains APSR as well.
4717 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4718 }
4719 if (Reg == ARM::VPR &&
4720 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4721 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4722 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4723 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4724 EReg = MRI->getEncodingValue(Reg);
4725 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4726 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4727 ") in register list");
4728 }
4729 continue;
4730 }
4731 // The register must be in the same register class as the first.
4732 if ((Reg == ARM::RA_AUTH_CODE &&
4733 RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) ||
4734 (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg)))
4735 return Error(RegLoc, "invalid register in register list");
4736 // In most cases, the list must be monotonically increasing. An
4737 // exception is CLRM, which is order-independent anyway, so
4738 // there's no potential for confusion if you write clrm {r2,r1}
4739 // instead of clrm {r1,r2}.
4740 if (EnforceOrder &&
4741 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4742 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))