LLVM 19.0.0git
GCNIterativeScheduler.cpp
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1//===- GCNIterativeScheduler.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the class GCNIterativeScheduler.
11///
12//===----------------------------------------------------------------------===//
13
15#include "GCNSchedStrategy.h"
17
18using namespace llvm;
19
20#define DEBUG_TYPE "machine-scheduler"
21
22namespace llvm {
23
24std::vector<const SUnit *> makeMinRegSchedule(ArrayRef<const SUnit *> TopRoots,
25 const ScheduleDAG &DAG);
26
27 std::vector<const SUnit*> makeGCNILPScheduler(ArrayRef<const SUnit*> BotRoots,
28 const ScheduleDAG &DAG);
29}
30
31// shim accessors for different order containers
33 return MI;
34}
35static inline MachineInstr *getMachineInstr(const SUnit *SU) {
36 return SU->getInstr();
37}
38static inline MachineInstr *getMachineInstr(const SUnit &SU) {
39 return SU.getInstr();
40}
41
42#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
47 const LiveIntervals *LIS,
48 unsigned MaxInstNum =
49 std::numeric_limits<unsigned>::max()) {
50 auto BB = Begin->getParent();
51 OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' '
52 << BB->getName() << ":\n";
53 auto I = Begin;
54 MaxInstNum = std::max(MaxInstNum, 1u);
55 for (; I != End && MaxInstNum; ++I, --MaxInstNum) {
56 if (!I->isDebugInstr() && LIS)
57 OS << LIS->getInstructionIndex(*I);
58 OS << '\t' << *I;
59 }
60 if (I != End) {
61 OS << "\t...\n";
62 I = std::prev(End);
63 if (!I->isDebugInstr() && LIS)
64 OS << LIS->getInstructionIndex(*I);
65 OS << '\t' << *I;
66 }
67 if (End != BB->end()) { // print boundary inst if present
68 OS << "----\n";
69 if (LIS) OS << LIS->getInstructionIndex(*End) << '\t';
70 OS << *End;
71 }
72}
73
78 const LiveIntervals *LIS) {
79 const auto BB = Begin->getParent();
80 const auto &MRI = BB->getParent()->getRegInfo();
81
82 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS);
83 OS << "LIn RP: " << print(getRegPressure(MRI, LiveIns));
84
85 const auto BottomMI = End == BB->end() ? std::prev(End) : End;
86 const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS);
87 OS << "LOt RP: " << print(getRegPressure(MRI, LiveOuts));
88}
89
92 const auto &ST = MF.getSubtarget<GCNSubtarget>();
93 for (const auto R : Regions) {
94 OS << "Region to schedule ";
95 printRegion(OS, R->Begin, R->End, LIS, 1);
96 printLivenessInfo(OS, R->Begin, R->End, LIS);
97 OS << "Max RP: " << print(R->MaxPressure, &ST);
98 }
99}
100
103 const Region *R,
104 const GCNRegPressure &RP) const {
105 OS << "\nAfter scheduling ";
106 printRegion(OS, R->Begin, R->End, LIS);
107 printSchedRP(OS, R->MaxPressure, RP);
108 OS << '\n';
109}
110
113 const GCNRegPressure &Before,
114 const GCNRegPressure &After) const {
115 const auto &ST = MF.getSubtarget<GCNSubtarget>();
116 OS << "RP before: " << print(Before, &ST)
117 << "RP after: " << print(After, &ST);
118}
119#endif
120
121// DAG builder helper
125
126 SmallVector<SUnit*, 8> BotRoots;
127public:
129 : Sch(_Sch) {
130 auto BB = R.Begin->getParent();
131 Sch.BaseClass::startBlock(BB);
132 Sch.BaseClass::enterRegion(BB, R.Begin, R.End, R.NumRegionInstrs);
133
134 Sch.buildSchedGraph(Sch.AA, nullptr, nullptr, nullptr,
135 /*TrackLaneMask*/true);
137 Sch.findRootsAndBiasEdges(TopRoots, BotRoots);
138 }
139
141 Sch.BaseClass::exitRegion();
142 Sch.BaseClass::finishBlock();
143 }
144
146 return TopRoots;
147 }
149 return BotRoots;
150 }
151};
152
155 Region &Rgn;
156 std::unique_ptr<MachineSchedStrategy> SaveSchedImpl;
157 GCNRegPressure SaveMaxRP;
158
159public:
161 MachineSchedStrategy &OverrideStrategy,
163 : Sch(_Sch)
164 , Rgn(R)
165 , SaveSchedImpl(std::move(_Sch.SchedImpl))
166 , SaveMaxRP(R.MaxPressure) {
167 Sch.SchedImpl.reset(&OverrideStrategy);
168 auto BB = R.Begin->getParent();
169 Sch.BaseClass::startBlock(BB);
170 Sch.BaseClass::enterRegion(BB, R.Begin, R.End, R.NumRegionInstrs);
171 }
172
174 Sch.BaseClass::exitRegion();
175 Sch.BaseClass::finishBlock();
176 Sch.SchedImpl.release();
177 Sch.SchedImpl = std::move(SaveSchedImpl);
178 }
179
180 void schedule() {
181 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End);
182 LLVM_DEBUG(dbgs() << "\nScheduling ";
183 printRegion(dbgs(), Rgn.Begin, Rgn.End, Sch.LIS, 2));
184 Sch.BaseClass::schedule();
185
186 // Unfortunately placeDebugValues incorrectly modifies RegionEnd, restore
187 Sch.RegionEnd = Rgn.End;
188 //assert(Rgn.End == Sch.RegionEnd);
189 Rgn.Begin = Sch.RegionBegin;
190 Rgn.MaxPressure.clear();
191 }
192
194 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End);
195 // DAG SUnits are stored using original region's order
196 // so just use SUnits as the restoring schedule
197 Sch.scheduleRegion(Rgn, Sch.SUnits, SaveMaxRP);
198 }
199};
200
201namespace {
202
203// just a stub to make base class happy
204class SchedStrategyStub : public MachineSchedStrategy {
205public:
206 bool shouldTrackPressure() const override { return false; }
207 bool shouldTrackLaneMasks() const override { return false; }
208 void initialize(ScheduleDAGMI *DAG) override {}
209 SUnit *pickNode(bool &IsTopNode) override { return nullptr; }
210 void schedNode(SUnit *SU, bool IsTopNode) override {}
211 void releaseTopNode(SUnit *SU) override {}
212 void releaseBottomNode(SUnit *SU) override {}
213};
214
215} // end anonymous namespace
216
218 StrategyKind S)
219 : BaseClass(C, std::make_unique<SchedStrategyStub>())
220 , Context(C)
221 , Strategy(S)
222 , UPTracker(*LIS) {
223}
224
225// returns max pressure for a region
229 const {
230 // For the purpose of pressure tracking bottom inst of the region should
231 // be also processed. End is either BB end, BB terminator inst or sched
232 // boundary inst.
233 auto const BBEnd = Begin->getParent()->end();
234 auto const BottomMI = End == BBEnd ? std::prev(End) : End;
235
236 // scheduleRegions walks bottom to top, so its likely we just get next
237 // instruction to track
238 auto AfterBottomMI = std::next(BottomMI);
239 if (AfterBottomMI == BBEnd ||
240 &*AfterBottomMI != UPTracker.getLastTrackedMI()) {
241 UPTracker.reset(*BottomMI);
242 } else {
244 }
245
246 for (auto I = BottomMI; I != Begin; --I)
248
249 UPTracker.recede(*Begin);
250
252 (dbgs() << "Tracked region ",
253 printRegion(dbgs(), Begin, End, LIS), false));
255}
256
257// returns max pressure for a tentative schedule
258template <typename Range> GCNRegPressure
260 Range &&Schedule) const {
261 auto const BBEnd = R.Begin->getParent()->end();
263 if (R.End != BBEnd) {
264 // R.End points to the boundary instruction but the
265 // schedule doesn't include it
266 RPTracker.reset(*R.End);
267 RPTracker.recede(*R.End);
268 } else {
269 // R.End doesn't point to the boundary instruction
270 RPTracker.reset(*std::prev(BBEnd));
271 }
272 for (auto I = Schedule.end(), B = Schedule.begin(); I != B;) {
274 }
275 return RPTracker.getMaxPressureAndReset();
276}
277
281 unsigned NumRegionInstrs) {
283 if (NumRegionInstrs > 2) {
284 Regions.push_back(
285 new (Alloc.Allocate())
286 Region { Begin, End, NumRegionInstrs,
287 getRegionPressure(Begin, End), nullptr });
288 }
289}
290
292 // do nothing
294 if (!Regions.empty() && Regions.back()->Begin == RegionBegin) {
295 dbgs() << "Max RP: "
296 << print(Regions.back()->MaxPressure,
297 &MF.getSubtarget<GCNSubtarget>());
298 } dbgs()
299 << '\n';);
300}
301
303 if (Regions.empty())
304 return;
305 switch (Strategy) {
306 case SCHEDULE_MINREGONLY: scheduleMinReg(); break;
307 case SCHEDULE_MINREGFORCED: scheduleMinReg(true); break;
309 case SCHEDULE_ILP: scheduleILP(false); break;
310 }
311}
312
313// Detach schedule from SUnits and interleave it with debug values.
314// Returned schedule becomes independent of DAG state.
315std::vector<MachineInstr*>
317 std::vector<MachineInstr*> Res;
318 Res.reserve(Schedule.size() * 2);
319
320 if (FirstDbgValue)
321 Res.push_back(FirstDbgValue);
322
323 const auto DbgB = DbgValues.begin(), DbgE = DbgValues.end();
324 for (const auto *SU : Schedule) {
325 Res.push_back(SU->getInstr());
326 const auto &D = std::find_if(DbgB, DbgE, [SU](decltype(*DbgB) &P) {
327 return P.second == SU->getInstr();
328 });
329 if (D != DbgE)
330 Res.push_back(D->first);
331 }
332 return Res;
333}
334
336 ScheduleRef Schedule,
337 const GCNRegPressure &MaxRP) {
338 R.BestSchedule.reset(
339 new TentativeSchedule{ detachSchedule(Schedule), MaxRP });
340}
341
343 assert(R.BestSchedule.get() && "No schedule specified");
344 scheduleRegion(R, R.BestSchedule->Schedule, R.BestSchedule->MaxPressure);
345 R.BestSchedule.reset();
346}
347
348// minimal required region scheduler, works for ranges of SUnits*,
349// SUnits or MachineIntrs*
350template <typename Range>
352 const GCNRegPressure &MaxRP) {
353 assert(RegionBegin == R.Begin && RegionEnd == R.End);
354 assert(LIS != nullptr);
355#ifndef NDEBUG
356 const auto SchedMaxRP = getSchedulePressure(R, Schedule);
357#endif
358 auto BB = R.Begin->getParent();
359 auto Top = R.Begin;
360 for (const auto &I : Schedule) {
361 auto MI = getMachineInstr(I);
362 if (MI != &*Top) {
363 BB->remove(MI);
364 BB->insert(Top, MI);
365 if (!MI->isDebugInstr())
366 LIS->handleMove(*MI, true);
367 }
368 if (!MI->isDebugInstr()) {
369 // Reset read - undef flags and update them later.
370 for (auto &Op : MI->all_defs())
371 Op.setIsUndef(false);
372
373 RegisterOperands RegOpers;
374 RegOpers.collect(*MI, *TRI, MRI, /*ShouldTrackLaneMasks*/true,
375 /*IgnoreDead*/false);
376 // Adjust liveness and add missing dead+read-undef flags.
377 auto SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
378 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
379 }
380 Top = std::next(MI->getIterator());
381 }
382 RegionBegin = getMachineInstr(Schedule.front());
383
384 // Schedule consisting of MachineInstr* is considered 'detached'
385 // and already interleaved with debug values
386 if (!std::is_same<decltype(*Schedule.begin()), MachineInstr*>::value) {
388 // Unfortunately placeDebugValues incorrectly modifies RegionEnd, restore
389 // assert(R.End == RegionEnd);
390 RegionEnd = R.End;
391 }
392
393 R.Begin = RegionBegin;
394 R.MaxPressure = MaxRP;
395
396#ifndef NDEBUG
397 const auto RegionMaxRP = getRegionPressure(R);
398 const auto &ST = MF.getSubtarget<GCNSubtarget>();
399#endif
400 assert(
401 (SchedMaxRP == RegionMaxRP && (MaxRP.empty() || SchedMaxRP == MaxRP)) ||
402 (dbgs() << "Max RP mismatch!!!\n"
403 "RP for schedule (calculated): "
404 << print(SchedMaxRP, &ST)
405 << "RP for schedule (reported): " << print(MaxRP, &ST)
406 << "RP after scheduling: " << print(RegionMaxRP, &ST),
407 false));
408}
409
410// Sort recorded regions by pressure - highest at the front
412 const auto &ST = MF.getSubtarget<GCNSubtarget>();
413 llvm::sort(Regions, [&ST, TargetOcc](const Region *R1, const Region *R2) {
414 return R2->MaxPressure.less(ST, R1->MaxPressure, TargetOcc);
415 });
416}
417
418///////////////////////////////////////////////////////////////////////////////
419// Legacy MaxOccupancy Strategy
420
421// Tries to increase occupancy applying minreg scheduler for a sequence of
422// most demanding regions. Obtained schedules are saved as BestSchedule for a
423// region.
424// TargetOcc is the best achievable occupancy for a kernel.
425// Returns better occupancy on success or current occupancy on fail.
426// BestSchedules aren't deleted on fail.
428 // TODO: assert Regions are sorted descending by pressure
429 const auto &ST = MF.getSubtarget<GCNSubtarget>();
430 const auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
431 LLVM_DEBUG(dbgs() << "Trying to improve occupancy, target = " << TargetOcc
432 << ", current = " << Occ << '\n');
433
434 auto NewOcc = TargetOcc;
435 for (auto *R : Regions) {
436 if (R->MaxPressure.getOccupancy(ST) >= NewOcc)
437 break;
438
439 LLVM_DEBUG(printRegion(dbgs(), R->Begin, R->End, LIS, 3);
440 printLivenessInfo(dbgs(), R->Begin, R->End, LIS));
441
442 BuildDAG DAG(*R, *this);
443 const auto MinSchedule = makeMinRegSchedule(DAG.getTopRoots(), *this);
444 const auto MaxRP = getSchedulePressure(*R, MinSchedule);
445 LLVM_DEBUG(dbgs() << "Occupancy improvement attempt:\n";
446 printSchedRP(dbgs(), R->MaxPressure, MaxRP));
447
448 NewOcc = std::min(NewOcc, MaxRP.getOccupancy(ST));
449 if (NewOcc <= Occ)
450 break;
451
452 setBestSchedule(*R, MinSchedule, MaxRP);
453 }
454 LLVM_DEBUG(dbgs() << "New occupancy = " << NewOcc
455 << ", prev occupancy = " << Occ << '\n');
456 if (NewOcc > Occ) {
458 MFI->increaseOccupancy(MF, NewOcc);
459 }
460
461 return std::max(NewOcc, Occ);
462}
463
465 bool TryMaximizeOccupancy) {
466 const auto &ST = MF.getSubtarget<GCNSubtarget>();
468 auto TgtOcc = MFI->getMinAllowedOccupancy();
469
470 sortRegionsByPressure(TgtOcc);
471 auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
472
473 if (TryMaximizeOccupancy && Occ < TgtOcc)
474 Occ = tryMaximizeOccupancy(TgtOcc);
475
476 // This is really weird but for some magic scheduling regions twice
477 // gives performance improvement
478 const int NumPasses = Occ < TgtOcc ? 2 : 1;
479
480 TgtOcc = std::min(Occ, TgtOcc);
481 LLVM_DEBUG(dbgs() << "Scheduling using default scheduler, "
482 "target occupancy = "
483 << TgtOcc << '\n');
485 unsigned FinalOccupancy = std::min(Occ, MFI->getOccupancy());
486
487 for (int I = 0; I < NumPasses; ++I) {
488 // running first pass with TargetOccupancy = 0 mimics previous scheduling
489 // approach and is a performance magic
490 LStrgy.setTargetOccupancy(I == 0 ? 0 : TgtOcc);
491 for (auto *R : Regions) {
492 OverrideLegacyStrategy Ovr(*R, LStrgy, *this);
493
494 Ovr.schedule();
495 const auto RP = getRegionPressure(*R);
496 LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP));
497
498 if (RP.getOccupancy(ST) < TgtOcc) {
499 LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc);
500 if (R->BestSchedule.get() &&
501 R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) {
502 LLVM_DEBUG(dbgs() << ", scheduling minimal register\n");
503 scheduleBest(*R);
504 } else {
505 LLVM_DEBUG(dbgs() << ", restoring\n");
506 Ovr.restoreOrder();
507 assert(R->MaxPressure.getOccupancy(ST) >= TgtOcc);
508 }
509 }
510 FinalOccupancy = std::min(FinalOccupancy, RP.getOccupancy(ST));
511 }
512 }
513 MFI->limitOccupancy(FinalOccupancy);
514}
515
516///////////////////////////////////////////////////////////////////////////////
517// Minimal Register Strategy
518
520 const auto &ST = MF.getSubtarget<GCNSubtarget>();
522 const auto TgtOcc = MFI->getOccupancy();
523 sortRegionsByPressure(TgtOcc);
524
525 auto MaxPressure = Regions.front()->MaxPressure;
526 for (auto *R : Regions) {
527 if (!force && R->MaxPressure.less(ST, MaxPressure, TgtOcc))
528 break;
529
530 BuildDAG DAG(*R, *this);
531 const auto MinSchedule = makeMinRegSchedule(DAG.getTopRoots(), *this);
532
533 const auto RP = getSchedulePressure(*R, MinSchedule);
534 LLVM_DEBUG(if (R->MaxPressure.less(ST, RP, TgtOcc)) {
535 dbgs() << "\nWarning: Pressure becomes worse after minreg!";
536 printSchedRP(dbgs(), R->MaxPressure, RP);
537 });
538
539 if (!force && MaxPressure.less(ST, RP, TgtOcc))
540 break;
541
542 scheduleRegion(*R, MinSchedule, RP);
544
545 MaxPressure = RP;
546 }
547}
548
549///////////////////////////////////////////////////////////////////////////////
550// ILP scheduler port
551
553 bool TryMaximizeOccupancy) {
554 const auto &ST = MF.getSubtarget<GCNSubtarget>();
556 auto TgtOcc = MFI->getMinAllowedOccupancy();
557
558 sortRegionsByPressure(TgtOcc);
559 auto Occ = Regions.front()->MaxPressure.getOccupancy(ST);
560
561 if (TryMaximizeOccupancy && Occ < TgtOcc)
562 Occ = tryMaximizeOccupancy(TgtOcc);
563
564 TgtOcc = std::min(Occ, TgtOcc);
565 LLVM_DEBUG(dbgs() << "Scheduling using default scheduler, "
566 "target occupancy = "
567 << TgtOcc << '\n');
568
569 unsigned FinalOccupancy = std::min(Occ, MFI->getOccupancy());
570 for (auto *R : Regions) {
571 BuildDAG DAG(*R, *this);
572 const auto ILPSchedule = makeGCNILPScheduler(DAG.getBottomRoots(), *this);
573
574 const auto RP = getSchedulePressure(*R, ILPSchedule);
575 LLVM_DEBUG(printSchedRP(dbgs(), R->MaxPressure, RP));
576
577 if (RP.getOccupancy(ST) < TgtOcc) {
578 LLVM_DEBUG(dbgs() << "Didn't fit into target occupancy O" << TgtOcc);
579 if (R->BestSchedule.get() &&
580 R->BestSchedule->MaxPressure.getOccupancy(ST) >= TgtOcc) {
581 LLVM_DEBUG(dbgs() << ", scheduling minimal register\n");
582 scheduleBest(*R);
583 }
584 } else {
585 scheduleRegion(*R, ILPSchedule, RP);
587 FinalOccupancy = std::min(FinalOccupancy, RP.getOccupancy(ST));
588 }
589 }
590 MFI->limitOccupancy(FinalOccupancy);
591}
unsigned const MachineRegisterInfo * MRI
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:529
Given that RA is a live value
#define LLVM_DEBUG(X)
Definition: Debug.h:101
bool End
Definition: ELF_riscv.cpp:480
static LLVM_DUMP_METHOD void printLivenessInfo(raw_ostream &OS, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, const LiveIntervals *LIS)
static MachineInstr * getMachineInstr(MachineInstr *MI)
static LLVM_DUMP_METHOD void printRegion(raw_ostream &OS, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, const LiveIntervals *LIS, unsigned MaxInstNum=std::numeric_limits< unsigned >::max())
This file defines the class GCNIterativeScheduler, which uses an iterative approach to find a best sc...
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define R2(n)
LLVMContext & Context
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)
Initialize the set of available library functions based on the specified target triple.
ArrayRef< const SUnit * > getTopRoots() const
BuildDAG(const Region &R, GCNIterativeScheduler &_Sch)
OverrideLegacyStrategy(Region &R, MachineSchedStrategy &OverrideStrategy, GCNIterativeScheduler &_Sch)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
This class represents an Operation in the Expression.
SpecificBumpPtrAllocator< Region > Alloc
void printSchedRP(raw_ostream &OS, const GCNRegPressure &Before, const GCNRegPressure &After) const
void enterRegion(MachineBasicBlock *BB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned RegionInstrs) override
Implement the ScheduleDAGInstrs interface for handling the next scheduling region.
void sortRegionsByPressure(unsigned TargetOcc)
std::vector< Region * > Regions
void scheduleILP(bool TryMaximizeOccupancy=true)
GCNIterativeScheduler(MachineSchedContext *C, StrategyKind S)
void printSchedResult(raw_ostream &OS, const Region *R, const GCNRegPressure &RP) const
unsigned tryMaximizeOccupancy(unsigned TargetOcc=std::numeric_limits< unsigned >::max())
void printRegions(raw_ostream &OS) const
void setBestSchedule(Region &R, ScheduleRef Schedule, const GCNRegPressure &MaxRP=GCNRegPressure())
void finalizeSchedule() override
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
void scheduleLegacyMaxOccupancy(bool TryMaximizeOccupancy=true)
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
GCNRegPressure getSchedulePressure(const Region &R, Range &&Schedule) const
void scheduleMinReg(bool force=false)
GCNRegPressure getRegionPressure(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End) const
void scheduleRegion(Region &R, Range &&Schedule, const GCNRegPressure &MaxRP=GCNRegPressure())
std::vector< MachineInstr * > detachSchedule(ScheduleRef Schedule) const
The goal of this scheduling strategy is to maximize kernel occupancy (i.e.
const MachineInstr * getLastTrackedMI() const
void setTargetOccupancy(unsigned Occ)
GCNRegPressure getMaxPressureAndReset()
void recede(const MachineInstr &MI)
void reset(const MachineRegisterInfo &MRI_, const LiveRegSet &LiveRegs_)
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
List of registers defined and used by a machine instruction.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
MachineBasicBlock * BB
The block in which to insert instructions.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DbgValueVector DbgValues
Remember instruction that precedes DBG_VALUE.
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
void buildSchedGraph(AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
const MachineFrameInfo & MFI
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
Implement the ScheduleDAGInstrs interface for handling the next scheduling region.
RegPressureTracker RPTracker
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
std::unique_ptr< MachineSchedStrategy > SchedImpl
void findRootsAndBiasEdges(SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)
LiveIntervals * LIS
void placeDebugValues()
Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
void InitDAGTopologicalSorting()
Creates the initial topological ordering from the DAG to be scheduled.
MachineRegisterInfo & MRI
Virtual/real register map.
Definition: ScheduleDAG.h:560
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:561
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:558
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:559
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:240
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1656
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
std::vector< const SUnit * > makeGCNILPScheduler(ArrayRef< const SUnit * > BotRoots, const ScheduleDAG &DAG)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
std::vector< const SUnit * > makeMinRegSchedule(ArrayRef< const SUnit * > TopRoots, const ScheduleDAG &DAG)
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
const MachineBasicBlock::iterator End
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...