Go to the documentation of this file.
32 cl::desc(
"Threshold for triggering vextract replacement"));
46 return "Hexagon optimize vextract";
65 "Hexagon optimize vextract",
false,
false)
67 unsigned HexagonVExtract::genElemLoad(
MachineInstr *ExtI,
unsigned BaseR,
73 Register ExtIdxR = ExtI->getOperand(2).getReg();
74 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
79 if (DI->
getOpcode() == Hexagon::A2_tfrsi) {
81 V &= (HST->getVectorLength()-1) & -4u;
83 BuildMI(ExtB, ExtI,
DL, HII->get(Hexagon::L2_loadri_io), ElemR)
91 BuildMI(ExtB, ExtI,
DL, HII->get(Hexagon::A2_andir), IdxR)
92 .
add(ExtI->getOperand(2))
94 BuildMI(ExtB, ExtI,
DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
104 const auto &HRI = *HST->getRegisterInfo();
109 std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap;
111 bool Changed =
false;
115 unsigned Opc =
MI.getOpcode();
116 if (Opc != Hexagon::V6_extractw)
119 VExtractMap[VecR].push_back(&
MI);
126 unsigned FiOpc = AR != 0 ? Hexagon::PS_fia : Hexagon::PS_fi;
127 auto MIB =
BuildMI(
BB, At, dl, HII->get(FiOpc), AddrR);
130 MIB.addFrameIndex(FI).addImm(
Offset);
134 for (
auto &
P : VExtractMap) {
135 unsigned VecR =
P.first;
140 Align Alignment = HRI.getSpillAlign(VecRC);
141 MaxAlign =
max(MaxAlign, Alignment);
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
153 ? Hexagon::V6_vS32b_ai
154 : Hexagon::PS_vstorerw_ai;
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
171 SR == 0 ? 0 : VecSize/2);
173 unsigned ElemR = genElemLoad(ExtI, BaseR,
MRI);
181 if (AR && MaxAlign) {
186 if (*MaxAlign >
Op.getImm())
187 Op.setImm(MaxAlign->value());
194 return new HexagonVExtract();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Hexagon target-specific information for each MachineFunction.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineOperand & getOperand(unsigned i) const
FunctionPass * createHexagonVExtract()
Represent the analysis usage information of a pass.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
MachineOperand class - Representation of each machine instruction operand.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const HexagonInstrInfo * getInstrInfo() const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
StringRef - Represent a constant reference to a string, i.e.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineBasicBlock * getParent() const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Align max(MaybeAlign Lhs, Align Rhs)
FunctionPass class - This class is used to implement most global optimizations.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
void initializeHexagonVExtractPass(PassRegistry &)