LLVM  13.0.0git
LegalizeFloatTypes.cpp
Go to the documentation of this file.
1 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements float type expansion and softening for LegalizeTypes.
10 // Softening is the act of turning a computation in an illegal floating point
11 // type into a computation in an integer type of the same size; also known as
12 // "soft float". For example, turning f32 arithmetic into operations using i32.
13 // The resulting integer value is the same as what you would get by performing
14 // the floating point operation and bitcasting the result to the integer type.
15 // Expansion is the act of changing a computation in an illegal type to be a
16 // computation in two identical registers of a smaller type. For example,
17 // implementing ppcf128 arithmetic in two f64 registers.
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "LegalizeTypes.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "legalize-types"
27 
28 /// GetFPLibCall - Return the right libcall for the given floating point type.
29 /// FIXME: This is a local version of RTLIB::getFPLibCall that should be
30 /// refactored away (see RTLIB::getPOWI for an example).
32  RTLIB::Libcall Call_F32,
33  RTLIB::Libcall Call_F64,
34  RTLIB::Libcall Call_F80,
35  RTLIB::Libcall Call_F128,
36  RTLIB::Libcall Call_PPCF128) {
37  return
38  VT == MVT::f32 ? Call_F32 :
39  VT == MVT::f64 ? Call_F64 :
40  VT == MVT::f80 ? Call_F80 :
41  VT == MVT::f128 ? Call_F128 :
42  VT == MVT::ppcf128 ? Call_PPCF128 :
43  RTLIB::UNKNOWN_LIBCALL;
44 }
45 
46 //===----------------------------------------------------------------------===//
47 // Convert Float Results to Integer
48 //===----------------------------------------------------------------------===//
49 
50 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
51  LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG);
52  dbgs() << "\n");
53  SDValue R = SDValue();
54 
55  switch (N->getOpcode()) {
56  default:
57 #ifndef NDEBUG
58  dbgs() << "SoftenFloatResult #" << ResNo << ": ";
59  N->dump(&DAG); dbgs() << "\n";
60 #endif
61  llvm_unreachable("Do not know how to soften the result of this operator!");
62 
63  case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
64  case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
65  case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
66  case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break;
68  R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
69  case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
71  case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
73  case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
74  case ISD::STRICT_FADD:
75  case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
76  case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break;
77  case ISD::STRICT_FCEIL:
78  case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
79  case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
80  case ISD::STRICT_FCOS:
81  case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break;
82  case ISD::STRICT_FDIV:
83  case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
84  case ISD::STRICT_FEXP:
85  case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break;
86  case ISD::STRICT_FEXP2:
87  case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break;
88  case ISD::STRICT_FFLOOR:
89  case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
90  case ISD::STRICT_FLOG:
91  case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
92  case ISD::STRICT_FLOG2:
93  case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
94  case ISD::STRICT_FLOG10:
95  case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
96  case ISD::STRICT_FMA:
97  case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
98  case ISD::STRICT_FMUL:
99  case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
101  case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
102  case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
104  case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
106  case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
107  case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break;
108  case ISD::STRICT_FPOW:
109  case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
110  case ISD::STRICT_FPOWI:
111  case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break;
112  case ISD::STRICT_FREM:
113  case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
114  case ISD::STRICT_FRINT:
115  case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
116  case ISD::STRICT_FROUND:
117  case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break;
119  case ISD::FROUNDEVEN: R = SoftenFloatRes_FROUNDEVEN(N); break;
120  case ISD::STRICT_FSIN:
121  case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
122  case ISD::STRICT_FSQRT:
123  case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
124  case ISD::STRICT_FSUB:
125  case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
126  case ISD::STRICT_FTRUNC:
127  case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
128  case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
129  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
130  case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
131  case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
132  case ISD::FREEZE: R = SoftenFloatRes_FREEZE(N); break;
135  case ISD::SINT_TO_FP:
136  case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
137  case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
138  case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
139  case ISD::VECREDUCE_FADD:
140  case ISD::VECREDUCE_FMUL:
141  case ISD::VECREDUCE_FMIN:
142  case ISD::VECREDUCE_FMAX:
143  R = SoftenFloatRes_VECREDUCE(N);
144  break;
147  R = SoftenFloatRes_VECREDUCE_SEQ(N);
148  break;
149  }
150 
151  // If R is null, the sub-method took care of registering the result.
152  if (R.getNode()) {
153  assert(R.getNode() != N);
154  SetSoftenedFloat(SDValue(N, ResNo), R);
155  }
156 }
157 
158 SDValue DAGTypeLegalizer::SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC) {
159  bool IsStrict = N->isStrictFPOpcode();
160  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
161  unsigned Offset = IsStrict ? 1 : 0;
162  assert(N->getNumOperands() == (1 + Offset) &&
163  "Unexpected number of operands!");
164  SDValue Op = GetSoftenedFloat(N->getOperand(0 + Offset));
165  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
167  EVT OpVT = N->getOperand(0 + Offset).getValueType();
168  CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
169  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
170  CallOptions, SDLoc(N),
171  Chain);
172  if (IsStrict)
173  ReplaceValueWith(SDValue(N, 1), Tmp.second);
174  return Tmp.first;
175 }
176 
177 SDValue DAGTypeLegalizer::SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC) {
178  bool IsStrict = N->isStrictFPOpcode();
179  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
180  unsigned Offset = IsStrict ? 1 : 0;
181  assert(N->getNumOperands() == (2 + Offset) &&
182  "Unexpected number of operands!");
183  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0 + Offset)),
184  GetSoftenedFloat(N->getOperand(1 + Offset)) };
185  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
187  EVT OpsVT[2] = { N->getOperand(0 + Offset).getValueType(),
188  N->getOperand(1 + Offset).getValueType() };
189  CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
190  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops,
191  CallOptions, SDLoc(N),
192  Chain);
193  if (IsStrict)
194  ReplaceValueWith(SDValue(N, 1), Tmp.second);
195  return Tmp.first;
196 }
197 
198 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
199  return BitConvertToInteger(N->getOperand(0));
200 }
201 
202 SDValue DAGTypeLegalizer::SoftenFloatRes_FREEZE(SDNode *N) {
203  EVT Ty = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
204  return DAG.getNode(ISD::FREEZE, SDLoc(N), Ty,
205  GetSoftenedFloat(N->getOperand(0)));
206 }
207 
208 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
209  unsigned ResNo) {
210  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
211  return BitConvertToInteger(Op);
212 }
213 
214 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
215  // Convert the inputs to integers, and build a new pair out of them.
216  return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N),
217  TLI.getTypeToTransformTo(*DAG.getContext(),
218  N->getValueType(0)),
219  BitConvertToInteger(N->getOperand(0)),
220  BitConvertToInteger(N->getOperand(1)));
221 }
222 
223 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) {
224  ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
225  // In ppcf128, the high 64 bits are always first in memory regardless
226  // of Endianness. LLVM's APFloat representation is not Endian sensitive,
227  // and so always converts into a 128-bit APInt in a non-Endian-sensitive
228  // way. However, APInt's are serialized in an Endian-sensitive fashion,
229  // so on big-Endian targets, the two doubles are output in the wrong
230  // order. Fix this by manually flipping the order of the high 64 bits
231  // and the low 64 bits here.
232  if (DAG.getDataLayout().isBigEndian() &&
234  uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
235  CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
236  APInt Val(128, words);
237  return DAG.getConstant(Val, SDLoc(CN),
238  TLI.getTypeToTransformTo(*DAG.getContext(),
239  CN->getValueType(0)));
240  } else {
241  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
242  TLI.getTypeToTransformTo(*DAG.getContext(),
243  CN->getValueType(0)));
244  }
245 }
246 
247 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
248  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
249  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
251  NewOp, N->getOperand(1));
252 }
253 
254 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
255  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
256  unsigned Size = NVT.getSizeInBits();
257 
258  // Mask = ~(1 << (Size-1))
260  API.clearBit(Size - 1);
261  SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
262  SDValue Op = GetSoftenedFloat(N->getOperand(0));
263  return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
264 }
265 
266 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
267  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
268  RTLIB::FMIN_F32,
269  RTLIB::FMIN_F64,
270  RTLIB::FMIN_F80,
271  RTLIB::FMIN_F128,
272  RTLIB::FMIN_PPCF128));
273 }
274 
275 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
276  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
277  RTLIB::FMAX_F32,
278  RTLIB::FMAX_F64,
279  RTLIB::FMAX_F80,
280  RTLIB::FMAX_F128,
281  RTLIB::FMAX_PPCF128));
282 }
283 
284 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
285  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
286  RTLIB::ADD_F32,
287  RTLIB::ADD_F64,
288  RTLIB::ADD_F80,
289  RTLIB::ADD_F128,
290  RTLIB::ADD_PPCF128));
291 }
292 
293 SDValue DAGTypeLegalizer::SoftenFloatRes_FCBRT(SDNode *N) {
294  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
295  RTLIB::CBRT_F32,
296  RTLIB::CBRT_F64,
297  RTLIB::CBRT_F80,
298  RTLIB::CBRT_F128,
299  RTLIB::CBRT_PPCF128));
300 }
301 
302 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
303  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
304  RTLIB::CEIL_F32,
305  RTLIB::CEIL_F64,
306  RTLIB::CEIL_F80,
307  RTLIB::CEIL_F128,
308  RTLIB::CEIL_PPCF128));
309 }
310 
311 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) {
312  SDValue LHS = GetSoftenedFloat(N->getOperand(0));
313  SDValue RHS = BitConvertToInteger(N->getOperand(1));
314  SDLoc dl(N);
315 
316  EVT LVT = LHS.getValueType();
317  EVT RVT = RHS.getValueType();
318 
319  unsigned LSize = LVT.getSizeInBits();
320  unsigned RSize = RVT.getSizeInBits();
321 
322  // First get the sign bit of second operand.
323  SDValue SignBit = DAG.getNode(
324  ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
325  DAG.getConstant(RSize - 1, dl,
326  TLI.getShiftAmountTy(RVT, DAG.getDataLayout())));
327  SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
328 
329  // Shift right or sign-extend it if the two operands have different types.
330  int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
331  if (SizeDiff > 0) {
332  SignBit =
333  DAG.getNode(ISD::SRL, dl, RVT, SignBit,
334  DAG.getConstant(SizeDiff, dl,
335  TLI.getShiftAmountTy(SignBit.getValueType(),
336  DAG.getDataLayout())));
337  SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
338  } else if (SizeDiff < 0) {
339  SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
340  SignBit =
341  DAG.getNode(ISD::SHL, dl, LVT, SignBit,
342  DAG.getConstant(-SizeDiff, dl,
343  TLI.getShiftAmountTy(SignBit.getValueType(),
344  DAG.getDataLayout())));
345  }
346 
347  // Clear the sign bit of the first operand.
348  SDValue Mask = DAG.getNode(
349  ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
350  DAG.getConstant(LSize - 1, dl,
351  TLI.getShiftAmountTy(LVT, DAG.getDataLayout())));
352  Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
353  LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
354 
355  // Or the value with the sign bit.
356  return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
357 }
358 
359 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
360  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
361  RTLIB::COS_F32,
362  RTLIB::COS_F64,
363  RTLIB::COS_F80,
364  RTLIB::COS_F128,
365  RTLIB::COS_PPCF128));
366 }
367 
368 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
369  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
370  RTLIB::DIV_F32,
371  RTLIB::DIV_F64,
372  RTLIB::DIV_F80,
373  RTLIB::DIV_F128,
374  RTLIB::DIV_PPCF128));
375 }
376 
377 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
378  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
379  RTLIB::EXP_F32,
380  RTLIB::EXP_F64,
381  RTLIB::EXP_F80,
382  RTLIB::EXP_F128,
383  RTLIB::EXP_PPCF128));
384 }
385 
386 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
387  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
388  RTLIB::EXP2_F32,
389  RTLIB::EXP2_F64,
390  RTLIB::EXP2_F80,
391  RTLIB::EXP2_F128,
392  RTLIB::EXP2_PPCF128));
393 }
394 
395 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
396  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
397  RTLIB::FLOOR_F32,
398  RTLIB::FLOOR_F64,
399  RTLIB::FLOOR_F80,
400  RTLIB::FLOOR_F128,
401  RTLIB::FLOOR_PPCF128));
402 }
403 
404 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
405  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
406  RTLIB::LOG_F32,
407  RTLIB::LOG_F64,
408  RTLIB::LOG_F80,
409  RTLIB::LOG_F128,
410  RTLIB::LOG_PPCF128));
411 }
412 
413 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
414  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
415  RTLIB::LOG2_F32,
416  RTLIB::LOG2_F64,
417  RTLIB::LOG2_F80,
418  RTLIB::LOG2_F128,
419  RTLIB::LOG2_PPCF128));
420 }
421 
422 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
423  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
424  RTLIB::LOG10_F32,
425  RTLIB::LOG10_F64,
426  RTLIB::LOG10_F80,
427  RTLIB::LOG10_F128,
428  RTLIB::LOG10_PPCF128));
429 }
430 
431 SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
432  bool IsStrict = N->isStrictFPOpcode();
433  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
434  unsigned Offset = IsStrict ? 1 : 0;
435  SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0 + Offset)),
436  GetSoftenedFloat(N->getOperand(1 + Offset)),
437  GetSoftenedFloat(N->getOperand(2 + Offset)) };
438  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
440  EVT OpsVT[3] = { N->getOperand(0 + Offset).getValueType(),
441  N->getOperand(1 + Offset).getValueType(),
442  N->getOperand(2 + Offset).getValueType() };
443  CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
444  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG,
445  GetFPLibCall(N->getValueType(0),
446  RTLIB::FMA_F32,
447  RTLIB::FMA_F64,
448  RTLIB::FMA_F80,
449  RTLIB::FMA_F128,
450  RTLIB::FMA_PPCF128),
451  NVT, Ops, CallOptions, SDLoc(N), Chain);
452  if (IsStrict)
453  ReplaceValueWith(SDValue(N, 1), Tmp.second);
454  return Tmp.first;
455 }
456 
457 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
458  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
459  RTLIB::MUL_F32,
460  RTLIB::MUL_F64,
461  RTLIB::MUL_F80,
462  RTLIB::MUL_F128,
463  RTLIB::MUL_PPCF128));
464 }
465 
466 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
467  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
468  RTLIB::NEARBYINT_F32,
469  RTLIB::NEARBYINT_F64,
470  RTLIB::NEARBYINT_F80,
471  RTLIB::NEARBYINT_F128,
472  RTLIB::NEARBYINT_PPCF128));
473 }
474 
475 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
476  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
477  SDLoc dl(N);
478 
479  // Expand Y = FNEG(X) -> Y = X ^ sign mask
480  APInt SignMask = APInt::getSignMask(NVT.getSizeInBits());
481  return DAG.getNode(ISD::XOR, dl, NVT, GetSoftenedFloat(N->getOperand(0)),
482  DAG.getConstant(SignMask, dl, NVT));
483 }
484 
485 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
486  bool IsStrict = N->isStrictFPOpcode();
487  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
488  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
489 
490  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
491 
492  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) {
493  Op = GetPromotedFloat(Op);
494  // If the promotion did the FP_EXTEND to the destination type for us,
495  // there's nothing left to do here.
496  if (Op.getValueType() == N->getValueType(0))
497  return BitConvertToInteger(Op);
498  }
499 
500  // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
501  // entirely possible for both f16 and f32 to be legal, so use the fully
502  // hard-float FP_EXTEND rather than FP16_TO_FP.
503  if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
504  if (IsStrict) {
506  { MVT::f32, MVT::Other }, { Chain, Op });
507  Chain = Op.getValue(1);
508  } else {
510  }
511  }
512 
513  RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
514  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
516  EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
517  CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
518  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
519  CallOptions, SDLoc(N),
520  Chain);
521  if (IsStrict)
522  ReplaceValueWith(SDValue(N, 1), Tmp.second);
523  return Tmp.first;
524 }
525 
526 // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special
527 // nodes?
528 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(SDNode *N) {
529  EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
530  SDValue Op = N->getOperand(0);
532  EVT OpsVT[1] = { N->getOperand(0).getValueType() };
533  CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
534  SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op,
535  CallOptions, SDLoc(N)).first;
536  if (N->getValueType(0) == MVT::f32)
537  return Res32;
538 
539  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
540  RTLIB::Libcall LC = RTLIB::getFPEXT(MVT::f32, N->getValueType(0));
541  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
542  return TLI.makeLibCall(DAG, LC, NVT, Res32, CallOptions, SDLoc(N)).first;
543 }
544 
545 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
546  bool IsStrict = N->isStrictFPOpcode();
547  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
548  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
549  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
550  RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
551  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
553  EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
554  CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
555  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
556  CallOptions, SDLoc(N),
557  Chain);
558  if (IsStrict)
559  ReplaceValueWith(SDValue(N, 1), Tmp.second);
560  return Tmp.first;
561 }
562 
563 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
564  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
565  RTLIB::POW_F32,
566  RTLIB::POW_F64,
567  RTLIB::POW_F80,
568  RTLIB::POW_F128,
569  RTLIB::POW_PPCF128));
570 }
571 
572 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
573  bool IsStrict = N->isStrictFPOpcode();
574  unsigned Offset = IsStrict ? 1 : 0;
575  assert(N->getOperand(1 + Offset).getValueType() == MVT::i32 &&
576  "Unsupported power type!");
577  RTLIB::Libcall LC = RTLIB::getPOWI(N->getValueType(0));
578  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
579  if (!TLI.getLibcallName(LC)) {
580  // Some targets don't have a powi libcall; use pow instead.
581  // FIXME: Implement this if some target needs it.
582  DAG.getContext()->emitError("Don't know how to soften fpowi to fpow");
583  return DAG.getUNDEF(N->getValueType(0));
584  }
585 
586  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
587  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0 + Offset)),
588  N->getOperand(1 + Offset) };
589  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
591  EVT OpsVT[2] = { N->getOperand(0 + Offset).getValueType(),
592  N->getOperand(1 + Offset).getValueType() };
593  CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true);
594  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops,
595  CallOptions, SDLoc(N),
596  Chain);
597  if (IsStrict)
598  ReplaceValueWith(SDValue(N, 1), Tmp.second);
599  return Tmp.first;
600 }
601 
602 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
603  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
604  RTLIB::REM_F32,
605  RTLIB::REM_F64,
606  RTLIB::REM_F80,
607  RTLIB::REM_F128,
608  RTLIB::REM_PPCF128));
609 }
610 
611 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
612  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
613  RTLIB::RINT_F32,
614  RTLIB::RINT_F64,
615  RTLIB::RINT_F80,
616  RTLIB::RINT_F128,
617  RTLIB::RINT_PPCF128));
618 }
619 
620 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
621  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
622  RTLIB::ROUND_F32,
623  RTLIB::ROUND_F64,
624  RTLIB::ROUND_F80,
625  RTLIB::ROUND_F128,
626  RTLIB::ROUND_PPCF128));
627 }
628 
629 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUNDEVEN(SDNode *N) {
630  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
631  RTLIB::ROUNDEVEN_F32,
632  RTLIB::ROUNDEVEN_F64,
633  RTLIB::ROUNDEVEN_F80,
634  RTLIB::ROUNDEVEN_F128,
635  RTLIB::ROUNDEVEN_PPCF128));
636 }
637 
638 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
639  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
640  RTLIB::SIN_F32,
641  RTLIB::SIN_F64,
642  RTLIB::SIN_F80,
643  RTLIB::SIN_F128,
644  RTLIB::SIN_PPCF128));
645 }
646 
647 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
648  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
649  RTLIB::SQRT_F32,
650  RTLIB::SQRT_F64,
651  RTLIB::SQRT_F80,
652  RTLIB::SQRT_F128,
653  RTLIB::SQRT_PPCF128));
654 }
655 
656 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
657  return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
658  RTLIB::SUB_F32,
659  RTLIB::SUB_F64,
660  RTLIB::SUB_F80,
661  RTLIB::SUB_F128,
662  RTLIB::SUB_PPCF128));
663 }
664 
665 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
666  return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
667  RTLIB::TRUNC_F32,
668  RTLIB::TRUNC_F64,
669  RTLIB::TRUNC_F80,
670  RTLIB::TRUNC_F128,
671  RTLIB::TRUNC_PPCF128));
672 }
673 
674 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
675  LoadSDNode *L = cast<LoadSDNode>(N);
676  EVT VT = N->getValueType(0);
677  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
678  SDLoc dl(N);
679 
680  auto MMOFlags =
681  L->getMemOperand()->getFlags() &
683  SDValue NewL;
684  if (L->getExtensionType() == ISD::NON_EXTLOAD) {
685  NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
686  L->getChain(), L->getBasePtr(), L->getOffset(),
687  L->getPointerInfo(), NVT, L->getOriginalAlign(),
688  MMOFlags, L->getAAInfo());
689  // Legalized the chain result - switch anything that used the old chain to
690  // use the new one.
691  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
692  return NewL;
693  }
694 
695  // Do a non-extending load followed by FP_EXTEND.
696  NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
697  dl, L->getChain(), L->getBasePtr(), L->getOffset(),
698  L->getPointerInfo(), L->getMemoryVT(),
699  L->getOriginalAlign(), MMOFlags, L->getAAInfo());
700  // Legalized the chain result - switch anything that used the old chain to
701  // use the new one.
702  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
703  auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL);
704  return BitConvertToInteger(ExtendNode);
705 }
706 
707 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N) {
708  SDValue LHS = GetSoftenedFloat(N->getOperand(1));
709  SDValue RHS = GetSoftenedFloat(N->getOperand(2));
710  return DAG.getSelect(SDLoc(N),
711  LHS.getValueType(), N->getOperand(0), LHS, RHS);
712 }
713 
714 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
715  SDValue LHS = GetSoftenedFloat(N->getOperand(2));
716  SDValue RHS = GetSoftenedFloat(N->getOperand(3));
717  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
718  LHS.getValueType(), N->getOperand(0),
719  N->getOperand(1), LHS, RHS, N->getOperand(4));
720 }
721 
722 SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
723  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
724  N->getValueType(0)));
725 }
726 
727 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
728  SDValue Chain = N->getOperand(0); // Get the chain.
729  SDValue Ptr = N->getOperand(1); // Get the pointer.
730  EVT VT = N->getValueType(0);
731  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
732  SDLoc dl(N);
733 
734  SDValue NewVAARG;
735  NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2),
736  N->getConstantOperandVal(3));
737 
738  // Legalized the chain result - switch anything that used the old chain to
739  // use the new one.
740  if (N != NewVAARG.getValue(1).getNode())
741  ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
742  return NewVAARG;
743 }
744 
745 SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
746  bool IsStrict = N->isStrictFPOpcode();
747  bool Signed = N->getOpcode() == ISD::SINT_TO_FP ||
748  N->getOpcode() == ISD::STRICT_SINT_TO_FP;
749  EVT SVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
750  EVT RVT = N->getValueType(0);
751  EVT NVT = EVT();
752  SDLoc dl(N);
753 
754  // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
755  // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
756  // match. Look for an appropriate libcall.
757  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
758  for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
759  t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
760  NVT = (MVT::SimpleValueType)t;
761  // The source needs to big enough to hold the operand.
762  if (NVT.bitsGE(SVT))
763  LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
764  }
765  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
766 
767  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
768  // Sign/zero extend the argument if the libcall takes a larger type.
770  NVT, N->getOperand(IsStrict ? 1 : 0));
772  CallOptions.setSExt(Signed);
773  CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
774  std::pair<SDValue, SDValue> Tmp =
775  TLI.makeLibCall(DAG, LC, TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
776  Op, CallOptions, dl, Chain);
777 
778  if (IsStrict)
779  ReplaceValueWith(SDValue(N, 1), Tmp.second);
780  return Tmp.first;
781 }
782 
783 SDValue DAGTypeLegalizer::SoftenFloatRes_VECREDUCE(SDNode *N) {
784  // Expand and soften recursively.
785  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduce(N, DAG));
786  return SDValue();
787 }
788 
789 SDValue DAGTypeLegalizer::SoftenFloatRes_VECREDUCE_SEQ(SDNode *N) {
790  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduceSeq(N, DAG));
791  return SDValue();
792 }
793 
794 //===----------------------------------------------------------------------===//
795 // Convert Float Operand to Integer
796 //===----------------------------------------------------------------------===//
797 
798 bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
799  LLVM_DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
800  dbgs() << "\n");
801  SDValue Res = SDValue();
802 
803  switch (N->getOpcode()) {
804  default:
805 #ifndef NDEBUG
806  dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
807  N->dump(&DAG); dbgs() << "\n";
808 #endif
809  llvm_unreachable("Do not know how to soften this operator's operand!");
810 
811  case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
812  case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
813  case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
815  case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
818  case ISD::FP_TO_SINT:
819  case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break;
820  case ISD::FP_TO_SINT_SAT:
821  case ISD::FP_TO_UINT_SAT:
822  Res = SoftenFloatOp_FP_TO_XINT_SAT(N); break;
823  case ISD::STRICT_LROUND:
824  case ISD::LROUND: Res = SoftenFloatOp_LROUND(N); break;
825  case ISD::STRICT_LLROUND:
826  case ISD::LLROUND: Res = SoftenFloatOp_LLROUND(N); break;
827  case ISD::STRICT_LRINT:
828  case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break;
829  case ISD::STRICT_LLRINT:
830  case ISD::LLRINT: Res = SoftenFloatOp_LLRINT(N); break;
831  case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
832  case ISD::STRICT_FSETCC:
833  case ISD::STRICT_FSETCCS:
834  case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
835  case ISD::STORE: Res = SoftenFloatOp_STORE(N, OpNo); break;
836  case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break;
837  }
838 
839  // If the result is null, the sub-method took care of registering results etc.
840  if (!Res.getNode()) return false;
841 
842  // If the result is N, the sub-method updated N in place. Tell the legalizer
843  // core about this to re-analyze.
844  if (Res.getNode() == N)
845  return true;
846 
847  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
848  "Invalid operand softening");
849 
850  ReplaceValueWith(SDValue(N, 0), Res);
851  return false;
852 }
853 
854 SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
855  SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
856 
857  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0);
858 }
859 
860 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
861  // We actually deal with the partially-softened FP_TO_FP16 node too, which
862  // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
863  assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 ||
864  N->getOpcode() == ISD::STRICT_FP_ROUND);
865 
866  bool IsStrict = N->isStrictFPOpcode();
867  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
868  EVT SVT = Op.getValueType();
869  EVT RVT = N->getValueType(0);
870  EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
871 
872  RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
873  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
874 
875  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
876  Op = GetSoftenedFloat(Op);
878  CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
879  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RVT, Op,
880  CallOptions, SDLoc(N),
881  Chain);
882  if (IsStrict) {
883  ReplaceValueWith(SDValue(N, 1), Tmp.second);
884  ReplaceValueWith(SDValue(N, 0), Tmp.first);
885  return SDValue();
886  }
887  return Tmp.first;
888 }
889 
890 SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
891  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
892  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
893 
894  EVT VT = NewLHS.getValueType();
895  NewLHS = GetSoftenedFloat(NewLHS);
896  NewRHS = GetSoftenedFloat(NewRHS);
897  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N),
898  N->getOperand(2), N->getOperand(3));
899 
900  // If softenSetCCOperands returned a scalar, we need to compare the result
901  // against zero to select between true and false values.
902  if (!NewRHS.getNode()) {
903  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
904  CCCode = ISD::SETNE;
905  }
906 
907  // Update N to have the operands specified.
908  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
909  DAG.getCondCode(CCCode), NewLHS, NewRHS,
910  N->getOperand(4)),
911  0);
912 }
913 
914 // Even if the result type is legal, no libcall may exactly match. (e.g. We
915 // don't have FP-i8 conversions) This helper method looks for an appropriate
916 // promoted libcall.
917 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted,
918  bool Signed) {
919  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
920  for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
921  IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
922  ++IntVT) {
923  Promoted = (MVT::SimpleValueType)IntVT;
924  // The type needs to big enough to hold the result.
925  if (Promoted.bitsGE(RetVT))
926  LC = Signed ? RTLIB::getFPTOSINT(SrcVT, Promoted)
927  : RTLIB::getFPTOUINT(SrcVT, Promoted);
928  }
929  return LC;
930 }
931 
932 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT(SDNode *N) {
933  bool IsStrict = N->isStrictFPOpcode();
934  bool Signed = N->getOpcode() == ISD::FP_TO_SINT ||
935  N->getOpcode() == ISD::STRICT_FP_TO_SINT;
936 
937  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
938  EVT SVT = Op.getValueType();
939  EVT RVT = N->getValueType(0);
940  EVT NVT = EVT();
941  SDLoc dl(N);
942 
943  // If the result is not legal, eg: fp -> i1, then it needs to be promoted to
944  // a larger type, eg: fp -> i32. Even if it is legal, no libcall may exactly
945  // match, eg. we don't have fp -> i8 conversions.
946  // Look for an appropriate libcall.
947  RTLIB::Libcall LC = findFPToIntLibcall(SVT, RVT, NVT, Signed);
948  assert(LC != RTLIB::UNKNOWN_LIBCALL && NVT.isSimple() &&
949  "Unsupported FP_TO_XINT!");
950 
951  Op = GetSoftenedFloat(Op);
952  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
954  CallOptions.setTypeListBeforeSoften(SVT, RVT, true);
955  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
956  CallOptions, dl, Chain);
957 
958  // Truncate the result if the libcall returns a larger type.
959  SDValue Res = DAG.getNode(ISD::TRUNCATE, dl, RVT, Tmp.first);
960 
961  if (!IsStrict)
962  return Res;
963 
964  ReplaceValueWith(SDValue(N, 1), Tmp.second);
965  ReplaceValueWith(SDValue(N, 0), Res);
966  return SDValue();
967 }
968 
969 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT_SAT(SDNode *N) {
970  SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
971  return Res;
972 }
973 
974 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
975  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
976  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
977 
978  EVT VT = NewLHS.getValueType();
979  NewLHS = GetSoftenedFloat(NewLHS);
980  NewRHS = GetSoftenedFloat(NewRHS);
981  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N),
982  N->getOperand(0), N->getOperand(1));
983 
984  // If softenSetCCOperands returned a scalar, we need to compare the result
985  // against zero to select between true and false values.
986  if (!NewRHS.getNode()) {
987  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
988  CCCode = ISD::SETNE;
989  }
990 
991  // Update N to have the operands specified.
992  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
993  N->getOperand(2), N->getOperand(3),
994  DAG.getCondCode(CCCode)),
995  0);
996 }
997 
998 SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
999  bool IsStrict = N->isStrictFPOpcode();
1000  SDValue Op0 = N->getOperand(IsStrict ? 1 : 0);
1001  SDValue Op1 = N->getOperand(IsStrict ? 2 : 1);
1002  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1003  ISD::CondCode CCCode =
1004  cast<CondCodeSDNode>(N->getOperand(IsStrict ? 3 : 2))->get();
1005 
1006  EVT VT = Op0.getValueType();
1007  SDValue NewLHS = GetSoftenedFloat(Op0);
1008  SDValue NewRHS = GetSoftenedFloat(Op1);
1009  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N), Op0, Op1,
1010  Chain, N->getOpcode() == ISD::STRICT_FSETCCS);
1011 
1012  // Update N to have the operands specified.
1013  if (NewRHS.getNode()) {
1014  if (IsStrict)
1015  NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS,
1016  NewRHS, DAG.getCondCode(CCCode));
1017  else
1018  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1019  DAG.getCondCode(CCCode)), 0);
1020  }
1021 
1022  // Otherwise, softenSetCCOperands returned a scalar, use it.
1023  assert((NewRHS.getNode() || NewLHS.getValueType() == N->getValueType(0)) &&
1024  "Unexpected setcc expansion!");
1025 
1026  if (IsStrict) {
1027  ReplaceValueWith(SDValue(N, 0), NewLHS);
1028  ReplaceValueWith(SDValue(N, 1), Chain);
1029  return SDValue();
1030  }
1031  return NewLHS;
1032 }
1033 
1034 SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
1035  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1036  assert(OpNo == 1 && "Can only soften the stored value!");
1037  StoreSDNode *ST = cast<StoreSDNode>(N);
1038  SDValue Val = ST->getValue();
1039  SDLoc dl(N);
1040 
1041  if (ST->isTruncatingStore())
1042  // Do an FP_ROUND followed by a non-truncating store.
1043  Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1044  Val, DAG.getIntPtrConstant(0, dl)));
1045  else
1046  Val = GetSoftenedFloat(Val);
1047 
1048  return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(),
1049  ST->getMemOperand());
1050 }
1051 
1052 SDValue DAGTypeLegalizer::SoftenFloatOp_FCOPYSIGN(SDNode *N) {
1053  SDValue LHS = N->getOperand(0);
1054  SDValue RHS = BitConvertToInteger(N->getOperand(1));
1055  SDLoc dl(N);
1056 
1057  EVT LVT = LHS.getValueType();
1058  EVT ILVT = EVT::getIntegerVT(*DAG.getContext(), LVT.getSizeInBits());
1059  EVT RVT = RHS.getValueType();
1060 
1061  unsigned LSize = LVT.getSizeInBits();
1062  unsigned RSize = RVT.getSizeInBits();
1063 
1064  // Shift right or sign-extend it if the two operands have different types.
1065  int SizeDiff = RSize - LSize;
1066  if (SizeDiff > 0) {
1067  RHS =
1068  DAG.getNode(ISD::SRL, dl, RVT, RHS,
1069  DAG.getConstant(SizeDiff, dl,
1070  TLI.getShiftAmountTy(RHS.getValueType(),
1071  DAG.getDataLayout())));
1072  RHS = DAG.getNode(ISD::TRUNCATE, dl, ILVT, RHS);
1073  } else if (SizeDiff < 0) {
1074  RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, RHS);
1075  RHS =
1076  DAG.getNode(ISD::SHL, dl, ILVT, RHS,
1077  DAG.getConstant(-SizeDiff, dl,
1078  TLI.getShiftAmountTy(RHS.getValueType(),
1079  DAG.getDataLayout())));
1080  }
1081 
1082  RHS = DAG.getBitcast(LVT, RHS);
1083  return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS);
1084 }
1085 
1086 SDValue DAGTypeLegalizer::SoftenFloatOp_Unary(SDNode *N, RTLIB::Libcall LC) {
1087  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1088  bool IsStrict = N->isStrictFPOpcode();
1089  unsigned Offset = IsStrict ? 1 : 0;
1090  SDValue Op = GetSoftenedFloat(N->getOperand(0 + Offset));
1091  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1093  EVT OpVT = N->getOperand(0 + Offset).getValueType();
1094  CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
1095  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
1096  CallOptions, SDLoc(N),
1097  Chain);
1098  if (IsStrict) {
1099  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1100  ReplaceValueWith(SDValue(N, 0), Tmp.first);
1101  return SDValue();
1102  }
1103 
1104  return Tmp.first;
1105 }
1106 
1107 SDValue DAGTypeLegalizer::SoftenFloatOp_LROUND(SDNode *N) {
1108  EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
1109  return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
1110  RTLIB::LROUND_F32,
1111  RTLIB::LROUND_F64,
1112  RTLIB::LROUND_F80,
1113  RTLIB::LROUND_F128,
1114  RTLIB::LROUND_PPCF128));
1115 }
1116 
1117 SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
1118  EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
1119  return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
1120  RTLIB::LLROUND_F32,
1121  RTLIB::LLROUND_F64,
1122  RTLIB::LLROUND_F80,
1123  RTLIB::LLROUND_F128,
1124  RTLIB::LLROUND_PPCF128));
1125 }
1126 
1127 SDValue DAGTypeLegalizer::SoftenFloatOp_LRINT(SDNode *N) {
1128  EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
1129  return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
1130  RTLIB::LRINT_F32,
1131  RTLIB::LRINT_F64,
1132  RTLIB::LRINT_F80,
1133  RTLIB::LRINT_F128,
1134  RTLIB::LRINT_PPCF128));
1135 }
1136 
1137 SDValue DAGTypeLegalizer::SoftenFloatOp_LLRINT(SDNode *N) {
1138  EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
1139  return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
1140  RTLIB::LLRINT_F32,
1141  RTLIB::LLRINT_F64,
1142  RTLIB::LLRINT_F80,
1143  RTLIB::LLRINT_F128,
1144  RTLIB::LLRINT_PPCF128));
1145 }
1146 
1147 //===----------------------------------------------------------------------===//
1148 // Float Result Expansion
1149 //===----------------------------------------------------------------------===//
1150 
1151 /// ExpandFloatResult - This method is called when the specified result of the
1152 /// specified node is found to need expansion. At this point, the node may also
1153 /// have invalid operands or may have other results that need promotion, we just
1154 /// know that (at least) one result needs expansion.
1155 void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
1156  LLVM_DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n");
1157  SDValue Lo, Hi;
1158  Lo = Hi = SDValue();
1159 
1160  // See if the target wants to custom expand this node.
1161  if (CustomLowerNode(N, N->getValueType(ResNo), true))
1162  return;
1163 
1164  switch (N->getOpcode()) {
1165  default:
1166 #ifndef NDEBUG
1167  dbgs() << "ExpandFloatResult #" << ResNo << ": ";
1168  N->dump(&DAG); dbgs() << "\n";
1169 #endif
1170  llvm_unreachable("Do not know how to expand the result of this operator!");
1171 
1172  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1173  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1174  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1175 
1176  case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1177  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1178  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1179  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1180  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1181  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1182 
1183  case ISD::ConstantFP: ExpandFloatRes_ConstantFP(N, Lo, Hi); break;
1184  case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1185  case ISD::STRICT_FMINNUM:
1186  case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
1187  case ISD::STRICT_FMAXNUM:
1188  case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
1189  case ISD::STRICT_FADD:
1190  case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1191  case ISD::FCBRT: ExpandFloatRes_FCBRT(N, Lo, Hi); break;
1192  case ISD::STRICT_FCEIL:
1193  case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
1194  case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1195  case ISD::STRICT_FCOS:
1196  case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break;
1197  case ISD::STRICT_FDIV:
1198  case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
1199  case ISD::STRICT_FEXP:
1200  case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break;
1201  case ISD::STRICT_FEXP2:
1202  case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break;
1203  case ISD::STRICT_FFLOOR:
1204  case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break;
1205  case ISD::STRICT_FLOG:
1206  case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break;
1207  case ISD::STRICT_FLOG2:
1208  case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break;
1209  case ISD::STRICT_FLOG10:
1210  case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break;
1211  case ISD::STRICT_FMA:
1212  case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
1213  case ISD::STRICT_FMUL:
1214  case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
1216  case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
1217  case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1218  case ISD::STRICT_FP_EXTEND:
1219  case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
1220  case ISD::STRICT_FPOW:
1221  case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break;
1222  case ISD::STRICT_FPOWI:
1223  case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break;
1224  case ISD::FREEZE: ExpandFloatRes_FREEZE(N, Lo, Hi); break;
1225  case ISD::STRICT_FRINT:
1226  case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
1227  case ISD::STRICT_FROUND:
1228  case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi); break;
1230  case ISD::FROUNDEVEN: ExpandFloatRes_FROUNDEVEN(N, Lo, Hi); break;
1231  case ISD::STRICT_FSIN:
1232  case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
1233  case ISD::STRICT_FSQRT:
1234  case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
1235  case ISD::STRICT_FSUB:
1236  case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1237  case ISD::STRICT_FTRUNC:
1238  case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
1239  case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
1242  case ISD::SINT_TO_FP:
1243  case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
1244  case ISD::STRICT_FREM:
1245  case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
1246  }
1247 
1248  // If Lo/Hi is null, the sub-method took care of registering results etc.
1249  if (Lo.getNode())
1250  SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
1251 }
1252 
1253 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
1254  SDValue &Hi) {
1255  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1256  assert(NVT.getSizeInBits() == 64 &&
1257  "Do not know how to expand this float constant!");
1258  APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
1259  SDLoc dl(N);
1261  APInt(64, C.getRawData()[1])),
1262  dl, NVT);
1264  APInt(64, C.getRawData()[0])),
1265  dl, NVT);
1266 }
1267 
1268 void DAGTypeLegalizer::ExpandFloatRes_Unary(SDNode *N, RTLIB::Libcall LC,
1269  SDValue &Lo, SDValue &Hi) {
1270  bool IsStrict = N->isStrictFPOpcode();
1271  unsigned Offset = IsStrict ? 1 : 0;
1272  SDValue Op = N->getOperand(0 + Offset);
1273  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1275  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, N->getValueType(0),
1276  Op, CallOptions, SDLoc(N),
1277  Chain);
1278  if (IsStrict)
1279  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1280  GetPairElements(Tmp.first, Lo, Hi);
1281 }
1282 
1283 void DAGTypeLegalizer::ExpandFloatRes_Binary(SDNode *N, RTLIB::Libcall LC,
1284  SDValue &Lo, SDValue &Hi) {
1285  bool IsStrict = N->isStrictFPOpcode();
1286  unsigned Offset = IsStrict ? 1 : 0;
1287  SDValue Ops[] = { N->getOperand(0 + Offset), N->getOperand(1 + Offset) };
1288  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1290  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, N->getValueType(0),
1291  Ops, CallOptions, SDLoc(N),
1292  Chain);
1293  if (IsStrict)
1294  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1295  GetPairElements(Tmp.first, Lo, Hi);
1296 }
1297 
1298 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
1299  SDValue &Hi) {
1300  assert(N->getValueType(0) == MVT::ppcf128 &&
1301  "Logic only correct for ppcf128!");
1302  SDLoc dl(N);
1303  SDValue Tmp;
1304  GetExpandedFloat(N->getOperand(0), Lo, Tmp);
1305  Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
1306  // Lo = Hi==fabs(Hi) ? Lo : -Lo;
1307  Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo,
1308  DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1309  ISD::SETEQ);
1310 }
1311 
1312 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
1313  SDValue &Hi) {
1314  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1315  RTLIB::FMIN_F32, RTLIB::FMIN_F64,
1316  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
1317  RTLIB::FMIN_PPCF128), Lo, Hi);
1318 }
1319 
1320 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
1321  SDValue &Hi) {
1322  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1323  RTLIB::FMAX_F32, RTLIB::FMAX_F64,
1324  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
1325  RTLIB::FMAX_PPCF128), Lo, Hi);
1326 }
1327 
1328 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
1329  SDValue &Hi) {
1330  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1331  RTLIB::ADD_F32, RTLIB::ADD_F64,
1332  RTLIB::ADD_F80, RTLIB::ADD_F128,
1333  RTLIB::ADD_PPCF128), Lo, Hi);
1334 }
1335 
1336 void DAGTypeLegalizer::ExpandFloatRes_FCBRT(SDNode *N, SDValue &Lo,
1337  SDValue &Hi) {
1338  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0), RTLIB::CBRT_F32,
1339  RTLIB::CBRT_F64, RTLIB::CBRT_F80,
1340  RTLIB::CBRT_F128,
1341  RTLIB::CBRT_PPCF128), Lo, Hi);
1342 }
1343 
1344 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
1345  SDValue &Lo, SDValue &Hi) {
1346  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1347  RTLIB::CEIL_F32, RTLIB::CEIL_F64,
1348  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
1349  RTLIB::CEIL_PPCF128), Lo, Hi);
1350 }
1351 
1352 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
1353  SDValue &Lo, SDValue &Hi) {
1354  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1355  RTLIB::COPYSIGN_F32,
1356  RTLIB::COPYSIGN_F64,
1357  RTLIB::COPYSIGN_F80,
1358  RTLIB::COPYSIGN_F128,
1359  RTLIB::COPYSIGN_PPCF128), Lo, Hi);
1360 }
1361 
1362 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
1363  SDValue &Lo, SDValue &Hi) {
1364  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1365  RTLIB::COS_F32, RTLIB::COS_F64,
1366  RTLIB::COS_F80, RTLIB::COS_F128,
1367  RTLIB::COS_PPCF128), Lo, Hi);
1368 }
1369 
1370 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
1371  SDValue &Hi) {
1372  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1373  RTLIB::DIV_F32,
1374  RTLIB::DIV_F64,
1375  RTLIB::DIV_F80,
1376  RTLIB::DIV_F128,
1377  RTLIB::DIV_PPCF128), Lo, Hi);
1378 }
1379 
1380 void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
1381  SDValue &Lo, SDValue &Hi) {
1382  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1383  RTLIB::EXP_F32, RTLIB::EXP_F64,
1384  RTLIB::EXP_F80, RTLIB::EXP_F128,
1385  RTLIB::EXP_PPCF128), Lo, Hi);
1386 }
1387 
1388 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
1389  SDValue &Lo, SDValue &Hi) {
1390  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1391  RTLIB::EXP2_F32, RTLIB::EXP2_F64,
1392  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
1393  RTLIB::EXP2_PPCF128), Lo, Hi);
1394 }
1395 
1396 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
1397  SDValue &Lo, SDValue &Hi) {
1398  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1399  RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
1400  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
1401  RTLIB::FLOOR_PPCF128), Lo, Hi);
1402 }
1403 
1404 void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
1405  SDValue &Lo, SDValue &Hi) {
1406  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1407  RTLIB::LOG_F32, RTLIB::LOG_F64,
1408  RTLIB::LOG_F80, RTLIB::LOG_F128,
1409  RTLIB::LOG_PPCF128), Lo, Hi);
1410 }
1411 
1412 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
1413  SDValue &Lo, SDValue &Hi) {
1414  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1415  RTLIB::LOG2_F32, RTLIB::LOG2_F64,
1416  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
1417  RTLIB::LOG2_PPCF128), Lo, Hi);
1418 }
1419 
1420 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(SDNode *N,
1421  SDValue &Lo, SDValue &Hi) {
1422  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1423  RTLIB::LOG10_F32, RTLIB::LOG10_F64,
1424  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
1425  RTLIB::LOG10_PPCF128), Lo, Hi);
1426 }
1427 
1428 void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
1429  SDValue &Hi) {
1430  bool IsStrict = N->isStrictFPOpcode();
1431  unsigned Offset = IsStrict ? 1 : 0;
1432  SDValue Ops[3] = { N->getOperand(0 + Offset), N->getOperand(1 + Offset),
1433  N->getOperand(2 + Offset) };
1434  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1436  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1437  RTLIB::FMA_F32,
1438  RTLIB::FMA_F64,
1439  RTLIB::FMA_F80,
1440  RTLIB::FMA_F128,
1441  RTLIB::FMA_PPCF128),
1442  N->getValueType(0), Ops, CallOptions,
1443  SDLoc(N), Chain);
1444  if (IsStrict)
1445  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1446  GetPairElements(Tmp.first, Lo, Hi);
1447 }
1448 
1449 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
1450  SDValue &Hi) {
1451  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1452  RTLIB::MUL_F32,
1453  RTLIB::MUL_F64,
1454  RTLIB::MUL_F80,
1455  RTLIB::MUL_F128,
1456  RTLIB::MUL_PPCF128), Lo, Hi);
1457 }
1458 
1459 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(SDNode *N,
1460  SDValue &Lo, SDValue &Hi) {
1461  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1462  RTLIB::NEARBYINT_F32,
1463  RTLIB::NEARBYINT_F64,
1464  RTLIB::NEARBYINT_F80,
1465  RTLIB::NEARBYINT_F128,
1466  RTLIB::NEARBYINT_PPCF128), Lo, Hi);
1467 }
1468 
1469 void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
1470  SDValue &Hi) {
1471  SDLoc dl(N);
1472  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1473  Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1474  Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
1475 }
1476 
1477 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
1478  SDValue &Hi) {
1479  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1480  SDLoc dl(N);
1481  bool IsStrict = N->isStrictFPOpcode();
1482 
1483  SDValue Chain;
1484  if (IsStrict) {
1485  // If the expanded type is the same as the input type, just bypass the node.
1486  if (NVT == N->getOperand(1).getValueType()) {
1487  Hi = N->getOperand(1);
1488  Chain = N->getOperand(0);
1489  } else {
1490  // Other we need to extend.
1491  Hi = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, { NVT, MVT::Other },
1492  { N->getOperand(0), N->getOperand(1) });
1493  Chain = Hi.getValue(1);
1494  }
1495  } else {
1496  Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
1497  }
1498 
1500  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1501 
1502  if (IsStrict)
1503  ReplaceValueWith(SDValue(N, 1), Chain);
1504 }
1505 
1506 void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
1507  SDValue &Lo, SDValue &Hi) {
1508  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1509  RTLIB::POW_F32, RTLIB::POW_F64,
1510  RTLIB::POW_F80, RTLIB::POW_F128,
1511  RTLIB::POW_PPCF128), Lo, Hi);
1512 }
1513 
1514 void DAGTypeLegalizer::ExpandFloatRes_FPOWI(SDNode *N,
1515  SDValue &Lo, SDValue &Hi) {
1516  ExpandFloatRes_Binary(N, RTLIB::getPOWI(N->getValueType(0)), Lo, Hi);
1517 }
1518 
1519 void DAGTypeLegalizer::ExpandFloatRes_FREEZE(SDNode *N,
1520  SDValue &Lo, SDValue &Hi) {
1521  assert(N->getValueType(0) == MVT::ppcf128 &&
1522  "Logic only correct for ppcf128!");
1523 
1524  SDLoc dl(N);
1525  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1526  Lo = DAG.getNode(ISD::FREEZE, dl, Lo.getValueType(), Lo);
1527  Hi = DAG.getNode(ISD::FREEZE, dl, Hi.getValueType(), Hi);
1528 }
1529 
1530 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
1531  SDValue &Lo, SDValue &Hi) {
1532  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1533  RTLIB::REM_F32, RTLIB::REM_F64,
1534  RTLIB::REM_F80, RTLIB::REM_F128,
1535  RTLIB::REM_PPCF128), Lo, Hi);
1536 }
1537 
1538 void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
1539  SDValue &Lo, SDValue &Hi) {
1540  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1541  RTLIB::RINT_F32, RTLIB::RINT_F64,
1542  RTLIB::RINT_F80, RTLIB::RINT_F128,
1543  RTLIB::RINT_PPCF128), Lo, Hi);
1544 }
1545 
1546 void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
1547  SDValue &Lo, SDValue &Hi) {
1548  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1549  RTLIB::ROUND_F32,
1550  RTLIB::ROUND_F64,
1551  RTLIB::ROUND_F80,
1552  RTLIB::ROUND_F128,
1553  RTLIB::ROUND_PPCF128), Lo, Hi);
1554 }
1555 
1556 void DAGTypeLegalizer::ExpandFloatRes_FROUNDEVEN(SDNode *N,
1557  SDValue &Lo, SDValue &Hi) {
1558  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1559  RTLIB::ROUNDEVEN_F32,
1560  RTLIB::ROUNDEVEN_F64,
1561  RTLIB::ROUNDEVEN_F80,
1562  RTLIB::ROUNDEVEN_F128,
1563  RTLIB::ROUNDEVEN_PPCF128), Lo, Hi);
1564 }
1565 
1566 void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
1567  SDValue &Lo, SDValue &Hi) {
1568  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1569  RTLIB::SIN_F32, RTLIB::SIN_F64,
1570  RTLIB::SIN_F80, RTLIB::SIN_F128,
1571  RTLIB::SIN_PPCF128), Lo, Hi);
1572 }
1573 
1574 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
1575  SDValue &Lo, SDValue &Hi) {
1576  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1577  RTLIB::SQRT_F32, RTLIB::SQRT_F64,
1578  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
1579  RTLIB::SQRT_PPCF128), Lo, Hi);
1580 }
1581 
1582 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
1583  SDValue &Hi) {
1584  ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
1585  RTLIB::SUB_F32,
1586  RTLIB::SUB_F64,
1587  RTLIB::SUB_F80,
1588  RTLIB::SUB_F128,
1589  RTLIB::SUB_PPCF128), Lo, Hi);
1590 }
1591 
1592 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
1593  SDValue &Lo, SDValue &Hi) {
1594  ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
1595  RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
1596  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
1597  RTLIB::TRUNC_PPCF128), Lo, Hi);
1598 }
1599 
1600 void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
1601  SDValue &Hi) {
1602  if (ISD::isNormalLoad(N)) {
1603  ExpandRes_NormalLoad(N, Lo, Hi);
1604  return;
1605  }
1606 
1607  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1608  LoadSDNode *LD = cast<LoadSDNode>(N);
1609  SDValue Chain = LD->getChain();
1610  SDValue Ptr = LD->getBasePtr();
1611  SDLoc dl(N);
1612 
1613  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
1614  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1615  assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1616 
1617  Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr,
1618  LD->getMemoryVT(), LD->getMemOperand());
1619 
1620  // Remember the chain.
1621  Chain = Hi.getValue(1);
1622 
1623  // The low part is zero.
1625  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1626 
1627  // Modified the chain - switch anything that used the old chain to use the
1628  // new one.
1629  ReplaceValueWith(SDValue(LD, 1), Chain);
1630 }
1631 
1632 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
1633  SDValue &Hi) {
1634  assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
1635  EVT VT = N->getValueType(0);
1636  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1637  bool Strict = N->isStrictFPOpcode();
1638  SDValue Src = N->getOperand(Strict ? 1 : 0);
1639  EVT SrcVT = Src.getValueType();
1640  bool isSigned = N->getOpcode() == ISD::SINT_TO_FP ||
1641  N->getOpcode() == ISD::STRICT_SINT_TO_FP;
1642  SDLoc dl(N);
1643  SDValue Chain = Strict ? N->getOperand(0) : DAG.getEntryNode();
1644 
1645  // TODO: Any other flags to propagate?
1646  SDNodeFlags Flags;
1647  Flags.setNoFPExcept(N->getFlags().hasNoFPExcept());
1648 
1649  // First do an SINT_TO_FP, whether the original was signed or unsigned.
1650  // When promoting partial word types to i32 we must honor the signedness,
1651  // though.
1652  if (SrcVT.bitsLE(MVT::i32)) {
1653  // The integer can be represented exactly in an f64.
1655  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1656  if (Strict) {
1657  Hi = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(NVT, MVT::Other),
1658  {Chain, Src}, Flags);
1659  Chain = Hi.getValue(1);
1660  } else
1661  Hi = DAG.getNode(N->getOpcode(), dl, NVT, Src);
1662  } else {
1663  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1664  if (SrcVT.bitsLE(MVT::i64)) {
1665  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1666  MVT::i64, Src);
1667  LC = RTLIB::SINTTOFP_I64_PPCF128;
1668  } else if (SrcVT.bitsLE(MVT::i128)) {
1669  Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
1670  LC = RTLIB::SINTTOFP_I128_PPCF128;
1671  }
1672  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
1673 
1675  CallOptions.setSExt(true);
1676  std::pair<SDValue, SDValue> Tmp =
1677  TLI.makeLibCall(DAG, LC, VT, Src, CallOptions, dl, Chain);
1678  if (Strict)
1679  Chain = Tmp.second;
1680  GetPairElements(Tmp.first, Lo, Hi);
1681  }
1682 
1683  // No need to complement for unsigned 32-bit integers
1684  if (isSigned || SrcVT.bitsLE(MVT::i32)) {
1685  if (Strict)
1686  ReplaceValueWith(SDValue(N, 1), Chain);
1687 
1688  return;
1689  }
1690 
1691  // Unsigned - fix up the SINT_TO_FP value just calculated.
1692  // FIXME: For unsigned i128 to ppc_fp128 conversion, we need to carefully
1693  // keep semantics correctness if the integer is not exactly representable
1694  // here. See ExpandLegalINT_TO_FP.
1695  Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
1696  SrcVT = Src.getValueType();
1697 
1698  // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128.
1699  static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
1700  static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
1701  static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
1702  ArrayRef<uint64_t> Parts;
1703 
1704  switch (SrcVT.getSimpleVT().SimpleTy) {
1705  default:
1706  llvm_unreachable("Unsupported UINT_TO_FP!");
1707  case MVT::i32:
1708  Parts = TwoE32;
1709  break;
1710  case MVT::i64:
1711  Parts = TwoE64;
1712  break;
1713  case MVT::i128:
1714  Parts = TwoE128;
1715  break;
1716  }
1717 
1718  // TODO: Are there other fast-math-flags to propagate to this FADD?
1719  SDValue NewLo = DAG.getConstantFP(
1720  APFloat(APFloat::PPCDoubleDouble(), APInt(128, Parts)), dl, MVT::ppcf128);
1721  if (Strict) {
1722  Lo = DAG.getNode(ISD::STRICT_FADD, dl, DAG.getVTList(VT, MVT::Other),
1723  {Chain, Hi, NewLo}, Flags);
1724  Chain = Lo.getValue(1);
1725  ReplaceValueWith(SDValue(N, 1), Chain);
1726  } else
1727  Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo);
1728  Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
1729  Lo, Hi, ISD::SETLT);
1730  GetPairElements(Lo, Lo, Hi);
1731 }
1732 
1733 
1734 //===----------------------------------------------------------------------===//
1735 // Float Operand Expansion
1736 //===----------------------------------------------------------------------===//
1737 
1738 /// ExpandFloatOperand - This method is called when the specified operand of the
1739 /// specified node is found to need expansion. At this point, all of the result
1740 /// types of the node are known to be legal, but other operands of the node may
1741 /// need promotion or expansion as well as the specified one.
1742 bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
1743  LLVM_DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n");
1744  SDValue Res = SDValue();
1745 
1746  // See if the target wants to custom expand this node.
1747  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1748  return false;
1749 
1750  switch (N->getOpcode()) {
1751  default:
1752 #ifndef NDEBUG
1753  dbgs() << "ExpandFloatOperand Op #" << OpNo << ": ";
1754  N->dump(&DAG); dbgs() << "\n";
1755 #endif
1756  llvm_unreachable("Do not know how to expand this operator's operand!");
1757 
1758  case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
1759  case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1760  case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1761 
1762  case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1763  case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1764  case ISD::STRICT_FP_ROUND:
1765  case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
1768  case ISD::FP_TO_SINT:
1769  case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_XINT(N); break;
1770  case ISD::LROUND: Res = ExpandFloatOp_LROUND(N); break;
1771  case ISD::LLROUND: Res = ExpandFloatOp_LLROUND(N); break;
1772  case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break;
1773  case ISD::LLRINT: Res = ExpandFloatOp_LLRINT(N); break;
1774  case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1775  case ISD::STRICT_FSETCC:
1776  case ISD::STRICT_FSETCCS:
1777  case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1778  case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1779  OpNo); break;
1780  }
1781 
1782  // If the result is null, the sub-method took care of registering results etc.
1783  if (!Res.getNode()) return false;
1784 
1785  // If the result is N, the sub-method updated N in place. Tell the legalizer
1786  // core about this.
1787  if (Res.getNode() == N)
1788  return true;
1789 
1790  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1791  "Invalid operand expansion");
1792 
1793  ReplaceValueWith(SDValue(N, 0), Res);
1794  return false;
1795 }
1796 
1797 /// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
1798 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1799 void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
1800  SDValue &NewRHS,
1801  ISD::CondCode &CCCode,
1802  const SDLoc &dl, SDValue &Chain,
1803  bool IsSignaling) {
1804  SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1805  GetExpandedFloat(NewLHS, LHSLo, LHSHi);
1806  GetExpandedFloat(NewRHS, RHSLo, RHSHi);
1807 
1808  assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
1809 
1810  // FIXME: This generated code sucks. We want to generate
1811  // FCMPU crN, hi1, hi2
1812  // BNE crN, L:
1813  // FCMPU crN, lo1, lo2
1814  // The following can be improved, but not that much.
1815  SDValue Tmp1, Tmp2, Tmp3, OutputChain;
1816  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
1817  RHSHi, ISD::SETOEQ, Chain, IsSignaling);
1818  OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue();
1819  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
1820  RHSLo, CCCode, OutputChain, IsSignaling);
1821  OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue();
1822  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1823  Tmp1 =
1824  DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, RHSHi,
1825  ISD::SETUNE, OutputChain, IsSignaling);
1826  OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue();
1827  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi,
1828  RHSHi, CCCode, OutputChain, IsSignaling);
1829  OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue();
1830  Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1831  NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
1832  NewRHS = SDValue(); // LHS is the result, not a compare.
1833  Chain = OutputChain;
1834 }
1835 
1836 SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
1837  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1838  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1839  SDValue Chain;
1840  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N), Chain);
1841 
1842  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1843  // against zero to select between true and false values.
1844  if (!NewRHS.getNode()) {
1845  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1846  CCCode = ISD::SETNE;
1847  }
1848 
1849  // Update N to have the operands specified.
1850  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1851  DAG.getCondCode(CCCode), NewLHS, NewRHS,
1852  N->getOperand(4)), 0);
1853 }
1854 
1855 SDValue DAGTypeLegalizer::ExpandFloatOp_FCOPYSIGN(SDNode *N) {
1856  assert(N->getOperand(1).getValueType() == MVT::ppcf128 &&
1857  "Logic only correct for ppcf128!");
1858  SDValue Lo, Hi;
1859  GetExpandedFloat(N->getOperand(1), Lo, Hi);
1860  // The ppcf128 value is providing only the sign; take it from the
1861  // higher-order double (which must have the larger magnitude).
1862  return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
1863  N->getValueType(0), N->getOperand(0), Hi);
1864 }
1865 
1866 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
1867  bool IsStrict = N->isStrictFPOpcode();
1868  assert(N->getOperand(IsStrict ? 1 : 0).getValueType() == MVT::ppcf128 &&
1869  "Logic only correct for ppcf128!");
1870  SDValue Lo, Hi;
1871  GetExpandedFloat(N->getOperand(IsStrict ? 1 : 0), Lo, Hi);
1872 
1873  if (!IsStrict)
1874  // Round it the rest of the way (e.g. to f32) if needed.
1875  return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
1876  N->getValueType(0), Hi, N->getOperand(1));
1877 
1878  // Eliminate the node if the input float type is the same as the output float
1879  // type.
1880  if (Hi.getValueType() == N->getValueType(0)) {
1881  // Connect the output chain to the input chain, unlinking the node.
1882  ReplaceValueWith(SDValue(N, 1), N->getOperand(0));
1883  ReplaceValueWith(SDValue(N, 0), Hi);
1884  return SDValue();
1885  }
1886 
1887  SDValue Expansion = DAG.getNode(ISD::STRICT_FP_ROUND, SDLoc(N),
1888  {N->getValueType(0), MVT::Other},
1889  {N->getOperand(0), Hi, N->getOperand(2)});
1890  ReplaceValueWith(SDValue(N, 1), Expansion.getValue(1));
1891  ReplaceValueWith(SDValue(N, 0), Expansion);
1892  return SDValue();
1893 }
1894 
1895 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_XINT(SDNode *N) {
1896  EVT RVT = N->getValueType(0);
1897  SDLoc dl(N);
1898 
1899  bool IsStrict = N->isStrictFPOpcode();
1900  bool Signed = N->getOpcode() == ISD::FP_TO_SINT ||
1901  N->getOpcode() == ISD::STRICT_FP_TO_SINT;
1902  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
1903  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1904 
1905  EVT NVT;
1906  RTLIB::Libcall LC = findFPToIntLibcall(Op.getValueType(), RVT, NVT, Signed);
1907  assert(LC != RTLIB::UNKNOWN_LIBCALL && NVT.isSimple() &&
1908  "Unsupported FP_TO_XINT!");
1910  std::pair<SDValue, SDValue> Tmp =
1911  TLI.makeLibCall(DAG, LC, NVT, Op, CallOptions, dl, Chain);
1912  if (!IsStrict)
1913  return Tmp.first;
1914 
1915  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1916  ReplaceValueWith(SDValue(N, 0), Tmp.first);
1917  return SDValue();
1918 }
1919 
1920 SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
1921  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1922  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1923  SDValue Chain;
1924  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N), Chain);
1925 
1926  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1927  // against zero to select between true and false values.
1928  if (!NewRHS.getNode()) {
1929  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1930  CCCode = ISD::SETNE;
1931  }
1932 
1933  // Update N to have the operands specified.
1934  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1935  N->getOperand(2), N->getOperand(3),
1936  DAG.getCondCode(CCCode)), 0);
1937 }
1938 
1939 SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
1940  bool IsStrict = N->isStrictFPOpcode();
1941  SDValue NewLHS = N->getOperand(IsStrict ? 1 : 0);
1942  SDValue NewRHS = N->getOperand(IsStrict ? 2 : 1);
1943  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
1944  ISD::CondCode CCCode =
1945  cast<CondCodeSDNode>(N->getOperand(IsStrict ? 3 : 2))->get();
1946  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N), Chain,
1947  N->getOpcode() == ISD::STRICT_FSETCCS);
1948 
1949  // FloatExpandSetCCOperands always returned a scalar.
1950  assert(!NewRHS.getNode() && "Expect to return scalar");
1951  assert(NewLHS.getValueType() == N->getValueType(0) &&
1952  "Unexpected setcc expansion!");
1953  if (Chain) {
1954  ReplaceValueWith(SDValue(N, 0), NewLHS);
1955  ReplaceValueWith(SDValue(N, 1), Chain);
1956  return SDValue();
1957  }
1958  return NewLHS;
1959 }
1960 
1961 SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
1962  if (ISD::isNormalStore(N))
1963  return ExpandOp_NormalStore(N, OpNo);
1964 
1965  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1966  assert(OpNo == 1 && "Can only expand the stored value so far");
1967  StoreSDNode *ST = cast<StoreSDNode>(N);
1968 
1969  SDValue Chain = ST->getChain();
1970  SDValue Ptr = ST->getBasePtr();
1971 
1972  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(),
1973  ST->getValue().getValueType());
1974  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1975  assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1976  (void)NVT;
1977 
1978  SDValue Lo, Hi;
1979  GetExpandedOp(ST->getValue(), Lo, Hi);
1980 
1981  return DAG.getTruncStore(Chain, SDLoc(N), Hi, Ptr,
1982  ST->getMemoryVT(), ST->getMemOperand());
1983 }
1984 
1985 SDValue DAGTypeLegalizer::ExpandFloatOp_LROUND(SDNode *N) {
1986  EVT RVT = N->getValueType(0);
1987  EVT RetVT = N->getOperand(0).getValueType();
1989  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1990  RTLIB::LROUND_F32,
1991  RTLIB::LROUND_F64,
1992  RTLIB::LROUND_F80,
1993  RTLIB::LROUND_F128,
1994  RTLIB::LROUND_PPCF128),
1995  RVT, N->getOperand(0), CallOptions, SDLoc(N)).first;
1996 }
1997 
1998 SDValue DAGTypeLegalizer::ExpandFloatOp_LLROUND(SDNode *N) {
1999  EVT RVT = N->getValueType(0);
2000  EVT RetVT = N->getOperand(0).getValueType();
2002  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2003  RTLIB::LLROUND_F32,
2004  RTLIB::LLROUND_F64,
2005  RTLIB::LLROUND_F80,
2006  RTLIB::LLROUND_F128,
2007  RTLIB::LLROUND_PPCF128),
2008  RVT, N->getOperand(0), CallOptions, SDLoc(N)).first;
2009 }
2010 
2011 SDValue DAGTypeLegalizer::ExpandFloatOp_LRINT(SDNode *N) {
2012  EVT RVT = N->getValueType(0);
2013  EVT RetVT = N->getOperand(0).getValueType();
2015  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2016  RTLIB::LRINT_F32,
2017  RTLIB::LRINT_F64,
2018  RTLIB::LRINT_F80,
2019  RTLIB::LRINT_F128,
2020  RTLIB::LRINT_PPCF128),
2021  RVT, N->getOperand(0), CallOptions, SDLoc(N)).first;
2022 }
2023 
2024 SDValue DAGTypeLegalizer::ExpandFloatOp_LLRINT(SDNode *N) {
2025  EVT RVT = N->getValueType(0);
2026  EVT RetVT = N->getOperand(0).getValueType();
2028  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
2029  RTLIB::LLRINT_F32,
2030  RTLIB::LLRINT_F64,
2031  RTLIB::LLRINT_F80,
2032  RTLIB::LLRINT_F128,
2033  RTLIB::LLRINT_PPCF128),
2034  RVT, N->getOperand(0), CallOptions, SDLoc(N)).first;
2035 }
2036 
2037 //===----------------------------------------------------------------------===//
2038 // Float Operand Promotion
2039 //===----------------------------------------------------------------------===//
2040 //
2041 
2043  if (OpVT == MVT::f16) {
2044  return ISD::FP16_TO_FP;
2045  } else if (RetVT == MVT::f16) {
2046  return ISD::FP_TO_FP16;
2047  }
2048 
2049  report_fatal_error("Attempt at an invalid promotion-related conversion");
2050 }
2051 
2052 bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
2053  LLVM_DEBUG(dbgs() << "Promote float operand " << OpNo << ": "; N->dump(&DAG);
2054  dbgs() << "\n");
2055  SDValue R = SDValue();
2056 
2057  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
2058  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2059  return false;
2060  }
2061 
2062  // Nodes that use a promotion-requiring floating point operand, but doesn't
2063  // produce a promotion-requiring floating point result, need to be legalized
2064  // to use the promoted float operand. Nodes that produce at least one
2065  // promotion-requiring floating point result have their operands legalized as
2066  // a part of PromoteFloatResult.
2067  switch (N->getOpcode()) {
2068  default:
2069  #ifndef NDEBUG
2070  dbgs() << "PromoteFloatOperand Op #" << OpNo << ": ";
2071  N->dump(&DAG); dbgs() << "\n";
2072  #endif
2073  llvm_unreachable("Do not know how to promote this operator's operand!");
2074 
2075  case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
2076  case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
2077  case ISD::FP_TO_SINT:
2078  case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;
2079  case ISD::FP_TO_SINT_SAT:
2080  case ISD::FP_TO_UINT_SAT:
2081  R = PromoteFloatOp_FP_TO_XINT_SAT(N, OpNo); break;
2082  case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
2083  case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
2084  case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
2085  case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
2086  }
2087 
2088  if (R.getNode())
2089  ReplaceValueWith(SDValue(N, 0), R);
2090  return false;
2091 }
2092 
2093 SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo) {
2094  SDValue Op = N->getOperand(0);
2095  EVT OpVT = Op->getValueType(0);
2096 
2097  SDValue Promoted = GetPromotedFloat(N->getOperand(0));
2098  EVT PromotedVT = Promoted->getValueType(0);
2099 
2100  // Convert the promoted float value to the desired IVT.
2101  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
2102  SDValue Convert = DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N),
2103  IVT, Promoted);
2104  // The final result type might not be an scalar so we need a bitcast. The
2105  // bitcast will be further legalized if needed.
2106  return DAG.getBitcast(N->getValueType(0), Convert);
2107 }
2108 
2109 // Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by
2110 // PromoteFloatRes_FCOPYSIGN.
2111 SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
2112  assert (OpNo == 1 && "Only Operand 1 must need promotion here");
2113  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2114 
2115  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
2116  N->getOperand(0), Op1);
2117 }
2118 
2119 // Convert the promoted float value to the desired integer type
2120 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {
2121  SDValue Op = GetPromotedFloat(N->getOperand(0));
2122  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
2123 }
2124 
2125 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N,
2126  unsigned OpNo) {
2127  SDValue Op = GetPromotedFloat(N->getOperand(0));
2128  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op,
2129  N->getOperand(1));
2130 }
2131 
2132 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo) {
2133  SDValue Op = GetPromotedFloat(N->getOperand(0));
2134  EVT VT = N->getValueType(0);
2135 
2136  // Desired VT is same as promoted type. Use promoted float directly.
2137  if (VT == Op->getValueType(0))
2138  return Op;
2139 
2140  // Else, extend the promoted float value to the desired VT.
2141  return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);
2142 }
2143 
2144 // Promote the float operands used for comparison. The true- and false-
2145 // operands have the same type as the result and are promoted, if needed, by
2146 // PromoteFloatRes_SELECT_CC
2147 SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo) {
2148  SDValue LHS = GetPromotedFloat(N->getOperand(0));
2149  SDValue RHS = GetPromotedFloat(N->getOperand(1));
2150 
2151  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
2152  LHS, RHS, N->getOperand(2), N->getOperand(3),
2153  N->getOperand(4));
2154 }
2155 
2156 // Construct a SETCC that compares the promoted values and sets the conditional
2157 // code.
2158 SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo) {
2159  EVT VT = N->getValueType(0);
2160  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2161  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2162  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2163 
2164  return DAG.getSetCC(SDLoc(N), VT, Op0, Op1, CCCode);
2165 
2166 }
2167 
2168 // Lower the promoted Float down to the integer value of same size and construct
2169 // a STORE of the integer value.
2170 SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
2171  StoreSDNode *ST = cast<StoreSDNode>(N);
2172  SDValue Val = ST->getValue();
2173  SDLoc DL(N);
2174 
2175  SDValue Promoted = GetPromotedFloat(Val);
2176  EVT VT = ST->getOperand(1).getValueType();
2177  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2178 
2179  SDValue NewVal;
2180  NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,
2181  IVT, Promoted);
2182 
2183  return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),
2184  ST->getMemOperand());
2185 }
2186 
2187 //===----------------------------------------------------------------------===//
2188 // Float Result Promotion
2189 //===----------------------------------------------------------------------===//
2190 
2191 void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
2192  LLVM_DEBUG(dbgs() << "Promote float result " << ResNo << ": "; N->dump(&DAG);
2193  dbgs() << "\n");
2194  SDValue R = SDValue();
2195 
2196  // See if the target wants to custom expand this node.
2197  if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
2198  LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
2199  return;
2200  }
2201 
2202  switch (N->getOpcode()) {
2203  // These opcodes cannot appear if promotion of FP16 is done in the backend
2204  // instead of Clang
2205  case ISD::FP16_TO_FP:
2206  case ISD::FP_TO_FP16:
2207  default:
2208 #ifndef NDEBUG
2209  dbgs() << "PromoteFloatResult #" << ResNo << ": ";
2210  N->dump(&DAG); dbgs() << "\n";
2211 #endif
2212  llvm_unreachable("Do not know how to promote this operator's result!");
2213 
2214  case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;
2215  case ISD::ConstantFP: R = PromoteFloatRes_ConstantFP(N); break;
2217  R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N); break;
2218  case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
2219 
2220  // Unary FP Operations
2221  case ISD::FABS:
2222  case ISD::FCBRT:
2223  case ISD::FCEIL:
2224  case ISD::FCOS:
2225  case ISD::FEXP:
2226  case ISD::FEXP2:
2227  case ISD::FFLOOR:
2228  case ISD::FLOG:
2229  case ISD::FLOG2:
2230  case ISD::FLOG10:
2231  case ISD::FNEARBYINT:
2232  case ISD::FNEG:
2233  case ISD::FRINT:
2234  case ISD::FROUND:
2235  case ISD::FROUNDEVEN:
2236  case ISD::FSIN:
2237  case ISD::FSQRT:
2238  case ISD::FTRUNC:
2239  case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
2240 
2241  // Binary FP Operations
2242  case ISD::FADD:
2243  case ISD::FDIV:
2244  case ISD::FMAXIMUM:
2245  case ISD::FMINIMUM:
2246  case ISD::FMAXNUM:
2247  case ISD::FMINNUM:
2248  case ISD::FMUL:
2249  case ISD::FPOW:
2250  case ISD::FREM:
2251  case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
2252 
2253  case ISD::FMA: // FMA is same as FMAD
2254  case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;
2255 
2256  case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break;
2257 
2258  case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
2259  case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break;
2260  case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
2261  case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
2262 
2263  case ISD::SINT_TO_FP:
2264  case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
2265  case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
2266  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
2267  case ISD::VECREDUCE_FADD:
2268  case ISD::VECREDUCE_FMUL:
2269  case ISD::VECREDUCE_FMIN:
2270  case ISD::VECREDUCE_FMAX:
2271  R = PromoteFloatRes_VECREDUCE(N);
2272  break;
2275  R = PromoteFloatRes_VECREDUCE_SEQ(N);
2276  break;
2277  }
2278 
2279  if (R.getNode())
2280  SetPromotedFloat(SDValue(N, ResNo), R);
2281 }
2282 
2283 // Bitcast from i16 to f16: convert the i16 to a f32 value instead.
2284 // At this point, it is not possible to determine if the bitcast value is
2285 // eventually stored to memory or promoted to f32 or promoted to a floating
2286 // point at a higher precision. Some of these cases are handled by FP_EXTEND,
2287 // STORE promotion handlers.
2288 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
2289  EVT VT = N->getValueType(0);
2290  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2291  // Input type isn't guaranteed to be a scalar int so bitcast if not. The
2292  // bitcast will be legalized further if necessary.
2293  EVT IVT = EVT::getIntegerVT(*DAG.getContext(),
2294  N->getOperand(0).getValueType().getSizeInBits());
2295  SDValue Cast = DAG.getBitcast(IVT, N->getOperand(0));
2296  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
2297 }
2298 
2299 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
2300  ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);
2301  EVT VT = N->getValueType(0);
2302  SDLoc DL(N);
2303 
2304  // Get the (bit-cast) APInt of the APFloat and build an integer constant
2305  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2306  SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(), DL,
2307  IVT);
2308 
2309  // Convert the Constant to the desired FP type
2310  // FIXME We might be able to do the conversion during compilation and get rid
2311  // of it from the object code
2312  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2313  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, C);
2314 }
2315 
2316 // If the Index operand is a constant, try to redirect the extract operation to
2317 // the correct legalized vector. If not, bit-convert the input vector to
2318 // equivalent integer vector. Extract the element as an (bit-cast) integer
2319 // value and convert it to the promoted type.
2320 SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
2321  SDLoc DL(N);
2322 
2323  // If the index is constant, try to extract the value from the legalized
2324  // vector type.
2325  if (isa<ConstantSDNode>(N->getOperand(1))) {
2326  SDValue Vec = N->getOperand(0);
2327  SDValue Idx = N->getOperand(1);
2328  EVT VecVT = Vec->getValueType(0);
2329  EVT EltVT = VecVT.getVectorElementType();
2330 
2331  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2332 
2333  switch (getTypeAction(VecVT)) {
2334  default: break;
2336  SDValue Res = GetScalarizedVector(N->getOperand(0));
2337  ReplaceValueWith(SDValue(N, 0), Res);
2338  return SDValue();
2339  }
2341  Vec = GetWidenedVector(Vec);
2342  SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
2343  ReplaceValueWith(SDValue(N, 0), Res);
2344  return SDValue();
2345  }
2347  SDValue Lo, Hi;
2348  GetSplitVector(Vec, Lo, Hi);
2349 
2350  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2351  SDValue Res;
2352  if (IdxVal < LoElts)
2353  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
2354  else
2355  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
2356  DAG.getConstant(IdxVal - LoElts, DL,
2357  Idx.getValueType()));
2358  ReplaceValueWith(SDValue(N, 0), Res);
2359  return SDValue();
2360  }
2361 
2362  }
2363  }
2364 
2365  // Bit-convert the input vector to the equivalent integer vector
2366  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
2367  EVT IVT = NewOp.getValueType().getVectorElementType();
2368 
2369  // Extract the element as an (bit-cast) integer value
2370  SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
2371  NewOp, N->getOperand(1));
2372 
2373  // Convert the element to the desired FP type
2374  EVT VT = N->getValueType(0);
2375  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2376  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, NewVal);
2377 }
2378 
2379 // FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the result
2380 // needs promotion, so does the argument X. Note that Y, if needed, will be
2381 // handled during operand promotion.
2382 SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(SDNode *N) {
2383  EVT VT = N->getValueType(0);
2384  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2385  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2386 
2387  SDValue Op1 = N->getOperand(1);
2388 
2389  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2390 }
2391 
2392 // Unary operation where the result and the operand have PromoteFloat type
2393 // action. Construct a new SDNode with the promoted float value of the old
2394 // operand.
2395 SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {
2396  EVT VT = N->getValueType(0);
2397  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2398  SDValue Op = GetPromotedFloat(N->getOperand(0));
2399 
2400  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
2401 }
2402 
2403 // Binary operations where the result and both operands have PromoteFloat type
2404 // action. Construct a new SDNode with the promoted float values of the old
2405 // operands.
2406 SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(SDNode *N) {
2407  EVT VT = N->getValueType(0);
2408  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2409  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2410  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2411  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
2412 }
2413 
2414 SDValue DAGTypeLegalizer::PromoteFloatRes_FMAD(SDNode *N) {
2415  EVT VT = N->getValueType(0);
2416  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2417  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2418  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2419  SDValue Op2 = GetPromotedFloat(N->getOperand(2));
2420 
2421  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
2422 }
2423 
2424 // Promote the Float (first) operand and retain the Integer (second) operand
2425 SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(SDNode *N) {
2426  EVT VT = N->getValueType(0);
2427  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2428  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2429  SDValue Op1 = N->getOperand(1);
2430 
2431  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2432 }
2433 
2434 // Explicit operation to reduce precision. Reduce the value to half precision
2435 // and promote it back to the legal type.
2436 SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
2437  SDLoc DL(N);
2438 
2439  SDValue Op = N->getOperand(0);
2440  EVT VT = N->getValueType(0);
2441  EVT OpVT = Op->getValueType(0);
2442  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2443  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2444 
2445  // Round promoted float to desired precision
2446  SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op);
2447  // Promote it back to the legal output type
2448  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
2449 }
2450 
2451 SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
2452  LoadSDNode *L = cast<LoadSDNode>(N);
2453  EVT VT = N->getValueType(0);
2454 
2455  // Load the value as an integer value with the same number of bits.
2456  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2457  SDValue newL = DAG.getLoad(
2458  L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
2459  L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT,
2460  L->getOriginalAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
2461  // Legalize the chain result by replacing uses of the old value chain with the
2462  // new one
2463  ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
2464 
2465  // Convert the integer value to the desired FP type
2466  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2467  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL);
2468 }
2469 
2470 // Construct a new SELECT node with the promoted true- and false- values.
2471 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) {
2472  SDValue TrueVal = GetPromotedFloat(N->getOperand(1));
2473  SDValue FalseVal = GetPromotedFloat(N->getOperand(2));
2474 
2475  return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
2476  N->getOperand(0), TrueVal, FalseVal);
2477 }
2478 
2479 // Construct a new SELECT_CC node with the promoted true- and false- values.
2480 // The operands used for comparison are promoted by PromoteFloatOp_SELECT_CC.
2481 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(SDNode *N) {
2482  SDValue TrueVal = GetPromotedFloat(N->getOperand(2));
2483  SDValue FalseVal = GetPromotedFloat(N->getOperand(3));
2484 
2485  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2486  TrueVal.getNode()->getValueType(0), N->getOperand(0),
2487  N->getOperand(1), TrueVal, FalseVal, N->getOperand(4));
2488 }
2489 
2490 // Construct a SDNode that transforms the SINT or UINT operand to the promoted
2491 // float type.
2492 SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(SDNode *N) {
2493  SDLoc DL(N);
2494  EVT VT = N->getValueType(0);
2495  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2496  SDValue NV = DAG.getNode(N->getOpcode(), DL, NVT, N->getOperand(0));
2497  // Round the value to the desired precision (that of the source type).
2498  return DAG.getNode(
2499  ISD::FP_EXTEND, DL, NVT,
2500  DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL)));
2501 }
2502 
2503 SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(SDNode *N) {
2504  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
2505  N->getValueType(0)));
2506 }
2507 
2508 SDValue DAGTypeLegalizer::PromoteFloatRes_VECREDUCE(SDNode *N) {
2509  // Expand and promote recursively.
2510  // TODO: This is non-optimal, but dealing with the concurrently happening
2511  // vector-legalization is non-trivial. We could do something similar to
2512  // PromoteFloatRes_EXTRACT_VECTOR_ELT here.
2513  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduce(N, DAG));
2514  return SDValue();
2515 }
2516 
2517 SDValue DAGTypeLegalizer::PromoteFloatRes_VECREDUCE_SEQ(SDNode *N) {
2518  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduceSeq(N, DAG));
2519  return SDValue();
2520 }
2521 
2522 SDValue DAGTypeLegalizer::BitcastToInt_ATOMIC_SWAP(SDNode *N) {
2523  EVT VT = N->getValueType(0);
2524 
2525  AtomicSDNode *AM = cast<AtomicSDNode>(N);
2526  SDLoc SL(N);
2527 
2528  SDValue CastVal = BitConvertToInteger(AM->getVal());
2529  EVT CastVT = CastVal.getValueType();
2530 
2531  SDValue NewAtomic
2532  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT,
2533  DAG.getVTList(CastVT, MVT::Other),
2534  { AM->getChain(), AM->getBasePtr(), CastVal },
2535  AM->getMemOperand());
2536 
2537  SDValue Result = NewAtomic;
2538 
2539  if (getTypeAction(VT) == TargetLowering::TypePromoteFloat) {
2540  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2541  Result = DAG.getNode(GetPromotionOpcode(VT, NFPVT), SL, NFPVT,
2542  NewAtomic);
2543  }
2544 
2545  // Legalize the chain result by replacing uses of the old value chain with the
2546  // new one
2547  ReplaceValueWith(SDValue(N, 1), NewAtomic.getValue(1));
2548 
2549  return Result;
2550 
2551 }
2552 
2553 //===----------------------------------------------------------------------===//
2554 // Half Result Soft Promotion
2555 //===----------------------------------------------------------------------===//
2556 
2557 void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
2558  LLVM_DEBUG(dbgs() << "Soft promote half result " << ResNo << ": ";
2559  N->dump(&DAG); dbgs() << "\n");
2560  SDValue R = SDValue();
2561 
2562  // See if the target wants to custom expand this node.
2563  if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
2564  LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
2565  return;
2566  }
2567 
2568  switch (N->getOpcode()) {
2569  default:
2570 #ifndef NDEBUG
2571  dbgs() << "SoftPromoteHalfResult #" << ResNo << ": ";
2572  N->dump(&DAG); dbgs() << "\n";
2573 #endif
2574  llvm_unreachable("Do not know how to soft promote this operator's result!");
2575 
2576  case ISD::BITCAST: R = SoftPromoteHalfRes_BITCAST(N); break;
2577  case ISD::ConstantFP: R = SoftPromoteHalfRes_ConstantFP(N); break;
2579  R = SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(N); break;
2580  case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break;
2581  case ISD::STRICT_FP_ROUND:
2582  case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break;
2583 
2584  // Unary FP Operations
2585  case ISD::FABS:
2586  case ISD::FCBRT:
2587  case ISD::FCEIL:
2588  case ISD::FCOS:
2589  case ISD::FEXP:
2590  case ISD::FEXP2:
2591  case ISD::FFLOOR:
2592  case ISD::FLOG:
2593  case ISD::FLOG2:
2594  case ISD::FLOG10:
2595  case ISD::FNEARBYINT:
2596  case ISD::FNEG:
2597  case ISD::FREEZE:
2598  case ISD::FRINT:
2599  case ISD::FROUND:
2600  case ISD::FROUNDEVEN:
2601  case ISD::FSIN:
2602  case ISD::FSQRT:
2603  case ISD::FTRUNC:
2604  case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break;
2605 
2606  // Binary FP Operations
2607  case ISD::FADD:
2608  case ISD::FDIV:
2609  case ISD::FMAXIMUM:
2610  case ISD::FMINIMUM:
2611  case ISD::FMAXNUM:
2612  case ISD::FMINNUM:
2613  case ISD::FMUL:
2614  case ISD::FPOW:
2615  case ISD::FREM:
2616  case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break;
2617 
2618  case ISD::FMA: // FMA is same as FMAD
2619  case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break;
2620 
2621  case ISD::FPOWI: R = SoftPromoteHalfRes_FPOWI(N); break;
2622 
2623  case ISD::LOAD: R = SoftPromoteHalfRes_LOAD(N); break;
2624  case ISD::SELECT: R = SoftPromoteHalfRes_SELECT(N); break;
2625  case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break;
2626  case ISD::SINT_TO_FP:
2627  case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break;
2628  case ISD::UNDEF: R = SoftPromoteHalfRes_UNDEF(N); break;
2629  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
2630  case ISD::VECREDUCE_FADD:
2631  case ISD::VECREDUCE_FMUL:
2632  case ISD::VECREDUCE_FMIN:
2633  case ISD::VECREDUCE_FMAX:
2634  R = SoftPromoteHalfRes_VECREDUCE(N);
2635  break;
2638  R = SoftPromoteHalfRes_VECREDUCE_SEQ(N);
2639  break;
2640  }
2641 
2642  if (R.getNode())
2643  SetSoftPromotedHalf(SDValue(N, ResNo), R);
2644 }
2645 
2646 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_BITCAST(SDNode *N) {
2647  return BitConvertToInteger(N->getOperand(0));
2648 }
2649 
2650 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_ConstantFP(SDNode *N) {
2651  ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
2652 
2653  // Get the (bit-cast) APInt of the APFloat and build an integer constant
2654  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
2655  MVT::i16);
2656 }
2657 
2658 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(SDNode *N) {
2659  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
2660  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2661  NewOp.getValueType().getVectorElementType(), NewOp,
2662  N->getOperand(1));
2663 }
2664 
2665 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FCOPYSIGN(SDNode *N) {
2666  SDValue LHS = GetSoftPromotedHalf(N->getOperand(0));
2667  SDValue RHS = BitConvertToInteger(N->getOperand(1));
2668  SDLoc dl(N);
2669 
2670  EVT LVT = LHS.getValueType();
2671  EVT RVT = RHS.getValueType();
2672 
2673  unsigned LSize = LVT.getSizeInBits();
2674  unsigned RSize = RVT.getSizeInBits();
2675 
2676  // First get the sign bit of second operand.
2677  SDValue SignBit = DAG.getNode(
2678  ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
2679  DAG.getConstant(RSize - 1, dl,
2680  TLI.getShiftAmountTy(RVT, DAG.getDataLayout())));
2681  SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
2682 
2683  // Shift right or sign-extend it if the two operands have different types.
2684  int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
2685  if (SizeDiff > 0) {
2686  SignBit =
2687  DAG.getNode(ISD::SRL, dl, RVT, SignBit,
2688  DAG.getConstant(SizeDiff, dl,
2689  TLI.getShiftAmountTy(SignBit.getValueType(),
2690  DAG.getDataLayout())));
2691  SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
2692  } else if (SizeDiff < 0) {
2693  SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
2694  SignBit =
2695  DAG.getNode(ISD::SHL, dl, LVT, SignBit,
2696  DAG.getConstant(-SizeDiff, dl,
2697  TLI.getShiftAmountTy(SignBit.getValueType(),
2698  DAG.getDataLayout())));
2699  }
2700 
2701  // Clear the sign bit of the first operand.
2702  SDValue Mask = DAG.getNode(
2703  ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
2704  DAG.getConstant(LSize - 1, dl,
2705  TLI.getShiftAmountTy(LVT, DAG.getDataLayout())));
2706  Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
2707  LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
2708 
2709  // Or the value with the sign bit.
2710  return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
2711 }
2712 
2713 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FMAD(SDNode *N) {
2714  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2715  SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0));
2716  SDValue Op1 = GetSoftPromotedHalf(N->getOperand(1));
2717  SDValue Op2 = GetSoftPromotedHalf(N->getOperand(2));
2718  SDLoc dl(N);
2719 
2720  // Promote to the larger FP type.
2721  Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0);
2722  Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1);
2723  Op2 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op2);
2724 
2725  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, Op0, Op1, Op2);
2726 
2727  // Convert back to FP16 as an integer.
2728  return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res);
2729 }
2730 
2731 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FPOWI(SDNode *N) {
2732  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2733  SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0));
2734  SDValue Op1 = N->getOperand(1);
2735  SDLoc dl(N);
2736 
2737  Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0);
2738 
2739  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, Op0, Op1);
2740 
2741  // Convert back to FP16 as an integer.
2742  return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res);
2743 }
2744 
2745 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FP_ROUND(SDNode *N) {
2746  if (N->isStrictFPOpcode()) {
2747  SDValue Res =
2749  {N->getOperand(0), N->getOperand(1)});
2750  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2751  return Res;
2752  }
2753 
2754  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), MVT::i16, N->getOperand(0));
2755 }
2756 
2757 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) {
2758  LoadSDNode *L = cast<LoadSDNode>(N);
2759 
2760  // Load the value as an integer value with the same number of bits.
2761  assert(L->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension!");
2762  SDValue NewL =
2764  SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(),
2766  L->getMemOperand()->getFlags(), L->getAAInfo());
2767  // Legalize the chain result by replacing uses of the old value chain with the
2768  // new one
2769  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
2770  return NewL;
2771 }
2772 
2773 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_SELECT(SDNode *N) {
2774  SDValue Op1 = GetSoftPromotedHalf(N->getOperand(1));
2775  SDValue Op2 = GetSoftPromotedHalf(N->getOperand(2));
2776  return DAG.getSelect(SDLoc(N), Op1.getValueType(), N->getOperand(0), Op1,
2777  Op2);
2778 }
2779 
2780 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_SELECT_CC(SDNode *N) {
2781  SDValue Op2 = GetSoftPromotedHalf(N->getOperand(2));
2782  SDValue Op3 = GetSoftPromotedHalf(N->getOperand(3));
2783  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), Op2.getValueType(),
2784  N->getOperand(0), N->getOperand(1), Op2, Op3,
2785  N->getOperand(4));
2786 }
2787 
2788 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_XINT_TO_FP(SDNode *N) {
2789  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2790  SDLoc dl(N);
2791 
2792  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
2793 
2794  // Round the value to the softened type.
2795  return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res);
2796 }
2797 
2798 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_UNDEF(SDNode *N) {
2799  return DAG.getUNDEF(MVT::i16);
2800 }
2801 
2802 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_UnaryOp(SDNode *N) {
2803  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2804  SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
2805  SDLoc dl(N);
2806 
2807  // Promote to the larger FP type.
2808  Op = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op);
2809 
2810  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, Op);
2811 
2812  // Convert back to FP16 as an integer.
2813  return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res);
2814 }
2815 
2816 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_BinOp(SDNode *N) {
2817  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2818  SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0));
2819  SDValue Op1 = GetSoftPromotedHalf(N->getOperand(1));
2820  SDLoc dl(N);
2821 
2822  // Promote to the larger FP type.
2823  Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0);
2824  Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1);
2825 
2826  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, Op0, Op1);
2827 
2828  // Convert back to FP16 as an integer.
2829  return DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, Res);
2830 }
2831 
2832 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_VECREDUCE(SDNode *N) {
2833  // Expand and soften recursively.
2834  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduce(N, DAG));
2835  return SDValue();
2836 }
2837 
2838 SDValue DAGTypeLegalizer::SoftPromoteHalfRes_VECREDUCE_SEQ(SDNode *N) {
2839  // Expand and soften.
2840  ReplaceValueWith(SDValue(N, 0), TLI.expandVecReduceSeq(N, DAG));
2841  return SDValue();
2842 }
2843 
2844 //===----------------------------------------------------------------------===//
2845 // Half Operand Soft Promotion
2846 //===----------------------------------------------------------------------===//
2847 
2848 bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
2849  LLVM_DEBUG(dbgs() << "Soft promote half operand " << OpNo << ": ";
2850  N->dump(&DAG); dbgs() << "\n");
2851  SDValue Res = SDValue();
2852 
2853  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
2854  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
2855  return false;
2856  }
2857 
2858  // Nodes that use a promotion-requiring floating point operand, but doesn't
2859  // produce a soft promotion-requiring floating point result, need to be
2860  // legalized to use the soft promoted float operand. Nodes that produce at
2861  // least one soft promotion-requiring floating point result have their
2862  // operands legalized as a part of PromoteFloatResult.
2863  switch (N->getOpcode()) {
2864  default:
2865  #ifndef NDEBUG
2866  dbgs() << "SoftPromoteHalfOperand Op #" << OpNo << ": ";
2867  N->dump(&DAG); dbgs() << "\n";
2868  #endif
2869  llvm_unreachable("Do not know how to soft promote this operator's operand!");
2870 
2871  case ISD::BITCAST: Res = SoftPromoteHalfOp_BITCAST(N); break;
2872  case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
2873  case ISD::FP_TO_SINT:
2874  case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
2875  case ISD::FP_TO_SINT_SAT:
2876  case ISD::FP_TO_UINT_SAT:
2877  Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
2878  case ISD::STRICT_FP_EXTEND:
2879  case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break;
2880  case ISD::SELECT_CC: Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
2881  case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break;
2882  case ISD::STORE: Res = SoftPromoteHalfOp_STORE(N, OpNo); break;
2883  }
2884 
2885  if (!Res.getNode())
2886  return false;
2887 
2888  assert(Res.getNode() != N && "Expected a new node!");
2889 
2890  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2891  "Invalid operand expansion");
2892 
2893  ReplaceValueWith(SDValue(N, 0), Res);
2894  return false;
2895 }
2896 
2897 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_BITCAST(SDNode *N) {
2898  SDValue Op0 = GetSoftPromotedHalf(N->getOperand(0));
2899 
2900  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Op0);
2901 }
2902 
2903 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FCOPYSIGN(SDNode *N,
2904  unsigned OpNo) {
2905  assert(OpNo == 1 && "Only Operand 1 must need promotion here");
2906  SDValue Op1 = N->getOperand(1);
2907  SDLoc dl(N);
2908 
2909  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op1.getValueType());
2910 
2911  Op1 = GetSoftPromotedHalf(Op1);
2912  Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1);
2913 
2914  return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), N->getOperand(0),
2915  Op1);
2916 }
2917 
2918 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
2919  bool IsStrict = N->isStrictFPOpcode();
2920  SDValue Op = GetSoftPromotedHalf(N->getOperand(IsStrict ? 1 : 0));
2921 
2922  if (IsStrict) {
2923  SDValue Res =
2925  {N->getValueType(0), MVT::Other}, {N->getOperand(0), Op});
2926  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2927  ReplaceValueWith(SDValue(N, 0), Res);
2928  return SDValue();
2929  }
2930 
2931  return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), Op);
2932 }
2933 
2934 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
2935  SDValue Op = N->getOperand(0);
2936  SDLoc dl(N);
2937 
2938  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
2939 
2940  Op = GetSoftPromotedHalf(Op);
2941 
2942  SDValue Res = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op);
2943 
2944  return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Res);
2945 }
2946 
2947 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N) {
2948  SDValue Op = N->getOperand(0);
2949  SDLoc dl(N);
2950 
2951  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
2952 
2953  Op = GetSoftPromotedHalf(Op);
2954 
2955  SDValue Res = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op);
2956 
2957  return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Res,
2958  N->getOperand(1));
2959 }
2960 
2961 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_SELECT_CC(SDNode *N,
2962  unsigned OpNo) {
2963  assert(OpNo == 0 && "Can only soften the comparison values");
2964  SDValue Op0 = N->getOperand(0);
2965  SDValue Op1 = N->getOperand(1);
2966  SDLoc dl(N);
2967 
2968  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op0.getValueType());
2969 
2970  Op0 = GetSoftPromotedHalf(Op0);
2971  Op1 = GetSoftPromotedHalf(Op1);
2972 
2973  // Promote to the larger FP type.
2974  Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0);
2975  Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1);
2976 
2977  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), Op0, Op1,
2978  N->getOperand(2), N->getOperand(3), N->getOperand(4));
2979 }
2980 
2981 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_SETCC(SDNode *N) {
2982  SDValue Op0 = N->getOperand(0);
2983  SDValue Op1 = N->getOperand(1);
2984  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2985  SDLoc dl(N);
2986 
2987  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op0.getValueType());
2988 
2989  Op0 = GetSoftPromotedHalf(Op0);
2990  Op1 = GetSoftPromotedHalf(Op1);
2991 
2992  // Promote to the larger FP type.
2993  Op0 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op0);
2994  Op1 = DAG.getNode(ISD::FP16_TO_FP, dl, NVT, Op1);
2995 
2996  return DAG.getSetCC(SDLoc(N), N->getValueType(0), Op0, Op1, CCCode);
2997 }
2998 
2999 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo) {
3000  assert(OpNo == 1 && "Can only soften the stored value!");
3001  StoreSDNode *ST = cast<StoreSDNode>(N);
3002  SDValue Val = ST->getValue();
3003  SDLoc dl(N);
3004 
3005  assert(!ST->isTruncatingStore() && "Unexpected truncating store.");
3006  SDValue Promoted = GetSoftPromotedHalf(Val);
3007  return DAG.getStore(ST->getChain(), dl, Promoted, ST->getBasePtr(),
3008  ST->getMemOperand());
3009 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:862
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:874
llvm::ISD::STRICT_FP_ROUND
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:445
llvm::ISD::isUNINDEXEDStore
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
Definition: SelectionDAGNodes.h:2726
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:490
llvm::LoadSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2276
llvm::ISD::STRICT_FSETCC
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:456
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4544
llvm::ISD::STRICT_FSQRT
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:392
llvm
Definition: AllocatorList.h:23
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Definition: SelectionDAGNodes.h:958
llvm::ISD::STRICT_FSIN
@ STRICT_FSIN
Definition: ISDOpcodes.h:395
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:623
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:838
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1366
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1321
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:888
llvm::ISD::STRICT_FMAXNUM
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:404
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:56
llvm::TargetLowering::expandVecReduce
SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const
Expand a VECREDUCE_* into an explicit calculation.
Definition: TargetLowering.cpp:8503
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::ISD::STRICT_UINT_TO_FP
@ STRICT_UINT_TO_FP
Definition: ISDOpcodes.h:430
llvm::ISD::STRICT_FMINNUM
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:405
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:45
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:791
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1361
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:8080
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
ErrorHandling.h
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1326
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:865
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1349
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:2828
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:460
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:775
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2256
llvm::SelectionDAG::EVTToAPFloatSemantics
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
Definition: SelectionDAG.h:1586
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7409
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:692
llvm::ISD::STRICT_FPOW
@ STRICT_FPOW
Definition: ISDOpcodes.h:393
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1214
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ore::NV
DiagnosticInfoOptimizationBase::Argument NV
Definition: OptimizationRemarkEmitter.h:136
llvm::tgtok::FalseVal
@ FalseVal
Definition: TGLexer.h:61
GetFPLibCall
static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128)
GetFPLibCall - Return the right libcall for the given floating point type.
Definition: LegalizeFloatTypes.cpp:31
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:229
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1198
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1344
llvm::EVT::bitsLE
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:273
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:209
llvm::ISD::STRICT_FLOG
@ STRICT_FLOG
Definition: ISDOpcodes.h:399
llvm::ISD::STRICT_FP_TO_UINT
@ STRICT_FP_TO_UINT
Definition: ISDOpcodes.h:423
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:857
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:445
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:180
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Definition: TargetLoweringBase.cpp:918
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
llvm::ISD::STRICT_FLOG2
@ STRICT_FLOG2
Definition: ISDOpcodes.h:401
llvm::ISD::STRICT_FROUND
@ STRICT_FROUND
Definition: ISDOpcodes.h:408
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:32
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:875
llvm::ISD::STRICT_FDIV
@ STRICT_FDIV
Definition: ISDOpcodes.h:384
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:953
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7359
llvm::ISD::STRICT_FP_TO_SINT
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:422
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:684
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:669
llvm::SelectionDAG::UpdateNodeOperands
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
Definition: SelectionDAG.cpp:8170
llvm::ISD::STRICT_FRINT
@ STRICT_FRINT
Definition: ISDOpcodes.h:402
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::SelectionDAG::getTruncStore
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7460
llvm::SelectionDAG::getVAArg
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
Definition: SelectionDAG.cpp:7839
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:947
llvm::ISD::STRICT_FNEARBYINT
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:403
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1347
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:263
llvm::ISD::STRICT_FP16_TO_FP
@ STRICT_FP16_TO_FP
Definition: ISDOpcodes.h:850
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:873
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:725
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:305
llvm::ISD::STRICT_FLOG10
@ STRICT_FLOG10
Definition: ISDOpcodes.h:400
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:877
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::isUNINDEXEDLoad
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
Definition: SelectionDAGNodes.h:2702
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:729
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:872
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:871
llvm::ISD::FP16_TO_FP
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:848
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
llvm::MVT::FIRST_INTEGER_VALUETYPE
@ FIRST_INTEGER_VALUETYPE
Definition: MachineValueType.h:47
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::TargetLowering::makeLibCall
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
Definition: TargetLowering.cpp:136
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:859
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:942
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1212
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:54
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:863
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:371
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1357
llvm::ISD::STRICT_FSETCCS
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:457
llvm::LLVMContext::emitError
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Definition: LLVMContext.cpp:251
llvm::DataLayout::isBigEndian
bool isBigEndian() const
Definition: DataLayout.h:242
llvm::TargetLowering::softenSetCCOperands
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const
Soften the operands of a comparison.
Definition: TargetLowering.cpp:280
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:901
findFPToIntLibcall
static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, bool Signed)
Definition: LegalizeFloatTypes.cpp:917
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:866
llvm::TargetLowering::MakeLibCallOptions
This structure is used to pass arguments to makeLibCall function.
Definition: TargetLowering.h:3869
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1215
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:464
llvm::APInt::getRawData
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:694
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:776
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1580
llvm::MemSDNode::getMemOperand
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Definition: SelectionDAGNodes.h:1330
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:911
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1471
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:489
llvm::ISD::STRICT_LRINT
@ STRICT_LRINT
Definition: ISDOpcodes.h:413
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:505
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1211
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1199
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:878
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:7845
llvm::ISD::FP_TO_FP16
@ FP_TO_FP16
Definition: ISDOpcodes.h:849
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:470
llvm::LoadSDNode::getExtensionType
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Definition: SelectionDAGNodes.h:2271
llvm::MemSDNode::getOriginalAlign
Align getOriginalAlign() const
Returns alignment and volatility of the memory access.
Definition: SelectionDAGNodes.h:1263
llvm::ISD::STRICT_LROUND
@ STRICT_LROUND
Definition: ISDOpcodes.h:411
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2284
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::APFloatBase::PPCDoubleDouble
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
Definition: APFloat.cpp:185
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::SelectionDAG::getAtomic
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition: SelectionDAG.cpp:7086
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::SelectionDAG::getSelectCC
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
Definition: SelectionDAG.h:1083
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::EVT::isByteSized
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:210
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2056
LegalizeTypes.h
llvm::ISD::STRICT_LLRINT
@ STRICT_LLRINT
Definition: ISDOpcodes.h:414
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::ISD::STRICT_FROUNDEVEN
@ STRICT_FROUNDEVEN
Definition: ISDOpcodes.h:409
llvm::ISD::STRICT_FEXP
@ STRICT_FEXP
Definition: ISDOpcodes.h:397
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:902
llvm::MemSDNode::getAAInfo
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Definition: SelectionDAGNodes.h:1296
llvm::ISD::STRICT_FCOS
@ STRICT_FCOS
Definition: ISDOpcodes.h:396
llvm::ArrayRef< uint64_t >
llvm::ISD::isNormalLoad
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Definition: SelectionDAGNodes.h:2671
llvm::SelectionDAG::getSelect
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
Definition: SelectionDAG.h:1071
llvm::APInt::getAllOnesValue
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:567
llvm::ISD::STRICT_FTRUNC
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:410
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:301
llvm::SDNodeFlags::setNoFPExcept
void setNoFPExcept(bool b)
Definition: SelectionDAGNodes.h:421
llvm::ISD::STRICT_SINT_TO_FP
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition: ISDOpcodes.h:429
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:879
llvm::ISD::STRICT_FSUB
@ STRICT_FSUB
Definition: ISDOpcodes.h:382
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::UNDEF
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:204
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:867
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:868
llvm::ISD::STRICT_FP_EXTEND
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:450
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:373
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1125
llvm::SelectionDAG::getConstantFP
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1527
llvm::APInt::clearBit
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1525
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:624
llvm::LoadSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2275
llvm::AtomicSDNode
This is an SDNode representing atomic operations.
Definition: SelectionDAGNodes.h:1399
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:858
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1364
llvm::ISD::STRICT_FMUL
@ STRICT_FMUL
Definition: ISDOpcodes.h:383
llvm::ISD::STRICT_FMA
@ STRICT_FMA
Definition: ISDOpcodes.h:386
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:889
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:233
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:790
llvm::TargetLowering::MakeLibCallOptions::setTypeListBeforeSoften
MakeLibCallOptions & setTypeListBeforeSoften(ArrayRef< EVT > OpsVT, EVT RetVT, bool Value=true)
Definition: TargetLowering.h:3904
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ISD::STRICT_FP_TO_FP16
@ STRICT_FP_TO_FP16
Definition: ISDOpcodes.h:851
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:861
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:516
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:869
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:860
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::ISD::BUILD_VECTOR
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:485
llvm::ISD::STRICT_FCEIL
@ STRICT_FCEIL
Definition: ISDOpcodes.h:406
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::LSBaseSDNode::getAddressingMode
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc,...
Definition: SelectionDAGNodes.h:2239
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:955
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:350
llvm::SDNodeFlags
These are IR-level optimization flags that may be propagated to SDNodes.
Definition: SelectionDAGNodes.h:371
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:912
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:730
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:214
llvm::AtomicSDNode::getVal
const SDValue & getVal() const
Definition: SelectionDAGNodes.h:1409
llvm::ISD::STRICT_FFLOOR
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:407
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:293
llvm::APInt::getSignMask
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:560
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:823
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:372
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:647
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:375
llvm::TargetLowering::expandFP_TO_INT_SAT
SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const
Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
Definition: TargetLowering.cpp:8594
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:51
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:211
N
#define N
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:649
llvm::ISD::STRICT_FADD
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:381
llvm::ISD::STRICT_LLROUND
@ STRICT_LLROUND
Definition: ISDOpcodes.h:412
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:876
llvm::ISD::STRICT_FREM
@ STRICT_FREM
Definition: ISDOpcodes.h:385
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:399
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:856
llvm::ISD::STRICT_FEXP2
@ STRICT_FEXP2
Definition: ISDOpcodes.h:398
llvm::ISD::BUILD_PAIR
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:222
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1022
llvm::EVT::bitsGE
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:257
llvm::ISD::STRICT_FPOWI
@ STRICT_FPOWI
Definition: ISDOpcodes.h:394
llvm::ISD::isNormalStore
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
Definition: SelectionDAGNodes.h:2709
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:48
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:212
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
raw_ostream.h
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:870
llvm::TargetLowering::expandVecReduceSeq
SDValue expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const
Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.
Definition: TargetLowering.cpp:8543
llvm::TargetLowering::MakeLibCallOptions::setSExt
MakeLibCallOptions & setSExt(bool Value=true)
Definition: TargetLowering.h:3884
llvm::tgtok::TrueVal
@ TrueVal
Definition: TGLexer.h:61
llvm::ConstantFPSDNode::getValueAPF
const APFloat & getValueAPF() const
Definition: SelectionDAGNodes.h:1591
llvm::ISD::FCANONICALIZE
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:477
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:864
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7376
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:804
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:209
llvm::MemSDNode::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: SelectionDAGNodes.h:1332
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1054
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:215
GetPromotionOpcode
static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT)
Definition: LegalizeFloatTypes.cpp:2042
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::SelectionDAG::getCondCode
SDValue getCondCode(ISD::CondCode Cond)
Definition: SelectionDAG.cpp:1738
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:374