LLVM  14.0.0git
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstddef>
60 #include <cstdint>
61 #include <cstring>
62 #include <iterator>
63 #include <string>
64 #include <tuple>
65 #include <utility>
66 
67 using namespace llvm;
68 
70  "jump-is-expensive", cl::init(false),
71  cl::desc("Do not create extra branches to split comparison logic."),
72  cl::Hidden);
73 
75  ("min-jump-table-entries", cl::init(4), cl::Hidden,
76  cl::desc("Set minimum number of entries to use a jump table."));
77 
79  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
80  cl::desc("Set maximum size of jump tables."));
81 
82 /// Minimum jump table density for normal functions.
83 static cl::opt<unsigned>
84  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
85  cl::desc("Minimum density for building a jump table in "
86  "a normal function"));
87 
88 /// Minimum jump table density for -Os or -Oz functions.
90  "optsize-jump-table-density", cl::init(40), cl::Hidden,
91  cl::desc("Minimum density for building a jump table in "
92  "an optsize function"));
93 
94 // FIXME: This option is only to test if the strict fp operation processed
95 // correctly by preventing mutating strict fp operation to normal fp operation
96 // during development. When the backend supports strict float operation, this
97 // option will be meaningless.
98 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
99  cl::desc("Don't mutate strict-float node to a legalize node"),
100  cl::init(false), cl::Hidden);
101 
102 static bool darwinHasSinCos(const Triple &TT) {
103  assert(TT.isOSDarwin() && "should be called with darwin triple");
104  // Don't bother with 32 bit x86.
105  if (TT.getArch() == Triple::x86)
106  return false;
107  // Macos < 10.9 has no sincos_stret.
108  if (TT.isMacOSX())
109  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
110  // iOS < 7.0 has no sincos_stret.
111  if (TT.isiOS())
112  return !TT.isOSVersionLT(7, 0);
113  // Any other darwin such as WatchOS/TvOS is new enough.
114  return true;
115 }
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
127  if (TT.isPPC()) {
128  setLibcallName(RTLIB::ADD_F128, "__addkf3");
129  setLibcallName(RTLIB::SUB_F128, "__subkf3");
130  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
131  setLibcallName(RTLIB::DIV_F128, "__divkf3");
132  setLibcallName(RTLIB::POWI_F128, "__powikf2");
133  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
134  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
135  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
136  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
137  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
139  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
140  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
142  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
143  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
144  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
145  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
146  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
147  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
148  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
149  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
150  setLibcallName(RTLIB::UNE_F128, "__nekf2");
151  setLibcallName(RTLIB::OGE_F128, "__gekf2");
152  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
153  setLibcallName(RTLIB::OLE_F128, "__lekf2");
154  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
155  setLibcallName(RTLIB::UO_F128, "__unordkf2");
156  }
157 
158  // A few names are different on particular architectures or environments.
159  if (TT.isOSDarwin()) {
160  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
161  // of the gnueabi-style __gnu_*_ieee.
162  // FIXME: What about other targets?
163  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
164  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
165 
166  // Some darwins have an optimized __bzero/bzero function.
167  switch (TT.getArch()) {
168  case Triple::x86:
169  case Triple::x86_64:
170  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
171  setLibcallName(RTLIB::BZERO, "__bzero");
172  break;
173  case Triple::aarch64:
174  case Triple::aarch64_32:
175  setLibcallName(RTLIB::BZERO, "bzero");
176  break;
177  default:
178  break;
179  }
180 
181  if (darwinHasSinCos(TT)) {
182  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
183  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
184  if (TT.isWatchABI()) {
185  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
187  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
189  }
190  }
191  } else {
192  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
193  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
194  }
195 
196  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
197  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
198  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
199  setLibcallName(RTLIB::SINCOS_F64, "sincos");
200  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
201  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
202  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
203  }
204 
205  if (TT.isPS4CPU()) {
206  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
207  setLibcallName(RTLIB::SINCOS_F64, "sincos");
208  }
209 
210  if (TT.isOSOpenBSD()) {
211  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
212  }
213 }
214 
215 /// GetFPLibCall - Helper to return the right libcall for the given floating
216 /// point type, or UNKNOWN_LIBCALL if there is none.
218  RTLIB::Libcall Call_F32,
219  RTLIB::Libcall Call_F64,
220  RTLIB::Libcall Call_F80,
221  RTLIB::Libcall Call_F128,
222  RTLIB::Libcall Call_PPCF128) {
223  return
224  VT == MVT::f32 ? Call_F32 :
225  VT == MVT::f64 ? Call_F64 :
226  VT == MVT::f80 ? Call_F80 :
227  VT == MVT::f128 ? Call_F128 :
228  VT == MVT::ppcf128 ? Call_PPCF128 :
229  RTLIB::UNKNOWN_LIBCALL;
230 }
231 
232 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
233 /// UNKNOWN_LIBCALL if there is none.
235  if (OpVT == MVT::f16) {
236  if (RetVT == MVT::f32)
237  return FPEXT_F16_F32;
238  if (RetVT == MVT::f64)
239  return FPEXT_F16_F64;
240  if (RetVT == MVT::f80)
241  return FPEXT_F16_F80;
242  if (RetVT == MVT::f128)
243  return FPEXT_F16_F128;
244  } else if (OpVT == MVT::f32) {
245  if (RetVT == MVT::f64)
246  return FPEXT_F32_F64;
247  if (RetVT == MVT::f128)
248  return FPEXT_F32_F128;
249  if (RetVT == MVT::ppcf128)
250  return FPEXT_F32_PPCF128;
251  } else if (OpVT == MVT::f64) {
252  if (RetVT == MVT::f128)
253  return FPEXT_F64_F128;
254  else if (RetVT == MVT::ppcf128)
255  return FPEXT_F64_PPCF128;
256  } else if (OpVT == MVT::f80) {
257  if (RetVT == MVT::f128)
258  return FPEXT_F80_F128;
259  }
260 
261  return UNKNOWN_LIBCALL;
262 }
263 
264 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
265 /// UNKNOWN_LIBCALL if there is none.
267  if (RetVT == MVT::f16) {
268  if (OpVT == MVT::f32)
269  return FPROUND_F32_F16;
270  if (OpVT == MVT::f64)
271  return FPROUND_F64_F16;
272  if (OpVT == MVT::f80)
273  return FPROUND_F80_F16;
274  if (OpVT == MVT::f128)
275  return FPROUND_F128_F16;
276  if (OpVT == MVT::ppcf128)
277  return FPROUND_PPCF128_F16;
278  } else if (RetVT == MVT::f32) {
279  if (OpVT == MVT::f64)
280  return FPROUND_F64_F32;
281  if (OpVT == MVT::f80)
282  return FPROUND_F80_F32;
283  if (OpVT == MVT::f128)
284  return FPROUND_F128_F32;
285  if (OpVT == MVT::ppcf128)
286  return FPROUND_PPCF128_F32;
287  } else if (RetVT == MVT::f64) {
288  if (OpVT == MVT::f80)
289  return FPROUND_F80_F64;
290  if (OpVT == MVT::f128)
291  return FPROUND_F128_F64;
292  if (OpVT == MVT::ppcf128)
293  return FPROUND_PPCF128_F64;
294  } else if (RetVT == MVT::f80) {
295  if (OpVT == MVT::f128)
296  return FPROUND_F128_F80;
297  }
298 
299  return UNKNOWN_LIBCALL;
300 }
301 
302 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
303 /// UNKNOWN_LIBCALL if there is none.
305  if (OpVT == MVT::f16) {
306  if (RetVT == MVT::i32)
307  return FPTOSINT_F16_I32;
308  if (RetVT == MVT::i64)
309  return FPTOSINT_F16_I64;
310  if (RetVT == MVT::i128)
311  return FPTOSINT_F16_I128;
312  } else if (OpVT == MVT::f32) {
313  if (RetVT == MVT::i32)
314  return FPTOSINT_F32_I32;
315  if (RetVT == MVT::i64)
316  return FPTOSINT_F32_I64;
317  if (RetVT == MVT::i128)
318  return FPTOSINT_F32_I128;
319  } else if (OpVT == MVT::f64) {
320  if (RetVT == MVT::i32)
321  return FPTOSINT_F64_I32;
322  if (RetVT == MVT::i64)
323  return FPTOSINT_F64_I64;
324  if (RetVT == MVT::i128)
325  return FPTOSINT_F64_I128;
326  } else if (OpVT == MVT::f80) {
327  if (RetVT == MVT::i32)
328  return FPTOSINT_F80_I32;
329  if (RetVT == MVT::i64)
330  return FPTOSINT_F80_I64;
331  if (RetVT == MVT::i128)
332  return FPTOSINT_F80_I128;
333  } else if (OpVT == MVT::f128) {
334  if (RetVT == MVT::i32)
335  return FPTOSINT_F128_I32;
336  if (RetVT == MVT::i64)
337  return FPTOSINT_F128_I64;
338  if (RetVT == MVT::i128)
339  return FPTOSINT_F128_I128;
340  } else if (OpVT == MVT::ppcf128) {
341  if (RetVT == MVT::i32)
342  return FPTOSINT_PPCF128_I32;
343  if (RetVT == MVT::i64)
344  return FPTOSINT_PPCF128_I64;
345  if (RetVT == MVT::i128)
346  return FPTOSINT_PPCF128_I128;
347  }
348  return UNKNOWN_LIBCALL;
349 }
350 
351 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
352 /// UNKNOWN_LIBCALL if there is none.
354  if (OpVT == MVT::f16) {
355  if (RetVT == MVT::i32)
356  return FPTOUINT_F16_I32;
357  if (RetVT == MVT::i64)
358  return FPTOUINT_F16_I64;
359  if (RetVT == MVT::i128)
360  return FPTOUINT_F16_I128;
361  } else if (OpVT == MVT::f32) {
362  if (RetVT == MVT::i32)
363  return FPTOUINT_F32_I32;
364  if (RetVT == MVT::i64)
365  return FPTOUINT_F32_I64;
366  if (RetVT == MVT::i128)
367  return FPTOUINT_F32_I128;
368  } else if (OpVT == MVT::f64) {
369  if (RetVT == MVT::i32)
370  return FPTOUINT_F64_I32;
371  if (RetVT == MVT::i64)
372  return FPTOUINT_F64_I64;
373  if (RetVT == MVT::i128)
374  return FPTOUINT_F64_I128;
375  } else if (OpVT == MVT::f80) {
376  if (RetVT == MVT::i32)
377  return FPTOUINT_F80_I32;
378  if (RetVT == MVT::i64)
379  return FPTOUINT_F80_I64;
380  if (RetVT == MVT::i128)
381  return FPTOUINT_F80_I128;
382  } else if (OpVT == MVT::f128) {
383  if (RetVT == MVT::i32)
384  return FPTOUINT_F128_I32;
385  if (RetVT == MVT::i64)
386  return FPTOUINT_F128_I64;
387  if (RetVT == MVT::i128)
388  return FPTOUINT_F128_I128;
389  } else if (OpVT == MVT::ppcf128) {
390  if (RetVT == MVT::i32)
391  return FPTOUINT_PPCF128_I32;
392  if (RetVT == MVT::i64)
393  return FPTOUINT_PPCF128_I64;
394  if (RetVT == MVT::i128)
395  return FPTOUINT_PPCF128_I128;
396  }
397  return UNKNOWN_LIBCALL;
398 }
399 
400 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
401 /// UNKNOWN_LIBCALL if there is none.
403  if (OpVT == MVT::i32) {
404  if (RetVT == MVT::f16)
405  return SINTTOFP_I32_F16;
406  if (RetVT == MVT::f32)
407  return SINTTOFP_I32_F32;
408  if (RetVT == MVT::f64)
409  return SINTTOFP_I32_F64;
410  if (RetVT == MVT::f80)
411  return SINTTOFP_I32_F80;
412  if (RetVT == MVT::f128)
413  return SINTTOFP_I32_F128;
414  if (RetVT == MVT::ppcf128)
415  return SINTTOFP_I32_PPCF128;
416  } else if (OpVT == MVT::i64) {
417  if (RetVT == MVT::f16)
418  return SINTTOFP_I64_F16;
419  if (RetVT == MVT::f32)
420  return SINTTOFP_I64_F32;
421  if (RetVT == MVT::f64)
422  return SINTTOFP_I64_F64;
423  if (RetVT == MVT::f80)
424  return SINTTOFP_I64_F80;
425  if (RetVT == MVT::f128)
426  return SINTTOFP_I64_F128;
427  if (RetVT == MVT::ppcf128)
428  return SINTTOFP_I64_PPCF128;
429  } else if (OpVT == MVT::i128) {
430  if (RetVT == MVT::f16)
431  return SINTTOFP_I128_F16;
432  if (RetVT == MVT::f32)
433  return SINTTOFP_I128_F32;
434  if (RetVT == MVT::f64)
435  return SINTTOFP_I128_F64;
436  if (RetVT == MVT::f80)
437  return SINTTOFP_I128_F80;
438  if (RetVT == MVT::f128)
439  return SINTTOFP_I128_F128;
440  if (RetVT == MVT::ppcf128)
441  return SINTTOFP_I128_PPCF128;
442  }
443  return UNKNOWN_LIBCALL;
444 }
445 
446 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
447 /// UNKNOWN_LIBCALL if there is none.
449  if (OpVT == MVT::i32) {
450  if (RetVT == MVT::f16)
451  return UINTTOFP_I32_F16;
452  if (RetVT == MVT::f32)
453  return UINTTOFP_I32_F32;
454  if (RetVT == MVT::f64)
455  return UINTTOFP_I32_F64;
456  if (RetVT == MVT::f80)
457  return UINTTOFP_I32_F80;
458  if (RetVT == MVT::f128)
459  return UINTTOFP_I32_F128;
460  if (RetVT == MVT::ppcf128)
461  return UINTTOFP_I32_PPCF128;
462  } else if (OpVT == MVT::i64) {
463  if (RetVT == MVT::f16)
464  return UINTTOFP_I64_F16;
465  if (RetVT == MVT::f32)
466  return UINTTOFP_I64_F32;
467  if (RetVT == MVT::f64)
468  return UINTTOFP_I64_F64;
469  if (RetVT == MVT::f80)
470  return UINTTOFP_I64_F80;
471  if (RetVT == MVT::f128)
472  return UINTTOFP_I64_F128;
473  if (RetVT == MVT::ppcf128)
474  return UINTTOFP_I64_PPCF128;
475  } else if (OpVT == MVT::i128) {
476  if (RetVT == MVT::f16)
477  return UINTTOFP_I128_F16;
478  if (RetVT == MVT::f32)
479  return UINTTOFP_I128_F32;
480  if (RetVT == MVT::f64)
481  return UINTTOFP_I128_F64;
482  if (RetVT == MVT::f80)
483  return UINTTOFP_I128_F80;
484  if (RetVT == MVT::f128)
485  return UINTTOFP_I128_F128;
486  if (RetVT == MVT::ppcf128)
487  return UINTTOFP_I128_PPCF128;
488  }
489  return UNKNOWN_LIBCALL;
490 }
491 
493  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
494  POWI_PPCF128);
495 }
496 
498  MVT VT) {
499  unsigned ModeN, ModelN;
500  switch (VT.SimpleTy) {
501  case MVT::i8:
502  ModeN = 0;
503  break;
504  case MVT::i16:
505  ModeN = 1;
506  break;
507  case MVT::i32:
508  ModeN = 2;
509  break;
510  case MVT::i64:
511  ModeN = 3;
512  break;
513  case MVT::i128:
514  ModeN = 4;
515  break;
516  default:
517  return UNKNOWN_LIBCALL;
518  }
519 
520  switch (Order) {
522  ModelN = 0;
523  break;
525  ModelN = 1;
526  break;
528  ModelN = 2;
529  break;
532  ModelN = 3;
533  break;
534  default:
535  return UNKNOWN_LIBCALL;
536  }
537 
538 #define LCALLS(A, B) \
539  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
540 #define LCALL5(A) \
541  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
542  switch (Opc) {
543  case ISD::ATOMIC_CMP_SWAP: {
544  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
545  return LC[ModeN][ModelN];
546  }
547  case ISD::ATOMIC_SWAP: {
548  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
549  return LC[ModeN][ModelN];
550  }
551  case ISD::ATOMIC_LOAD_ADD: {
552  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
553  return LC[ModeN][ModelN];
554  }
555  case ISD::ATOMIC_LOAD_OR: {
556  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
557  return LC[ModeN][ModelN];
558  }
559  case ISD::ATOMIC_LOAD_CLR: {
560  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
561  return LC[ModeN][ModelN];
562  }
563  case ISD::ATOMIC_LOAD_XOR: {
564  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
565  return LC[ModeN][ModelN];
566  }
567  default:
568  return UNKNOWN_LIBCALL;
569  }
570 #undef LCALLS
571 #undef LCALL5
572 }
573 
574 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
575 #define OP_TO_LIBCALL(Name, Enum) \
576  case Name: \
577  switch (VT.SimpleTy) { \
578  default: \
579  return UNKNOWN_LIBCALL; \
580  case MVT::i8: \
581  return Enum##_1; \
582  case MVT::i16: \
583  return Enum##_2; \
584  case MVT::i32: \
585  return Enum##_4; \
586  case MVT::i64: \
587  return Enum##_8; \
588  case MVT::i128: \
589  return Enum##_16; \
590  }
591 
592  switch (Opc) {
593  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
594  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
595  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
596  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
597  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
598  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
599  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
600  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
601  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
602  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
603  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
604  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
605  }
606 
607 #undef OP_TO_LIBCALL
608 
609  return UNKNOWN_LIBCALL;
610 }
611 
613  switch (ElementSize) {
614  case 1:
615  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
616  case 2:
617  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
618  case 4:
619  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
620  case 8:
621  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
622  case 16:
623  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
624  default:
625  return UNKNOWN_LIBCALL;
626  }
627 }
628 
630  switch (ElementSize) {
631  case 1:
632  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
633  case 2:
634  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
635  case 4:
636  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
637  case 8:
638  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
639  case 16:
640  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
641  default:
642  return UNKNOWN_LIBCALL;
643  }
644 }
645 
647  switch (ElementSize) {
648  case 1:
649  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
650  case 2:
651  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
652  case 4:
653  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
654  case 8:
655  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
656  case 16:
657  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
658  default:
659  return UNKNOWN_LIBCALL;
660  }
661 }
662 
663 /// InitCmpLibcallCCs - Set default comparison libcall CC.
664 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
665  std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
666  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
667  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
668  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
669  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
670  CCs[RTLIB::UNE_F32] = ISD::SETNE;
671  CCs[RTLIB::UNE_F64] = ISD::SETNE;
672  CCs[RTLIB::UNE_F128] = ISD::SETNE;
673  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
674  CCs[RTLIB::OGE_F32] = ISD::SETGE;
675  CCs[RTLIB::OGE_F64] = ISD::SETGE;
676  CCs[RTLIB::OGE_F128] = ISD::SETGE;
677  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
678  CCs[RTLIB::OLT_F32] = ISD::SETLT;
679  CCs[RTLIB::OLT_F64] = ISD::SETLT;
680  CCs[RTLIB::OLT_F128] = ISD::SETLT;
681  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
682  CCs[RTLIB::OLE_F32] = ISD::SETLE;
683  CCs[RTLIB::OLE_F64] = ISD::SETLE;
684  CCs[RTLIB::OLE_F128] = ISD::SETLE;
685  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
686  CCs[RTLIB::OGT_F32] = ISD::SETGT;
687  CCs[RTLIB::OGT_F64] = ISD::SETGT;
688  CCs[RTLIB::OGT_F128] = ISD::SETGT;
689  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
690  CCs[RTLIB::UO_F32] = ISD::SETNE;
691  CCs[RTLIB::UO_F64] = ISD::SETNE;
692  CCs[RTLIB::UO_F128] = ISD::SETNE;
693  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
694 }
695 
696 /// NOTE: The TargetMachine owns TLOF.
698  initActions();
699 
700  // Perform these initializations only once.
702  MaxLoadsPerMemcmp = 8;
706  HasMultipleConditionRegisters = false;
707  HasExtractBitsInsn = false;
708  JumpIsExpensive = JumpIsExpensiveOverride;
710  EnableExtLdPromotion = false;
711  StackPointerRegisterToSaveRestore = 0;
712  BooleanContents = UndefinedBooleanContent;
713  BooleanFloatContents = UndefinedBooleanContent;
714  BooleanVectorContents = UndefinedBooleanContent;
715  SchedPreferenceInfo = Sched::ILP;
718  // TODO: the default will be switched to 0 in the next commit, along
719  // with the Target-specific changes necessary.
720  MaxAtomicSizeInBitsSupported = 1024;
721 
722  MinCmpXchgSizeInBits = 0;
723  SupportsUnalignedAtomics = false;
724 
725  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
726 
727  InitLibcalls(TM.getTargetTriple());
728  InitCmpLibcallCCs(CmpLibcallCCs);
729 }
730 
732  // All operations default to being supported.
733  memset(OpActions, 0, sizeof(OpActions));
734  memset(LoadExtActions, 0, sizeof(LoadExtActions));
735  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
736  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
737  memset(CondCodeActions, 0, sizeof(CondCodeActions));
738  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
739  std::fill(std::begin(TargetDAGCombineArray),
740  std::end(TargetDAGCombineArray), 0);
741 
742  for (MVT VT : MVT::fp_valuetypes()) {
743  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
744  if (IntVT.isValid()) {
747  }
748  }
749 
750  // Set default actions for various operations.
751  for (MVT VT : MVT::all_valuetypes()) {
752  // Default all indexed load / store to expand.
753  for (unsigned IM = (unsigned)ISD::PRE_INC;
754  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
755  setIndexedLoadAction(IM, VT, Expand);
756  setIndexedStoreAction(IM, VT, Expand);
759  }
760 
761  // Most backends expect to see the node which just returns the value loaded.
763 
764  // These operations default to expand.
797 
798  // Overflow operations default to expand
805 
806  // ADDCARRY operations default to expand
812 
813  // ADDC/ADDE/SUBC/SUBE default to expand.
818 
819  // Absolute difference
822 
823  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
826 
829 
830  // These library functions default to expand.
834 
835  // These operations default to expand for vector types.
836  if (VT.isVector()) {
843  }
844 
845  // Constrained floating-point operations default to expand.
846 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
847  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
848 #include "llvm/IR/ConstrainedOps.def"
849 
850  // For most targets @llvm.get.dynamic.area.offset just returns 0.
852 
853  // Vector reduction default to expand.
869 
870  // Named vector shuffles default to expand.
872  }
873 
874  // Most targets ignore the @llvm.prefetch intrinsic.
876 
877  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
879 
880  // ConstantFP nodes default to expand. Targets can either change this to
881  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
882  // to optimize expansions for certain constants.
888 
889  // These library functions default to expand.
890  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
906  }
907 
908  // Default ISD::TRAP to expand (which turns it into abort).
910 
911  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
912  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
914 
916 }
917 
919  EVT) const {
920  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
921 }
922 
924  bool LegalTypes) const {
925  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
926  if (LHSTy.isVector())
927  return LHSTy;
928  MVT ShiftVT =
929  LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
930  // If any possible shift value won't fit in the prefered type, just use
931  // something safe. Assume it will be legalized when the shift is expanded.
932  if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
933  ShiftVT = MVT::i32;
934  assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
935  "ShiftVT is still too small!");
936  return ShiftVT;
937 }
938 
939 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
940  assert(isTypeLegal(VT));
941  switch (Op) {
942  default:
943  return false;
944  case ISD::SDIV:
945  case ISD::UDIV:
946  case ISD::SREM:
947  case ISD::UREM:
948  return true;
949  }
950 }
951 
953  unsigned DestAS) const {
954  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
955 }
956 
958  // If the command-line option was specified, ignore this request.
960  JumpIsExpensive = isExpensive;
961 }
962 
964 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
965  // If this is a simple type, use the ComputeRegisterProp mechanism.
966  if (VT.isSimple()) {
967  MVT SVT = VT.getSimpleVT();
968  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
969  MVT NVT = TransformToType[SVT.SimpleTy];
970  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
971 
972  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
973  LA == TypeSoftPromoteHalf ||
974  (NVT.isVector() ||
975  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
976  "Promote may not follow Expand or Promote");
977 
978  if (LA == TypeSplitVector)
979  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
980  if (LA == TypeScalarizeVector)
981  return LegalizeKind(LA, SVT.getVectorElementType());
982  return LegalizeKind(LA, NVT);
983  }
984 
985  // Handle Extended Scalar Types.
986  if (!VT.isVector()) {
987  assert(VT.isInteger() && "Float types must be simple");
988  unsigned BitSize = VT.getSizeInBits();
989  // First promote to a power-of-two size, then expand if necessary.
990  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
991  EVT NVT = VT.getRoundIntegerType(Context);
992  assert(NVT != VT && "Unable to round integer VT");
993  LegalizeKind NextStep = getTypeConversion(Context, NVT);
994  // Avoid multi-step promotion.
995  if (NextStep.first == TypePromoteInteger)
996  return NextStep;
997  // Return rounded integer type.
998  return LegalizeKind(TypePromoteInteger, NVT);
999  }
1000 
1003  }
1004 
1005  // Handle vector types.
1006  ElementCount NumElts = VT.getVectorElementCount();
1007  EVT EltVT = VT.getVectorElementType();
1008 
1009  // Vectors with only one element are always scalarized.
1010  if (NumElts.isScalar())
1011  return LegalizeKind(TypeScalarizeVector, EltVT);
1012 
1013  // Try to widen vector elements until the element type is a power of two and
1014  // promote it to a legal type later on, for example:
1015  // <3 x i8> -> <4 x i8> -> <4 x i32>
1016  if (EltVT.isInteger()) {
1017  // Vectors with a number of elements that is not a power of two are always
1018  // widened, for example <3 x i8> -> <4 x i8>.
1019  if (!VT.isPow2VectorType()) {
1020  NumElts = NumElts.coefficientNextPowerOf2();
1021  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1022  return LegalizeKind(TypeWidenVector, NVT);
1023  }
1024 
1025  // Examine the element type.
1026  LegalizeKind LK = getTypeConversion(Context, EltVT);
1027 
1028  // If type is to be expanded, split the vector.
1029  // <4 x i140> -> <2 x i140>
1030  if (LK.first == TypeExpandInteger) {
1031  if (VT.getVectorElementCount().isScalable())
1035  }
1036 
1037  // Promote the integer element types until a legal vector type is found
1038  // or until the element integer type is too big. If a legal type was not
1039  // found, fallback to the usual mechanism of widening/splitting the
1040  // vector.
1041  EVT OldEltVT = EltVT;
1042  while (true) {
1043  // Increase the bitwidth of the element to the next pow-of-two
1044  // (which is greater than 8 bits).
1045  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1047 
1048  // Stop trying when getting a non-simple element type.
1049  // Note that vector elements may be greater than legal vector element
1050  // types. Example: X86 XMM registers hold 64bit element on 32bit
1051  // systems.
1052  if (!EltVT.isSimple())
1053  break;
1054 
1055  // Build a new vector type and check if it is legal.
1056  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1057  // Found a legal promoted vector type.
1058  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1060  EVT::getVectorVT(Context, EltVT, NumElts));
1061  }
1062 
1063  // Reset the type to the unexpanded type if we did not find a legal vector
1064  // type with a promoted vector element type.
1065  EltVT = OldEltVT;
1066  }
1067 
1068  // Try to widen the vector until a legal type is found.
1069  // If there is no wider legal type, split the vector.
1070  while (true) {
1071  // Round up to the next power of 2.
1072  NumElts = NumElts.coefficientNextPowerOf2();
1073 
1074  // If there is no simple vector type with this many elements then there
1075  // cannot be a larger legal vector type. Note that this assumes that
1076  // there are no skipped intermediate vector types in the simple types.
1077  if (!EltVT.isSimple())
1078  break;
1079  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1080  if (LargerVector == MVT())
1081  break;
1082 
1083  // If this type is legal then widen the vector.
1084  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1085  return LegalizeKind(TypeWidenVector, LargerVector);
1086  }
1087 
1088  // Widen odd vectors to next power of two.
1089  if (!VT.isPow2VectorType()) {
1090  EVT NVT = VT.getPow2VectorType(Context);
1091  return LegalizeKind(TypeWidenVector, NVT);
1092  }
1093 
1096 
1097  // Vectors with illegal element types are expanded.
1098  EVT NVT = EVT::getVectorVT(Context, EltVT,
1100  return LegalizeKind(TypeSplitVector, NVT);
1101 }
1102 
1103 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1104  unsigned &NumIntermediates,
1105  MVT &RegisterVT,
1106  TargetLoweringBase *TLI) {
1107  // Figure out the right, legal destination reg to copy into.
1109  MVT EltTy = VT.getVectorElementType();
1110 
1111  unsigned NumVectorRegs = 1;
1112 
1113  // Scalable vectors cannot be scalarized, so splitting or widening is
1114  // required.
1115  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1117  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1118 
1119  // FIXME: We don't support non-power-of-2-sized vectors for now.
1120  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1121  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1122  // Split EC to unit size (scalable property is preserved).
1123  NumVectorRegs = EC.getKnownMinValue();
1124  EC = ElementCount::getFixed(1);
1125  }
1126 
1127  // Divide the input until we get to a supported size. This will
1128  // always end up with an EC that represent a scalar or a scalable
1129  // scalar.
1130  while (EC.getKnownMinValue() > 1 &&
1131  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1132  EC = EC.divideCoefficientBy(2);
1133  NumVectorRegs <<= 1;
1134  }
1135 
1136  NumIntermediates = NumVectorRegs;
1137 
1138  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1139  if (!TLI->isTypeLegal(NewVT))
1140  NewVT = EltTy;
1141  IntermediateVT = NewVT;
1142 
1143  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1144 
1145  // Convert sizes such as i33 to i64.
1146  if (!isPowerOf2_32(LaneSizeInBits))
1147  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1148 
1149  MVT DestVT = TLI->getRegisterType(NewVT);
1150  RegisterVT = DestVT;
1151  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1152  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1153 
1154  // Otherwise, promotion or legal types use the same number of registers as
1155  // the vector decimated to the appropriate level.
1156  return NumVectorRegs;
1157 }
1158 
1159 /// isLegalRC - Return true if the value types that can be represented by the
1160 /// specified register class are all legal.
1162  const TargetRegisterClass &RC) const {
1163  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1164  if (isTypeLegal(*I))
1165  return true;
1166  return false;
1167 }
1168 
1169 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1170 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1173  MachineBasicBlock *MBB) const {
1174  MachineInstr *MI = &InitialMI;
1175  MachineFunction &MF = *MI->getMF();
1176  MachineFrameInfo &MFI = MF.getFrameInfo();
1177 
1178  // We're handling multiple types of operands here:
1179  // PATCHPOINT MetaArgs - live-in, read only, direct
1180  // STATEPOINT Deopt Spill - live-through, read only, indirect
1181  // STATEPOINT Deopt Alloca - live-through, read only, direct
1182  // (We're currently conservative and mark the deopt slots read/write in
1183  // practice.)
1184  // STATEPOINT GC Spill - live-through, read/write, indirect
1185  // STATEPOINT GC Alloca - live-through, read/write, direct
1186  // The live-in vs live-through is handled already (the live through ones are
1187  // all stack slots), but we need to handle the different type of stackmap
1188  // operands and memory effects here.
1189 
1190  if (!llvm::any_of(MI->operands(),
1191  [](MachineOperand &Operand) { return Operand.isFI(); }))
1192  return MBB;
1193 
1194  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1195 
1196  // Inherit previous memory operands.
1197  MIB.cloneMemRefs(*MI);
1198 
1199  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1200  MachineOperand &MO = MI->getOperand(i);
1201  if (!MO.isFI()) {
1202  // Index of Def operand this Use it tied to.
1203  // Since Defs are coming before Uses, if Use is tied, then
1204  // index of Def must be smaller that index of that Use.
1205  // Also, Defs preserve their position in new MI.
1206  unsigned TiedTo = i;
1207  if (MO.isReg() && MO.isTied())
1208  TiedTo = MI->findTiedOperandIdx(i);
1209  MIB.add(MO);
1210  if (TiedTo < i)
1211  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1212  continue;
1213  }
1214 
1215  // foldMemoryOperand builds a new MI after replacing a single FI operand
1216  // with the canonical set of five x86 addressing-mode operands.
1217  int FI = MO.getIndex();
1218 
1219  // Add frame index operands recognized by stackmaps.cpp
1220  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1221  // indirect-mem-ref tag, size, #FI, offset.
1222  // Used for spills inserted by StatepointLowering. This codepath is not
1223  // used for patchpoints/stackmaps at all, for these spilling is done via
1224  // foldMemoryOperand callback only.
1225  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1226  MIB.addImm(StackMaps::IndirectMemRefOp);
1227  MIB.addImm(MFI.getObjectSize(FI));
1228  MIB.add(MO);
1229  MIB.addImm(0);
1230  } else {
1231  // direct-mem-ref tag, #FI, offset.
1232  // Used by patchpoint, and direct alloca arguments to statepoints
1233  MIB.addImm(StackMaps::DirectMemRefOp);
1234  MIB.add(MO);
1235  MIB.addImm(0);
1236  }
1237 
1238  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1239 
1240  // Add a new memory operand for this FI.
1241  assert(MFI.getObjectOffset(FI) != -1);
1242 
1243  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1244  // PATCHPOINT should be updated to do the same. (TODO)
1245  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1246  auto Flags = MachineMemOperand::MOLoad;
1248  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1249  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1250  MIB->addMemOperand(MF, MMO);
1251  }
1252  }
1254  MI->eraseFromParent();
1255  return MBB;
1256 }
1257 
1258 /// findRepresentativeClass - Return the largest legal super-reg register class
1259 /// of the register class for the specified type and its associated "cost".
1260 // This function is in TargetLowering because it uses RegClassForVT which would
1261 // need to be moved to TargetRegisterInfo and would necessitate moving
1262 // isTypeLegal over as well - a massive change that would just require
1263 // TargetLowering having a TargetRegisterInfo class member that it would use.
1264 std::pair<const TargetRegisterClass *, uint8_t>
1266  MVT VT) const {
1267  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1268  if (!RC)
1269  return std::make_pair(RC, 0);
1270 
1271  // Compute the set of all super-register classes.
1272  BitVector SuperRegRC(TRI->getNumRegClasses());
1273  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1274  SuperRegRC.setBitsInMask(RCI.getMask());
1275 
1276  // Find the first legal register class with the largest spill size.
1277  const TargetRegisterClass *BestRC = RC;
1278  for (unsigned i : SuperRegRC.set_bits()) {
1279  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1280  // We want the largest possible spill size.
1281  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1282  continue;
1283  if (!isLegalRC(*TRI, *SuperRC))
1284  continue;
1285  BestRC = SuperRC;
1286  }
1287  return std::make_pair(BestRC, 1);
1288 }
1289 
1290 /// computeRegisterProperties - Once all of the register classes are added,
1291 /// this allows us to compute derived properties we expose.
1293  const TargetRegisterInfo *TRI) {
1295  "Too many value types for ValueTypeActions to hold!");
1296 
1297  // Everything defaults to needing one register.
1298  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1299  NumRegistersForVT[i] = 1;
1300  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1301  }
1302  // ...except isVoid, which doesn't need any registers.
1303  NumRegistersForVT[MVT::isVoid] = 0;
1304 
1305  // Find the largest integer register class.
1306  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1307  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1308  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1309 
1310  // Every integer value type larger than this largest register takes twice as
1311  // many registers to represent as the previous ValueType.
1312  for (unsigned ExpandedReg = LargestIntReg + 1;
1313  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1314  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1315  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1316  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1317  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1319  }
1320 
1321  // Inspect all of the ValueType's smaller than the largest integer
1322  // register to see which ones need promotion.
1323  unsigned LegalIntReg = LargestIntReg;
1324  for (unsigned IntReg = LargestIntReg - 1;
1325  IntReg >= (unsigned)MVT::i1; --IntReg) {
1326  MVT IVT = (MVT::SimpleValueType)IntReg;
1327  if (isTypeLegal(IVT)) {
1328  LegalIntReg = IntReg;
1329  } else {
1330  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1331  (MVT::SimpleValueType)LegalIntReg;
1332  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1333  }
1334  }
1335 
1336  // ppcf128 type is really two f64's.
1337  if (!isTypeLegal(MVT::ppcf128)) {
1338  if (isTypeLegal(MVT::f64)) {
1339  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1340  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1341  TransformToType[MVT::ppcf128] = MVT::f64;
1342  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1343  } else {
1344  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1345  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1346  TransformToType[MVT::ppcf128] = MVT::i128;
1347  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1348  }
1349  }
1350 
1351  // Decide how to handle f128. If the target does not have native f128 support,
1352  // expand it to i128 and we will be generating soft float library calls.
1353  if (!isTypeLegal(MVT::f128)) {
1354  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1355  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1356  TransformToType[MVT::f128] = MVT::i128;
1357  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1358  }
1359 
1360  // Decide how to handle f64. If the target does not have native f64 support,
1361  // expand it to i64 and we will be generating soft float library calls.
1362  if (!isTypeLegal(MVT::f64)) {
1363  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1364  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1365  TransformToType[MVT::f64] = MVT::i64;
1366  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1367  }
1368 
1369  // Decide how to handle f32. If the target does not have native f32 support,
1370  // expand it to i32 and we will be generating soft float library calls.
1371  if (!isTypeLegal(MVT::f32)) {
1372  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1373  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1374  TransformToType[MVT::f32] = MVT::i32;
1375  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1376  }
1377 
1378  // Decide how to handle f16. If the target does not have native f16 support,
1379  // promote it to f32, because there are no f16 library calls (except for
1380  // conversions).
1381  if (!isTypeLegal(MVT::f16)) {
1382  // Allow targets to control how we legalize half.
1383  if (softPromoteHalfType()) {
1384  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1385  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1386  TransformToType[MVT::f16] = MVT::f32;
1387  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1388  } else {
1389  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1390  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1391  TransformToType[MVT::f16] = MVT::f32;
1392  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1393  }
1394  }
1395 
1396  // Loop over all of the vector value types to see which need transformations.
1397  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1398  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1399  MVT VT = (MVT::SimpleValueType) i;
1400  if (isTypeLegal(VT))
1401  continue;
1402 
1403  MVT EltVT = VT.getVectorElementType();
1405  bool IsLegalWiderType = false;
1406  bool IsScalable = VT.isScalableVector();
1407  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1408  switch (PreferredAction) {
1409  case TypePromoteInteger: {
1410  MVT::SimpleValueType EndVT = IsScalable ?
1413  // Try to promote the elements of integer vectors. If no legal
1414  // promotion was found, fall through to the widen-vector method.
1415  for (unsigned nVT = i + 1;
1416  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1417  MVT SVT = (MVT::SimpleValueType) nVT;
1418  // Promote vectors of integers to vectors with the same number
1419  // of elements, with a wider element type.
1420  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1421  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1422  TransformToType[i] = SVT;
1423  RegisterTypeForVT[i] = SVT;
1424  NumRegistersForVT[i] = 1;
1425  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1426  IsLegalWiderType = true;
1427  break;
1428  }
1429  }
1430  if (IsLegalWiderType)
1431  break;
1433  }
1434 
1435  case TypeWidenVector:
1436  if (isPowerOf2_32(EC.getKnownMinValue())) {
1437  // Try to widen the vector.
1438  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1439  MVT SVT = (MVT::SimpleValueType) nVT;
1440  if (SVT.getVectorElementType() == EltVT &&
1441  SVT.isScalableVector() == IsScalable &&
1443  EC.getKnownMinValue() &&
1444  isTypeLegal(SVT)) {
1445  TransformToType[i] = SVT;
1446  RegisterTypeForVT[i] = SVT;
1447  NumRegistersForVT[i] = 1;
1448  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1449  IsLegalWiderType = true;
1450  break;
1451  }
1452  }
1453  if (IsLegalWiderType)
1454  break;
1455  } else {
1456  // Only widen to the next power of 2 to keep consistency with EVT.
1457  MVT NVT = VT.getPow2VectorType();
1458  if (isTypeLegal(NVT)) {
1459  TransformToType[i] = NVT;
1460  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1461  RegisterTypeForVT[i] = NVT;
1462  NumRegistersForVT[i] = 1;
1463  break;
1464  }
1465  }
1467 
1468  case TypeSplitVector:
1469  case TypeScalarizeVector: {
1470  MVT IntermediateVT;
1471  MVT RegisterVT;
1472  unsigned NumIntermediates;
1473  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1474  NumIntermediates, RegisterVT, this);
1475  NumRegistersForVT[i] = NumRegisters;
1476  assert(NumRegistersForVT[i] == NumRegisters &&
1477  "NumRegistersForVT size cannot represent NumRegisters!");
1478  RegisterTypeForVT[i] = RegisterVT;
1479 
1480  MVT NVT = VT.getPow2VectorType();
1481  if (NVT == VT) {
1482  // Type is already a power of 2. The default action is to split.
1483  TransformToType[i] = MVT::Other;
1484  if (PreferredAction == TypeScalarizeVector)
1485  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1486  else if (PreferredAction == TypeSplitVector)
1487  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1488  else if (EC.getKnownMinValue() > 1)
1489  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1490  else
1491  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1494  } else {
1495  TransformToType[i] = NVT;
1496  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1497  }
1498  break;
1499  }
1500  default:
1501  llvm_unreachable("Unknown vector legalization action!");
1502  }
1503  }
1504 
1505  // Determine the 'representative' register class for each value type.
1506  // An representative register class is the largest (meaning one which is
1507  // not a sub-register class / subreg register class) legal register class for
1508  // a group of value types. For example, on i386, i8, i16, and i32
1509  // representative would be GR32; while on x86_64 it's GR64.
1510  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1511  const TargetRegisterClass* RRC;
1512  uint8_t Cost;
1513  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1514  RepRegClassForVT[i] = RRC;
1515  RepRegClassCostForVT[i] = Cost;
1516  }
1517 }
1518 
1520  EVT VT) const {
1521  assert(!VT.isVector() && "No default SetCC type for vectors!");
1522  return getPointerTy(DL).SimpleTy;
1523 }
1524 
1526  return MVT::i32; // return the default value
1527 }
1528 
1529 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1530 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1531 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1532 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1533 ///
1534 /// This method returns the number of registers needed, and the VT for each
1535 /// register. It also returns the VT and quantity of the intermediate values
1536 /// before they are promoted/expanded.
1538  EVT VT, EVT &IntermediateVT,
1539  unsigned &NumIntermediates,
1540  MVT &RegisterVT) const {
1541  ElementCount EltCnt = VT.getVectorElementCount();
1542 
1543  // If there is a wider vector type with the same element type as this one,
1544  // or a promoted vector type that has the same number of elements which
1545  // are wider, then we should convert to that legal vector type.
1546  // This handles things like <2 x float> -> <4 x float> and
1547  // <4 x i1> -> <4 x i32>.
1549  if (!EltCnt.isScalar() &&
1550  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1551  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1552  if (isTypeLegal(RegisterEVT)) {
1553  IntermediateVT = RegisterEVT;
1554  RegisterVT = RegisterEVT.getSimpleVT();
1555  NumIntermediates = 1;
1556  return 1;
1557  }
1558  }
1559 
1560  // Figure out the right, legal destination reg to copy into.
1561  EVT EltTy = VT.getVectorElementType();
1562 
1563  unsigned NumVectorRegs = 1;
1564 
1565  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1566  // types like done elsewhere in SelectionDAG.
1567  if (EltCnt.isScalable()) {
1568  LegalizeKind LK;
1569  EVT PartVT = VT;
1570  do {
1571  // Iterate until we've found a legal (part) type to hold VT.
1572  LK = getTypeConversion(Context, PartVT);
1573  PartVT = LK.second;
1574  } while (LK.first != TypeLegal);
1575 
1576  if (!PartVT.isVector()) {
1578  "Don't know how to legalize this scalable vector type");
1579  }
1580 
1581  NumIntermediates =
1584  IntermediateVT = PartVT;
1585  RegisterVT = getRegisterType(Context, IntermediateVT);
1586  return NumIntermediates;
1587  }
1588 
1589  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1590  // we could break down into LHS/RHS like LegalizeDAG does.
1591  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1592  NumVectorRegs = EltCnt.getKnownMinValue();
1593  EltCnt = ElementCount::getFixed(1);
1594  }
1595 
1596  // Divide the input until we get to a supported size. This will always
1597  // end with a scalar if the target doesn't support vectors.
1598  while (EltCnt.getKnownMinValue() > 1 &&
1599  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1600  EltCnt = EltCnt.divideCoefficientBy(2);
1601  NumVectorRegs <<= 1;
1602  }
1603 
1604  NumIntermediates = NumVectorRegs;
1605 
1606  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1607  if (!isTypeLegal(NewVT))
1608  NewVT = EltTy;
1609  IntermediateVT = NewVT;
1610 
1611  MVT DestVT = getRegisterType(Context, NewVT);
1612  RegisterVT = DestVT;
1613 
1614  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1615  TypeSize NewVTSize = NewVT.getSizeInBits();
1616  // Convert sizes such as i33 to i64.
1617  if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
1618  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1619  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1620  }
1621 
1622  // Otherwise, promotion or legal types use the same number of registers as
1623  // the vector decimated to the appropriate level.
1624  return NumVectorRegs;
1625 }
1626 
1628  uint64_t NumCases,
1629  uint64_t Range,
1630  ProfileSummaryInfo *PSI,
1631  BlockFrequencyInfo *BFI) const {
1632  // FIXME: This function check the maximum table size and density, but the
1633  // minimum size is not checked. It would be nice if the minimum size is
1634  // also combined within this function. Currently, the minimum size check is
1635  // performed in findJumpTable() in SelectionDAGBuiler and
1636  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1637  const bool OptForSize =
1638  SI->getParent()->getParent()->hasOptSize() ||
1639  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1640  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1641  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1642 
1643  // Check whether the number of cases is small enough and
1644  // the range is dense enough for a jump table.
1645  return (OptForSize || Range <= MaxJumpTableSize) &&
1646  (NumCases * 100 >= Range * MinDensity);
1647 }
1648 
1649 /// Get the EVTs and ArgFlags collections that represent the legalized return
1650 /// type of the given function. This does not require a DAG or a return value,
1651 /// and is suitable for use before any DAGs for the function are constructed.
1652 /// TODO: Move this out of TargetLowering.cpp.
1654  AttributeList attr,
1656  const TargetLowering &TLI, const DataLayout &DL) {
1657  SmallVector<EVT, 4> ValueVTs;
1658  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1659  unsigned NumValues = ValueVTs.size();
1660  if (NumValues == 0) return;
1661 
1662  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1663  EVT VT = ValueVTs[j];
1664  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1665 
1666  if (attr.hasRetAttr(Attribute::SExt))
1667  ExtendKind = ISD::SIGN_EXTEND;
1668  else if (attr.hasRetAttr(Attribute::ZExt))
1669  ExtendKind = ISD::ZERO_EXTEND;
1670 
1671  // FIXME: C calling convention requires the return type to be promoted to
1672  // at least 32-bit. But this is not necessary for non-C calling
1673  // conventions. The frontend should mark functions whose return values
1674  // require promoting with signext or zeroext attributes.
1675  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1676  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1677  if (VT.bitsLT(MinVT))
1678  VT = MinVT;
1679  }
1680 
1681  unsigned NumParts =
1682  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1683  MVT PartVT =
1684  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1685 
1686  // 'inreg' on function refers to return value
1687  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1688  if (attr.hasRetAttr(Attribute::InReg))
1689  Flags.setInReg();
1690 
1691  // Propagate extension type if any
1692  if (attr.hasRetAttr(Attribute::SExt))
1693  Flags.setSExt();
1694  else if (attr.hasRetAttr(Attribute::ZExt))
1695  Flags.setZExt();
1696 
1697  for (unsigned i = 0; i < NumParts; ++i)
1698  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1699  }
1700 }
1701 
1702 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1703 /// function arguments in the caller parameter area. This is the actual
1704 /// alignment, not its logarithm.
1706  const DataLayout &DL) const {
1707  return DL.getABITypeAlign(Ty).value();
1708 }
1709 
1711  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1712  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1713  // Check if the specified alignment is sufficient based on the data layout.
1714  // TODO: While using the data layout works in practice, a better solution
1715  // would be to implement this check directly (make this a virtual function).
1716  // For example, the ABI alignment may change based on software platform while
1717  // this function should only be affected by hardware implementation.
1718  Type *Ty = VT.getTypeForEVT(Context);
1719  if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1720  // Assume that an access that meets the ABI-specified alignment is fast.
1721  if (Fast != nullptr)
1722  *Fast = true;
1723  return true;
1724  }
1725 
1726  // This is a misaligned access.
1727  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1728 }
1729 
1731  LLVMContext &Context, const DataLayout &DL, EVT VT,
1732  const MachineMemOperand &MMO, bool *Fast) const {
1734  MMO.getAlign(), MMO.getFlags(), Fast);
1735 }
1736 
1738  const DataLayout &DL, EVT VT,
1739  unsigned AddrSpace, Align Alignment,
1741  bool *Fast) const {
1742  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1743  Flags, Fast);
1744 }
1745 
1747  const DataLayout &DL, EVT VT,
1748  const MachineMemOperand &MMO,
1749  bool *Fast) const {
1750  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1751  MMO.getFlags(), Fast);
1752 }
1753 
1755  const DataLayout &DL, LLT Ty,
1756  const MachineMemOperand &MMO,
1757  bool *Fast) const {
1759  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1760  MMO.getFlags(), Fast);
1761 }
1762 
1763 //===----------------------------------------------------------------------===//
1764 // TargetTransformInfo Helpers
1765 //===----------------------------------------------------------------------===//
1766 
1768  enum InstructionOpcodes {
1769 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1770 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1771 #include "llvm/IR/Instruction.def"
1772  };
1773  switch (static_cast<InstructionOpcodes>(Opcode)) {
1774  case Ret: return 0;
1775  case Br: return 0;
1776  case Switch: return 0;
1777  case IndirectBr: return 0;
1778  case Invoke: return 0;
1779  case CallBr: return 0;
1780  case Resume: return 0;
1781  case Unreachable: return 0;
1782  case CleanupRet: return 0;
1783  case CatchRet: return 0;
1784  case CatchPad: return 0;
1785  case CatchSwitch: return 0;
1786  case CleanupPad: return 0;
1787  case FNeg: return ISD::FNEG;
1788  case Add: return ISD::ADD;
1789  case FAdd: return ISD::FADD;
1790  case Sub: return ISD::SUB;
1791  case FSub: return ISD::FSUB;
1792  case Mul: return ISD::MUL;
1793  case FMul: return ISD::FMUL;
1794  case UDiv: return ISD::UDIV;
1795  case SDiv: return ISD::SDIV;
1796  case FDiv: return ISD::FDIV;
1797  case URem: return ISD::UREM;
1798  case SRem: return ISD::SREM;
1799  case FRem: return ISD::FREM;
1800  case Shl: return ISD::SHL;
1801  case LShr: return ISD::SRL;
1802  case AShr: return ISD::SRA;
1803  case And: return ISD::AND;
1804  case Or: return ISD::OR;
1805  case Xor: return ISD::XOR;
1806  case Alloca: return 0;
1807  case Load: return ISD::LOAD;
1808  case Store: return ISD::STORE;
1809  case GetElementPtr: return 0;
1810  case Fence: return 0;
1811  case AtomicCmpXchg: return 0;
1812  case AtomicRMW: return 0;
1813  case Trunc: return ISD::TRUNCATE;
1814  case ZExt: return ISD::ZERO_EXTEND;
1815  case SExt: return ISD::SIGN_EXTEND;
1816  case FPToUI: return ISD::FP_TO_UINT;
1817  case FPToSI: return ISD::FP_TO_SINT;
1818  case UIToFP: return ISD::UINT_TO_FP;
1819  case SIToFP: return ISD::SINT_TO_FP;
1820  case FPTrunc: return ISD::FP_ROUND;
1821  case FPExt: return ISD::FP_EXTEND;
1822  case PtrToInt: return ISD::BITCAST;
1823  case IntToPtr: return ISD::BITCAST;
1824  case BitCast: return ISD::BITCAST;
1825  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1826  case ICmp: return ISD::SETCC;
1827  case FCmp: return ISD::SETCC;
1828  case PHI: return 0;
1829  case Call: return 0;
1830  case Select: return ISD::SELECT;
1831  case UserOp1: return 0;
1832  case UserOp2: return 0;
1833  case VAArg: return 0;
1834  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1835  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1836  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1837  case ExtractValue: return ISD::MERGE_VALUES;
1838  case InsertValue: return ISD::MERGE_VALUES;
1839  case LandingPad: return 0;
1840  case Freeze: return ISD::FREEZE;
1841  }
1842 
1843  llvm_unreachable("Unknown instruction type encountered!");
1844 }
1845 
1846 std::pair<InstructionCost, MVT>
1848  Type *Ty) const {
1849  LLVMContext &C = Ty->getContext();
1850  EVT MTy = getValueType(DL, Ty);
1851 
1852  InstructionCost Cost = 1;
1853  // We keep legalizing the type until we find a legal kind. We assume that
1854  // the only operation that costs anything is the split. After splitting
1855  // we need to handle two types.
1856  while (true) {
1857  LegalizeKind LK = getTypeConversion(C, MTy);
1858 
1859  if (LK.first == TypeScalarizeScalableVector) {
1860  // Ensure we return a sensible simple VT here, since many callers of this
1861  // function require it.
1862  MVT VT = MTy.isSimple() ? MTy.getSimpleVT() : MVT::i64;
1863  return std::make_pair(InstructionCost::getInvalid(), VT);
1864  }
1865 
1866  if (LK.first == TypeLegal)
1867  return std::make_pair(Cost, MTy.getSimpleVT());
1868 
1869  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1870  Cost *= 2;
1871 
1872  // Do not loop with f128 type.
1873  if (MTy == LK.second)
1874  return std::make_pair(Cost, MTy.getSimpleVT());
1875 
1876  // Keep legalizing the type.
1877  MTy = LK.second;
1878  }
1879 }
1880 
1881 Value *
1883  bool UseTLS) const {
1884  // compiler-rt provides a variable with a magic name. Targets that do not
1885  // link with compiler-rt may also provide such a variable.
1886  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1887  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1888  auto UnsafeStackPtr =
1889  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1890 
1891  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1892 
1893  if (!UnsafeStackPtr) {
1894  auto TLSModel = UseTLS ?
1897  // The global variable is not defined yet, define it ourselves.
1898  // We use the initial-exec TLS model because we do not support the
1899  // variable living anywhere other than in the main executable.
1900  UnsafeStackPtr = new GlobalVariable(
1901  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1902  UnsafeStackPtrVar, nullptr, TLSModel);
1903  } else {
1904  // The variable exists, check its type and attributes.
1905  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1906  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1907  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1908  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1909  (UseTLS ? "" : "not ") + "be thread-local");
1910  }
1911  return UnsafeStackPtr;
1912 }
1913 
1914 Value *
1916  if (!TM.getTargetTriple().isAndroid())
1917  return getDefaultSafeStackPointerLocation(IRB, true);
1918 
1919  // Android provides a libc function to retrieve the address of the current
1920  // thread's unsafe stack pointer.
1921  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1922  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1923  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1924  StackPtrTy->getPointerTo(0));
1925  return IRB.CreateCall(Fn);
1926 }
1927 
1928 //===----------------------------------------------------------------------===//
1929 // Loop Strength Reduction hooks
1930 //===----------------------------------------------------------------------===//
1931 
1932 /// isLegalAddressingMode - Return true if the addressing mode represented
1933 /// by AM is legal for this target, for a load/store of the specified type.
1935  const AddrMode &AM, Type *Ty,
1936  unsigned AS, Instruction *I) const {
1937  // The default implementation of this implements a conservative RISCy, r+r and
1938  // r+i addr mode.
1939 
1940  // Allows a sign-extended 16-bit immediate field.
1941  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1942  return false;
1943 
1944  // No global is ever allowed as a base.
1945  if (AM.BaseGV)
1946  return false;
1947 
1948  // Only support r+r,
1949  switch (AM.Scale) {
1950  case 0: // "r+i" or just "i", depending on HasBaseReg.
1951  break;
1952  case 1:
1953  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1954  return false;
1955  // Otherwise we have r+r or r+i.
1956  break;
1957  case 2:
1958  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1959  return false;
1960  // Allow 2*r as r+r.
1961  break;
1962  default: // Don't allow n * r
1963  return false;
1964  }
1965 
1966  return true;
1967 }
1968 
1969 //===----------------------------------------------------------------------===//
1970 // Stack Protector
1971 //===----------------------------------------------------------------------===//
1972 
1973 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1974 // so that SelectionDAG handle SSP.
1976  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1977  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1978  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1979  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1980  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1981  G->setVisibility(GlobalValue::HiddenVisibility);
1982  return C;
1983  }
1984  return nullptr;
1985 }
1986 
1987 // Currently only support "standard" __stack_chk_guard.
1988 // TODO: add LOAD_STACK_GUARD support.
1990  if (!M.getNamedValue("__stack_chk_guard")) {
1991  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1993  "__stack_chk_guard");
1994 
1995  // FreeBSD has "__stack_chk_guard" defined externally on libc.so
1996  if (TM.getRelocationModel() == Reloc::Static &&
1998  !TM.getTargetTriple().isOSFreeBSD())
1999  GV->setDSOLocal(true);
2000  }
2001 }
2002 
2003 // Currently only support "standard" __stack_chk_guard.
2004 // TODO: add LOAD_STACK_GUARD support.
2006  return M.getNamedValue("__stack_chk_guard");
2007 }
2008 
2010  return nullptr;
2011 }
2012 
2014  return MinimumJumpTableEntries;
2015 }
2016 
2019 }
2020 
2021 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2022  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2023 }
2024 
2026  return MaximumJumpTableSize;
2027 }
2028 
2030  MaximumJumpTableSize = Val;
2031 }
2032 
2035 }
2036 
2038  if (TM.Options.LoopAlignment)
2039  return Align(TM.Options.LoopAlignment);
2040  return PrefLoopAlignment;
2041 }
2042 
2043 //===----------------------------------------------------------------------===//
2044 // Reciprocal Estimates
2045 //===----------------------------------------------------------------------===//
2046 
2047 /// Get the reciprocal estimate attribute string for a function that will
2048 /// override the target defaults.
2050  const Function &F = MF.getFunction();
2051  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2052 }
2053 
2054 /// Construct a string for the given reciprocal operation of the given type.
2055 /// This string should match the corresponding option to the front-end's
2056 /// "-mrecip" flag assuming those strings have been passed through in an
2057 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2058 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2059  std::string Name = VT.isVector() ? "vec-" : "";
2060 
2061  Name += IsSqrt ? "sqrt" : "div";
2062 
2063  // TODO: Handle "half" or other float types?
2064  if (VT.getScalarType() == MVT::f64) {
2065  Name += "d";
2066  } else {
2067  assert(VT.getScalarType() == MVT::f32 &&
2068  "Unexpected FP type for reciprocal estimate");
2069  Name += "f";
2070  }
2071 
2072  return Name;
2073 }
2074 
2075 /// Return the character position and value (a single numeric character) of a
2076 /// customized refinement operation in the input string if it exists. Return
2077 /// false if there is no customized refinement step count.
2078 static bool parseRefinementStep(StringRef In, size_t &Position,
2079  uint8_t &Value) {
2080  const char RefStepToken = ':';
2081  Position = In.find(RefStepToken);
2082  if (Position == StringRef::npos)
2083  return false;
2084 
2085  StringRef RefStepString = In.substr(Position + 1);
2086  // Allow exactly one numeric character for the additional refinement
2087  // step parameter.
2088  if (RefStepString.size() == 1) {
2089  char RefStepChar = RefStepString[0];
2090  if (isDigit(RefStepChar)) {
2091  Value = RefStepChar - '0';
2092  return true;
2093  }
2094  }
2095  report_fatal_error("Invalid refinement step for -recip.");
2096 }
2097 
2098 /// For the input attribute string, return one of the ReciprocalEstimate enum
2099 /// status values (enabled, disabled, or not specified) for this operation on
2100 /// the specified data type.
2101 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2102  if (Override.empty())
2103  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2104 
2105  SmallVector<StringRef, 4> OverrideVector;
2106  Override.split(OverrideVector, ',');
2107  unsigned NumArgs = OverrideVector.size();
2108 
2109  // Check if "all", "none", or "default" was specified.
2110  if (NumArgs == 1) {
2111  // Look for an optional setting of the number of refinement steps needed
2112  // for this type of reciprocal operation.
2113  size_t RefPos;
2114  uint8_t RefSteps;
2115  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2116  // Split the string for further processing.
2117  Override = Override.substr(0, RefPos);
2118  }
2119 
2120  // All reciprocal types are enabled.
2121  if (Override == "all")
2123 
2124  // All reciprocal types are disabled.
2125  if (Override == "none")
2127 
2128  // Target defaults for enablement are used.
2129  if (Override == "default")
2130  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2131  }
2132 
2133  // The attribute string may omit the size suffix ('f'/'d').
2134  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2135  std::string VTNameNoSize = VTName;
2136  VTNameNoSize.pop_back();
2137  static const char DisabledPrefix = '!';
2138 
2139  for (StringRef RecipType : OverrideVector) {
2140  size_t RefPos;
2141  uint8_t RefSteps;
2142  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2143  RecipType = RecipType.substr(0, RefPos);
2144 
2145  // Ignore the disablement token for string matching.
2146  bool IsDisabled = RecipType[0] == DisabledPrefix;
2147  if (IsDisabled)
2148  RecipType = RecipType.substr(1);
2149 
2150  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2153  }
2154 
2155  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2156 }
2157 
2158 /// For the input attribute string, return the customized refinement step count
2159 /// for this operation on the specified data type. If the step count does not
2160 /// exist, return the ReciprocalEstimate enum value for unspecified.
2161 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2162  if (Override.empty())
2163  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2164 
2165  SmallVector<StringRef, 4> OverrideVector;
2166  Override.split(OverrideVector, ',');
2167  unsigned NumArgs = OverrideVector.size();
2168 
2169  // Check if "all", "default", or "none" was specified.
2170  if (NumArgs == 1) {
2171  // Look for an optional setting of the number of refinement steps needed
2172  // for this type of reciprocal operation.
2173  size_t RefPos;
2174  uint8_t RefSteps;
2175  if (!parseRefinementStep(Override, RefPos, RefSteps))
2176  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2177 
2178  // Split the string for further processing.
2179  Override = Override.substr(0, RefPos);
2180  assert(Override != "none" &&
2181  "Disabled reciprocals, but specifed refinement steps?");
2182 
2183  // If this is a general override, return the specified number of steps.
2184  if (Override == "all" || Override == "default")
2185  return RefSteps;
2186  }
2187 
2188  // The attribute string may omit the size suffix ('f'/'d').
2189  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2190  std::string VTNameNoSize = VTName;
2191  VTNameNoSize.pop_back();
2192 
2193  for (StringRef RecipType : OverrideVector) {
2194  size_t RefPos;
2195  uint8_t RefSteps;
2196  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2197  continue;
2198 
2199  RecipType = RecipType.substr(0, RefPos);
2200  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2201  return RefSteps;
2202  }
2203 
2204  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2205 }
2206 
2208  MachineFunction &MF) const {
2209  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2210 }
2211 
2213  MachineFunction &MF) const {
2214  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2215 }
2216 
2218  MachineFunction &MF) const {
2219  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2220 }
2221 
2223  MachineFunction &MF) const {
2224  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2225 }
2226 
2228  MF.getRegInfo().freezeReservedRegs(MF);
2229 }
2230 
2233  const DataLayout &DL) const {
2235  if (LI.isVolatile())
2237 
2238  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2240 
2241  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2243 
2246 
2247  Flags |= getTargetMMOFlags(LI);
2248  return Flags;
2249 }
2250 
2253  const DataLayout &DL) const {
2255 
2256  if (SI.isVolatile())
2258 
2259  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2261 
2262  // FIXME: Not preserving dereferenceable
2263  Flags |= getTargetMMOFlags(SI);
2264  return Flags;
2265 }
2266 
2269  const DataLayout &DL) const {
2271 
2272  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2273  if (RMW->isVolatile())
2275  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2276  if (CmpX->isVolatile())
2278  } else
2279  llvm_unreachable("not an atomic instruction");
2280 
2281  // FIXME: Not preserving dereferenceable
2282  Flags |= getTargetMMOFlags(AI);
2283  return Flags;
2284 }
2285 
2287  Instruction *Inst,
2288  AtomicOrdering Ord) const {
2289  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2290  return Builder.CreateFence(Ord);
2291  else
2292  return nullptr;
2293 }
2294 
2296  Instruction *Inst,
2297  AtomicOrdering Ord) const {
2298  if (isAcquireOrStronger(Ord))
2299  return Builder.CreateFence(Ord);
2300  else
2301  return nullptr;
2302 }
2303 
2304 //===----------------------------------------------------------------------===//
2305 // GlobalISel Hooks
2306 //===----------------------------------------------------------------------===//
2307 
2309  const TargetTransformInfo *TTI) const {
2310  auto &MF = *MI.getMF();
2311  auto &MRI = MF.getRegInfo();
2312  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2313  // this helper function computes the maximum number of uses we should consider
2314  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2315  // break even in terms of code size when the original MI has 2 users vs
2316  // choosing to potentially spill. Any more than 2 users we we have a net code
2317  // size increase. This doesn't take into account register pressure though.
2318  auto maxUses = [](unsigned RematCost) {
2319  // A cost of 1 means remats are basically free.
2320  if (RematCost == 1)
2321  return UINT_MAX;
2322  if (RematCost == 2)
2323  return 2U;
2324 
2325  // Remat is too expensive, only sink if there's one user.
2326  if (RematCost > 2)
2327  return 1U;
2328  llvm_unreachable("Unexpected remat cost");
2329  };
2330 
2331  // Helper to walk through uses and terminate if we've reached a limit. Saves
2332  // us spending time traversing uses if all we want to know is if it's >= min.
2333  auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) {
2334  unsigned NumUses = 0;
2336  for (; UI != UE && NumUses < MaxUses; ++UI) {
2337  NumUses++;
2338  }
2339  // If we haven't reached the end yet then there are more than MaxUses users.
2340  return UI == UE;
2341  };
2342 
2343  switch (MI.getOpcode()) {
2344  default:
2345  return false;
2346  // Constants-like instructions should be close to their users.
2347  // We don't want long live-ranges for them.
2348  case TargetOpcode::G_CONSTANT:
2349  case TargetOpcode::G_FCONSTANT:
2350  case TargetOpcode::G_FRAME_INDEX:
2351  case TargetOpcode::G_INTTOPTR:
2352  return true;
2353  case TargetOpcode::G_GLOBAL_VALUE: {
2354  unsigned RematCost = TTI->getGISelRematGlobalCost();
2355  Register Reg = MI.getOperand(0).getReg();
2356  unsigned MaxUses = maxUses(RematCost);
2357  if (MaxUses == UINT_MAX)
2358  return true; // Remats are "free" so always localize.
2359  bool B = isUsesAtMost(Reg, MaxUses);
2360  return B;
2361  }
2362  }
2363 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:452
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:872
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:2049
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:884
i
i
Definition: README.txt:29
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:683
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:2021
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2262
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3177
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::TargetLoweringBase::getByValTypeAlignment
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1705
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:710
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:933
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:563
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2296
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1390
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:319
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:574
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:192
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:538
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1058
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:664
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1387
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:848
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:293
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1391
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:323
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1089
llvm::ElementCount
Definition: TypeSize.h:385
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:898
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:374
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1150
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:59
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:519
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1161
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:311
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:48
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1143
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:674
llvm::Triple::x86
@ x86
Definition: Triple.h:83
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:217
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3175
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:179
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:662
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:59
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:801
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1386
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:216
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:2029
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:431
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:646
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1134
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:103
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:367
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::GlobalVariable
Definition: GlobalVariable.h:40
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:132
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:731
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:875
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1915
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:337
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1265
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:785
llvm::TargetLoweringBase::getPrefLoopAlignment
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
Definition: TargetLoweringBase.cpp:2037
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1103
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:347
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:70
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::AttributeList
Definition: Attributes.h:398
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:131
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1627
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:74
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1228
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:504
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:2033
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:906
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1847
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2941
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:769
STLExtras.h
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1212
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1882
llvm::TargetLoweringBase::emitTrailingFence
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Definition: TargetLoweringBase.cpp:2295
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:267
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:258
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:54
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:209
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:331
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1172
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:216
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::EVT::isZeroSized
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:125
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:381
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3198
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2232
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:627
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1144
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:385
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:448
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:290
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
Definition: TargetLoweringBase.cpp:923
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::TargetLoweringBase::emitLeadingFence
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: TargetLoweringBase.cpp:2286
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:130
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3163
llvm::ElementCount::isScalar
bool isScalar() const
Counting predicates.
Definition: TypeSize.h:395
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:334
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:610
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1240
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:885
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1067
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:663
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:676
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2308
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:360
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:640
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1388
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:229
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:439
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:228
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:102
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:748
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:226
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:354
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:747
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:758
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2078
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2380
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:266
Twine.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1062
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:883
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:887
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:905
TargetOpcodes.h
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:264
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3213
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:852
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1142
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:118
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:145
llvm::Instruction
Definition: Instruction.h:45
llvm::isDereferenceablePointer
bool isDereferenceablePointer(const Value *V, Type *Ty, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Return true if this is always a dereferenceable pointer.
Definition: Loads.cpp:234
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1934
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1149
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2253
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:739
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:2005
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:882
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:881
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:402
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1537
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:505
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1394
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3190
llvm::BitVector
Definition: BitVector.h:74
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:318
llvm::RTLIB::getFPLibCall
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Definition: TargetLoweringBase.cpp:217
llvm::ISD::ABDS
@ ABDS
Definition: ISDOpcodes.h:621
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:590
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1989
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:214
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1115
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1443
llvm::TargetOptions::LoopAlignment
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
Definition: TargetOptions.h:351
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:467
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:273
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:939
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:315
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:869
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:959
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:609
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1226
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:57
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1525
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3231
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:377
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2215
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3192
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:626
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:911
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:2025
llvm::cl::opt< bool >
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:2013
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1193
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1975
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:310
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:304
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:742
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1547
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:308
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:929
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:876
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1229
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:470
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1131
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1147
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:786
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:912
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1233
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:282
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:921
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1238
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:210
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:513
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:208
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:492
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:198
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2222
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1088
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:301
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:233
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:511
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1225
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2268
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:675
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1146
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1213
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:888
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:637
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1125
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:328
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1140
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:336
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:476
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:632
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1519
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1658
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2212
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:264
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3234
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:650
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1091
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MVT::all_valuetypes
static auto all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1407
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2252
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:141
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1366
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1235
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:291
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:296
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2161
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::isAcquireOrStronger
bool isAcquireOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:128
Triple.h
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1177
TargetOptions.h
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:912
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1095
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:629
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:206
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:629
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1315
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:692
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1607
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:304
llvm::ISD::ABDU
@ ABDU
Definition: ISDOpcodes.h:622
llvm::isReleaseOrStronger
bool isReleaseOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:889
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1141
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2378
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3246
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3227
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RecurKind::Mul
@ Mul
Product of integers.
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:877
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1767
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:355
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:878
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:431
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:127
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1237
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:379
llvm::getApproximateEVTForLLT
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
Definition: LowLevelType.cpp:55
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:139
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1139
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:575
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:346
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:207
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:634
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:846
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:952
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:339
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2207
Attributes.h
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:2009
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:415
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1389
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2379
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:899
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:234
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:800
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:612
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2244
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:300
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2381
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2101
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:257
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1234
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:296
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:361
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1314
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: TargetLoweringBase.cpp:918
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:879
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:687
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:178
Enabled
static bool Enabled
Definition: Statistic.cpp:46
llvm::TypeSize
Definition: TypeSize.h:416
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:577
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::LinearPolySize< ElementCount >::getScalable
static ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1236
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:776
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:353
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:413
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:733
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:957
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:211
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2919
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2058
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:922
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:740
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:314
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:215
llvm::InstructionCost::getInvalid
static InstructionCost getInvalid(CostType Val=0)
Definition: InstructionCost.h:73
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:497
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1737
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:301
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:833
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:480
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:378
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1101
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1653
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1710
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:212
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1068
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:381
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:199
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:780
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:54
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:212
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1292
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1539
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:670
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1317
llvm::AttributeList::hasRetAttr
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:736
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2017
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:129
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:261
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:671
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:165
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1477
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2377
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:432
llvm::TypeSize::getKnownMinSize
ScalarTy getKnownMinSize() const
Definition: TypeSize.h:426
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:628
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:886
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2272
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:402
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:808
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:866
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:368
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3227
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3211
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:697
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1145
llvm::MVT::fp_valuetypes
static auto fp_valuetypes()
Definition: MachineValueType.h:1418
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1426
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:51
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1239
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:213
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1241
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2227
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:156
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1102
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:182
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:880
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LinearPolySize::divideCoefficientBy
LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:360
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:500
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:874
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3225
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2217
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:814
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:220
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
TargetRegisterInfo.h
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:52
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2270
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::LinearPolySize::coefficientNextPowerOf2
LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:365
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:327
llvm::MVT::VALUETYPE_SIZE
@ VALUETYPE_SIZE
Definition: MachineValueType.h:277
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1148
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:706
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:946
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:315
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1158
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:232
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:380
llvm::LLT
Definition: LowLevelTypeImpl.h:40