LLVM  13.0.0git
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <cstring>
61 #include <iterator>
62 #include <string>
63 #include <tuple>
64 #include <utility>
65 
66 using namespace llvm;
67 
69  "jump-is-expensive", cl::init(false),
70  cl::desc("Do not create extra branches to split comparison logic."),
71  cl::Hidden);
72 
74  ("min-jump-table-entries", cl::init(4), cl::Hidden,
75  cl::desc("Set minimum number of entries to use a jump table."));
76 
78  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79  cl::desc("Set maximum size of jump tables."));
80 
81 /// Minimum jump table density for normal functions.
82 static cl::opt<unsigned>
83  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84  cl::desc("Minimum density for building a jump table in "
85  "a normal function"));
86 
87 /// Minimum jump table density for -Os or -Oz functions.
89  "optsize-jump-table-density", cl::init(40), cl::Hidden,
90  cl::desc("Minimum density for building a jump table in "
91  "an optsize function"));
92 
93 // FIXME: This option is only to test if the strict fp operation processed
94 // correctly by preventing mutating strict fp operation to normal fp operation
95 // during development. When the backend supports strict float operation, this
96 // option will be meaningless.
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98  cl::desc("Don't mutate strict-float node to a legalize node"),
99  cl::init(false), cl::Hidden);
100 
101 static bool darwinHasSinCos(const Triple &TT) {
102  assert(TT.isOSDarwin() && "should be called with darwin triple");
103  // Don't bother with 32 bit x86.
104  if (TT.getArch() == Triple::x86)
105  return false;
106  // Macos < 10.9 has no sincos_stret.
107  if (TT.isMacOSX())
108  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109  // iOS < 7.0 has no sincos_stret.
110  if (TT.isiOS())
111  return !TT.isOSVersionLT(7, 0);
112  // Any other darwin such as WatchOS/TvOS is new enough.
113  return true;
114 }
115 
116 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117 #define HANDLE_LIBCALL(code, name) \
118  setLibcallName(RTLIB::code, name);
119 #include "llvm/IR/RuntimeLibcalls.def"
120 #undef HANDLE_LIBCALL
121  // Initialize calling conventions to their default.
122  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 
125  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
126  if (TT.isPPC()) {
127  setLibcallName(RTLIB::ADD_F128, "__addkf3");
128  setLibcallName(RTLIB::SUB_F128, "__subkf3");
129  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
130  setLibcallName(RTLIB::DIV_F128, "__divkf3");
131  setLibcallName(RTLIB::POWI_F128, "__powikf2");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
139  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
140  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
142  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
143  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
144  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
145  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
146  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
147  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
148  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
149  setLibcallName(RTLIB::UNE_F128, "__nekf2");
150  setLibcallName(RTLIB::OGE_F128, "__gekf2");
151  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
152  setLibcallName(RTLIB::OLE_F128, "__lekf2");
153  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
154  setLibcallName(RTLIB::UO_F128, "__unordkf2");
155  }
156 
157  // A few names are different on particular architectures or environments.
158  if (TT.isOSDarwin()) {
159  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
160  // of the gnueabi-style __gnu_*_ieee.
161  // FIXME: What about other targets?
162  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
163  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
164 
165  // Some darwins have an optimized __bzero/bzero function.
166  switch (TT.getArch()) {
167  case Triple::x86:
168  case Triple::x86_64:
169  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
170  setLibcallName(RTLIB::BZERO, "__bzero");
171  break;
172  case Triple::aarch64:
173  case Triple::aarch64_32:
174  setLibcallName(RTLIB::BZERO, "bzero");
175  break;
176  default:
177  break;
178  }
179 
180  if (darwinHasSinCos(TT)) {
181  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
182  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
183  if (TT.isWatchABI()) {
184  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
186  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
188  }
189  }
190  } else {
191  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
192  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
193  }
194 
195  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
196  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
197  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
198  setLibcallName(RTLIB::SINCOS_F64, "sincos");
199  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
200  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
201  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
202  }
203 
204  if (TT.isPS4CPU()) {
205  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
206  setLibcallName(RTLIB::SINCOS_F64, "sincos");
207  }
208 
209  if (TT.isOSOpenBSD()) {
210  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
211  }
212 }
213 
214 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
215 /// UNKNOWN_LIBCALL if there is none.
217  if (OpVT == MVT::f16) {
218  if (RetVT == MVT::f32)
219  return FPEXT_F16_F32;
220  if (RetVT == MVT::f64)
221  return FPEXT_F16_F64;
222  if (RetVT == MVT::f128)
223  return FPEXT_F16_F128;
224  } else if (OpVT == MVT::f32) {
225  if (RetVT == MVT::f64)
226  return FPEXT_F32_F64;
227  if (RetVT == MVT::f128)
228  return FPEXT_F32_F128;
229  if (RetVT == MVT::ppcf128)
230  return FPEXT_F32_PPCF128;
231  } else if (OpVT == MVT::f64) {
232  if (RetVT == MVT::f128)
233  return FPEXT_F64_F128;
234  else if (RetVT == MVT::ppcf128)
235  return FPEXT_F64_PPCF128;
236  } else if (OpVT == MVT::f80) {
237  if (RetVT == MVT::f128)
238  return FPEXT_F80_F128;
239  }
240 
241  return UNKNOWN_LIBCALL;
242 }
243 
244 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
245 /// UNKNOWN_LIBCALL if there is none.
247  if (RetVT == MVT::f16) {
248  if (OpVT == MVT::f32)
249  return FPROUND_F32_F16;
250  if (OpVT == MVT::f64)
251  return FPROUND_F64_F16;
252  if (OpVT == MVT::f80)
253  return FPROUND_F80_F16;
254  if (OpVT == MVT::f128)
255  return FPROUND_F128_F16;
256  if (OpVT == MVT::ppcf128)
257  return FPROUND_PPCF128_F16;
258  } else if (RetVT == MVT::f32) {
259  if (OpVT == MVT::f64)
260  return FPROUND_F64_F32;
261  if (OpVT == MVT::f80)
262  return FPROUND_F80_F32;
263  if (OpVT == MVT::f128)
264  return FPROUND_F128_F32;
265  if (OpVT == MVT::ppcf128)
266  return FPROUND_PPCF128_F32;
267  } else if (RetVT == MVT::f64) {
268  if (OpVT == MVT::f80)
269  return FPROUND_F80_F64;
270  if (OpVT == MVT::f128)
271  return FPROUND_F128_F64;
272  if (OpVT == MVT::ppcf128)
273  return FPROUND_PPCF128_F64;
274  } else if (RetVT == MVT::f80) {
275  if (OpVT == MVT::f128)
276  return FPROUND_F128_F80;
277  }
278 
279  return UNKNOWN_LIBCALL;
280 }
281 
282 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
283 /// UNKNOWN_LIBCALL if there is none.
285  if (OpVT == MVT::f16) {
286  if (RetVT == MVT::i32)
287  return FPTOSINT_F16_I32;
288  if (RetVT == MVT::i64)
289  return FPTOSINT_F16_I64;
290  if (RetVT == MVT::i128)
291  return FPTOSINT_F16_I128;
292  } else if (OpVT == MVT::f32) {
293  if (RetVT == MVT::i32)
294  return FPTOSINT_F32_I32;
295  if (RetVT == MVT::i64)
296  return FPTOSINT_F32_I64;
297  if (RetVT == MVT::i128)
298  return FPTOSINT_F32_I128;
299  } else if (OpVT == MVT::f64) {
300  if (RetVT == MVT::i32)
301  return FPTOSINT_F64_I32;
302  if (RetVT == MVT::i64)
303  return FPTOSINT_F64_I64;
304  if (RetVT == MVT::i128)
305  return FPTOSINT_F64_I128;
306  } else if (OpVT == MVT::f80) {
307  if (RetVT == MVT::i32)
308  return FPTOSINT_F80_I32;
309  if (RetVT == MVT::i64)
310  return FPTOSINT_F80_I64;
311  if (RetVT == MVT::i128)
312  return FPTOSINT_F80_I128;
313  } else if (OpVT == MVT::f128) {
314  if (RetVT == MVT::i32)
315  return FPTOSINT_F128_I32;
316  if (RetVT == MVT::i64)
317  return FPTOSINT_F128_I64;
318  if (RetVT == MVT::i128)
319  return FPTOSINT_F128_I128;
320  } else if (OpVT == MVT::ppcf128) {
321  if (RetVT == MVT::i32)
322  return FPTOSINT_PPCF128_I32;
323  if (RetVT == MVT::i64)
324  return FPTOSINT_PPCF128_I64;
325  if (RetVT == MVT::i128)
326  return FPTOSINT_PPCF128_I128;
327  }
328  return UNKNOWN_LIBCALL;
329 }
330 
331 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
332 /// UNKNOWN_LIBCALL if there is none.
334  if (OpVT == MVT::f16) {
335  if (RetVT == MVT::i32)
336  return FPTOUINT_F16_I32;
337  if (RetVT == MVT::i64)
338  return FPTOUINT_F16_I64;
339  if (RetVT == MVT::i128)
340  return FPTOUINT_F16_I128;
341  } else if (OpVT == MVT::f32) {
342  if (RetVT == MVT::i32)
343  return FPTOUINT_F32_I32;
344  if (RetVT == MVT::i64)
345  return FPTOUINT_F32_I64;
346  if (RetVT == MVT::i128)
347  return FPTOUINT_F32_I128;
348  } else if (OpVT == MVT::f64) {
349  if (RetVT == MVT::i32)
350  return FPTOUINT_F64_I32;
351  if (RetVT == MVT::i64)
352  return FPTOUINT_F64_I64;
353  if (RetVT == MVT::i128)
354  return FPTOUINT_F64_I128;
355  } else if (OpVT == MVT::f80) {
356  if (RetVT == MVT::i32)
357  return FPTOUINT_F80_I32;
358  if (RetVT == MVT::i64)
359  return FPTOUINT_F80_I64;
360  if (RetVT == MVT::i128)
361  return FPTOUINT_F80_I128;
362  } else if (OpVT == MVT::f128) {
363  if (RetVT == MVT::i32)
364  return FPTOUINT_F128_I32;
365  if (RetVT == MVT::i64)
366  return FPTOUINT_F128_I64;
367  if (RetVT == MVT::i128)
368  return FPTOUINT_F128_I128;
369  } else if (OpVT == MVT::ppcf128) {
370  if (RetVT == MVT::i32)
371  return FPTOUINT_PPCF128_I32;
372  if (RetVT == MVT::i64)
373  return FPTOUINT_PPCF128_I64;
374  if (RetVT == MVT::i128)
375  return FPTOUINT_PPCF128_I128;
376  }
377  return UNKNOWN_LIBCALL;
378 }
379 
380 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
381 /// UNKNOWN_LIBCALL if there is none.
383  if (OpVT == MVT::i32) {
384  if (RetVT == MVT::f16)
385  return SINTTOFP_I32_F16;
386  if (RetVT == MVT::f32)
387  return SINTTOFP_I32_F32;
388  if (RetVT == MVT::f64)
389  return SINTTOFP_I32_F64;
390  if (RetVT == MVT::f80)
391  return SINTTOFP_I32_F80;
392  if (RetVT == MVT::f128)
393  return SINTTOFP_I32_F128;
394  if (RetVT == MVT::ppcf128)
395  return SINTTOFP_I32_PPCF128;
396  } else if (OpVT == MVT::i64) {
397  if (RetVT == MVT::f16)
398  return SINTTOFP_I64_F16;
399  if (RetVT == MVT::f32)
400  return SINTTOFP_I64_F32;
401  if (RetVT == MVT::f64)
402  return SINTTOFP_I64_F64;
403  if (RetVT == MVT::f80)
404  return SINTTOFP_I64_F80;
405  if (RetVT == MVT::f128)
406  return SINTTOFP_I64_F128;
407  if (RetVT == MVT::ppcf128)
408  return SINTTOFP_I64_PPCF128;
409  } else if (OpVT == MVT::i128) {
410  if (RetVT == MVT::f16)
411  return SINTTOFP_I128_F16;
412  if (RetVT == MVT::f32)
413  return SINTTOFP_I128_F32;
414  if (RetVT == MVT::f64)
415  return SINTTOFP_I128_F64;
416  if (RetVT == MVT::f80)
417  return SINTTOFP_I128_F80;
418  if (RetVT == MVT::f128)
419  return SINTTOFP_I128_F128;
420  if (RetVT == MVT::ppcf128)
421  return SINTTOFP_I128_PPCF128;
422  }
423  return UNKNOWN_LIBCALL;
424 }
425 
426 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
427 /// UNKNOWN_LIBCALL if there is none.
429  if (OpVT == MVT::i32) {
430  if (RetVT == MVT::f16)
431  return UINTTOFP_I32_F16;
432  if (RetVT == MVT::f32)
433  return UINTTOFP_I32_F32;
434  if (RetVT == MVT::f64)
435  return UINTTOFP_I32_F64;
436  if (RetVT == MVT::f80)
437  return UINTTOFP_I32_F80;
438  if (RetVT == MVT::f128)
439  return UINTTOFP_I32_F128;
440  if (RetVT == MVT::ppcf128)
441  return UINTTOFP_I32_PPCF128;
442  } else if (OpVT == MVT::i64) {
443  if (RetVT == MVT::f16)
444  return UINTTOFP_I64_F16;
445  if (RetVT == MVT::f32)
446  return UINTTOFP_I64_F32;
447  if (RetVT == MVT::f64)
448  return UINTTOFP_I64_F64;
449  if (RetVT == MVT::f80)
450  return UINTTOFP_I64_F80;
451  if (RetVT == MVT::f128)
452  return UINTTOFP_I64_F128;
453  if (RetVT == MVT::ppcf128)
454  return UINTTOFP_I64_PPCF128;
455  } else if (OpVT == MVT::i128) {
456  if (RetVT == MVT::f16)
457  return UINTTOFP_I128_F16;
458  if (RetVT == MVT::f32)
459  return UINTTOFP_I128_F32;
460  if (RetVT == MVT::f64)
461  return UINTTOFP_I128_F64;
462  if (RetVT == MVT::f80)
463  return UINTTOFP_I128_F80;
464  if (RetVT == MVT::f128)
465  return UINTTOFP_I128_F128;
466  if (RetVT == MVT::ppcf128)
467  return UINTTOFP_I128_PPCF128;
468  }
469  return UNKNOWN_LIBCALL;
470 }
471 
473  MVT VT) {
474  unsigned ModeN, ModelN;
475  switch (VT.SimpleTy) {
476  case MVT::i8:
477  ModeN = 0;
478  break;
479  case MVT::i16:
480  ModeN = 1;
481  break;
482  case MVT::i32:
483  ModeN = 2;
484  break;
485  case MVT::i64:
486  ModeN = 3;
487  break;
488  case MVT::i128:
489  ModeN = 4;
490  break;
491  default:
492  return UNKNOWN_LIBCALL;
493  }
494 
495  switch (Order) {
497  ModelN = 0;
498  break;
500  ModelN = 1;
501  break;
503  ModelN = 2;
504  break;
507  ModelN = 3;
508  break;
509  default:
510  return UNKNOWN_LIBCALL;
511  }
512 
513 #define LCALLS(A, B) \
514  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
515 #define LCALL5(A) \
516  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
517  switch (Opc) {
518  case ISD::ATOMIC_CMP_SWAP: {
519  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
520  return LC[ModeN][ModelN];
521  }
522  case ISD::ATOMIC_SWAP: {
523  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
524  return LC[ModeN][ModelN];
525  }
526  case ISD::ATOMIC_LOAD_ADD: {
527  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
528  return LC[ModeN][ModelN];
529  }
530  case ISD::ATOMIC_LOAD_OR: {
531  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
532  return LC[ModeN][ModelN];
533  }
534  case ISD::ATOMIC_LOAD_CLR: {
535  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
536  return LC[ModeN][ModelN];
537  }
538  case ISD::ATOMIC_LOAD_XOR: {
539  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
540  return LC[ModeN][ModelN];
541  }
542  default:
543  return UNKNOWN_LIBCALL;
544  }
545 #undef LCALLS
546 #undef LCALL5
547 }
548 
549 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
550 #define OP_TO_LIBCALL(Name, Enum) \
551  case Name: \
552  switch (VT.SimpleTy) { \
553  default: \
554  return UNKNOWN_LIBCALL; \
555  case MVT::i8: \
556  return Enum##_1; \
557  case MVT::i16: \
558  return Enum##_2; \
559  case MVT::i32: \
560  return Enum##_4; \
561  case MVT::i64: \
562  return Enum##_8; \
563  case MVT::i128: \
564  return Enum##_16; \
565  }
566 
567  switch (Opc) {
568  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
569  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
570  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
571  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
572  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
573  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
574  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
575  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
576  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
577  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
578  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
579  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
580  }
581 
582 #undef OP_TO_LIBCALL
583 
584  return UNKNOWN_LIBCALL;
585 }
586 
588  switch (ElementSize) {
589  case 1:
590  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
591  case 2:
592  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
593  case 4:
594  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
595  case 8:
596  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
597  case 16:
598  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
599  default:
600  return UNKNOWN_LIBCALL;
601  }
602 }
603 
605  switch (ElementSize) {
606  case 1:
607  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
608  case 2:
609  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
610  case 4:
611  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
612  case 8:
613  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
614  case 16:
615  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
616  default:
617  return UNKNOWN_LIBCALL;
618  }
619 }
620 
622  switch (ElementSize) {
623  case 1:
624  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
625  case 2:
626  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
627  case 4:
628  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
629  case 8:
630  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
631  case 16:
632  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
633  default:
634  return UNKNOWN_LIBCALL;
635  }
636 }
637 
638 /// InitCmpLibcallCCs - Set default comparison libcall CC.
639 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
640  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
641  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
642  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
643  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
644  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
645  CCs[RTLIB::UNE_F32] = ISD::SETNE;
646  CCs[RTLIB::UNE_F64] = ISD::SETNE;
647  CCs[RTLIB::UNE_F128] = ISD::SETNE;
648  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
649  CCs[RTLIB::OGE_F32] = ISD::SETGE;
650  CCs[RTLIB::OGE_F64] = ISD::SETGE;
651  CCs[RTLIB::OGE_F128] = ISD::SETGE;
652  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
653  CCs[RTLIB::OLT_F32] = ISD::SETLT;
654  CCs[RTLIB::OLT_F64] = ISD::SETLT;
655  CCs[RTLIB::OLT_F128] = ISD::SETLT;
656  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
657  CCs[RTLIB::OLE_F32] = ISD::SETLE;
658  CCs[RTLIB::OLE_F64] = ISD::SETLE;
659  CCs[RTLIB::OLE_F128] = ISD::SETLE;
660  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
661  CCs[RTLIB::OGT_F32] = ISD::SETGT;
662  CCs[RTLIB::OGT_F64] = ISD::SETGT;
663  CCs[RTLIB::OGT_F128] = ISD::SETGT;
664  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
665  CCs[RTLIB::UO_F32] = ISD::SETNE;
666  CCs[RTLIB::UO_F64] = ISD::SETNE;
667  CCs[RTLIB::UO_F128] = ISD::SETNE;
668  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
669 }
670 
671 /// NOTE: The TargetMachine owns TLOF.
673  initActions();
674 
675  // Perform these initializations only once.
677  MaxLoadsPerMemcmp = 8;
681  HasMultipleConditionRegisters = false;
682  HasExtractBitsInsn = false;
683  JumpIsExpensive = JumpIsExpensiveOverride;
685  EnableExtLdPromotion = false;
686  StackPointerRegisterToSaveRestore = 0;
687  BooleanContents = UndefinedBooleanContent;
688  BooleanFloatContents = UndefinedBooleanContent;
689  BooleanVectorContents = UndefinedBooleanContent;
690  SchedPreferenceInfo = Sched::ILP;
693  // TODO: the default will be switched to 0 in the next commit, along
694  // with the Target-specific changes necessary.
695  MaxAtomicSizeInBitsSupported = 1024;
696 
697  MinCmpXchgSizeInBits = 0;
698  SupportsUnalignedAtomics = false;
699 
700  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
701 
702  InitLibcalls(TM.getTargetTriple());
703  InitCmpLibcallCCs(CmpLibcallCCs);
704 }
705 
707  // All operations default to being supported.
708  memset(OpActions, 0, sizeof(OpActions));
709  memset(LoadExtActions, 0, sizeof(LoadExtActions));
710  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
711  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
712  memset(CondCodeActions, 0, sizeof(CondCodeActions));
713  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
714  std::fill(std::begin(TargetDAGCombineArray),
715  std::end(TargetDAGCombineArray), 0);
716 
717  for (MVT VT : MVT::fp_valuetypes()) {
718  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
719  if (IntVT.isValid()) {
722  }
723  }
724 
725  // Set default actions for various operations.
726  for (MVT VT : MVT::all_valuetypes()) {
727  // Default all indexed load / store to expand.
728  for (unsigned IM = (unsigned)ISD::PRE_INC;
729  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
730  setIndexedLoadAction(IM, VT, Expand);
731  setIndexedStoreAction(IM, VT, Expand);
734  }
735 
736  // Most backends expect to see the node which just returns the value loaded.
738 
739  // These operations default to expand.
772 
773  // Overflow operations default to expand
780 
781  // ADDCARRY operations default to expand
787 
788  // ADDC/ADDE/SUBC/SUBE default to expand.
793 
794  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
797 
800 
801  // These library functions default to expand.
805 
806  // These operations default to expand for vector types.
807  if (VT.isVector()) {
814  }
815 
816  // Constrained floating-point operations default to expand.
817 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
818  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
819 #include "llvm/IR/ConstrainedOps.def"
820 
821  // For most targets @llvm.get.dynamic.area.offset just returns 0.
823 
824  // Vector reduction default to expand.
840 
841  // Named vector shuffles default to expand.
843  }
844 
845  // Most targets ignore the @llvm.prefetch intrinsic.
847 
848  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
850 
851  // ConstantFP nodes default to expand. Targets can either change this to
852  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
853  // to optimize expansions for certain constants.
859 
860  // These library functions default to expand.
861  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
879  }
880 
881  // Default ISD::TRAP to expand (which turns it into abort).
883 
884  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
885  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
887 
889 }
890 
892  EVT) const {
893  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
894 }
895 
897  bool LegalTypes) const {
898  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
899  if (LHSTy.isVector())
900  return LHSTy;
901  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
902  : getPointerTy(DL);
903 }
904 
905 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
906  assert(isTypeLegal(VT));
907  switch (Op) {
908  default:
909  return false;
910  case ISD::SDIV:
911  case ISD::UDIV:
912  case ISD::SREM:
913  case ISD::UREM:
914  return true;
915  }
916 }
917 
919  unsigned DestAS) const {
920  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
921 }
922 
924  // If the command-line option was specified, ignore this request.
926  JumpIsExpensive = isExpensive;
927 }
928 
930 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
931  // If this is a simple type, use the ComputeRegisterProp mechanism.
932  if (VT.isSimple()) {
933  MVT SVT = VT.getSimpleVT();
934  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
935  MVT NVT = TransformToType[SVT.SimpleTy];
936  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
937 
938  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
939  LA == TypeSoftPromoteHalf ||
940  (NVT.isVector() ||
941  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
942  "Promote may not follow Expand or Promote");
943 
944  if (LA == TypeSplitVector)
945  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
946  if (LA == TypeScalarizeVector)
947  return LegalizeKind(LA, SVT.getVectorElementType());
948  return LegalizeKind(LA, NVT);
949  }
950 
951  // Handle Extended Scalar Types.
952  if (!VT.isVector()) {
953  assert(VT.isInteger() && "Float types must be simple");
954  unsigned BitSize = VT.getSizeInBits();
955  // First promote to a power-of-two size, then expand if necessary.
956  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
957  EVT NVT = VT.getRoundIntegerType(Context);
958  assert(NVT != VT && "Unable to round integer VT");
959  LegalizeKind NextStep = getTypeConversion(Context, NVT);
960  // Avoid multi-step promotion.
961  if (NextStep.first == TypePromoteInteger)
962  return NextStep;
963  // Return rounded integer type.
964  return LegalizeKind(TypePromoteInteger, NVT);
965  }
966 
969  }
970 
971  // Handle vector types.
972  ElementCount NumElts = VT.getVectorElementCount();
973  EVT EltVT = VT.getVectorElementType();
974 
975  // Vectors with only one element are always scalarized.
976  if (NumElts.isScalar())
977  return LegalizeKind(TypeScalarizeVector, EltVT);
978 
980  report_fatal_error("Cannot legalize this vector");
981 
982  // Try to widen vector elements until the element type is a power of two and
983  // promote it to a legal type later on, for example:
984  // <3 x i8> -> <4 x i8> -> <4 x i32>
985  if (EltVT.isInteger()) {
986  // Vectors with a number of elements that is not a power of two are always
987  // widened, for example <3 x i8> -> <4 x i8>.
988  if (!VT.isPow2VectorType()) {
989  NumElts = NumElts.coefficientNextPowerOf2();
990  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
991  return LegalizeKind(TypeWidenVector, NVT);
992  }
993 
994  // Examine the element type.
995  LegalizeKind LK = getTypeConversion(Context, EltVT);
996 
997  // If type is to be expanded, split the vector.
998  // <4 x i140> -> <2 x i140>
999  if (LK.first == TypeExpandInteger)
1002 
1003  // Promote the integer element types until a legal vector type is found
1004  // or until the element integer type is too big. If a legal type was not
1005  // found, fallback to the usual mechanism of widening/splitting the
1006  // vector.
1007  EVT OldEltVT = EltVT;
1008  while (true) {
1009  // Increase the bitwidth of the element to the next pow-of-two
1010  // (which is greater than 8 bits).
1011  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1013 
1014  // Stop trying when getting a non-simple element type.
1015  // Note that vector elements may be greater than legal vector element
1016  // types. Example: X86 XMM registers hold 64bit element on 32bit
1017  // systems.
1018  if (!EltVT.isSimple())
1019  break;
1020 
1021  // Build a new vector type and check if it is legal.
1022  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1023  // Found a legal promoted vector type.
1024  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1026  EVT::getVectorVT(Context, EltVT, NumElts));
1027  }
1028 
1029  // Reset the type to the unexpanded type if we did not find a legal vector
1030  // type with a promoted vector element type.
1031  EltVT = OldEltVT;
1032  }
1033 
1034  // Try to widen the vector until a legal type is found.
1035  // If there is no wider legal type, split the vector.
1036  while (true) {
1037  // Round up to the next power of 2.
1038  NumElts = NumElts.coefficientNextPowerOf2();
1039 
1040  // If there is no simple vector type with this many elements then there
1041  // cannot be a larger legal vector type. Note that this assumes that
1042  // there are no skipped intermediate vector types in the simple types.
1043  if (!EltVT.isSimple())
1044  break;
1045  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1046  if (LargerVector == MVT())
1047  break;
1048 
1049  // If this type is legal then widen the vector.
1050  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1051  return LegalizeKind(TypeWidenVector, LargerVector);
1052  }
1053 
1054  // Widen odd vectors to next power of two.
1055  if (!VT.isPow2VectorType()) {
1056  EVT NVT = VT.getPow2VectorType(Context);
1057  return LegalizeKind(TypeWidenVector, NVT);
1058  }
1059 
1060  // Vectors with illegal element types are expanded.
1061  EVT NVT = EVT::getVectorVT(Context, EltVT,
1063  return LegalizeKind(TypeSplitVector, NVT);
1064 }
1065 
1066 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1067  unsigned &NumIntermediates,
1068  MVT &RegisterVT,
1069  TargetLoweringBase *TLI) {
1070  // Figure out the right, legal destination reg to copy into.
1072  MVT EltTy = VT.getVectorElementType();
1073 
1074  unsigned NumVectorRegs = 1;
1075 
1076  // Scalable vectors cannot be scalarized, so splitting or widening is
1077  // required.
1078  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1080  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1081 
1082  // FIXME: We don't support non-power-of-2-sized vectors for now.
1083  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1084  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1085  // Split EC to unit size (scalable property is preserved).
1086  NumVectorRegs = EC.getKnownMinValue();
1087  EC = ElementCount::getFixed(1);
1088  }
1089 
1090  // Divide the input until we get to a supported size. This will
1091  // always end up with an EC that represent a scalar or a scalable
1092  // scalar.
1093  while (EC.getKnownMinValue() > 1 &&
1094  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1095  EC = EC.divideCoefficientBy(2);
1096  NumVectorRegs <<= 1;
1097  }
1098 
1099  NumIntermediates = NumVectorRegs;
1100 
1101  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1102  if (!TLI->isTypeLegal(NewVT))
1103  NewVT = EltTy;
1104  IntermediateVT = NewVT;
1105 
1106  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1107 
1108  // Convert sizes such as i33 to i64.
1109  if (!isPowerOf2_32(LaneSizeInBits))
1110  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1111 
1112  MVT DestVT = TLI->getRegisterType(NewVT);
1113  RegisterVT = DestVT;
1114  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1115  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1116 
1117  // Otherwise, promotion or legal types use the same number of registers as
1118  // the vector decimated to the appropriate level.
1119  return NumVectorRegs;
1120 }
1121 
1122 /// isLegalRC - Return true if the value types that can be represented by the
1123 /// specified register class are all legal.
1125  const TargetRegisterClass &RC) const {
1126  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1127  if (isTypeLegal(*I))
1128  return true;
1129  return false;
1130 }
1131 
1132 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1133 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1136  MachineBasicBlock *MBB) const {
1137  MachineInstr *MI = &InitialMI;
1138  MachineFunction &MF = *MI->getMF();
1139  MachineFrameInfo &MFI = MF.getFrameInfo();
1140 
1141  // We're handling multiple types of operands here:
1142  // PATCHPOINT MetaArgs - live-in, read only, direct
1143  // STATEPOINT Deopt Spill - live-through, read only, indirect
1144  // STATEPOINT Deopt Alloca - live-through, read only, direct
1145  // (We're currently conservative and mark the deopt slots read/write in
1146  // practice.)
1147  // STATEPOINT GC Spill - live-through, read/write, indirect
1148  // STATEPOINT GC Alloca - live-through, read/write, direct
1149  // The live-in vs live-through is handled already (the live through ones are
1150  // all stack slots), but we need to handle the different type of stackmap
1151  // operands and memory effects here.
1152 
1153  if (!llvm::any_of(MI->operands(),
1154  [](MachineOperand &Operand) { return Operand.isFI(); }))
1155  return MBB;
1156 
1157  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1158 
1159  // Inherit previous memory operands.
1160  MIB.cloneMemRefs(*MI);
1161 
1162  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1163  MachineOperand &MO = MI->getOperand(i);
1164  if (!MO.isFI()) {
1165  // Index of Def operand this Use it tied to.
1166  // Since Defs are coming before Uses, if Use is tied, then
1167  // index of Def must be smaller that index of that Use.
1168  // Also, Defs preserve their position in new MI.
1169  unsigned TiedTo = i;
1170  if (MO.isReg() && MO.isTied())
1171  TiedTo = MI->findTiedOperandIdx(i);
1172  MIB.add(MO);
1173  if (TiedTo < i)
1174  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1175  continue;
1176  }
1177 
1178  // foldMemoryOperand builds a new MI after replacing a single FI operand
1179  // with the canonical set of five x86 addressing-mode operands.
1180  int FI = MO.getIndex();
1181 
1182  // Add frame index operands recognized by stackmaps.cpp
1183  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1184  // indirect-mem-ref tag, size, #FI, offset.
1185  // Used for spills inserted by StatepointLowering. This codepath is not
1186  // used for patchpoints/stackmaps at all, for these spilling is done via
1187  // foldMemoryOperand callback only.
1188  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1189  MIB.addImm(StackMaps::IndirectMemRefOp);
1190  MIB.addImm(MFI.getObjectSize(FI));
1191  MIB.add(MO);
1192  MIB.addImm(0);
1193  } else {
1194  // direct-mem-ref tag, #FI, offset.
1195  // Used by patchpoint, and direct alloca arguments to statepoints
1196  MIB.addImm(StackMaps::DirectMemRefOp);
1197  MIB.add(MO);
1198  MIB.addImm(0);
1199  }
1200 
1201  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1202 
1203  // Add a new memory operand for this FI.
1204  assert(MFI.getObjectOffset(FI) != -1);
1205 
1206  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1207  // PATCHPOINT should be updated to do the same. (TODO)
1208  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1209  auto Flags = MachineMemOperand::MOLoad;
1211  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1212  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1213  MIB->addMemOperand(MF, MMO);
1214  }
1215  }
1217  MI->eraseFromParent();
1218  return MBB;
1219 }
1220 
1221 /// findRepresentativeClass - Return the largest legal super-reg register class
1222 /// of the register class for the specified type and its associated "cost".
1223 // This function is in TargetLowering because it uses RegClassForVT which would
1224 // need to be moved to TargetRegisterInfo and would necessitate moving
1225 // isTypeLegal over as well - a massive change that would just require
1226 // TargetLowering having a TargetRegisterInfo class member that it would use.
1227 std::pair<const TargetRegisterClass *, uint8_t>
1229  MVT VT) const {
1230  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1231  if (!RC)
1232  return std::make_pair(RC, 0);
1233 
1234  // Compute the set of all super-register classes.
1235  BitVector SuperRegRC(TRI->getNumRegClasses());
1236  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1237  SuperRegRC.setBitsInMask(RCI.getMask());
1238 
1239  // Find the first legal register class with the largest spill size.
1240  const TargetRegisterClass *BestRC = RC;
1241  for (unsigned i : SuperRegRC.set_bits()) {
1242  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1243  // We want the largest possible spill size.
1244  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1245  continue;
1246  if (!isLegalRC(*TRI, *SuperRC))
1247  continue;
1248  BestRC = SuperRC;
1249  }
1250  return std::make_pair(BestRC, 1);
1251 }
1252 
1253 /// computeRegisterProperties - Once all of the register classes are added,
1254 /// this allows us to compute derived properties we expose.
1256  const TargetRegisterInfo *TRI) {
1258  "Too many value types for ValueTypeActions to hold!");
1259 
1260  // Everything defaults to needing one register.
1261  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1262  NumRegistersForVT[i] = 1;
1263  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1264  }
1265  // ...except isVoid, which doesn't need any registers.
1266  NumRegistersForVT[MVT::isVoid] = 0;
1267 
1268  // Find the largest integer register class.
1269  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1270  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1271  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1272 
1273  // Every integer value type larger than this largest register takes twice as
1274  // many registers to represent as the previous ValueType.
1275  for (unsigned ExpandedReg = LargestIntReg + 1;
1276  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1277  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1278  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1279  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1280  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1282  }
1283 
1284  // Inspect all of the ValueType's smaller than the largest integer
1285  // register to see which ones need promotion.
1286  unsigned LegalIntReg = LargestIntReg;
1287  for (unsigned IntReg = LargestIntReg - 1;
1288  IntReg >= (unsigned)MVT::i1; --IntReg) {
1289  MVT IVT = (MVT::SimpleValueType)IntReg;
1290  if (isTypeLegal(IVT)) {
1291  LegalIntReg = IntReg;
1292  } else {
1293  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1294  (MVT::SimpleValueType)LegalIntReg;
1295  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1296  }
1297  }
1298 
1299  // ppcf128 type is really two f64's.
1300  if (!isTypeLegal(MVT::ppcf128)) {
1301  if (isTypeLegal(MVT::f64)) {
1302  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1303  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1304  TransformToType[MVT::ppcf128] = MVT::f64;
1305  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1306  } else {
1307  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1308  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1309  TransformToType[MVT::ppcf128] = MVT::i128;
1310  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1311  }
1312  }
1313 
1314  // Decide how to handle f128. If the target does not have native f128 support,
1315  // expand it to i128 and we will be generating soft float library calls.
1316  if (!isTypeLegal(MVT::f128)) {
1317  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1318  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1319  TransformToType[MVT::f128] = MVT::i128;
1320  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1321  }
1322 
1323  // Decide how to handle f64. If the target does not have native f64 support,
1324  // expand it to i64 and we will be generating soft float library calls.
1325  if (!isTypeLegal(MVT::f64)) {
1326  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1327  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1328  TransformToType[MVT::f64] = MVT::i64;
1329  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1330  }
1331 
1332  // Decide how to handle f32. If the target does not have native f32 support,
1333  // expand it to i32 and we will be generating soft float library calls.
1334  if (!isTypeLegal(MVT::f32)) {
1335  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1336  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1337  TransformToType[MVT::f32] = MVT::i32;
1338  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1339  }
1340 
1341  // Decide how to handle f16. If the target does not have native f16 support,
1342  // promote it to f32, because there are no f16 library calls (except for
1343  // conversions).
1344  if (!isTypeLegal(MVT::f16)) {
1345  // Allow targets to control how we legalize half.
1346  if (softPromoteHalfType()) {
1347  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1348  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1349  TransformToType[MVT::f16] = MVT::f32;
1350  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1351  } else {
1352  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1353  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1354  TransformToType[MVT::f16] = MVT::f32;
1355  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1356  }
1357  }
1358 
1359  // Loop over all of the vector value types to see which need transformations.
1360  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1361  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1362  MVT VT = (MVT::SimpleValueType) i;
1363  if (isTypeLegal(VT))
1364  continue;
1365 
1366  MVT EltVT = VT.getVectorElementType();
1368  bool IsLegalWiderType = false;
1369  bool IsScalable = VT.isScalableVector();
1370  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1371  switch (PreferredAction) {
1372  case TypePromoteInteger: {
1373  MVT::SimpleValueType EndVT = IsScalable ?
1376  // Try to promote the elements of integer vectors. If no legal
1377  // promotion was found, fall through to the widen-vector method.
1378  for (unsigned nVT = i + 1;
1379  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1380  MVT SVT = (MVT::SimpleValueType) nVT;
1381  // Promote vectors of integers to vectors with the same number
1382  // of elements, with a wider element type.
1383  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1384  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1385  TransformToType[i] = SVT;
1386  RegisterTypeForVT[i] = SVT;
1387  NumRegistersForVT[i] = 1;
1388  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1389  IsLegalWiderType = true;
1390  break;
1391  }
1392  }
1393  if (IsLegalWiderType)
1394  break;
1396  }
1397 
1398  case TypeWidenVector:
1399  if (isPowerOf2_32(EC.getKnownMinValue())) {
1400  // Try to widen the vector.
1401  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1402  MVT SVT = (MVT::SimpleValueType) nVT;
1403  if (SVT.getVectorElementType() == EltVT &&
1404  SVT.isScalableVector() == IsScalable &&
1406  EC.getKnownMinValue() &&
1407  isTypeLegal(SVT)) {
1408  TransformToType[i] = SVT;
1409  RegisterTypeForVT[i] = SVT;
1410  NumRegistersForVT[i] = 1;
1411  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1412  IsLegalWiderType = true;
1413  break;
1414  }
1415  }
1416  if (IsLegalWiderType)
1417  break;
1418  } else {
1419  // Only widen to the next power of 2 to keep consistency with EVT.
1420  MVT NVT = VT.getPow2VectorType();
1421  if (isTypeLegal(NVT)) {
1422  TransformToType[i] = NVT;
1423  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1424  RegisterTypeForVT[i] = NVT;
1425  NumRegistersForVT[i] = 1;
1426  break;
1427  }
1428  }
1430 
1431  case TypeSplitVector:
1432  case TypeScalarizeVector: {
1433  MVT IntermediateVT;
1434  MVT RegisterVT;
1435  unsigned NumIntermediates;
1436  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1437  NumIntermediates, RegisterVT, this);
1438  NumRegistersForVT[i] = NumRegisters;
1439  assert(NumRegistersForVT[i] == NumRegisters &&
1440  "NumRegistersForVT size cannot represent NumRegisters!");
1441  RegisterTypeForVT[i] = RegisterVT;
1442 
1443  MVT NVT = VT.getPow2VectorType();
1444  if (NVT == VT) {
1445  // Type is already a power of 2. The default action is to split.
1446  TransformToType[i] = MVT::Other;
1447  if (PreferredAction == TypeScalarizeVector)
1448  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1449  else if (PreferredAction == TypeSplitVector)
1450  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1451  else if (EC.getKnownMinValue() > 1)
1452  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1453  else
1454  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1457  } else {
1458  TransformToType[i] = NVT;
1459  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1460  }
1461  break;
1462  }
1463  default:
1464  llvm_unreachable("Unknown vector legalization action!");
1465  }
1466  }
1467 
1468  // Determine the 'representative' register class for each value type.
1469  // An representative register class is the largest (meaning one which is
1470  // not a sub-register class / subreg register class) legal register class for
1471  // a group of value types. For example, on i386, i8, i16, and i32
1472  // representative would be GR32; while on x86_64 it's GR64.
1473  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1474  const TargetRegisterClass* RRC;
1475  uint8_t Cost;
1476  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1477  RepRegClassForVT[i] = RRC;
1478  RepRegClassCostForVT[i] = Cost;
1479  }
1480 }
1481 
1483  EVT VT) const {
1484  assert(!VT.isVector() && "No default SetCC type for vectors!");
1485  return getPointerTy(DL).SimpleTy;
1486 }
1487 
1489  return MVT::i32; // return the default value
1490 }
1491 
1492 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1493 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1494 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1495 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1496 ///
1497 /// This method returns the number of registers needed, and the VT for each
1498 /// register. It also returns the VT and quantity of the intermediate values
1499 /// before they are promoted/expanded.
1501  EVT &IntermediateVT,
1502  unsigned &NumIntermediates,
1503  MVT &RegisterVT) const {
1504  ElementCount EltCnt = VT.getVectorElementCount();
1505 
1506  // If there is a wider vector type with the same element type as this one,
1507  // or a promoted vector type that has the same number of elements which
1508  // are wider, then we should convert to that legal vector type.
1509  // This handles things like <2 x float> -> <4 x float> and
1510  // <4 x i1> -> <4 x i32>.
1512  if (EltCnt.getKnownMinValue() != 1 &&
1513  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1514  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1515  if (isTypeLegal(RegisterEVT)) {
1516  IntermediateVT = RegisterEVT;
1517  RegisterVT = RegisterEVT.getSimpleVT();
1518  NumIntermediates = 1;
1519  return 1;
1520  }
1521  }
1522 
1523  // Figure out the right, legal destination reg to copy into.
1524  EVT EltTy = VT.getVectorElementType();
1525 
1526  unsigned NumVectorRegs = 1;
1527 
1528  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1529  // types like done elsewhere in SelectionDAG.
1530  if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) {
1531  LegalizeKind LK;
1532  EVT PartVT = VT;
1533  do {
1534  // Iterate until we've found a legal (part) type to hold VT.
1535  LK = getTypeConversion(Context, PartVT);
1536  PartVT = LK.second;
1537  } while (LK.first != TypeLegal);
1538 
1539  NumIntermediates = VT.getVectorElementCount().getKnownMinValue() /
1541 
1542  // FIXME: This code needs to be extended to handle more complex vector
1543  // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only
1544  // supported cases are vectors that are broken down into equal parts
1545  // such as nxv6i64 -> 3 x nxv2i64.
1546  assert((PartVT.getVectorElementCount() * NumIntermediates) ==
1547  VT.getVectorElementCount() &&
1548  "Expected an integer multiple of PartVT");
1549  IntermediateVT = PartVT;
1550  RegisterVT = getRegisterType(Context, IntermediateVT);
1551  return NumIntermediates;
1552  }
1553 
1554  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1555  // we could break down into LHS/RHS like LegalizeDAG does.
1556  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1557  NumVectorRegs = EltCnt.getKnownMinValue();
1558  EltCnt = ElementCount::getFixed(1);
1559  }
1560 
1561  // Divide the input until we get to a supported size. This will always
1562  // end with a scalar if the target doesn't support vectors.
1563  while (EltCnt.getKnownMinValue() > 1 &&
1564  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1565  EltCnt = EltCnt.divideCoefficientBy(2);
1566  NumVectorRegs <<= 1;
1567  }
1568 
1569  NumIntermediates = NumVectorRegs;
1570 
1571  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1572  if (!isTypeLegal(NewVT))
1573  NewVT = EltTy;
1574  IntermediateVT = NewVT;
1575 
1576  MVT DestVT = getRegisterType(Context, NewVT);
1577  RegisterVT = DestVT;
1578 
1579  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1580  TypeSize NewVTSize = NewVT.getSizeInBits();
1581  // Convert sizes such as i33 to i64.
1582  if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
1583  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1584  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1585  }
1586 
1587  // Otherwise, promotion or legal types use the same number of registers as
1588  // the vector decimated to the appropriate level.
1589  return NumVectorRegs;
1590 }
1591 
1593  uint64_t NumCases,
1594  uint64_t Range,
1595  ProfileSummaryInfo *PSI,
1596  BlockFrequencyInfo *BFI) const {
1597  // FIXME: This function check the maximum table size and density, but the
1598  // minimum size is not checked. It would be nice if the minimum size is
1599  // also combined within this function. Currently, the minimum size check is
1600  // performed in findJumpTable() in SelectionDAGBuiler and
1601  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1602  const bool OptForSize =
1603  SI->getParent()->getParent()->hasOptSize() ||
1604  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1605  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1606  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1607 
1608  // Check whether the number of cases is small enough and
1609  // the range is dense enough for a jump table.
1610  return (OptForSize || Range <= MaxJumpTableSize) &&
1611  (NumCases * 100 >= Range * MinDensity);
1612 }
1613 
1614 /// Get the EVTs and ArgFlags collections that represent the legalized return
1615 /// type of the given function. This does not require a DAG or a return value,
1616 /// and is suitable for use before any DAGs for the function are constructed.
1617 /// TODO: Move this out of TargetLowering.cpp.
1619  AttributeList attr,
1621  const TargetLowering &TLI, const DataLayout &DL) {
1622  SmallVector<EVT, 4> ValueVTs;
1623  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1624  unsigned NumValues = ValueVTs.size();
1625  if (NumValues == 0) return;
1626 
1627  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1628  EVT VT = ValueVTs[j];
1629  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1630 
1631  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1632  ExtendKind = ISD::SIGN_EXTEND;
1633  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1634  ExtendKind = ISD::ZERO_EXTEND;
1635 
1636  // FIXME: C calling convention requires the return type to be promoted to
1637  // at least 32-bit. But this is not necessary for non-C calling
1638  // conventions. The frontend should mark functions whose return values
1639  // require promoting with signext or zeroext attributes.
1640  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1641  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1642  if (VT.bitsLT(MinVT))
1643  VT = MinVT;
1644  }
1645 
1646  unsigned NumParts =
1647  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1648  MVT PartVT =
1649  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1650 
1651  // 'inreg' on function refers to return value
1652  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1653  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1654  Flags.setInReg();
1655 
1656  // Propagate extension type if any
1657  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1658  Flags.setSExt();
1659  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1660  Flags.setZExt();
1661 
1662  for (unsigned i = 0; i < NumParts; ++i)
1663  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1664  }
1665 }
1666 
1667 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1668 /// function arguments in the caller parameter area. This is the actual
1669 /// alignment, not its logarithm.
1671  const DataLayout &DL) const {
1672  return DL.getABITypeAlign(Ty).value();
1673 }
1674 
1676  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1677  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1678  // Check if the specified alignment is sufficient based on the data layout.
1679  // TODO: While using the data layout works in practice, a better solution
1680  // would be to implement this check directly (make this a virtual function).
1681  // For example, the ABI alignment may change based on software platform while
1682  // this function should only be affected by hardware implementation.
1683  Type *Ty = VT.getTypeForEVT(Context);
1684  if (Alignment >= DL.getABITypeAlign(Ty)) {
1685  // Assume that an access that meets the ABI-specified alignment is fast.
1686  if (Fast != nullptr)
1687  *Fast = true;
1688  return true;
1689  }
1690 
1691  // This is a misaligned access.
1692  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1693 }
1694 
1696  LLVMContext &Context, const DataLayout &DL, EVT VT,
1697  const MachineMemOperand &MMO, bool *Fast) const {
1699  MMO.getAlign(), MMO.getFlags(), Fast);
1700 }
1701 
1703  const DataLayout &DL, EVT VT,
1704  unsigned AddrSpace, Align Alignment,
1706  bool *Fast) const {
1707  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1708  Flags, Fast);
1709 }
1710 
1712  const DataLayout &DL, EVT VT,
1713  const MachineMemOperand &MMO,
1714  bool *Fast) const {
1715  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1716  MMO.getFlags(), Fast);
1717 }
1718 
1720  const DataLayout &DL, LLT Ty,
1721  const MachineMemOperand &MMO,
1722  bool *Fast) const {
1724  MMO.getAlign(), MMO.getFlags(), Fast);
1725 }
1726 
1727 //===----------------------------------------------------------------------===//
1728 // TargetTransformInfo Helpers
1729 //===----------------------------------------------------------------------===//
1730 
1732  enum InstructionOpcodes {
1733 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1734 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1735 #include "llvm/IR/Instruction.def"
1736  };
1737  switch (static_cast<InstructionOpcodes>(Opcode)) {
1738  case Ret: return 0;
1739  case Br: return 0;
1740  case Switch: return 0;
1741  case IndirectBr: return 0;
1742  case Invoke: return 0;
1743  case CallBr: return 0;
1744  case Resume: return 0;
1745  case Unreachable: return 0;
1746  case CleanupRet: return 0;
1747  case CatchRet: return 0;
1748  case CatchPad: return 0;
1749  case CatchSwitch: return 0;
1750  case CleanupPad: return 0;
1751  case FNeg: return ISD::FNEG;
1752  case Add: return ISD::ADD;
1753  case FAdd: return ISD::FADD;
1754  case Sub: return ISD::SUB;
1755  case FSub: return ISD::FSUB;
1756  case Mul: return ISD::MUL;
1757  case FMul: return ISD::FMUL;
1758  case UDiv: return ISD::UDIV;
1759  case SDiv: return ISD::SDIV;
1760  case FDiv: return ISD::FDIV;
1761  case URem: return ISD::UREM;
1762  case SRem: return ISD::SREM;
1763  case FRem: return ISD::FREM;
1764  case Shl: return ISD::SHL;
1765  case LShr: return ISD::SRL;
1766  case AShr: return ISD::SRA;
1767  case And: return ISD::AND;
1768  case Or: return ISD::OR;
1769  case Xor: return ISD::XOR;
1770  case Alloca: return 0;
1771  case Load: return ISD::LOAD;
1772  case Store: return ISD::STORE;
1773  case GetElementPtr: return 0;
1774  case Fence: return 0;
1775  case AtomicCmpXchg: return 0;
1776  case AtomicRMW: return 0;
1777  case Trunc: return ISD::TRUNCATE;
1778  case ZExt: return ISD::ZERO_EXTEND;
1779  case SExt: return ISD::SIGN_EXTEND;
1780  case FPToUI: return ISD::FP_TO_UINT;
1781  case FPToSI: return ISD::FP_TO_SINT;
1782  case UIToFP: return ISD::UINT_TO_FP;
1783  case SIToFP: return ISD::SINT_TO_FP;
1784  case FPTrunc: return ISD::FP_ROUND;
1785  case FPExt: return ISD::FP_EXTEND;
1786  case PtrToInt: return ISD::BITCAST;
1787  case IntToPtr: return ISD::BITCAST;
1788  case BitCast: return ISD::BITCAST;
1789  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1790  case ICmp: return ISD::SETCC;
1791  case FCmp: return ISD::SETCC;
1792  case PHI: return 0;
1793  case Call: return 0;
1794  case Select: return ISD::SELECT;
1795  case UserOp1: return 0;
1796  case UserOp2: return 0;
1797  case VAArg: return 0;
1798  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1799  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1800  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1801  case ExtractValue: return ISD::MERGE_VALUES;
1802  case InsertValue: return ISD::MERGE_VALUES;
1803  case LandingPad: return 0;
1804  case Freeze: return ISD::FREEZE;
1805  }
1806 
1807  llvm_unreachable("Unknown instruction type encountered!");
1808 }
1809 
1810 std::pair<int, MVT>
1812  Type *Ty) const {
1813  LLVMContext &C = Ty->getContext();
1814  EVT MTy = getValueType(DL, Ty);
1815 
1816  int Cost = 1;
1817  // We keep legalizing the type until we find a legal kind. We assume that
1818  // the only operation that costs anything is the split. After splitting
1819  // we need to handle two types.
1820  while (true) {
1821  LegalizeKind LK = getTypeConversion(C, MTy);
1822 
1823  if (LK.first == TypeLegal)
1824  return std::make_pair(Cost, MTy.getSimpleVT());
1825 
1826  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1827  Cost *= 2;
1828 
1829  // Do not loop with f128 type.
1830  if (MTy == LK.second)
1831  return std::make_pair(Cost, MTy.getSimpleVT());
1832 
1833  // Keep legalizing the type.
1834  MTy = LK.second;
1835  }
1836 }
1837 
1839  bool UseTLS) const {
1840  // compiler-rt provides a variable with a magic name. Targets that do not
1841  // link with compiler-rt may also provide such a variable.
1842  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1843  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1844  auto UnsafeStackPtr =
1845  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1846 
1847  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1848 
1849  if (!UnsafeStackPtr) {
1850  auto TLSModel = UseTLS ?
1853  // The global variable is not defined yet, define it ourselves.
1854  // We use the initial-exec TLS model because we do not support the
1855  // variable living anywhere other than in the main executable.
1856  UnsafeStackPtr = new GlobalVariable(
1857  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1858  UnsafeStackPtrVar, nullptr, TLSModel);
1859  } else {
1860  // The variable exists, check its type and attributes.
1861  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1862  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1863  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1864  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1865  (UseTLS ? "" : "not ") + "be thread-local");
1866  }
1867  return UnsafeStackPtr;
1868 }
1869 
1871  if (!TM.getTargetTriple().isAndroid())
1872  return getDefaultSafeStackPointerLocation(IRB, true);
1873 
1874  // Android provides a libc function to retrieve the address of the current
1875  // thread's unsafe stack pointer.
1876  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1877  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1878  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1879  StackPtrTy->getPointerTo(0));
1880  return IRB.CreateCall(Fn);
1881 }
1882 
1883 //===----------------------------------------------------------------------===//
1884 // Loop Strength Reduction hooks
1885 //===----------------------------------------------------------------------===//
1886 
1887 /// isLegalAddressingMode - Return true if the addressing mode represented
1888 /// by AM is legal for this target, for a load/store of the specified type.
1890  const AddrMode &AM, Type *Ty,
1891  unsigned AS, Instruction *I) const {
1892  // The default implementation of this implements a conservative RISCy, r+r and
1893  // r+i addr mode.
1894 
1895  // Allows a sign-extended 16-bit immediate field.
1896  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1897  return false;
1898 
1899  // No global is ever allowed as a base.
1900  if (AM.BaseGV)
1901  return false;
1902 
1903  // Only support r+r,
1904  switch (AM.Scale) {
1905  case 0: // "r+i" or just "i", depending on HasBaseReg.
1906  break;
1907  case 1:
1908  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1909  return false;
1910  // Otherwise we have r+r or r+i.
1911  break;
1912  case 2:
1913  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1914  return false;
1915  // Allow 2*r as r+r.
1916  break;
1917  default: // Don't allow n * r
1918  return false;
1919  }
1920 
1921  return true;
1922 }
1923 
1924 //===----------------------------------------------------------------------===//
1925 // Stack Protector
1926 //===----------------------------------------------------------------------===//
1927 
1928 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1929 // so that SelectionDAG handle SSP.
1931  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1932  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1933  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1934  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1935  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1936  G->setVisibility(GlobalValue::HiddenVisibility);
1937  return C;
1938  }
1939  return nullptr;
1940 }
1941 
1942 // Currently only support "standard" __stack_chk_guard.
1943 // TODO: add LOAD_STACK_GUARD support.
1945  if (!M.getNamedValue("__stack_chk_guard")) {
1946  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1948  "__stack_chk_guard");
1949  if (TM.getRelocationModel() == Reloc::Static &&
1951  GV->setDSOLocal(true);
1952  }
1953 }
1954 
1955 // Currently only support "standard" __stack_chk_guard.
1956 // TODO: add LOAD_STACK_GUARD support.
1958  return M.getNamedValue("__stack_chk_guard");
1959 }
1960 
1962  return nullptr;
1963 }
1964 
1966  return MinimumJumpTableEntries;
1967 }
1968 
1971 }
1972 
1973 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1974  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1975 }
1976 
1978  return MaximumJumpTableSize;
1979 }
1980 
1982  MaximumJumpTableSize = Val;
1983 }
1984 
1987 }
1988 
1989 //===----------------------------------------------------------------------===//
1990 // Reciprocal Estimates
1991 //===----------------------------------------------------------------------===//
1992 
1993 /// Get the reciprocal estimate attribute string for a function that will
1994 /// override the target defaults.
1996  const Function &F = MF.getFunction();
1997  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1998 }
1999 
2000 /// Construct a string for the given reciprocal operation of the given type.
2001 /// This string should match the corresponding option to the front-end's
2002 /// "-mrecip" flag assuming those strings have been passed through in an
2003 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2004 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2005  std::string Name = VT.isVector() ? "vec-" : "";
2006 
2007  Name += IsSqrt ? "sqrt" : "div";
2008 
2009  // TODO: Handle "half" or other float types?
2010  if (VT.getScalarType() == MVT::f64) {
2011  Name += "d";
2012  } else {
2013  assert(VT.getScalarType() == MVT::f32 &&
2014  "Unexpected FP type for reciprocal estimate");
2015  Name += "f";
2016  }
2017 
2018  return Name;
2019 }
2020 
2021 /// Return the character position and value (a single numeric character) of a
2022 /// customized refinement operation in the input string if it exists. Return
2023 /// false if there is no customized refinement step count.
2024 static bool parseRefinementStep(StringRef In, size_t &Position,
2025  uint8_t &Value) {
2026  const char RefStepToken = ':';
2027  Position = In.find(RefStepToken);
2028  if (Position == StringRef::npos)
2029  return false;
2030 
2031  StringRef RefStepString = In.substr(Position + 1);
2032  // Allow exactly one numeric character for the additional refinement
2033  // step parameter.
2034  if (RefStepString.size() == 1) {
2035  char RefStepChar = RefStepString[0];
2036  if (isDigit(RefStepChar)) {
2037  Value = RefStepChar - '0';
2038  return true;
2039  }
2040  }
2041  report_fatal_error("Invalid refinement step for -recip.");
2042 }
2043 
2044 /// For the input attribute string, return one of the ReciprocalEstimate enum
2045 /// status values (enabled, disabled, or not specified) for this operation on
2046 /// the specified data type.
2047 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2048  if (Override.empty())
2049  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2050 
2051  SmallVector<StringRef, 4> OverrideVector;
2052  Override.split(OverrideVector, ',');
2053  unsigned NumArgs = OverrideVector.size();
2054 
2055  // Check if "all", "none", or "default" was specified.
2056  if (NumArgs == 1) {
2057  // Look for an optional setting of the number of refinement steps needed
2058  // for this type of reciprocal operation.
2059  size_t RefPos;
2060  uint8_t RefSteps;
2061  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2062  // Split the string for further processing.
2063  Override = Override.substr(0, RefPos);
2064  }
2065 
2066  // All reciprocal types are enabled.
2067  if (Override == "all")
2069 
2070  // All reciprocal types are disabled.
2071  if (Override == "none")
2073 
2074  // Target defaults for enablement are used.
2075  if (Override == "default")
2076  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2077  }
2078 
2079  // The attribute string may omit the size suffix ('f'/'d').
2080  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2081  std::string VTNameNoSize = VTName;
2082  VTNameNoSize.pop_back();
2083  static const char DisabledPrefix = '!';
2084 
2085  for (StringRef RecipType : OverrideVector) {
2086  size_t RefPos;
2087  uint8_t RefSteps;
2088  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2089  RecipType = RecipType.substr(0, RefPos);
2090 
2091  // Ignore the disablement token for string matching.
2092  bool IsDisabled = RecipType[0] == DisabledPrefix;
2093  if (IsDisabled)
2094  RecipType = RecipType.substr(1);
2095 
2096  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2099  }
2100 
2101  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2102 }
2103 
2104 /// For the input attribute string, return the customized refinement step count
2105 /// for this operation on the specified data type. If the step count does not
2106 /// exist, return the ReciprocalEstimate enum value for unspecified.
2107 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2108  if (Override.empty())
2109  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2110 
2111  SmallVector<StringRef, 4> OverrideVector;
2112  Override.split(OverrideVector, ',');
2113  unsigned NumArgs = OverrideVector.size();
2114 
2115  // Check if "all", "default", or "none" was specified.
2116  if (NumArgs == 1) {
2117  // Look for an optional setting of the number of refinement steps needed
2118  // for this type of reciprocal operation.
2119  size_t RefPos;
2120  uint8_t RefSteps;
2121  if (!parseRefinementStep(Override, RefPos, RefSteps))
2122  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2123 
2124  // Split the string for further processing.
2125  Override = Override.substr(0, RefPos);
2126  assert(Override != "none" &&
2127  "Disabled reciprocals, but specifed refinement steps?");
2128 
2129  // If this is a general override, return the specified number of steps.
2130  if (Override == "all" || Override == "default")
2131  return RefSteps;
2132  }
2133 
2134  // The attribute string may omit the size suffix ('f'/'d').
2135  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2136  std::string VTNameNoSize = VTName;
2137  VTNameNoSize.pop_back();
2138 
2139  for (StringRef RecipType : OverrideVector) {
2140  size_t RefPos;
2141  uint8_t RefSteps;
2142  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2143  continue;
2144 
2145  RecipType = RecipType.substr(0, RefPos);
2146  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2147  return RefSteps;
2148  }
2149 
2150  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2151 }
2152 
2154  MachineFunction &MF) const {
2155  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2156 }
2157 
2159  MachineFunction &MF) const {
2160  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2161 }
2162 
2164  MachineFunction &MF) const {
2165  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2166 }
2167 
2169  MachineFunction &MF) const {
2170  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2171 }
2172 
2174  MF.getRegInfo().freezeReservedRegs(MF);
2175 }
2176 
2179  const DataLayout &DL) const {
2181  if (LI.isVolatile())
2183 
2184  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2186 
2187  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2189 
2192 
2193  Flags |= getTargetMMOFlags(LI);
2194  return Flags;
2195 }
2196 
2199  const DataLayout &DL) const {
2201 
2202  if (SI.isVolatile())
2204 
2205  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2207 
2208  // FIXME: Not preserving dereferenceable
2209  Flags |= getTargetMMOFlags(SI);
2210  return Flags;
2211 }
2212 
2215  const DataLayout &DL) const {
2217 
2218  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2219  if (RMW->isVolatile())
2221  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2222  if (CmpX->isVolatile())
2224  } else
2225  llvm_unreachable("not an atomic instruction");
2226 
2227  // FIXME: Not preserving dereferenceable
2228  Flags |= getTargetMMOFlags(AI);
2229  return Flags;
2230 }
2231 
2232 //===----------------------------------------------------------------------===//
2233 // GlobalISel Hooks
2234 //===----------------------------------------------------------------------===//
2235 
2237  const TargetTransformInfo *TTI) const {
2238  auto &MF = *MI.getMF();
2239  auto &MRI = MF.getRegInfo();
2240  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2241  // this helper function computes the maximum number of uses we should consider
2242  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2243  // break even in terms of code size when the original MI has 2 users vs
2244  // choosing to potentially spill. Any more than 2 users we we have a net code
2245  // size increase. This doesn't take into account register pressure though.
2246  auto maxUses = [](unsigned RematCost) {
2247  // A cost of 1 means remats are basically free.
2248  if (RematCost == 1)
2249  return UINT_MAX;
2250  if (RematCost == 2)
2251  return 2U;
2252 
2253  // Remat is too expensive, only sink if there's one user.
2254  if (RematCost > 2)
2255  return 1U;
2256  llvm_unreachable("Unexpected remat cost");
2257  };
2258 
2259  // Helper to walk through uses and terminate if we've reached a limit. Saves
2260  // us spending time traversing uses if all we want to know is if it's >= min.
2261  auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) {
2262  unsigned NumUses = 0;
2264  for (; UI != UE && NumUses < MaxUses; ++UI) {
2265  NumUses++;
2266  }
2267  // If we haven't reached the end yet then there are more than MaxUses users.
2268  return UI == UE;
2269  };
2270 
2271  switch (MI.getOpcode()) {
2272  default:
2273  return false;
2274  // Constants-like instructions should be close to their users.
2275  // We don't want long live-ranges for them.
2276  case TargetOpcode::G_CONSTANT:
2277  case TargetOpcode::G_FCONSTANT:
2278  case TargetOpcode::G_FRAME_INDEX:
2279  case TargetOpcode::G_INTTOPTR:
2280  return true;
2281  case TargetOpcode::G_GLOBAL_VALUE: {
2282  unsigned RematCost = TTI->getGISelRematGlobalCost();
2283  Register Reg = MI.getOperand(0).getReg();
2284  unsigned MaxUses = maxUses(RematCost);
2285  if (MaxUses == UINT_MAX)
2286  return true; // Remats are "free" so always localize.
2287  bool B = isUsesAtMost(Reg, MaxUses);
2288  return B;
2289  }
2290  }
2291 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:428
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:857
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:1995
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:869
i
i
Definition: README.txt:29
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:684
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:1973
llvm::TargetLoweringBase::getByValTypeAlignment
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1670
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2206
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3064
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:695
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:902
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:557
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:499
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2240
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1360
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:312
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:549
llvm
Definition: AllocatorList.h:23
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:188
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:538
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1000
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:618
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:639
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1357
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:833
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:256
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1361
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:315
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1069
llvm::ElementCount
Definition: TypeSize.h:386
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:883
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:368
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1131
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:56
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:513
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1124
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:304
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:45
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1124
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:659
llvm::Triple::x86
@ x86
Definition: Triple.h:83
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:213
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:262
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:994
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3062
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:179
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:647
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:59
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:786
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1356
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:212
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:347
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:1981
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:621
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1118
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:438
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:101
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:361
llvm::IRBuilder<>
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::GlobalVariable
Definition: GlobalVariable.h:40
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:130
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:706
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:860
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:717
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:330
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1228
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:770
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1066
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:340
llvm::EVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
Definition: ValueTypes.h:155
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:70
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::AttributeList
Definition: Attributes.h:375
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:121
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:687
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1592
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:74
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1209
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:485
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:1985
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:891
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2828
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:229
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:754
STLExtras.h
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1193
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:266
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:492
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:243
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:54
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:205
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:328
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1135
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:209
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:373
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3085
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2178
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:612
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1125
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:428
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:283
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Definition: TargetLoweringBase.cpp:896
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:354
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::AttributeList::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:1538
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:32
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3050
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ElementCount::isScalar
bool isScalar() const
Counting predicates.
Definition: TypeSize.h:396
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:315
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:612
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1221
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:870
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1030
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:648
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:673
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2236
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:664
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:354
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:714
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:625
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1358
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:218
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:431
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:224
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:101
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:730
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:211
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:348
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:732
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:743
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2024
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2324
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:246
Twine.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1004
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1870
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:868
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:720
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:302
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:643
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:872
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:890
TargetOpcodes.h
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:249
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3100
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1838
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:837
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1123
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:139
llvm::Instruction
Definition: Instruction.h:45
llvm::isDereferenceablePointer
bool isDereferenceablePointer(const Value *V, Type *Ty, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Return true if this is always a dereferenceable pointer.
Definition: Loads.cpp:234
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1889
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1130
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2197
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:724
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1957
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:867
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:866
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:803
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:401
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1500
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:507
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1364
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:504
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3077
llvm::BitVector
Definition: BitVector.h:74
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:617
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:83
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:311
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:584
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1944
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:210
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1099
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1348
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:443
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:265
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:905
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:308
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:854
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:928
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1207
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:80
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:214
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:54
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1488
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3118
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:371
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2157
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3079
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:611
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:896
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:1977
llvm::cl::opt< bool >
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1965
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:378
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1174
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:303
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:113
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1498
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:302
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:898
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:861
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1210
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:723
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:464
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1112
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1128
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:771
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:881
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1214
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:265
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:906
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1219
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:206
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:204
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:194
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2168
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1073
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:294
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:241
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:505
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1206
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2214
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:660
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1127
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1194
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:873
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:471
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1106
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:321
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1121
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:329
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:470
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:634
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1482
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1609
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2158
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:259
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:815
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3121
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1076
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2198
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1336
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:367
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1216
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:284
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:297
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2107
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
llvm::MachineFunction
Definition: MachineFunction.h:227
Triple.h
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1119
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:897
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1080
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:604
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:149
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:614
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1285
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:713
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:284
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:237
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:874
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1122
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2322
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3133
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3114
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RecurKind::Mul
@ Mul
Product of integers.
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:862
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1731
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:349
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:863
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:419
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1218
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:373
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1120
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:569
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:339
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:203
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:619
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:801
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:918
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:335
llvm::MVT::all_valuetypes
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1358
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2153
Attributes.h
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1961
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:407
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1359
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2323
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:884
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:216
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned integer type wi...
Definition: ISDOpcodes.h:785
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:587
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2188
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:293
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2325
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2047
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:242
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1215
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:288
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:355
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1335
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
Definition: TargetLoweringBase.cpp:891
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:864
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:776
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:178
Enabled
static bool Enabled
Definition: Statistic.cpp:50
llvm::TypeSize
Definition: TypeSize.h:417
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:574
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:263
llvm::LinearPolySize< ElementCount >::getScalable
static ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:202
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1217
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:715
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:235
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:333
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:395
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:717
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:923
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:207
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2806
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2004
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:907
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:725
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:307
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:211
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:472
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1702
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:293
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1811
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:818
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:474
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:372
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1086
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1618
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:642
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1675
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:211
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1053
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:375
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
MachineInstrBuilder.h
llvm::getMVTForLLT
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: LowLevelType.cpp:46
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:238
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:195
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:765
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:51
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:208
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1255
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1490
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:655
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:273
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1287
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1969
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:644
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:123
llvm::MVT::LAST_VALUETYPE
@ LAST_VALUETYPE
Definition: MachineValueType.h:260
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:656
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:164
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1433
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2321
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:424
llvm::TypeSize::getKnownMinSize
ScalarTy getKnownMinSize() const
Definition: TypeSize.h:427
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:613
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:871
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2216
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:382
DerivedTypes.h
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:851
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:362
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3149
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3098
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:672
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1126
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1382
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:48
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1220
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:209
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:711
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1222
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2173
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:160
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:182
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:865
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LinearPolySize::divideCoefficientBy
LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:361
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:494
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:859
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3112
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2163
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:272
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:799
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:209
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
TargetRegisterInfo.h
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:52
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2344
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:342
llvm::LinearPolySize::coefficientNextPowerOf2
LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:366
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:77
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:320
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1129
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:701
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:915
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:306
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1100
llvm::MVT::fp_valuetypes
static mvt_range fp_valuetypes()
Definition: MachineValueType.h:1367
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1930
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:228
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:374
llvm::LLT
Definition: LowLevelTypeImpl.h:40