LLVM  16.0.0git
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <cstring>
61 #include <iterator>
62 #include <string>
63 #include <tuple>
64 #include <utility>
65 
66 using namespace llvm;
67 
69  "jump-is-expensive", cl::init(false),
70  cl::desc("Do not create extra branches to split comparison logic."),
71  cl::Hidden);
72 
74  ("min-jump-table-entries", cl::init(4), cl::Hidden,
75  cl::desc("Set minimum number of entries to use a jump table."));
76 
78  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79  cl::desc("Set maximum size of jump tables."));
80 
81 /// Minimum jump table density for normal functions.
82 static cl::opt<unsigned>
83  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84  cl::desc("Minimum density for building a jump table in "
85  "a normal function"));
86 
87 /// Minimum jump table density for -Os or -Oz functions.
89  "optsize-jump-table-density", cl::init(40), cl::Hidden,
90  cl::desc("Minimum density for building a jump table in "
91  "an optsize function"));
92 
93 // FIXME: This option is only to test if the strict fp operation processed
94 // correctly by preventing mutating strict fp operation to normal fp operation
95 // during development. When the backend supports strict float operation, this
96 // option will be meaningless.
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98  cl::desc("Don't mutate strict-float node to a legalize node"),
99  cl::init(false), cl::Hidden);
100 
101 static bool darwinHasSinCos(const Triple &TT) {
102  assert(TT.isOSDarwin() && "should be called with darwin triple");
103  // Don't bother with 32 bit x86.
104  if (TT.getArch() == Triple::x86)
105  return false;
106  // Macos < 10.9 has no sincos_stret.
107  if (TT.isMacOSX())
108  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109  // iOS < 7.0 has no sincos_stret.
110  if (TT.isiOS())
111  return !TT.isOSVersionLT(7, 0);
112  // Any other darwin such as WatchOS/TvOS is new enough.
113  return true;
114 }
115 
116 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117 #define HANDLE_LIBCALL(code, name) \
118  setLibcallName(RTLIB::code, name);
119 #include "llvm/IR/RuntimeLibcalls.def"
120 #undef HANDLE_LIBCALL
121  // Initialize calling conventions to their default.
122  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 
125  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
126  if (TT.isPPC()) {
127  setLibcallName(RTLIB::ADD_F128, "__addkf3");
128  setLibcallName(RTLIB::SUB_F128, "__subkf3");
129  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
130  setLibcallName(RTLIB::DIV_F128, "__divkf3");
131  setLibcallName(RTLIB::POWI_F128, "__powikf2");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
139  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
140  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
142  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
143  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
144  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
145  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
146  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
147  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
148  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
149  setLibcallName(RTLIB::UNE_F128, "__nekf2");
150  setLibcallName(RTLIB::OGE_F128, "__gekf2");
151  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
152  setLibcallName(RTLIB::OLE_F128, "__lekf2");
153  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
154  setLibcallName(RTLIB::UO_F128, "__unordkf2");
155  }
156 
157  // A few names are different on particular architectures or environments.
158  if (TT.isOSDarwin()) {
159  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
160  // of the gnueabi-style __gnu_*_ieee.
161  // FIXME: What about other targets?
162  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
163  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
164 
165  // Some darwins have an optimized __bzero/bzero function.
166  switch (TT.getArch()) {
167  case Triple::x86:
168  case Triple::x86_64:
169  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
170  setLibcallName(RTLIB::BZERO, "__bzero");
171  break;
172  case Triple::aarch64:
173  case Triple::aarch64_32:
174  setLibcallName(RTLIB::BZERO, "bzero");
175  break;
176  default:
177  break;
178  }
179 
180  if (darwinHasSinCos(TT)) {
181  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
182  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
183  if (TT.isWatchABI()) {
184  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
186  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
188  }
189  }
190  } else {
191  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
192  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
193  }
194 
195  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
196  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
197  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
198  setLibcallName(RTLIB::SINCOS_F64, "sincos");
199  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
200  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
201  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
202  }
203 
204  if (TT.isPS()) {
205  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
206  setLibcallName(RTLIB::SINCOS_F64, "sincos");
207  }
208 
209  if (TT.isOSOpenBSD()) {
210  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
211  }
212 }
213 
214 /// GetFPLibCall - Helper to return the right libcall for the given floating
215 /// point type, or UNKNOWN_LIBCALL if there is none.
217  RTLIB::Libcall Call_F32,
218  RTLIB::Libcall Call_F64,
219  RTLIB::Libcall Call_F80,
220  RTLIB::Libcall Call_F128,
221  RTLIB::Libcall Call_PPCF128) {
222  return
223  VT == MVT::f32 ? Call_F32 :
224  VT == MVT::f64 ? Call_F64 :
225  VT == MVT::f80 ? Call_F80 :
226  VT == MVT::f128 ? Call_F128 :
227  VT == MVT::ppcf128 ? Call_PPCF128 :
228  RTLIB::UNKNOWN_LIBCALL;
229 }
230 
231 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
234  if (OpVT == MVT::f16) {
235  if (RetVT == MVT::f32)
236  return FPEXT_F16_F32;
237  if (RetVT == MVT::f64)
238  return FPEXT_F16_F64;
239  if (RetVT == MVT::f80)
240  return FPEXT_F16_F80;
241  if (RetVT == MVT::f128)
242  return FPEXT_F16_F128;
243  } else if (OpVT == MVT::f32) {
244  if (RetVT == MVT::f64)
245  return FPEXT_F32_F64;
246  if (RetVT == MVT::f128)
247  return FPEXT_F32_F128;
248  if (RetVT == MVT::ppcf128)
249  return FPEXT_F32_PPCF128;
250  } else if (OpVT == MVT::f64) {
251  if (RetVT == MVT::f128)
252  return FPEXT_F64_F128;
253  else if (RetVT == MVT::ppcf128)
254  return FPEXT_F64_PPCF128;
255  } else if (OpVT == MVT::f80) {
256  if (RetVT == MVT::f128)
257  return FPEXT_F80_F128;
258  }
259 
260  return UNKNOWN_LIBCALL;
261 }
262 
263 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
264 /// UNKNOWN_LIBCALL if there is none.
266  if (RetVT == MVT::f16) {
267  if (OpVT == MVT::f32)
268  return FPROUND_F32_F16;
269  if (OpVT == MVT::f64)
270  return FPROUND_F64_F16;
271  if (OpVT == MVT::f80)
272  return FPROUND_F80_F16;
273  if (OpVT == MVT::f128)
274  return FPROUND_F128_F16;
275  if (OpVT == MVT::ppcf128)
276  return FPROUND_PPCF128_F16;
277  } else if (RetVT == MVT::bf16) {
278  if (OpVT == MVT::f32)
279  return FPROUND_F32_BF16;
280  if (OpVT == MVT::f64)
281  return FPROUND_F64_BF16;
282  } else if (RetVT == MVT::f32) {
283  if (OpVT == MVT::f64)
284  return FPROUND_F64_F32;
285  if (OpVT == MVT::f80)
286  return FPROUND_F80_F32;
287  if (OpVT == MVT::f128)
288  return FPROUND_F128_F32;
289  if (OpVT == MVT::ppcf128)
290  return FPROUND_PPCF128_F32;
291  } else if (RetVT == MVT::f64) {
292  if (OpVT == MVT::f80)
293  return FPROUND_F80_F64;
294  if (OpVT == MVT::f128)
295  return FPROUND_F128_F64;
296  if (OpVT == MVT::ppcf128)
297  return FPROUND_PPCF128_F64;
298  } else if (RetVT == MVT::f80) {
299  if (OpVT == MVT::f128)
300  return FPROUND_F128_F80;
301  }
302 
303  return UNKNOWN_LIBCALL;
304 }
305 
306 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
309  if (OpVT == MVT::f16) {
310  if (RetVT == MVT::i32)
311  return FPTOSINT_F16_I32;
312  if (RetVT == MVT::i64)
313  return FPTOSINT_F16_I64;
314  if (RetVT == MVT::i128)
315  return FPTOSINT_F16_I128;
316  } else if (OpVT == MVT::f32) {
317  if (RetVT == MVT::i32)
318  return FPTOSINT_F32_I32;
319  if (RetVT == MVT::i64)
320  return FPTOSINT_F32_I64;
321  if (RetVT == MVT::i128)
322  return FPTOSINT_F32_I128;
323  } else if (OpVT == MVT::f64) {
324  if (RetVT == MVT::i32)
325  return FPTOSINT_F64_I32;
326  if (RetVT == MVT::i64)
327  return FPTOSINT_F64_I64;
328  if (RetVT == MVT::i128)
329  return FPTOSINT_F64_I128;
330  } else if (OpVT == MVT::f80) {
331  if (RetVT == MVT::i32)
332  return FPTOSINT_F80_I32;
333  if (RetVT == MVT::i64)
334  return FPTOSINT_F80_I64;
335  if (RetVT == MVT::i128)
336  return FPTOSINT_F80_I128;
337  } else if (OpVT == MVT::f128) {
338  if (RetVT == MVT::i32)
339  return FPTOSINT_F128_I32;
340  if (RetVT == MVT::i64)
341  return FPTOSINT_F128_I64;
342  if (RetVT == MVT::i128)
343  return FPTOSINT_F128_I128;
344  } else if (OpVT == MVT::ppcf128) {
345  if (RetVT == MVT::i32)
346  return FPTOSINT_PPCF128_I32;
347  if (RetVT == MVT::i64)
348  return FPTOSINT_PPCF128_I64;
349  if (RetVT == MVT::i128)
350  return FPTOSINT_PPCF128_I128;
351  }
352  return UNKNOWN_LIBCALL;
353 }
354 
355 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
356 /// UNKNOWN_LIBCALL if there is none.
358  if (OpVT == MVT::f16) {
359  if (RetVT == MVT::i32)
360  return FPTOUINT_F16_I32;
361  if (RetVT == MVT::i64)
362  return FPTOUINT_F16_I64;
363  if (RetVT == MVT::i128)
364  return FPTOUINT_F16_I128;
365  } else if (OpVT == MVT::f32) {
366  if (RetVT == MVT::i32)
367  return FPTOUINT_F32_I32;
368  if (RetVT == MVT::i64)
369  return FPTOUINT_F32_I64;
370  if (RetVT == MVT::i128)
371  return FPTOUINT_F32_I128;
372  } else if (OpVT == MVT::f64) {
373  if (RetVT == MVT::i32)
374  return FPTOUINT_F64_I32;
375  if (RetVT == MVT::i64)
376  return FPTOUINT_F64_I64;
377  if (RetVT == MVT::i128)
378  return FPTOUINT_F64_I128;
379  } else if (OpVT == MVT::f80) {
380  if (RetVT == MVT::i32)
381  return FPTOUINT_F80_I32;
382  if (RetVT == MVT::i64)
383  return FPTOUINT_F80_I64;
384  if (RetVT == MVT::i128)
385  return FPTOUINT_F80_I128;
386  } else if (OpVT == MVT::f128) {
387  if (RetVT == MVT::i32)
388  return FPTOUINT_F128_I32;
389  if (RetVT == MVT::i64)
390  return FPTOUINT_F128_I64;
391  if (RetVT == MVT::i128)
392  return FPTOUINT_F128_I128;
393  } else if (OpVT == MVT::ppcf128) {
394  if (RetVT == MVT::i32)
395  return FPTOUINT_PPCF128_I32;
396  if (RetVT == MVT::i64)
397  return FPTOUINT_PPCF128_I64;
398  if (RetVT == MVT::i128)
399  return FPTOUINT_PPCF128_I128;
400  }
401  return UNKNOWN_LIBCALL;
402 }
403 
404 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
405 /// UNKNOWN_LIBCALL if there is none.
407  if (OpVT == MVT::i32) {
408  if (RetVT == MVT::f16)
409  return SINTTOFP_I32_F16;
410  if (RetVT == MVT::f32)
411  return SINTTOFP_I32_F32;
412  if (RetVT == MVT::f64)
413  return SINTTOFP_I32_F64;
414  if (RetVT == MVT::f80)
415  return SINTTOFP_I32_F80;
416  if (RetVT == MVT::f128)
417  return SINTTOFP_I32_F128;
418  if (RetVT == MVT::ppcf128)
419  return SINTTOFP_I32_PPCF128;
420  } else if (OpVT == MVT::i64) {
421  if (RetVT == MVT::f16)
422  return SINTTOFP_I64_F16;
423  if (RetVT == MVT::f32)
424  return SINTTOFP_I64_F32;
425  if (RetVT == MVT::f64)
426  return SINTTOFP_I64_F64;
427  if (RetVT == MVT::f80)
428  return SINTTOFP_I64_F80;
429  if (RetVT == MVT::f128)
430  return SINTTOFP_I64_F128;
431  if (RetVT == MVT::ppcf128)
432  return SINTTOFP_I64_PPCF128;
433  } else if (OpVT == MVT::i128) {
434  if (RetVT == MVT::f16)
435  return SINTTOFP_I128_F16;
436  if (RetVT == MVT::f32)
437  return SINTTOFP_I128_F32;
438  if (RetVT == MVT::f64)
439  return SINTTOFP_I128_F64;
440  if (RetVT == MVT::f80)
441  return SINTTOFP_I128_F80;
442  if (RetVT == MVT::f128)
443  return SINTTOFP_I128_F128;
444  if (RetVT == MVT::ppcf128)
445  return SINTTOFP_I128_PPCF128;
446  }
447  return UNKNOWN_LIBCALL;
448 }
449 
450 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
451 /// UNKNOWN_LIBCALL if there is none.
453  if (OpVT == MVT::i32) {
454  if (RetVT == MVT::f16)
455  return UINTTOFP_I32_F16;
456  if (RetVT == MVT::f32)
457  return UINTTOFP_I32_F32;
458  if (RetVT == MVT::f64)
459  return UINTTOFP_I32_F64;
460  if (RetVT == MVT::f80)
461  return UINTTOFP_I32_F80;
462  if (RetVT == MVT::f128)
463  return UINTTOFP_I32_F128;
464  if (RetVT == MVT::ppcf128)
465  return UINTTOFP_I32_PPCF128;
466  } else if (OpVT == MVT::i64) {
467  if (RetVT == MVT::f16)
468  return UINTTOFP_I64_F16;
469  if (RetVT == MVT::f32)
470  return UINTTOFP_I64_F32;
471  if (RetVT == MVT::f64)
472  return UINTTOFP_I64_F64;
473  if (RetVT == MVT::f80)
474  return UINTTOFP_I64_F80;
475  if (RetVT == MVT::f128)
476  return UINTTOFP_I64_F128;
477  if (RetVT == MVT::ppcf128)
478  return UINTTOFP_I64_PPCF128;
479  } else if (OpVT == MVT::i128) {
480  if (RetVT == MVT::f16)
481  return UINTTOFP_I128_F16;
482  if (RetVT == MVT::f32)
483  return UINTTOFP_I128_F32;
484  if (RetVT == MVT::f64)
485  return UINTTOFP_I128_F64;
486  if (RetVT == MVT::f80)
487  return UINTTOFP_I128_F80;
488  if (RetVT == MVT::f128)
489  return UINTTOFP_I128_F128;
490  if (RetVT == MVT::ppcf128)
491  return UINTTOFP_I128_PPCF128;
492  }
493  return UNKNOWN_LIBCALL;
494 }
495 
497  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
498  POWI_PPCF128);
499 }
500 
502  MVT VT) {
503  unsigned ModeN, ModelN;
504  switch (VT.SimpleTy) {
505  case MVT::i8:
506  ModeN = 0;
507  break;
508  case MVT::i16:
509  ModeN = 1;
510  break;
511  case MVT::i32:
512  ModeN = 2;
513  break;
514  case MVT::i64:
515  ModeN = 3;
516  break;
517  case MVT::i128:
518  ModeN = 4;
519  break;
520  default:
521  return UNKNOWN_LIBCALL;
522  }
523 
524  switch (Order) {
526  ModelN = 0;
527  break;
529  ModelN = 1;
530  break;
532  ModelN = 2;
533  break;
536  ModelN = 3;
537  break;
538  default:
539  return UNKNOWN_LIBCALL;
540  }
541 
542 #define LCALLS(A, B) \
543  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
544 #define LCALL5(A) \
545  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
546  switch (Opc) {
547  case ISD::ATOMIC_CMP_SWAP: {
548  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
549  return LC[ModeN][ModelN];
550  }
551  case ISD::ATOMIC_SWAP: {
552  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
553  return LC[ModeN][ModelN];
554  }
555  case ISD::ATOMIC_LOAD_ADD: {
556  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
557  return LC[ModeN][ModelN];
558  }
559  case ISD::ATOMIC_LOAD_OR: {
560  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
561  return LC[ModeN][ModelN];
562  }
563  case ISD::ATOMIC_LOAD_CLR: {
564  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
565  return LC[ModeN][ModelN];
566  }
567  case ISD::ATOMIC_LOAD_XOR: {
568  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
569  return LC[ModeN][ModelN];
570  }
571  default:
572  return UNKNOWN_LIBCALL;
573  }
574 #undef LCALLS
575 #undef LCALL5
576 }
577 
578 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
579 #define OP_TO_LIBCALL(Name, Enum) \
580  case Name: \
581  switch (VT.SimpleTy) { \
582  default: \
583  return UNKNOWN_LIBCALL; \
584  case MVT::i8: \
585  return Enum##_1; \
586  case MVT::i16: \
587  return Enum##_2; \
588  case MVT::i32: \
589  return Enum##_4; \
590  case MVT::i64: \
591  return Enum##_8; \
592  case MVT::i128: \
593  return Enum##_16; \
594  }
595 
596  switch (Opc) {
597  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
598  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
599  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
600  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
601  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
602  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
603  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
604  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
605  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
606  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
607  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
608  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
609  }
610 
611 #undef OP_TO_LIBCALL
612 
613  return UNKNOWN_LIBCALL;
614 }
615 
617  switch (ElementSize) {
618  case 1:
619  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
620  case 2:
621  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
622  case 4:
623  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
624  case 8:
625  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
626  case 16:
627  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
628  default:
629  return UNKNOWN_LIBCALL;
630  }
631 }
632 
634  switch (ElementSize) {
635  case 1:
636  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
637  case 2:
638  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
639  case 4:
640  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
641  case 8:
642  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
643  case 16:
644  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
645  default:
646  return UNKNOWN_LIBCALL;
647  }
648 }
649 
651  switch (ElementSize) {
652  case 1:
653  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
654  case 2:
655  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
656  case 4:
657  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
658  case 8:
659  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
660  case 16:
661  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
662  default:
663  return UNKNOWN_LIBCALL;
664  }
665 }
666 
667 /// InitCmpLibcallCCs - Set default comparison libcall CC.
668 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
669  std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
670  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
671  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
672  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
673  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
674  CCs[RTLIB::UNE_F32] = ISD::SETNE;
675  CCs[RTLIB::UNE_F64] = ISD::SETNE;
676  CCs[RTLIB::UNE_F128] = ISD::SETNE;
677  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
678  CCs[RTLIB::OGE_F32] = ISD::SETGE;
679  CCs[RTLIB::OGE_F64] = ISD::SETGE;
680  CCs[RTLIB::OGE_F128] = ISD::SETGE;
681  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
682  CCs[RTLIB::OLT_F32] = ISD::SETLT;
683  CCs[RTLIB::OLT_F64] = ISD::SETLT;
684  CCs[RTLIB::OLT_F128] = ISD::SETLT;
685  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
686  CCs[RTLIB::OLE_F32] = ISD::SETLE;
687  CCs[RTLIB::OLE_F64] = ISD::SETLE;
688  CCs[RTLIB::OLE_F128] = ISD::SETLE;
689  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
690  CCs[RTLIB::OGT_F32] = ISD::SETGT;
691  CCs[RTLIB::OGT_F64] = ISD::SETGT;
692  CCs[RTLIB::OGT_F128] = ISD::SETGT;
693  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
694  CCs[RTLIB::UO_F32] = ISD::SETNE;
695  CCs[RTLIB::UO_F64] = ISD::SETNE;
696  CCs[RTLIB::UO_F128] = ISD::SETNE;
697  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
698 }
699 
700 /// NOTE: The TargetMachine owns TLOF.
702  initActions();
703 
704  // Perform these initializations only once.
706  MaxLoadsPerMemcmp = 8;
710  HasMultipleConditionRegisters = false;
711  HasExtractBitsInsn = false;
712  JumpIsExpensive = JumpIsExpensiveOverride;
714  EnableExtLdPromotion = false;
715  StackPointerRegisterToSaveRestore = 0;
716  BooleanContents = UndefinedBooleanContent;
717  BooleanFloatContents = UndefinedBooleanContent;
718  BooleanVectorContents = UndefinedBooleanContent;
719  SchedPreferenceInfo = Sched::ILP;
722  MaxBytesForAlignment = 0;
723  // TODO: the default will be switched to 0 in the next commit, along
724  // with the Target-specific changes necessary.
725  MaxAtomicSizeInBitsSupported = 1024;
726 
727  MaxDivRemBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
728 
729  MinCmpXchgSizeInBits = 0;
730  SupportsUnalignedAtomics = false;
731 
732  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
733 
734  InitLibcalls(TM.getTargetTriple());
735  InitCmpLibcallCCs(CmpLibcallCCs);
736 }
737 
739  // All operations default to being supported.
740  memset(OpActions, 0, sizeof(OpActions));
741  memset(LoadExtActions, 0, sizeof(LoadExtActions));
742  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
743  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
744  memset(CondCodeActions, 0, sizeof(CondCodeActions));
745  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
746  std::fill(std::begin(TargetDAGCombineArray),
747  std::end(TargetDAGCombineArray), 0);
748 
749  // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
750  // remove this and targets should individually set these types if not legal.
753  for (MVT VT : {MVT::i2, MVT::i4})
754  OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
755  }
756  for (MVT AVT : MVT::all_valuetypes()) {
757  for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
758  setTruncStoreAction(AVT, VT, Expand);
761  }
762  }
763  for (unsigned IM = (unsigned)ISD::PRE_INC;
764  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
765  for (MVT VT : {MVT::i2, MVT::i4}) {
766  setIndexedLoadAction(IM, VT, Expand);
767  setIndexedStoreAction(IM, VT, Expand);
770  }
771  }
772 
773  for (MVT VT : MVT::fp_valuetypes()) {
774  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
775  if (IntVT.isValid()) {
778  }
779  }
780 
781  // Set default actions for various operations.
782  for (MVT VT : MVT::all_valuetypes()) {
783  // Default all indexed load / store to expand.
784  for (unsigned IM = (unsigned)ISD::PRE_INC;
785  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
786  setIndexedLoadAction(IM, VT, Expand);
787  setIndexedStoreAction(IM, VT, Expand);
790  }
791 
792  // Most backends expect to see the node which just returns the value loaded.
794 
795  // These operations default to expand.
813  VT, Expand);
814 
815  // Overflow operations default to expand
818  VT, Expand);
819 
820  // ADDCARRY operations default to expand
823  VT, Expand);
824 
825  // ADDC/ADDE/SUBC/SUBE default to expand.
827  Expand);
828 
829  // Halving adds
832  Expand);
833 
834  // Absolute difference
836 
837  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
839  Expand);
840 
842 
843  // These library functions default to expand.
845 
846  // These operations default to expand for vector types.
847  if (VT.isVector())
852  VT, Expand);
853 
854  // Constrained floating-point operations default to expand.
855 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
856  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
857 #include "llvm/IR/ConstrainedOps.def"
858 
859  // For most targets @llvm.get.dynamic.area.offset just returns 0.
861 
862  // Vector reduction default to expand.
869  VT, Expand);
870 
871  // Named vector shuffles default to expand.
873 
874  // VP_SREM/UREM default to expand.
875  // TODO: Expand all VP intrinsics.
876  setOperationAction(ISD::VP_SREM, VT, Expand);
877  setOperationAction(ISD::VP_UREM, VT, Expand);
878  }
879 
880  // Most targets ignore the @llvm.prefetch intrinsic.
882 
883  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
885 
886  // ConstantFP nodes default to expand. Targets can either change this to
887  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
888  // to optimize expansions for certain constants.
891  Expand);
892 
893  // These library functions default to expand.
899 
900  // Default ISD::TRAP to expand (which turns it into abort).
902 
903  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
904  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
906 
908 }
909 
911  EVT) const {
912  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
913 }
914 
916  bool LegalTypes) const {
917  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
918  if (LHSTy.isVector())
919  return LHSTy;
920  MVT ShiftVT =
921  LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
922  // If any possible shift value won't fit in the prefered type, just use
923  // something safe. Assume it will be legalized when the shift is expanded.
924  if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
925  ShiftVT = MVT::i32;
926  assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
927  "ShiftVT is still too small!");
928  return ShiftVT;
929 }
930 
931 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
932  assert(isTypeLegal(VT));
933  switch (Op) {
934  default:
935  return false;
936  case ISD::SDIV:
937  case ISD::UDIV:
938  case ISD::SREM:
939  case ISD::UREM:
940  return true;
941  }
942 }
943 
945  unsigned DestAS) const {
946  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
947 }
948 
950  // If the command-line option was specified, ignore this request.
952  JumpIsExpensive = isExpensive;
953 }
954 
957  // If this is a simple type, use the ComputeRegisterProp mechanism.
958  if (VT.isSimple()) {
959  MVT SVT = VT.getSimpleVT();
960  assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
961  MVT NVT = TransformToType[SVT.SimpleTy];
962  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
963 
964  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
965  LA == TypeSoftPromoteHalf ||
966  (NVT.isVector() ||
967  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
968  "Promote may not follow Expand or Promote");
969 
970  if (LA == TypeSplitVector)
971  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
972  if (LA == TypeScalarizeVector)
973  return LegalizeKind(LA, SVT.getVectorElementType());
974  return LegalizeKind(LA, NVT);
975  }
976 
977  // Handle Extended Scalar Types.
978  if (!VT.isVector()) {
979  assert(VT.isInteger() && "Float types must be simple");
980  unsigned BitSize = VT.getSizeInBits();
981  // First promote to a power-of-two size, then expand if necessary.
982  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
983  EVT NVT = VT.getRoundIntegerType(Context);
984  assert(NVT != VT && "Unable to round integer VT");
985  LegalizeKind NextStep = getTypeConversion(Context, NVT);
986  // Avoid multi-step promotion.
987  if (NextStep.first == TypePromoteInteger)
988  return NextStep;
989  // Return rounded integer type.
990  return LegalizeKind(TypePromoteInteger, NVT);
991  }
992 
995  }
996 
997  // Handle vector types.
998  ElementCount NumElts = VT.getVectorElementCount();
999  EVT EltVT = VT.getVectorElementType();
1000 
1001  // Vectors with only one element are always scalarized.
1002  if (NumElts.isScalar())
1003  return LegalizeKind(TypeScalarizeVector, EltVT);
1004 
1005  // Try to widen vector elements until the element type is a power of two and
1006  // promote it to a legal type later on, for example:
1007  // <3 x i8> -> <4 x i8> -> <4 x i32>
1008  if (EltVT.isInteger()) {
1009  // Vectors with a number of elements that is not a power of two are always
1010  // widened, for example <3 x i8> -> <4 x i8>.
1011  if (!VT.isPow2VectorType()) {
1012  NumElts = NumElts.coefficientNextPowerOf2();
1013  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1014  return LegalizeKind(TypeWidenVector, NVT);
1015  }
1016 
1017  // Examine the element type.
1018  LegalizeKind LK = getTypeConversion(Context, EltVT);
1019 
1020  // If type is to be expanded, split the vector.
1021  // <4 x i140> -> <2 x i140>
1022  if (LK.first == TypeExpandInteger) {
1023  if (VT.getVectorElementCount().isScalable())
1027  }
1028 
1029  // Promote the integer element types until a legal vector type is found
1030  // or until the element integer type is too big. If a legal type was not
1031  // found, fallback to the usual mechanism of widening/splitting the
1032  // vector.
1033  EVT OldEltVT = EltVT;
1034  while (true) {
1035  // Increase the bitwidth of the element to the next pow-of-two
1036  // (which is greater than 8 bits).
1037  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1039 
1040  // Stop trying when getting a non-simple element type.
1041  // Note that vector elements may be greater than legal vector element
1042  // types. Example: X86 XMM registers hold 64bit element on 32bit
1043  // systems.
1044  if (!EltVT.isSimple())
1045  break;
1046 
1047  // Build a new vector type and check if it is legal.
1048  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1049  // Found a legal promoted vector type.
1050  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1052  EVT::getVectorVT(Context, EltVT, NumElts));
1053  }
1054 
1055  // Reset the type to the unexpanded type if we did not find a legal vector
1056  // type with a promoted vector element type.
1057  EltVT = OldEltVT;
1058  }
1059 
1060  // Try to widen the vector until a legal type is found.
1061  // If there is no wider legal type, split the vector.
1062  while (true) {
1063  // Round up to the next power of 2.
1064  NumElts = NumElts.coefficientNextPowerOf2();
1065 
1066  // If there is no simple vector type with this many elements then there
1067  // cannot be a larger legal vector type. Note that this assumes that
1068  // there are no skipped intermediate vector types in the simple types.
1069  if (!EltVT.isSimple())
1070  break;
1071  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1072  if (LargerVector == MVT())
1073  break;
1074 
1075  // If this type is legal then widen the vector.
1076  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1077  return LegalizeKind(TypeWidenVector, LargerVector);
1078  }
1079 
1080  // Widen odd vectors to next power of two.
1081  if (!VT.isPow2VectorType()) {
1082  EVT NVT = VT.getPow2VectorType(Context);
1083  return LegalizeKind(TypeWidenVector, NVT);
1084  }
1085 
1088 
1089  // Vectors with illegal element types are expanded.
1090  EVT NVT = EVT::getVectorVT(Context, EltVT,
1092  return LegalizeKind(TypeSplitVector, NVT);
1093 }
1094 
1095 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1096  unsigned &NumIntermediates,
1097  MVT &RegisterVT,
1098  TargetLoweringBase *TLI) {
1099  // Figure out the right, legal destination reg to copy into.
1101  MVT EltTy = VT.getVectorElementType();
1102 
1103  unsigned NumVectorRegs = 1;
1104 
1105  // Scalable vectors cannot be scalarized, so splitting or widening is
1106  // required.
1107  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1109  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1110 
1111  // FIXME: We don't support non-power-of-2-sized vectors for now.
1112  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1113  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1114  // Split EC to unit size (scalable property is preserved).
1115  NumVectorRegs = EC.getKnownMinValue();
1116  EC = ElementCount::getFixed(1);
1117  }
1118 
1119  // Divide the input until we get to a supported size. This will
1120  // always end up with an EC that represent a scalar or a scalable
1121  // scalar.
1122  while (EC.getKnownMinValue() > 1 &&
1123  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1124  EC = EC.divideCoefficientBy(2);
1125  NumVectorRegs <<= 1;
1126  }
1127 
1128  NumIntermediates = NumVectorRegs;
1129 
1130  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1131  if (!TLI->isTypeLegal(NewVT))
1132  NewVT = EltTy;
1133  IntermediateVT = NewVT;
1134 
1135  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1136 
1137  // Convert sizes such as i33 to i64.
1138  if (!isPowerOf2_32(LaneSizeInBits))
1139  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1140 
1141  MVT DestVT = TLI->getRegisterType(NewVT);
1142  RegisterVT = DestVT;
1143  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1144  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1145 
1146  // Otherwise, promotion or legal types use the same number of registers as
1147  // the vector decimated to the appropriate level.
1148  return NumVectorRegs;
1149 }
1150 
1151 /// isLegalRC - Return true if the value types that can be represented by the
1152 /// specified register class are all legal.
1154  const TargetRegisterClass &RC) const {
1155  for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1156  if (isTypeLegal(*I))
1157  return true;
1158  return false;
1159 }
1160 
1161 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1162 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1165  MachineBasicBlock *MBB) const {
1166  MachineInstr *MI = &InitialMI;
1167  MachineFunction &MF = *MI->getMF();
1168  MachineFrameInfo &MFI = MF.getFrameInfo();
1169 
1170  // We're handling multiple types of operands here:
1171  // PATCHPOINT MetaArgs - live-in, read only, direct
1172  // STATEPOINT Deopt Spill - live-through, read only, indirect
1173  // STATEPOINT Deopt Alloca - live-through, read only, direct
1174  // (We're currently conservative and mark the deopt slots read/write in
1175  // practice.)
1176  // STATEPOINT GC Spill - live-through, read/write, indirect
1177  // STATEPOINT GC Alloca - live-through, read/write, direct
1178  // The live-in vs live-through is handled already (the live through ones are
1179  // all stack slots), but we need to handle the different type of stackmap
1180  // operands and memory effects here.
1181 
1182  if (llvm::none_of(MI->operands(),
1183  [](MachineOperand &Operand) { return Operand.isFI(); }))
1184  return MBB;
1185 
1186  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1187 
1188  // Inherit previous memory operands.
1189  MIB.cloneMemRefs(*MI);
1190 
1191  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1192  MachineOperand &MO = MI->getOperand(i);
1193  if (!MO.isFI()) {
1194  // Index of Def operand this Use it tied to.
1195  // Since Defs are coming before Uses, if Use is tied, then
1196  // index of Def must be smaller that index of that Use.
1197  // Also, Defs preserve their position in new MI.
1198  unsigned TiedTo = i;
1199  if (MO.isReg() && MO.isTied())
1200  TiedTo = MI->findTiedOperandIdx(i);
1201  MIB.add(MO);
1202  if (TiedTo < i)
1203  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1204  continue;
1205  }
1206 
1207  // foldMemoryOperand builds a new MI after replacing a single FI operand
1208  // with the canonical set of five x86 addressing-mode operands.
1209  int FI = MO.getIndex();
1210 
1211  // Add frame index operands recognized by stackmaps.cpp
1212  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1213  // indirect-mem-ref tag, size, #FI, offset.
1214  // Used for spills inserted by StatepointLowering. This codepath is not
1215  // used for patchpoints/stackmaps at all, for these spilling is done via
1216  // foldMemoryOperand callback only.
1217  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1218  MIB.addImm(StackMaps::IndirectMemRefOp);
1219  MIB.addImm(MFI.getObjectSize(FI));
1220  MIB.add(MO);
1221  MIB.addImm(0);
1222  } else {
1223  // direct-mem-ref tag, #FI, offset.
1224  // Used by patchpoint, and direct alloca arguments to statepoints
1225  MIB.addImm(StackMaps::DirectMemRefOp);
1226  MIB.add(MO);
1227  MIB.addImm(0);
1228  }
1229 
1230  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1231 
1232  // Add a new memory operand for this FI.
1233  assert(MFI.getObjectOffset(FI) != -1);
1234 
1235  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1236  // PATCHPOINT should be updated to do the same. (TODO)
1237  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1238  auto Flags = MachineMemOperand::MOLoad;
1240  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1241  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1242  MIB->addMemOperand(MF, MMO);
1243  }
1244  }
1246  MI->eraseFromParent();
1247  return MBB;
1248 }
1249 
1250 /// findRepresentativeClass - Return the largest legal super-reg register class
1251 /// of the register class for the specified type and its associated "cost".
1252 // This function is in TargetLowering because it uses RegClassForVT which would
1253 // need to be moved to TargetRegisterInfo and would necessitate moving
1254 // isTypeLegal over as well - a massive change that would just require
1255 // TargetLowering having a TargetRegisterInfo class member that it would use.
1256 std::pair<const TargetRegisterClass *, uint8_t>
1258  MVT VT) const {
1259  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1260  if (!RC)
1261  return std::make_pair(RC, 0);
1262 
1263  // Compute the set of all super-register classes.
1264  BitVector SuperRegRC(TRI->getNumRegClasses());
1265  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1266  SuperRegRC.setBitsInMask(RCI.getMask());
1267 
1268  // Find the first legal register class with the largest spill size.
1269  const TargetRegisterClass *BestRC = RC;
1270  for (unsigned i : SuperRegRC.set_bits()) {
1271  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1272  // We want the largest possible spill size.
1273  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1274  continue;
1275  if (!isLegalRC(*TRI, *SuperRC))
1276  continue;
1277  BestRC = SuperRC;
1278  }
1279  return std::make_pair(BestRC, 1);
1280 }
1281 
1282 /// computeRegisterProperties - Once all of the register classes are added,
1283 /// this allows us to compute derived properties we expose.
1285  const TargetRegisterInfo *TRI) {
1287  "Too many value types for ValueTypeActions to hold!");
1288 
1289  // Everything defaults to needing one register.
1290  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1291  NumRegistersForVT[i] = 1;
1292  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1293  }
1294  // ...except isVoid, which doesn't need any registers.
1295  NumRegistersForVT[MVT::isVoid] = 0;
1296 
1297  // Find the largest integer register class.
1298  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1299  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1300  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1301 
1302  // Every integer value type larger than this largest register takes twice as
1303  // many registers to represent as the previous ValueType.
1304  for (unsigned ExpandedReg = LargestIntReg + 1;
1305  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1306  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1307  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1308  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1309  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1311  }
1312 
1313  // Inspect all of the ValueType's smaller than the largest integer
1314  // register to see which ones need promotion.
1315  unsigned LegalIntReg = LargestIntReg;
1316  for (unsigned IntReg = LargestIntReg - 1;
1317  IntReg >= (unsigned)MVT::i1; --IntReg) {
1318  MVT IVT = (MVT::SimpleValueType)IntReg;
1319  if (isTypeLegal(IVT)) {
1320  LegalIntReg = IntReg;
1321  } else {
1322  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1323  (MVT::SimpleValueType)LegalIntReg;
1324  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1325  }
1326  }
1327 
1328  // ppcf128 type is really two f64's.
1329  if (!isTypeLegal(MVT::ppcf128)) {
1330  if (isTypeLegal(MVT::f64)) {
1331  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1332  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1333  TransformToType[MVT::ppcf128] = MVT::f64;
1334  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1335  } else {
1336  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1337  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1338  TransformToType[MVT::ppcf128] = MVT::i128;
1339  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1340  }
1341  }
1342 
1343  // Decide how to handle f128. If the target does not have native f128 support,
1344  // expand it to i128 and we will be generating soft float library calls.
1345  if (!isTypeLegal(MVT::f128)) {
1346  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1347  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1348  TransformToType[MVT::f128] = MVT::i128;
1349  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1350  }
1351 
1352  // Decide how to handle f64. If the target does not have native f64 support,
1353  // expand it to i64 and we will be generating soft float library calls.
1354  if (!isTypeLegal(MVT::f64)) {
1355  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1356  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1357  TransformToType[MVT::f64] = MVT::i64;
1358  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1359  }
1360 
1361  // Decide how to handle f32. If the target does not have native f32 support,
1362  // expand it to i32 and we will be generating soft float library calls.
1363  if (!isTypeLegal(MVT::f32)) {
1364  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1365  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1366  TransformToType[MVT::f32] = MVT::i32;
1367  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1368  }
1369 
1370  // Decide how to handle f16. If the target does not have native f16 support,
1371  // promote it to f32, because there are no f16 library calls (except for
1372  // conversions).
1373  if (!isTypeLegal(MVT::f16)) {
1374  // Allow targets to control how we legalize half.
1375  if (softPromoteHalfType()) {
1376  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1377  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1378  TransformToType[MVT::f16] = MVT::f32;
1379  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1380  } else {
1381  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1382  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1383  TransformToType[MVT::f16] = MVT::f32;
1384  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1385  }
1386  }
1387 
1388  // Decide how to handle bf16. If the target does not have native bf16 support,
1389  // promote it to f32, because there are no bf16 library calls (except for
1390  // converting from f32 to bf16).
1391  if (!isTypeLegal(MVT::bf16)) {
1392  NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1393  RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1394  TransformToType[MVT::bf16] = MVT::f32;
1395  ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
1396  }
1397 
1398  // Loop over all of the vector value types to see which need transformations.
1399  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1400  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1401  MVT VT = (MVT::SimpleValueType) i;
1402  if (isTypeLegal(VT))
1403  continue;
1404 
1405  MVT EltVT = VT.getVectorElementType();
1407  bool IsLegalWiderType = false;
1408  bool IsScalable = VT.isScalableVector();
1409  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1410  switch (PreferredAction) {
1411  case TypePromoteInteger: {
1412  MVT::SimpleValueType EndVT = IsScalable ?
1415  // Try to promote the elements of integer vectors. If no legal
1416  // promotion was found, fall through to the widen-vector method.
1417  for (unsigned nVT = i + 1;
1418  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1419  MVT SVT = (MVT::SimpleValueType) nVT;
1420  // Promote vectors of integers to vectors with the same number
1421  // of elements, with a wider element type.
1422  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1423  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1424  TransformToType[i] = SVT;
1425  RegisterTypeForVT[i] = SVT;
1426  NumRegistersForVT[i] = 1;
1427  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1428  IsLegalWiderType = true;
1429  break;
1430  }
1431  }
1432  if (IsLegalWiderType)
1433  break;
1434  [[fallthrough]];
1435  }
1436 
1437  case TypeWidenVector:
1438  if (isPowerOf2_32(EC.getKnownMinValue())) {
1439  // Try to widen the vector.
1440  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1441  MVT SVT = (MVT::SimpleValueType) nVT;
1442  if (SVT.getVectorElementType() == EltVT &&
1443  SVT.isScalableVector() == IsScalable &&
1445  EC.getKnownMinValue() &&
1446  isTypeLegal(SVT)) {
1447  TransformToType[i] = SVT;
1448  RegisterTypeForVT[i] = SVT;
1449  NumRegistersForVT[i] = 1;
1450  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1451  IsLegalWiderType = true;
1452  break;
1453  }
1454  }
1455  if (IsLegalWiderType)
1456  break;
1457  } else {
1458  // Only widen to the next power of 2 to keep consistency with EVT.
1459  MVT NVT = VT.getPow2VectorType();
1460  if (isTypeLegal(NVT)) {
1461  TransformToType[i] = NVT;
1462  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1463  RegisterTypeForVT[i] = NVT;
1464  NumRegistersForVT[i] = 1;
1465  break;
1466  }
1467  }
1468  [[fallthrough]];
1469 
1470  case TypeSplitVector:
1471  case TypeScalarizeVector: {
1472  MVT IntermediateVT;
1473  MVT RegisterVT;
1474  unsigned NumIntermediates;
1475  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1476  NumIntermediates, RegisterVT, this);
1477  NumRegistersForVT[i] = NumRegisters;
1478  assert(NumRegistersForVT[i] == NumRegisters &&
1479  "NumRegistersForVT size cannot represent NumRegisters!");
1480  RegisterTypeForVT[i] = RegisterVT;
1481 
1482  MVT NVT = VT.getPow2VectorType();
1483  if (NVT == VT) {
1484  // Type is already a power of 2. The default action is to split.
1485  TransformToType[i] = MVT::Other;
1486  if (PreferredAction == TypeScalarizeVector)
1487  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1488  else if (PreferredAction == TypeSplitVector)
1489  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1490  else if (EC.getKnownMinValue() > 1)
1491  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1492  else
1493  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1496  } else {
1497  TransformToType[i] = NVT;
1498  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1499  }
1500  break;
1501  }
1502  default:
1503  llvm_unreachable("Unknown vector legalization action!");
1504  }
1505  }
1506 
1507  // Determine the 'representative' register class for each value type.
1508  // An representative register class is the largest (meaning one which is
1509  // not a sub-register class / subreg register class) legal register class for
1510  // a group of value types. For example, on i386, i8, i16, and i32
1511  // representative would be GR32; while on x86_64 it's GR64.
1512  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1513  const TargetRegisterClass* RRC;
1514  uint8_t Cost;
1516  RepRegClassForVT[i] = RRC;
1517  RepRegClassCostForVT[i] = Cost;
1518  }
1519 }
1520 
1522  EVT VT) const {
1523  assert(!VT.isVector() && "No default SetCC type for vectors!");
1524  return getPointerTy(DL).SimpleTy;
1525 }
1526 
1528  return MVT::i32; // return the default value
1529 }
1530 
1531 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1532 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1533 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1534 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1535 ///
1536 /// This method returns the number of registers needed, and the VT for each
1537 /// register. It also returns the VT and quantity of the intermediate values
1538 /// before they are promoted/expanded.
1540  EVT VT, EVT &IntermediateVT,
1541  unsigned &NumIntermediates,
1542  MVT &RegisterVT) const {
1543  ElementCount EltCnt = VT.getVectorElementCount();
1544 
1545  // If there is a wider vector type with the same element type as this one,
1546  // or a promoted vector type that has the same number of elements which
1547  // are wider, then we should convert to that legal vector type.
1548  // This handles things like <2 x float> -> <4 x float> and
1549  // <4 x i1> -> <4 x i32>.
1551  if (!EltCnt.isScalar() &&
1552  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1553  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1554  if (isTypeLegal(RegisterEVT)) {
1555  IntermediateVT = RegisterEVT;
1556  RegisterVT = RegisterEVT.getSimpleVT();
1557  NumIntermediates = 1;
1558  return 1;
1559  }
1560  }
1561 
1562  // Figure out the right, legal destination reg to copy into.
1563  EVT EltTy = VT.getVectorElementType();
1564 
1565  unsigned NumVectorRegs = 1;
1566 
1567  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1568  // types like done elsewhere in SelectionDAG.
1569  if (EltCnt.isScalable()) {
1570  LegalizeKind LK;
1571  EVT PartVT = VT;
1572  do {
1573  // Iterate until we've found a legal (part) type to hold VT.
1574  LK = getTypeConversion(Context, PartVT);
1575  PartVT = LK.second;
1576  } while (LK.first != TypeLegal);
1577 
1578  if (!PartVT.isVector()) {
1580  "Don't know how to legalize this scalable vector type");
1581  }
1582 
1583  NumIntermediates =
1586  IntermediateVT = PartVT;
1587  RegisterVT = getRegisterType(Context, IntermediateVT);
1588  return NumIntermediates;
1589  }
1590 
1591  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1592  // we could break down into LHS/RHS like LegalizeDAG does.
1593  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1594  NumVectorRegs = EltCnt.getKnownMinValue();
1595  EltCnt = ElementCount::getFixed(1);
1596  }
1597 
1598  // Divide the input until we get to a supported size. This will always
1599  // end with a scalar if the target doesn't support vectors.
1600  while (EltCnt.getKnownMinValue() > 1 &&
1601  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1602  EltCnt = EltCnt.divideCoefficientBy(2);
1603  NumVectorRegs <<= 1;
1604  }
1605 
1606  NumIntermediates = NumVectorRegs;
1607 
1608  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1609  if (!isTypeLegal(NewVT))
1610  NewVT = EltTy;
1611  IntermediateVT = NewVT;
1612 
1613  MVT DestVT = getRegisterType(Context, NewVT);
1614  RegisterVT = DestVT;
1615 
1616  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1617  TypeSize NewVTSize = NewVT.getSizeInBits();
1618  // Convert sizes such as i33 to i64.
1619  if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
1620  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1621  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1622  }
1623 
1624  // Otherwise, promotion or legal types use the same number of registers as
1625  // the vector decimated to the appropriate level.
1626  return NumVectorRegs;
1627 }
1628 
1630  uint64_t NumCases,
1631  uint64_t Range,
1632  ProfileSummaryInfo *PSI,
1633  BlockFrequencyInfo *BFI) const {
1634  // FIXME: This function check the maximum table size and density, but the
1635  // minimum size is not checked. It would be nice if the minimum size is
1636  // also combined within this function. Currently, the minimum size check is
1637  // performed in findJumpTable() in SelectionDAGBuiler and
1638  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1639  const bool OptForSize =
1640  SI->getParent()->getParent()->hasOptSize() ||
1641  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1642  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1643  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1644 
1645  // Check whether the number of cases is small enough and
1646  // the range is dense enough for a jump table.
1647  return (OptForSize || Range <= MaxJumpTableSize) &&
1648  (NumCases * 100 >= Range * MinDensity);
1649 }
1650 
1652  EVT ConditionVT) const {
1653  return getRegisterType(Context, ConditionVT);
1654 }
1655 
1656 /// Get the EVTs and ArgFlags collections that represent the legalized return
1657 /// type of the given function. This does not require a DAG or a return value,
1658 /// and is suitable for use before any DAGs for the function are constructed.
1659 /// TODO: Move this out of TargetLowering.cpp.
1661  AttributeList attr,
1663  const TargetLowering &TLI, const DataLayout &DL) {
1664  SmallVector<EVT, 4> ValueVTs;
1665  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1666  unsigned NumValues = ValueVTs.size();
1667  if (NumValues == 0) return;
1668 
1669  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1670  EVT VT = ValueVTs[j];
1671  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1672 
1673  if (attr.hasRetAttr(Attribute::SExt))
1674  ExtendKind = ISD::SIGN_EXTEND;
1675  else if (attr.hasRetAttr(Attribute::ZExt))
1676  ExtendKind = ISD::ZERO_EXTEND;
1677 
1678  // FIXME: C calling convention requires the return type to be promoted to
1679  // at least 32-bit. But this is not necessary for non-C calling
1680  // conventions. The frontend should mark functions whose return values
1681  // require promoting with signext or zeroext attributes.
1682  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1683  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1684  if (VT.bitsLT(MinVT))
1685  VT = MinVT;
1686  }
1687 
1688  unsigned NumParts =
1689  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1690  MVT PartVT =
1691  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1692 
1693  // 'inreg' on function refers to return value
1694  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1695  if (attr.hasRetAttr(Attribute::InReg))
1696  Flags.setInReg();
1697 
1698  // Propagate extension type if any
1699  if (attr.hasRetAttr(Attribute::SExt))
1700  Flags.setSExt();
1701  else if (attr.hasRetAttr(Attribute::ZExt))
1702  Flags.setZExt();
1703 
1704  for (unsigned i = 0; i < NumParts; ++i)
1705  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1706  }
1707 }
1708 
1709 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1710 /// function arguments in the caller parameter area. This is the actual
1711 /// alignment, not its logarithm.
1713  const DataLayout &DL) const {
1714  return DL.getABITypeAlign(Ty).value();
1715 }
1716 
1718  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1719  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1720  // Check if the specified alignment is sufficient based on the data layout.
1721  // TODO: While using the data layout works in practice, a better solution
1722  // would be to implement this check directly (make this a virtual function).
1723  // For example, the ABI alignment may change based on software platform while
1724  // this function should only be affected by hardware implementation.
1725  Type *Ty = VT.getTypeForEVT(Context);
1726  if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1727  // Assume that an access that meets the ABI-specified alignment is fast.
1728  if (Fast != nullptr)
1729  *Fast = true;
1730  return true;
1731  }
1732 
1733  // This is a misaligned access.
1734  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1735 }
1736 
1738  LLVMContext &Context, const DataLayout &DL, EVT VT,
1739  const MachineMemOperand &MMO, bool *Fast) const {
1741  MMO.getAlign(), MMO.getFlags(), Fast);
1742 }
1743 
1745  const DataLayout &DL, EVT VT,
1746  unsigned AddrSpace, Align Alignment,
1748  bool *Fast) const {
1749  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1750  Flags, Fast);
1751 }
1752 
1754  const DataLayout &DL, EVT VT,
1755  const MachineMemOperand &MMO,
1756  bool *Fast) const {
1757  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1758  MMO.getFlags(), Fast);
1759 }
1760 
1762  const DataLayout &DL, LLT Ty,
1763  const MachineMemOperand &MMO,
1764  bool *Fast) const {
1766  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1767  MMO.getFlags(), Fast);
1768 }
1769 
1770 //===----------------------------------------------------------------------===//
1771 // TargetTransformInfo Helpers
1772 //===----------------------------------------------------------------------===//
1773 
1775  enum InstructionOpcodes {
1776 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1777 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1778 #include "llvm/IR/Instruction.def"
1779  };
1780  switch (static_cast<InstructionOpcodes>(Opcode)) {
1781  case Ret: return 0;
1782  case Br: return 0;
1783  case Switch: return 0;
1784  case IndirectBr: return 0;
1785  case Invoke: return 0;
1786  case CallBr: return 0;
1787  case Resume: return 0;
1788  case Unreachable: return 0;
1789  case CleanupRet: return 0;
1790  case CatchRet: return 0;
1791  case CatchPad: return 0;
1792  case CatchSwitch: return 0;
1793  case CleanupPad: return 0;
1794  case FNeg: return ISD::FNEG;
1795  case Add: return ISD::ADD;
1796  case FAdd: return ISD::FADD;
1797  case Sub: return ISD::SUB;
1798  case FSub: return ISD::FSUB;
1799  case Mul: return ISD::MUL;
1800  case FMul: return ISD::FMUL;
1801  case UDiv: return ISD::UDIV;
1802  case SDiv: return ISD::SDIV;
1803  case FDiv: return ISD::FDIV;
1804  case URem: return ISD::UREM;
1805  case SRem: return ISD::SREM;
1806  case FRem: return ISD::FREM;
1807  case Shl: return ISD::SHL;
1808  case LShr: return ISD::SRL;
1809  case AShr: return ISD::SRA;
1810  case And: return ISD::AND;
1811  case Or: return ISD::OR;
1812  case Xor: return ISD::XOR;
1813  case Alloca: return 0;
1814  case Load: return ISD::LOAD;
1815  case Store: return ISD::STORE;
1816  case GetElementPtr: return 0;
1817  case Fence: return 0;
1818  case AtomicCmpXchg: return 0;
1819  case AtomicRMW: return 0;
1820  case Trunc: return ISD::TRUNCATE;
1821  case ZExt: return ISD::ZERO_EXTEND;
1822  case SExt: return ISD::SIGN_EXTEND;
1823  case FPToUI: return ISD::FP_TO_UINT;
1824  case FPToSI: return ISD::FP_TO_SINT;
1825  case UIToFP: return ISD::UINT_TO_FP;
1826  case SIToFP: return ISD::SINT_TO_FP;
1827  case FPTrunc: return ISD::FP_ROUND;
1828  case FPExt: return ISD::FP_EXTEND;
1829  case PtrToInt: return ISD::BITCAST;
1830  case IntToPtr: return ISD::BITCAST;
1831  case BitCast: return ISD::BITCAST;
1832  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1833  case ICmp: return ISD::SETCC;
1834  case FCmp: return ISD::SETCC;
1835  case PHI: return 0;
1836  case Call: return 0;
1837  case Select: return ISD::SELECT;
1838  case UserOp1: return 0;
1839  case UserOp2: return 0;
1840  case VAArg: return 0;
1841  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1842  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1843  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1844  case ExtractValue: return ISD::MERGE_VALUES;
1845  case InsertValue: return ISD::MERGE_VALUES;
1846  case LandingPad: return 0;
1847  case Freeze: return ISD::FREEZE;
1848  }
1849 
1850  llvm_unreachable("Unknown instruction type encountered!");
1851 }
1852 
1853 Value *
1855  bool UseTLS) const {
1856  // compiler-rt provides a variable with a magic name. Targets that do not
1857  // link with compiler-rt may also provide such a variable.
1858  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1859  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1860  auto UnsafeStackPtr =
1861  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1862 
1863  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1864 
1865  if (!UnsafeStackPtr) {
1866  auto TLSModel = UseTLS ?
1869  // The global variable is not defined yet, define it ourselves.
1870  // We use the initial-exec TLS model because we do not support the
1871  // variable living anywhere other than in the main executable.
1872  UnsafeStackPtr = new GlobalVariable(
1873  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1874  UnsafeStackPtrVar, nullptr, TLSModel);
1875  } else {
1876  // The variable exists, check its type and attributes.
1877  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1878  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1879  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1880  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1881  (UseTLS ? "" : "not ") + "be thread-local");
1882  }
1883  return UnsafeStackPtr;
1884 }
1885 
1886 Value *
1888  if (!TM.getTargetTriple().isAndroid())
1889  return getDefaultSafeStackPointerLocation(IRB, true);
1890 
1891  // Android provides a libc function to retrieve the address of the current
1892  // thread's unsafe stack pointer.
1893  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1894  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1895  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1896  StackPtrTy->getPointerTo(0));
1897  return IRB.CreateCall(Fn);
1898 }
1899 
1900 //===----------------------------------------------------------------------===//
1901 // Loop Strength Reduction hooks
1902 //===----------------------------------------------------------------------===//
1903 
1904 /// isLegalAddressingMode - Return true if the addressing mode represented
1905 /// by AM is legal for this target, for a load/store of the specified type.
1907  const AddrMode &AM, Type *Ty,
1908  unsigned AS, Instruction *I) const {
1909  // The default implementation of this implements a conservative RISCy, r+r and
1910  // r+i addr mode.
1911 
1912  // Allows a sign-extended 16-bit immediate field.
1913  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1914  return false;
1915 
1916  // No global is ever allowed as a base.
1917  if (AM.BaseGV)
1918  return false;
1919 
1920  // Only support r+r,
1921  switch (AM.Scale) {
1922  case 0: // "r+i" or just "i", depending on HasBaseReg.
1923  break;
1924  case 1:
1925  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1926  return false;
1927  // Otherwise we have r+r or r+i.
1928  break;
1929  case 2:
1930  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1931  return false;
1932  // Allow 2*r as r+r.
1933  break;
1934  default: // Don't allow n * r
1935  return false;
1936  }
1937 
1938  return true;
1939 }
1940 
1941 //===----------------------------------------------------------------------===//
1942 // Stack Protector
1943 //===----------------------------------------------------------------------===//
1944 
1945 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1946 // so that SelectionDAG handle SSP.
1948  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1949  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1950  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1951  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1952  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1953  G->setVisibility(GlobalValue::HiddenVisibility);
1954  return C;
1955  }
1956  return nullptr;
1957 }
1958 
1959 // Currently only support "standard" __stack_chk_guard.
1960 // TODO: add LOAD_STACK_GUARD support.
1962  if (!M.getNamedValue("__stack_chk_guard")) {
1963  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1965  "__stack_chk_guard");
1966 
1967  // FreeBSD has "__stack_chk_guard" defined externally on libc.so
1968  if (TM.getRelocationModel() == Reloc::Static &&
1970  !TM.getTargetTriple().isOSFreeBSD())
1971  GV->setDSOLocal(true);
1972  }
1973 }
1974 
1975 // Currently only support "standard" __stack_chk_guard.
1976 // TODO: add LOAD_STACK_GUARD support.
1978  return M.getNamedValue("__stack_chk_guard");
1979 }
1980 
1982  return nullptr;
1983 }
1984 
1986  return MinimumJumpTableEntries;
1987 }
1988 
1991 }
1992 
1993 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1994  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1995 }
1996 
1998  return MaximumJumpTableSize;
1999 }
2000 
2002  MaximumJumpTableSize = Val;
2003 }
2004 
2007 }
2008 
2010  if (TM.Options.LoopAlignment)
2011  return Align(TM.Options.LoopAlignment);
2012  return PrefLoopAlignment;
2013 }
2014 
2016  MachineBasicBlock *MBB) const {
2017  return MaxBytesForAlignment;
2018 }
2019 
2020 //===----------------------------------------------------------------------===//
2021 // Reciprocal Estimates
2022 //===----------------------------------------------------------------------===//
2023 
2024 /// Get the reciprocal estimate attribute string for a function that will
2025 /// override the target defaults.
2027  const Function &F = MF.getFunction();
2028  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2029 }
2030 
2031 /// Construct a string for the given reciprocal operation of the given type.
2032 /// This string should match the corresponding option to the front-end's
2033 /// "-mrecip" flag assuming those strings have been passed through in an
2034 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2035 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2036  std::string Name = VT.isVector() ? "vec-" : "";
2037 
2038  Name += IsSqrt ? "sqrt" : "div";
2039 
2040  // TODO: Handle other float types?
2041  if (VT.getScalarType() == MVT::f64) {
2042  Name += "d";
2043  } else if (VT.getScalarType() == MVT::f16) {
2044  Name += "h";
2045  } else {
2046  assert(VT.getScalarType() == MVT::f32 &&
2047  "Unexpected FP type for reciprocal estimate");
2048  Name += "f";
2049  }
2050 
2051  return Name;
2052 }
2053 
2054 /// Return the character position and value (a single numeric character) of a
2055 /// customized refinement operation in the input string if it exists. Return
2056 /// false if there is no customized refinement step count.
2057 static bool parseRefinementStep(StringRef In, size_t &Position,
2058  uint8_t &Value) {
2059  const char RefStepToken = ':';
2060  Position = In.find(RefStepToken);
2061  if (Position == StringRef::npos)
2062  return false;
2063 
2064  StringRef RefStepString = In.substr(Position + 1);
2065  // Allow exactly one numeric character for the additional refinement
2066  // step parameter.
2067  if (RefStepString.size() == 1) {
2068  char RefStepChar = RefStepString[0];
2069  if (isDigit(RefStepChar)) {
2070  Value = RefStepChar - '0';
2071  return true;
2072  }
2073  }
2074  report_fatal_error("Invalid refinement step for -recip.");
2075 }
2076 
2077 /// For the input attribute string, return one of the ReciprocalEstimate enum
2078 /// status values (enabled, disabled, or not specified) for this operation on
2079 /// the specified data type.
2080 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2081  if (Override.empty())
2082  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2083 
2084  SmallVector<StringRef, 4> OverrideVector;
2085  Override.split(OverrideVector, ',');
2086  unsigned NumArgs = OverrideVector.size();
2087 
2088  // Check if "all", "none", or "default" was specified.
2089  if (NumArgs == 1) {
2090  // Look for an optional setting of the number of refinement steps needed
2091  // for this type of reciprocal operation.
2092  size_t RefPos;
2093  uint8_t RefSteps;
2094  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2095  // Split the string for further processing.
2096  Override = Override.substr(0, RefPos);
2097  }
2098 
2099  // All reciprocal types are enabled.
2100  if (Override == "all")
2102 
2103  // All reciprocal types are disabled.
2104  if (Override == "none")
2106 
2107  // Target defaults for enablement are used.
2108  if (Override == "default")
2109  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2110  }
2111 
2112  // The attribute string may omit the size suffix ('f'/'d').
2113  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2114  std::string VTNameNoSize = VTName;
2115  VTNameNoSize.pop_back();
2116  static const char DisabledPrefix = '!';
2117 
2118  for (StringRef RecipType : OverrideVector) {
2119  size_t RefPos;
2120  uint8_t RefSteps;
2121  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2122  RecipType = RecipType.substr(0, RefPos);
2123 
2124  // Ignore the disablement token for string matching.
2125  bool IsDisabled = RecipType[0] == DisabledPrefix;
2126  if (IsDisabled)
2127  RecipType = RecipType.substr(1);
2128 
2129  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2132  }
2133 
2134  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2135 }
2136 
2137 /// For the input attribute string, return the customized refinement step count
2138 /// for this operation on the specified data type. If the step count does not
2139 /// exist, return the ReciprocalEstimate enum value for unspecified.
2140 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2141  if (Override.empty())
2142  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2143 
2144  SmallVector<StringRef, 4> OverrideVector;
2145  Override.split(OverrideVector, ',');
2146  unsigned NumArgs = OverrideVector.size();
2147 
2148  // Check if "all", "default", or "none" was specified.
2149  if (NumArgs == 1) {
2150  // Look for an optional setting of the number of refinement steps needed
2151  // for this type of reciprocal operation.
2152  size_t RefPos;
2153  uint8_t RefSteps;
2154  if (!parseRefinementStep(Override, RefPos, RefSteps))
2155  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2156 
2157  // Split the string for further processing.
2158  Override = Override.substr(0, RefPos);
2159  assert(Override != "none" &&
2160  "Disabled reciprocals, but specifed refinement steps?");
2161 
2162  // If this is a general override, return the specified number of steps.
2163  if (Override == "all" || Override == "default")
2164  return RefSteps;
2165  }
2166 
2167  // The attribute string may omit the size suffix ('f'/'d').
2168  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2169  std::string VTNameNoSize = VTName;
2170  VTNameNoSize.pop_back();
2171 
2172  for (StringRef RecipType : OverrideVector) {
2173  size_t RefPos;
2174  uint8_t RefSteps;
2175  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2176  continue;
2177 
2178  RecipType = RecipType.substr(0, RefPos);
2179  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2180  return RefSteps;
2181  }
2182 
2183  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2184 }
2185 
2187  MachineFunction &MF) const {
2188  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2189 }
2190 
2192  MachineFunction &MF) const {
2193  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2194 }
2195 
2197  MachineFunction &MF) const {
2198  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2199 }
2200 
2202  MachineFunction &MF) const {
2203  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2204 }
2205 
2207  MF.getRegInfo().freezeReservedRegs(MF);
2208 }
2209 
2212  const DataLayout &DL) const {
2214  if (LI.isVolatile())
2216 
2217  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2219 
2220  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2222 
2225 
2226  Flags |= getTargetMMOFlags(LI);
2227  return Flags;
2228 }
2229 
2232  const DataLayout &DL) const {
2234 
2235  if (SI.isVolatile())
2237 
2238  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2240 
2241  // FIXME: Not preserving dereferenceable
2242  Flags |= getTargetMMOFlags(SI);
2243  return Flags;
2244 }
2245 
2248  const DataLayout &DL) const {
2250 
2251  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2252  if (RMW->isVolatile())
2254  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2255  if (CmpX->isVolatile())
2257  } else
2258  llvm_unreachable("not an atomic instruction");
2259 
2260  // FIXME: Not preserving dereferenceable
2261  Flags |= getTargetMMOFlags(AI);
2262  return Flags;
2263 }
2264 
2266  Instruction *Inst,
2267  AtomicOrdering Ord) const {
2268  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2269  return Builder.CreateFence(Ord);
2270  else
2271  return nullptr;
2272 }
2273 
2275  Instruction *Inst,
2276  AtomicOrdering Ord) const {
2277  if (isAcquireOrStronger(Ord))
2278  return Builder.CreateFence(Ord);
2279  else
2280  return nullptr;
2281 }
2282 
2283 //===----------------------------------------------------------------------===//
2284 // GlobalISel Hooks
2285 //===----------------------------------------------------------------------===//
2286 
2288  const TargetTransformInfo *TTI) const {
2289  auto &MF = *MI.getMF();
2290  auto &MRI = MF.getRegInfo();
2291  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2292  // this helper function computes the maximum number of uses we should consider
2293  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2294  // break even in terms of code size when the original MI has 2 users vs
2295  // choosing to potentially spill. Any more than 2 users we we have a net code
2296  // size increase. This doesn't take into account register pressure though.
2297  auto maxUses = [](unsigned RematCost) {
2298  // A cost of 1 means remats are basically free.
2299  if (RematCost == 1)
2301  if (RematCost == 2)
2302  return 2U;
2303 
2304  // Remat is too expensive, only sink if there's one user.
2305  if (RematCost > 2)
2306  return 1U;
2307  llvm_unreachable("Unexpected remat cost");
2308  };
2309 
2310  switch (MI.getOpcode()) {
2311  default:
2312  return false;
2313  // Constants-like instructions should be close to their users.
2314  // We don't want long live-ranges for them.
2315  case TargetOpcode::G_CONSTANT:
2316  case TargetOpcode::G_FCONSTANT:
2317  case TargetOpcode::G_FRAME_INDEX:
2318  case TargetOpcode::G_INTTOPTR:
2319  return true;
2320  case TargetOpcode::G_GLOBAL_VALUE: {
2321  unsigned RematCost = TTI->getGISelRematGlobalCost();
2322  Register Reg = MI.getOperand(0).getReg();
2323  unsigned MaxUses = maxUses(RematCost);
2324  if (MaxUses == UINT_MAX)
2325  return true; // Remats are "free" so always localize.
2326  return MRI.hasAtMostUserInstrs(Reg, MaxUses);
2327  }
2328  }
2329 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:459
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:917
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:2026
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:929
i
i
Definition: README.txt:29
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:1993
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2419
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3369
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::TargetLoweringBase::getByValTypeAlignment
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1712
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:957
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:586
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:531
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2460
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1448
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:111
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:578
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:190
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1096
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1604
llvm::TargetLoweringBase::getPreferredSwitchConditionType
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
Definition: TargetLoweringBase.cpp:1651
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:668
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1445
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:291
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:322
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:104
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1099
llvm::ElementCount
Definition: TypeSize.h:404
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:943
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:387
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1195
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:61
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:542
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1153
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:50
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1188
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:708
llvm::Triple::x86
@ x86
Definition: Triple.h:85
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:215
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3367
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:192
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:696
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:52
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:839
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1444
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:214
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:376
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:2001
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:650
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1181
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:101
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::GlobalVariable
Definition: GlobalVariable.h:39
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:738
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:920
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1887
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:350
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1257
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::TargetLoweringBase::getPrefLoopAlignment
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
Definition: TargetLoweringBase.cpp:2009
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1095
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:360
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:68
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::AttributeList
Definition: Attributes.h:425
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:139
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1629
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
llvm::StringRef::substr
StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:561
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1275
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:516
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:2005
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:951
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3129
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:803
STLExtras.h
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1259
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1854
llvm::TargetLoweringBase::emitTrailingFence
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Definition: TargetLoweringBase.cpp:2274
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:261
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:268
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:207
llvm::MVT::i4
@ i4
Definition: MachineValueType.h:45
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1164
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:216
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::EVT::isZeroSized
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:124
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:386
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3390
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2211
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2402
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1189
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:360
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:452
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
Definition: TargetLoweringBase.cpp:915
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::TargetLoweringBase::emitLeadingFence
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: TargetLoweringBase.cpp:2265
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:383
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2385
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::ISD::AVGFLOORU
@ AVGFLOORU
Definition: ISDOpcodes.h:644
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3355
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ElementCount::isScalar
bool isScalar() const
Counting predicates.
Definition: TypeSize.h:414
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:344
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1287
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:930
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1153
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:697
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:713
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2287
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::IntegerType::MAX_INT_BITS
@ MAX_INT_BITS
Maximum number of bits that can be specified.
Definition: DerivedTypes.h:52
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
InlinePriorityMode::Cost
@ Cost
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1446
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:444
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:226
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:101
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:234
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:792
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2057
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2555
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
Definition: TargetLoweringBase.cpp:956
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:265
Twine.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1100
llvm::MVT::i2
@ i2
Definition: MachineValueType.h:44
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:928
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:331
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:932
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:950
llvm::TargetLoweringBase::getMaxPermittedBytesForAlignment
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
Definition: TargetLoweringBase.cpp:2015
llvm::NextPowerOf2
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:611
TargetOpcodes.h
llvm::ISD::DELETED_NODE
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:274
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3405
llvm::AMDGPU::CPol::NT
@ NT
Definition: SIDefines.h:310
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:890
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1187
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::Instruction
Definition: Instruction.h:42
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1906
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1194
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1977
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:927
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:926
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:403
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1539
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:509
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1452
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3382
llvm::MVT::v64i4
@ v64i4
Definition: MachineValueType.h:81
llvm::BitVector
Definition: BitVector.h:75
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::RTLIB::getFPLibCall
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Definition: TargetLoweringBase.cpp:216
llvm::ISD::ABDS
@ ABDS
Definition: ISDOpcodes.h:655
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:613
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1961
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:212
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1162
llvm::TargetOptions::LoopAlignment
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
Definition: TargetOptions.h:373
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:474
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:272
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:931
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:914
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:999
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:560
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1273
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:59
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1527
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3423
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::ISD::AVGCEILU
@ AVGCEILU
Definition: ISDOpcodes.h:649
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2336
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3384
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:956
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:1997
llvm::cl::opt< bool >
llvm::ISD::AVGCEILS
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:648
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1985
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1240
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1947
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:298
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:683
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1611
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:310
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:953
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:921
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1276
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:771
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:486
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1176
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1192
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:936
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:650
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1280
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:292
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:966
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1285
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:208
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:535
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:206
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:496
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:196
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2201
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:314
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:233
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1272
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2247
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1191
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1260
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:933
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:669
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1170
size
i< reg-> size
Definition: README.txt:166
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:341
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1185
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:632
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1521
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1722
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2191
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:253
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:890
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3426
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1136
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MVT::all_valuetypes
static auto all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1467
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2231
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1282
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:296
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2140
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MVT::bf16
@ bf16
Definition: MachineValueType.h:55
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::isAcquireOrStronger
bool isAcquireOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:128
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Triple.h
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1225
TargetOptions.h
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:957
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1140
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:633
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:176
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:663
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1373
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:716
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:308
llvm::isDereferenceablePointer
bool isDereferenceablePointer(const Value *V, Type *Ty, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Return true if this is always a dereferenceable pointer.
Definition: Loads.cpp:219
llvm::ISD::ABDU
@ ABDU
Definition: ISDOpcodes.h:656
llvm::isReleaseOrStronger
bool isReleaseOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:934
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1186
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2553
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3438
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3419
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:922
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1774
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:368
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2375
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:923
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1284
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:392
llvm::getApproximateEVTForLLT
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
Definition: LowLevelType.cpp:54
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1184
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:598
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:314
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:205
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:872
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:944
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:346
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2186
Attributes.h
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1981
llvm::MachineRegisterInfo::hasAtMostUserInstrs
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
Definition: MachineRegisterInfo.cpp:423
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:420
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2554
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:944
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2353
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:233
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:838
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:616
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2556
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2080
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:267
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1281
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:374
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1327
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: TargetLoweringBase.cpp:910
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:924
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::enum_seq
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
Definition: Sequence.h:327
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:173
Enabled
static bool Enabled
Definition: Statistic.cpp:46
llvm::TypeSize
Definition: TypeSize.h:435
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:605
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::LinearPolySize< ElementCount >::getScalable
static ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:204
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1283
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:774
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:357
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:420
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:765
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:949
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:209
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3103
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2035
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:967
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:213
llvm::force_iteration_on_noniterable_enum
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
Definition: Sequence.h:108
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:501
llvm::ISD::IS_FPCLASS
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:506
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1744
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:871
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:496
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
llvm::MVT::v128i2
@ v128i2
Definition: MachineValueType.h:78
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:391
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:60
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1146
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1660
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1717
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:211
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1113
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:197
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:814
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:56
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:210
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1284
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1603
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1375
llvm::AttributeList::hasRetAttr
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:772
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1989
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:705
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:165
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1541
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2552
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:437
llvm::TypeSize::getKnownMinSize
ScalarTy getKnownMinSize() const
Definition: TypeSize.h:445
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:808
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:662
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:931
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2429
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:406
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:911
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:381
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3278
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3403
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:701
llvm::cl::desc
Definition: CommandLine.h:413
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1190
llvm::MVT::fp_valuetypes
static auto fp_valuetypes()
Definition: MachineValueType.h:1478
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:53
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1286
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:211
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1288
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2206
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1086
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:195
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:925
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LinearPolySize::divideCoefficientBy
LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:360
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:919
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3417
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2196
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:689
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
TargetRegisterInfo.h
llvm::ISD::AVGFLOORS
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:643
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:51
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2269
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:353
llvm::LinearPolySize::coefficientNextPowerOf2
LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:370
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
llvm::MVT::VALUETYPE_SIZE
@ VALUETYPE_SIZE
Definition: MachineValueType.h:287
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1193
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:708
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:986
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:319
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1202
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:230
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393
llvm::LLT
Definition: LowLevelTypeImpl.h:39