LLVM  15.0.0git
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <cstring>
61 #include <iterator>
62 #include <string>
63 #include <tuple>
64 #include <utility>
65 
66 using namespace llvm;
67 
69  "jump-is-expensive", cl::init(false),
70  cl::desc("Do not create extra branches to split comparison logic."),
71  cl::Hidden);
72 
74  ("min-jump-table-entries", cl::init(4), cl::Hidden,
75  cl::desc("Set minimum number of entries to use a jump table."));
76 
78  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79  cl::desc("Set maximum size of jump tables."));
80 
81 /// Minimum jump table density for normal functions.
82 static cl::opt<unsigned>
83  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84  cl::desc("Minimum density for building a jump table in "
85  "a normal function"));
86 
87 /// Minimum jump table density for -Os or -Oz functions.
89  "optsize-jump-table-density", cl::init(40), cl::Hidden,
90  cl::desc("Minimum density for building a jump table in "
91  "an optsize function"));
92 
93 // FIXME: This option is only to test if the strict fp operation processed
94 // correctly by preventing mutating strict fp operation to normal fp operation
95 // during development. When the backend supports strict float operation, this
96 // option will be meaningless.
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98  cl::desc("Don't mutate strict-float node to a legalize node"),
99  cl::init(false), cl::Hidden);
100 
101 static bool darwinHasSinCos(const Triple &TT) {
102  assert(TT.isOSDarwin() && "should be called with darwin triple");
103  // Don't bother with 32 bit x86.
104  if (TT.getArch() == Triple::x86)
105  return false;
106  // Macos < 10.9 has no sincos_stret.
107  if (TT.isMacOSX())
108  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109  // iOS < 7.0 has no sincos_stret.
110  if (TT.isiOS())
111  return !TT.isOSVersionLT(7, 0);
112  // Any other darwin such as WatchOS/TvOS is new enough.
113  return true;
114 }
115 
116 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117 #define HANDLE_LIBCALL(code, name) \
118  setLibcallName(RTLIB::code, name);
119 #include "llvm/IR/RuntimeLibcalls.def"
120 #undef HANDLE_LIBCALL
121  // Initialize calling conventions to their default.
122  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 
125  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
126  if (TT.isPPC()) {
127  setLibcallName(RTLIB::ADD_F128, "__addkf3");
128  setLibcallName(RTLIB::SUB_F128, "__subkf3");
129  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
130  setLibcallName(RTLIB::DIV_F128, "__divkf3");
131  setLibcallName(RTLIB::POWI_F128, "__powikf2");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
139  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
140  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
142  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
143  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
144  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
145  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
146  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
147  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
148  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
149  setLibcallName(RTLIB::UNE_F128, "__nekf2");
150  setLibcallName(RTLIB::OGE_F128, "__gekf2");
151  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
152  setLibcallName(RTLIB::OLE_F128, "__lekf2");
153  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
154  setLibcallName(RTLIB::UO_F128, "__unordkf2");
155  }
156 
157  // A few names are different on particular architectures or environments.
158  if (TT.isOSDarwin()) {
159  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
160  // of the gnueabi-style __gnu_*_ieee.
161  // FIXME: What about other targets?
162  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
163  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
164 
165  // Some darwins have an optimized __bzero/bzero function.
166  switch (TT.getArch()) {
167  case Triple::x86:
168  case Triple::x86_64:
169  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
170  setLibcallName(RTLIB::BZERO, "__bzero");
171  break;
172  case Triple::aarch64:
173  case Triple::aarch64_32:
174  setLibcallName(RTLIB::BZERO, "bzero");
175  break;
176  default:
177  break;
178  }
179 
180  if (darwinHasSinCos(TT)) {
181  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
182  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
183  if (TT.isWatchABI()) {
184  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
186  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
188  }
189  }
190  } else {
191  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
192  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
193  }
194 
195  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
196  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
197  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
198  setLibcallName(RTLIB::SINCOS_F64, "sincos");
199  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
200  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
201  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
202  }
203 
204  if (TT.isPS4()) {
205  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
206  setLibcallName(RTLIB::SINCOS_F64, "sincos");
207  }
208 
209  if (TT.isOSOpenBSD()) {
210  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
211  }
212 }
213 
214 /// GetFPLibCall - Helper to return the right libcall for the given floating
215 /// point type, or UNKNOWN_LIBCALL if there is none.
217  RTLIB::Libcall Call_F32,
218  RTLIB::Libcall Call_F64,
219  RTLIB::Libcall Call_F80,
220  RTLIB::Libcall Call_F128,
221  RTLIB::Libcall Call_PPCF128) {
222  return
223  VT == MVT::f32 ? Call_F32 :
224  VT == MVT::f64 ? Call_F64 :
225  VT == MVT::f80 ? Call_F80 :
226  VT == MVT::f128 ? Call_F128 :
227  VT == MVT::ppcf128 ? Call_PPCF128 :
228  RTLIB::UNKNOWN_LIBCALL;
229 }
230 
231 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
234  if (OpVT == MVT::f16) {
235  if (RetVT == MVT::f32)
236  return FPEXT_F16_F32;
237  if (RetVT == MVT::f64)
238  return FPEXT_F16_F64;
239  if (RetVT == MVT::f80)
240  return FPEXT_F16_F80;
241  if (RetVT == MVT::f128)
242  return FPEXT_F16_F128;
243  } else if (OpVT == MVT::f32) {
244  if (RetVT == MVT::f64)
245  return FPEXT_F32_F64;
246  if (RetVT == MVT::f128)
247  return FPEXT_F32_F128;
248  if (RetVT == MVT::ppcf128)
249  return FPEXT_F32_PPCF128;
250  } else if (OpVT == MVT::f64) {
251  if (RetVT == MVT::f128)
252  return FPEXT_F64_F128;
253  else if (RetVT == MVT::ppcf128)
254  return FPEXT_F64_PPCF128;
255  } else if (OpVT == MVT::f80) {
256  if (RetVT == MVT::f128)
257  return FPEXT_F80_F128;
258  }
259 
260  return UNKNOWN_LIBCALL;
261 }
262 
263 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
264 /// UNKNOWN_LIBCALL if there is none.
266  if (RetVT == MVT::f16) {
267  if (OpVT == MVT::f32)
268  return FPROUND_F32_F16;
269  if (OpVT == MVT::f64)
270  return FPROUND_F64_F16;
271  if (OpVT == MVT::f80)
272  return FPROUND_F80_F16;
273  if (OpVT == MVT::f128)
274  return FPROUND_F128_F16;
275  if (OpVT == MVT::ppcf128)
276  return FPROUND_PPCF128_F16;
277  } else if (RetVT == MVT::f32) {
278  if (OpVT == MVT::f64)
279  return FPROUND_F64_F32;
280  if (OpVT == MVT::f80)
281  return FPROUND_F80_F32;
282  if (OpVT == MVT::f128)
283  return FPROUND_F128_F32;
284  if (OpVT == MVT::ppcf128)
285  return FPROUND_PPCF128_F32;
286  } else if (RetVT == MVT::f64) {
287  if (OpVT == MVT::f80)
288  return FPROUND_F80_F64;
289  if (OpVT == MVT::f128)
290  return FPROUND_F128_F64;
291  if (OpVT == MVT::ppcf128)
292  return FPROUND_PPCF128_F64;
293  } else if (RetVT == MVT::f80) {
294  if (OpVT == MVT::f128)
295  return FPROUND_F128_F80;
296  }
297 
298  return UNKNOWN_LIBCALL;
299 }
300 
301 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
302 /// UNKNOWN_LIBCALL if there is none.
304  if (OpVT == MVT::f16) {
305  if (RetVT == MVT::i32)
306  return FPTOSINT_F16_I32;
307  if (RetVT == MVT::i64)
308  return FPTOSINT_F16_I64;
309  if (RetVT == MVT::i128)
310  return FPTOSINT_F16_I128;
311  } else if (OpVT == MVT::f32) {
312  if (RetVT == MVT::i32)
313  return FPTOSINT_F32_I32;
314  if (RetVT == MVT::i64)
315  return FPTOSINT_F32_I64;
316  if (RetVT == MVT::i128)
317  return FPTOSINT_F32_I128;
318  } else if (OpVT == MVT::f64) {
319  if (RetVT == MVT::i32)
320  return FPTOSINT_F64_I32;
321  if (RetVT == MVT::i64)
322  return FPTOSINT_F64_I64;
323  if (RetVT == MVT::i128)
324  return FPTOSINT_F64_I128;
325  } else if (OpVT == MVT::f80) {
326  if (RetVT == MVT::i32)
327  return FPTOSINT_F80_I32;
328  if (RetVT == MVT::i64)
329  return FPTOSINT_F80_I64;
330  if (RetVT == MVT::i128)
331  return FPTOSINT_F80_I128;
332  } else if (OpVT == MVT::f128) {
333  if (RetVT == MVT::i32)
334  return FPTOSINT_F128_I32;
335  if (RetVT == MVT::i64)
336  return FPTOSINT_F128_I64;
337  if (RetVT == MVT::i128)
338  return FPTOSINT_F128_I128;
339  } else if (OpVT == MVT::ppcf128) {
340  if (RetVT == MVT::i32)
341  return FPTOSINT_PPCF128_I32;
342  if (RetVT == MVT::i64)
343  return FPTOSINT_PPCF128_I64;
344  if (RetVT == MVT::i128)
345  return FPTOSINT_PPCF128_I128;
346  }
347  return UNKNOWN_LIBCALL;
348 }
349 
350 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
351 /// UNKNOWN_LIBCALL if there is none.
353  if (OpVT == MVT::f16) {
354  if (RetVT == MVT::i32)
355  return FPTOUINT_F16_I32;
356  if (RetVT == MVT::i64)
357  return FPTOUINT_F16_I64;
358  if (RetVT == MVT::i128)
359  return FPTOUINT_F16_I128;
360  } else if (OpVT == MVT::f32) {
361  if (RetVT == MVT::i32)
362  return FPTOUINT_F32_I32;
363  if (RetVT == MVT::i64)
364  return FPTOUINT_F32_I64;
365  if (RetVT == MVT::i128)
366  return FPTOUINT_F32_I128;
367  } else if (OpVT == MVT::f64) {
368  if (RetVT == MVT::i32)
369  return FPTOUINT_F64_I32;
370  if (RetVT == MVT::i64)
371  return FPTOUINT_F64_I64;
372  if (RetVT == MVT::i128)
373  return FPTOUINT_F64_I128;
374  } else if (OpVT == MVT::f80) {
375  if (RetVT == MVT::i32)
376  return FPTOUINT_F80_I32;
377  if (RetVT == MVT::i64)
378  return FPTOUINT_F80_I64;
379  if (RetVT == MVT::i128)
380  return FPTOUINT_F80_I128;
381  } else if (OpVT == MVT::f128) {
382  if (RetVT == MVT::i32)
383  return FPTOUINT_F128_I32;
384  if (RetVT == MVT::i64)
385  return FPTOUINT_F128_I64;
386  if (RetVT == MVT::i128)
387  return FPTOUINT_F128_I128;
388  } else if (OpVT == MVT::ppcf128) {
389  if (RetVT == MVT::i32)
390  return FPTOUINT_PPCF128_I32;
391  if (RetVT == MVT::i64)
392  return FPTOUINT_PPCF128_I64;
393  if (RetVT == MVT::i128)
394  return FPTOUINT_PPCF128_I128;
395  }
396  return UNKNOWN_LIBCALL;
397 }
398 
399 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
400 /// UNKNOWN_LIBCALL if there is none.
402  if (OpVT == MVT::i32) {
403  if (RetVT == MVT::f16)
404  return SINTTOFP_I32_F16;
405  if (RetVT == MVT::f32)
406  return SINTTOFP_I32_F32;
407  if (RetVT == MVT::f64)
408  return SINTTOFP_I32_F64;
409  if (RetVT == MVT::f80)
410  return SINTTOFP_I32_F80;
411  if (RetVT == MVT::f128)
412  return SINTTOFP_I32_F128;
413  if (RetVT == MVT::ppcf128)
414  return SINTTOFP_I32_PPCF128;
415  } else if (OpVT == MVT::i64) {
416  if (RetVT == MVT::f16)
417  return SINTTOFP_I64_F16;
418  if (RetVT == MVT::f32)
419  return SINTTOFP_I64_F32;
420  if (RetVT == MVT::f64)
421  return SINTTOFP_I64_F64;
422  if (RetVT == MVT::f80)
423  return SINTTOFP_I64_F80;
424  if (RetVT == MVT::f128)
425  return SINTTOFP_I64_F128;
426  if (RetVT == MVT::ppcf128)
427  return SINTTOFP_I64_PPCF128;
428  } else if (OpVT == MVT::i128) {
429  if (RetVT == MVT::f16)
430  return SINTTOFP_I128_F16;
431  if (RetVT == MVT::f32)
432  return SINTTOFP_I128_F32;
433  if (RetVT == MVT::f64)
434  return SINTTOFP_I128_F64;
435  if (RetVT == MVT::f80)
436  return SINTTOFP_I128_F80;
437  if (RetVT == MVT::f128)
438  return SINTTOFP_I128_F128;
439  if (RetVT == MVT::ppcf128)
440  return SINTTOFP_I128_PPCF128;
441  }
442  return UNKNOWN_LIBCALL;
443 }
444 
445 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
446 /// UNKNOWN_LIBCALL if there is none.
448  if (OpVT == MVT::i32) {
449  if (RetVT == MVT::f16)
450  return UINTTOFP_I32_F16;
451  if (RetVT == MVT::f32)
452  return UINTTOFP_I32_F32;
453  if (RetVT == MVT::f64)
454  return UINTTOFP_I32_F64;
455  if (RetVT == MVT::f80)
456  return UINTTOFP_I32_F80;
457  if (RetVT == MVT::f128)
458  return UINTTOFP_I32_F128;
459  if (RetVT == MVT::ppcf128)
460  return UINTTOFP_I32_PPCF128;
461  } else if (OpVT == MVT::i64) {
462  if (RetVT == MVT::f16)
463  return UINTTOFP_I64_F16;
464  if (RetVT == MVT::f32)
465  return UINTTOFP_I64_F32;
466  if (RetVT == MVT::f64)
467  return UINTTOFP_I64_F64;
468  if (RetVT == MVT::f80)
469  return UINTTOFP_I64_F80;
470  if (RetVT == MVT::f128)
471  return UINTTOFP_I64_F128;
472  if (RetVT == MVT::ppcf128)
473  return UINTTOFP_I64_PPCF128;
474  } else if (OpVT == MVT::i128) {
475  if (RetVT == MVT::f16)
476  return UINTTOFP_I128_F16;
477  if (RetVT == MVT::f32)
478  return UINTTOFP_I128_F32;
479  if (RetVT == MVT::f64)
480  return UINTTOFP_I128_F64;
481  if (RetVT == MVT::f80)
482  return UINTTOFP_I128_F80;
483  if (RetVT == MVT::f128)
484  return UINTTOFP_I128_F128;
485  if (RetVT == MVT::ppcf128)
486  return UINTTOFP_I128_PPCF128;
487  }
488  return UNKNOWN_LIBCALL;
489 }
490 
492  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
493  POWI_PPCF128);
494 }
495 
497  MVT VT) {
498  unsigned ModeN, ModelN;
499  switch (VT.SimpleTy) {
500  case MVT::i8:
501  ModeN = 0;
502  break;
503  case MVT::i16:
504  ModeN = 1;
505  break;
506  case MVT::i32:
507  ModeN = 2;
508  break;
509  case MVT::i64:
510  ModeN = 3;
511  break;
512  case MVT::i128:
513  ModeN = 4;
514  break;
515  default:
516  return UNKNOWN_LIBCALL;
517  }
518 
519  switch (Order) {
521  ModelN = 0;
522  break;
524  ModelN = 1;
525  break;
527  ModelN = 2;
528  break;
531  ModelN = 3;
532  break;
533  default:
534  return UNKNOWN_LIBCALL;
535  }
536 
537 #define LCALLS(A, B) \
538  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
539 #define LCALL5(A) \
540  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
541  switch (Opc) {
542  case ISD::ATOMIC_CMP_SWAP: {
543  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
544  return LC[ModeN][ModelN];
545  }
546  case ISD::ATOMIC_SWAP: {
547  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
548  return LC[ModeN][ModelN];
549  }
550  case ISD::ATOMIC_LOAD_ADD: {
551  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
552  return LC[ModeN][ModelN];
553  }
554  case ISD::ATOMIC_LOAD_OR: {
555  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
556  return LC[ModeN][ModelN];
557  }
558  case ISD::ATOMIC_LOAD_CLR: {
559  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
560  return LC[ModeN][ModelN];
561  }
562  case ISD::ATOMIC_LOAD_XOR: {
563  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
564  return LC[ModeN][ModelN];
565  }
566  default:
567  return UNKNOWN_LIBCALL;
568  }
569 #undef LCALLS
570 #undef LCALL5
571 }
572 
573 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
574 #define OP_TO_LIBCALL(Name, Enum) \
575  case Name: \
576  switch (VT.SimpleTy) { \
577  default: \
578  return UNKNOWN_LIBCALL; \
579  case MVT::i8: \
580  return Enum##_1; \
581  case MVT::i16: \
582  return Enum##_2; \
583  case MVT::i32: \
584  return Enum##_4; \
585  case MVT::i64: \
586  return Enum##_8; \
587  case MVT::i128: \
588  return Enum##_16; \
589  }
590 
591  switch (Opc) {
592  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
593  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
594  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
595  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
596  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
597  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
598  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
599  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
600  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
601  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
602  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
603  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
604  }
605 
606 #undef OP_TO_LIBCALL
607 
608  return UNKNOWN_LIBCALL;
609 }
610 
612  switch (ElementSize) {
613  case 1:
614  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
615  case 2:
616  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
617  case 4:
618  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
619  case 8:
620  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
621  case 16:
622  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
623  default:
624  return UNKNOWN_LIBCALL;
625  }
626 }
627 
629  switch (ElementSize) {
630  case 1:
631  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
632  case 2:
633  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
634  case 4:
635  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
636  case 8:
637  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
638  case 16:
639  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
640  default:
641  return UNKNOWN_LIBCALL;
642  }
643 }
644 
646  switch (ElementSize) {
647  case 1:
648  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
649  case 2:
650  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
651  case 4:
652  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
653  case 8:
654  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
655  case 16:
656  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
657  default:
658  return UNKNOWN_LIBCALL;
659  }
660 }
661 
662 /// InitCmpLibcallCCs - Set default comparison libcall CC.
663 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
664  std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
665  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
666  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
667  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
668  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
669  CCs[RTLIB::UNE_F32] = ISD::SETNE;
670  CCs[RTLIB::UNE_F64] = ISD::SETNE;
671  CCs[RTLIB::UNE_F128] = ISD::SETNE;
672  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
673  CCs[RTLIB::OGE_F32] = ISD::SETGE;
674  CCs[RTLIB::OGE_F64] = ISD::SETGE;
675  CCs[RTLIB::OGE_F128] = ISD::SETGE;
676  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
677  CCs[RTLIB::OLT_F32] = ISD::SETLT;
678  CCs[RTLIB::OLT_F64] = ISD::SETLT;
679  CCs[RTLIB::OLT_F128] = ISD::SETLT;
680  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
681  CCs[RTLIB::OLE_F32] = ISD::SETLE;
682  CCs[RTLIB::OLE_F64] = ISD::SETLE;
683  CCs[RTLIB::OLE_F128] = ISD::SETLE;
684  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
685  CCs[RTLIB::OGT_F32] = ISD::SETGT;
686  CCs[RTLIB::OGT_F64] = ISD::SETGT;
687  CCs[RTLIB::OGT_F128] = ISD::SETGT;
688  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
689  CCs[RTLIB::UO_F32] = ISD::SETNE;
690  CCs[RTLIB::UO_F64] = ISD::SETNE;
691  CCs[RTLIB::UO_F128] = ISD::SETNE;
692  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
693 }
694 
695 /// NOTE: The TargetMachine owns TLOF.
697  initActions();
698 
699  // Perform these initializations only once.
701  MaxLoadsPerMemcmp = 8;
705  HasMultipleConditionRegisters = false;
706  HasExtractBitsInsn = false;
707  JumpIsExpensive = JumpIsExpensiveOverride;
709  EnableExtLdPromotion = false;
710  StackPointerRegisterToSaveRestore = 0;
711  BooleanContents = UndefinedBooleanContent;
712  BooleanFloatContents = UndefinedBooleanContent;
713  BooleanVectorContents = UndefinedBooleanContent;
714  SchedPreferenceInfo = Sched::ILP;
717  MaxBytesForAlignment = 0;
718  // TODO: the default will be switched to 0 in the next commit, along
719  // with the Target-specific changes necessary.
720  MaxAtomicSizeInBitsSupported = 1024;
721 
722  MinCmpXchgSizeInBits = 0;
723  SupportsUnalignedAtomics = false;
724 
725  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
726 
727  InitLibcalls(TM.getTargetTriple());
728  InitCmpLibcallCCs(CmpLibcallCCs);
729 }
730 
732  // All operations default to being supported.
733  memset(OpActions, 0, sizeof(OpActions));
734  memset(LoadExtActions, 0, sizeof(LoadExtActions));
735  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
736  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
737  memset(CondCodeActions, 0, sizeof(CondCodeActions));
738  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
739  std::fill(std::begin(TargetDAGCombineArray),
740  std::end(TargetDAGCombineArray), 0);
741 
742  for (MVT VT : MVT::fp_valuetypes()) {
743  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
744  if (IntVT.isValid()) {
747  }
748  }
749 
750  // Set default actions for various operations.
751  for (MVT VT : MVT::all_valuetypes()) {
752  // Default all indexed load / store to expand.
753  for (unsigned IM = (unsigned)ISD::PRE_INC;
754  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
755  setIndexedLoadAction(IM, VT, Expand);
756  setIndexedStoreAction(IM, VT, Expand);
759  }
760 
761  // Most backends expect to see the node which just returns the value loaded.
763 
764  // These operations default to expand.
782  VT, Expand);
783 
784  // Overflow operations default to expand
787  VT, Expand);
788 
789  // ADDCARRY operations default to expand
792  VT, Expand);
793 
794  // ADDC/ADDE/SUBC/SUBE default to expand.
796  Expand);
797 
798  // Halving adds
801  Expand);
802 
803  // Absolute difference
805 
806  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
808  Expand);
809 
811 
812  // These library functions default to expand.
814 
815  // These operations default to expand for vector types.
816  if (VT.isVector())
821  VT, Expand);
822 
823  // Constrained floating-point operations default to expand.
824 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
825  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
826 #include "llvm/IR/ConstrainedOps.def"
827 
828  // For most targets @llvm.get.dynamic.area.offset just returns 0.
830 
831  // Vector reduction default to expand.
838  VT, Expand);
839 
840  // Named vector shuffles default to expand.
842  }
843 
844  // Most targets ignore the @llvm.prefetch intrinsic.
846 
847  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
849 
850  // ConstantFP nodes default to expand. Targets can either change this to
851  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
852  // to optimize expansions for certain constants.
855  Expand);
856 
857  // These library functions default to expand.
863 
864  // Default ISD::TRAP to expand (which turns it into abort).
866 
867  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
868  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
870 
872 }
873 
875  EVT) const {
876  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
877 }
878 
880  bool LegalTypes) const {
881  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
882  if (LHSTy.isVector())
883  return LHSTy;
884  MVT ShiftVT =
885  LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
886  // If any possible shift value won't fit in the prefered type, just use
887  // something safe. Assume it will be legalized when the shift is expanded.
888  if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
889  ShiftVT = MVT::i32;
890  assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
891  "ShiftVT is still too small!");
892  return ShiftVT;
893 }
894 
895 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
896  assert(isTypeLegal(VT));
897  switch (Op) {
898  default:
899  return false;
900  case ISD::SDIV:
901  case ISD::UDIV:
902  case ISD::SREM:
903  case ISD::UREM:
904  return true;
905  }
906 }
907 
909  unsigned DestAS) const {
910  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
911 }
912 
914  // If the command-line option was specified, ignore this request.
916  JumpIsExpensive = isExpensive;
917 }
918 
920 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
921  // If this is a simple type, use the ComputeRegisterProp mechanism.
922  if (VT.isSimple()) {
923  MVT SVT = VT.getSimpleVT();
924  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
925  MVT NVT = TransformToType[SVT.SimpleTy];
926  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
927 
928  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
929  LA == TypeSoftPromoteHalf ||
930  (NVT.isVector() ||
931  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
932  "Promote may not follow Expand or Promote");
933 
934  if (LA == TypeSplitVector)
935  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
936  if (LA == TypeScalarizeVector)
937  return LegalizeKind(LA, SVT.getVectorElementType());
938  return LegalizeKind(LA, NVT);
939  }
940 
941  // Handle Extended Scalar Types.
942  if (!VT.isVector()) {
943  assert(VT.isInteger() && "Float types must be simple");
944  unsigned BitSize = VT.getSizeInBits();
945  // First promote to a power-of-two size, then expand if necessary.
946  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
947  EVT NVT = VT.getRoundIntegerType(Context);
948  assert(NVT != VT && "Unable to round integer VT");
949  LegalizeKind NextStep = getTypeConversion(Context, NVT);
950  // Avoid multi-step promotion.
951  if (NextStep.first == TypePromoteInteger)
952  return NextStep;
953  // Return rounded integer type.
954  return LegalizeKind(TypePromoteInteger, NVT);
955  }
956 
959  }
960 
961  // Handle vector types.
962  ElementCount NumElts = VT.getVectorElementCount();
963  EVT EltVT = VT.getVectorElementType();
964 
965  // Vectors with only one element are always scalarized.
966  if (NumElts.isScalar())
967  return LegalizeKind(TypeScalarizeVector, EltVT);
968 
969  // Try to widen vector elements until the element type is a power of two and
970  // promote it to a legal type later on, for example:
971  // <3 x i8> -> <4 x i8> -> <4 x i32>
972  if (EltVT.isInteger()) {
973  // Vectors with a number of elements that is not a power of two are always
974  // widened, for example <3 x i8> -> <4 x i8>.
975  if (!VT.isPow2VectorType()) {
976  NumElts = NumElts.coefficientNextPowerOf2();
977  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
978  return LegalizeKind(TypeWidenVector, NVT);
979  }
980 
981  // Examine the element type.
982  LegalizeKind LK = getTypeConversion(Context, EltVT);
983 
984  // If type is to be expanded, split the vector.
985  // <4 x i140> -> <2 x i140>
986  if (LK.first == TypeExpandInteger) {
991  }
992 
993  // Promote the integer element types until a legal vector type is found
994  // or until the element integer type is too big. If a legal type was not
995  // found, fallback to the usual mechanism of widening/splitting the
996  // vector.
997  EVT OldEltVT = EltVT;
998  while (true) {
999  // Increase the bitwidth of the element to the next pow-of-two
1000  // (which is greater than 8 bits).
1001  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1003 
1004  // Stop trying when getting a non-simple element type.
1005  // Note that vector elements may be greater than legal vector element
1006  // types. Example: X86 XMM registers hold 64bit element on 32bit
1007  // systems.
1008  if (!EltVT.isSimple())
1009  break;
1010 
1011  // Build a new vector type and check if it is legal.
1012  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1013  // Found a legal promoted vector type.
1014  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1016  EVT::getVectorVT(Context, EltVT, NumElts));
1017  }
1018 
1019  // Reset the type to the unexpanded type if we did not find a legal vector
1020  // type with a promoted vector element type.
1021  EltVT = OldEltVT;
1022  }
1023 
1024  // Try to widen the vector until a legal type is found.
1025  // If there is no wider legal type, split the vector.
1026  while (true) {
1027  // Round up to the next power of 2.
1028  NumElts = NumElts.coefficientNextPowerOf2();
1029 
1030  // If there is no simple vector type with this many elements then there
1031  // cannot be a larger legal vector type. Note that this assumes that
1032  // there are no skipped intermediate vector types in the simple types.
1033  if (!EltVT.isSimple())
1034  break;
1035  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1036  if (LargerVector == MVT())
1037  break;
1038 
1039  // If this type is legal then widen the vector.
1040  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1041  return LegalizeKind(TypeWidenVector, LargerVector);
1042  }
1043 
1044  // Widen odd vectors to next power of two.
1045  if (!VT.isPow2VectorType()) {
1046  EVT NVT = VT.getPow2VectorType(Context);
1047  return LegalizeKind(TypeWidenVector, NVT);
1048  }
1049 
1052 
1053  // Vectors with illegal element types are expanded.
1054  EVT NVT = EVT::getVectorVT(Context, EltVT,
1056  return LegalizeKind(TypeSplitVector, NVT);
1057 }
1058 
1059 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1060  unsigned &NumIntermediates,
1061  MVT &RegisterVT,
1062  TargetLoweringBase *TLI) {
1063  // Figure out the right, legal destination reg to copy into.
1065  MVT EltTy = VT.getVectorElementType();
1066 
1067  unsigned NumVectorRegs = 1;
1068 
1069  // Scalable vectors cannot be scalarized, so splitting or widening is
1070  // required.
1071  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1073  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1074 
1075  // FIXME: We don't support non-power-of-2-sized vectors for now.
1076  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1077  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1078  // Split EC to unit size (scalable property is preserved).
1079  NumVectorRegs = EC.getKnownMinValue();
1080  EC = ElementCount::getFixed(1);
1081  }
1082 
1083  // Divide the input until we get to a supported size. This will
1084  // always end up with an EC that represent a scalar or a scalable
1085  // scalar.
1086  while (EC.getKnownMinValue() > 1 &&
1087  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1088  EC = EC.divideCoefficientBy(2);
1089  NumVectorRegs <<= 1;
1090  }
1091 
1092  NumIntermediates = NumVectorRegs;
1093 
1094  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1095  if (!TLI->isTypeLegal(NewVT))
1096  NewVT = EltTy;
1097  IntermediateVT = NewVT;
1098 
1099  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1100 
1101  // Convert sizes such as i33 to i64.
1102  if (!isPowerOf2_32(LaneSizeInBits))
1103  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1104 
1105  MVT DestVT = TLI->getRegisterType(NewVT);
1106  RegisterVT = DestVT;
1107  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1108  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1109 
1110  // Otherwise, promotion or legal types use the same number of registers as
1111  // the vector decimated to the appropriate level.
1112  return NumVectorRegs;
1113 }
1114 
1115 /// isLegalRC - Return true if the value types that can be represented by the
1116 /// specified register class are all legal.
1118  const TargetRegisterClass &RC) const {
1119  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1120  if (isTypeLegal(*I))
1121  return true;
1122  return false;
1123 }
1124 
1125 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1126 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1129  MachineBasicBlock *MBB) const {
1130  MachineInstr *MI = &InitialMI;
1131  MachineFunction &MF = *MI->getMF();
1132  MachineFrameInfo &MFI = MF.getFrameInfo();
1133 
1134  // We're handling multiple types of operands here:
1135  // PATCHPOINT MetaArgs - live-in, read only, direct
1136  // STATEPOINT Deopt Spill - live-through, read only, indirect
1137  // STATEPOINT Deopt Alloca - live-through, read only, direct
1138  // (We're currently conservative and mark the deopt slots read/write in
1139  // practice.)
1140  // STATEPOINT GC Spill - live-through, read/write, indirect
1141  // STATEPOINT GC Alloca - live-through, read/write, direct
1142  // The live-in vs live-through is handled already (the live through ones are
1143  // all stack slots), but we need to handle the different type of stackmap
1144  // operands and memory effects here.
1145 
1146  if (llvm::none_of(MI->operands(),
1147  [](MachineOperand &Operand) { return Operand.isFI(); }))
1148  return MBB;
1149 
1150  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1151 
1152  // Inherit previous memory operands.
1153  MIB.cloneMemRefs(*MI);
1154 
1155  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1156  MachineOperand &MO = MI->getOperand(i);
1157  if (!MO.isFI()) {
1158  // Index of Def operand this Use it tied to.
1159  // Since Defs are coming before Uses, if Use is tied, then
1160  // index of Def must be smaller that index of that Use.
1161  // Also, Defs preserve their position in new MI.
1162  unsigned TiedTo = i;
1163  if (MO.isReg() && MO.isTied())
1164  TiedTo = MI->findTiedOperandIdx(i);
1165  MIB.add(MO);
1166  if (TiedTo < i)
1167  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1168  continue;
1169  }
1170 
1171  // foldMemoryOperand builds a new MI after replacing a single FI operand
1172  // with the canonical set of five x86 addressing-mode operands.
1173  int FI = MO.getIndex();
1174 
1175  // Add frame index operands recognized by stackmaps.cpp
1176  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1177  // indirect-mem-ref tag, size, #FI, offset.
1178  // Used for spills inserted by StatepointLowering. This codepath is not
1179  // used for patchpoints/stackmaps at all, for these spilling is done via
1180  // foldMemoryOperand callback only.
1181  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1182  MIB.addImm(StackMaps::IndirectMemRefOp);
1183  MIB.addImm(MFI.getObjectSize(FI));
1184  MIB.add(MO);
1185  MIB.addImm(0);
1186  } else {
1187  // direct-mem-ref tag, #FI, offset.
1188  // Used by patchpoint, and direct alloca arguments to statepoints
1189  MIB.addImm(StackMaps::DirectMemRefOp);
1190  MIB.add(MO);
1191  MIB.addImm(0);
1192  }
1193 
1194  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1195 
1196  // Add a new memory operand for this FI.
1197  assert(MFI.getObjectOffset(FI) != -1);
1198 
1199  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1200  // PATCHPOINT should be updated to do the same. (TODO)
1201  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1202  auto Flags = MachineMemOperand::MOLoad;
1204  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1205  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1206  MIB->addMemOperand(MF, MMO);
1207  }
1208  }
1210  MI->eraseFromParent();
1211  return MBB;
1212 }
1213 
1214 /// findRepresentativeClass - Return the largest legal super-reg register class
1215 /// of the register class for the specified type and its associated "cost".
1216 // This function is in TargetLowering because it uses RegClassForVT which would
1217 // need to be moved to TargetRegisterInfo and would necessitate moving
1218 // isTypeLegal over as well - a massive change that would just require
1219 // TargetLowering having a TargetRegisterInfo class member that it would use.
1220 std::pair<const TargetRegisterClass *, uint8_t>
1222  MVT VT) const {
1223  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1224  if (!RC)
1225  return std::make_pair(RC, 0);
1226 
1227  // Compute the set of all super-register classes.
1228  BitVector SuperRegRC(TRI->getNumRegClasses());
1229  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1230  SuperRegRC.setBitsInMask(RCI.getMask());
1231 
1232  // Find the first legal register class with the largest spill size.
1233  const TargetRegisterClass *BestRC = RC;
1234  for (unsigned i : SuperRegRC.set_bits()) {
1235  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1236  // We want the largest possible spill size.
1237  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1238  continue;
1239  if (!isLegalRC(*TRI, *SuperRC))
1240  continue;
1241  BestRC = SuperRC;
1242  }
1243  return std::make_pair(BestRC, 1);
1244 }
1245 
1246 /// computeRegisterProperties - Once all of the register classes are added,
1247 /// this allows us to compute derived properties we expose.
1249  const TargetRegisterInfo *TRI) {
1251  "Too many value types for ValueTypeActions to hold!");
1252 
1253  // Everything defaults to needing one register.
1254  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1255  NumRegistersForVT[i] = 1;
1256  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1257  }
1258  // ...except isVoid, which doesn't need any registers.
1259  NumRegistersForVT[MVT::isVoid] = 0;
1260 
1261  // Find the largest integer register class.
1262  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1263  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1264  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1265 
1266  // Every integer value type larger than this largest register takes twice as
1267  // many registers to represent as the previous ValueType.
1268  for (unsigned ExpandedReg = LargestIntReg + 1;
1269  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1270  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1271  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1272  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1273  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1275  }
1276 
1277  // Inspect all of the ValueType's smaller than the largest integer
1278  // register to see which ones need promotion.
1279  unsigned LegalIntReg = LargestIntReg;
1280  for (unsigned IntReg = LargestIntReg - 1;
1281  IntReg >= (unsigned)MVT::i1; --IntReg) {
1282  MVT IVT = (MVT::SimpleValueType)IntReg;
1283  if (isTypeLegal(IVT)) {
1284  LegalIntReg = IntReg;
1285  } else {
1286  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1287  (MVT::SimpleValueType)LegalIntReg;
1288  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1289  }
1290  }
1291 
1292  // ppcf128 type is really two f64's.
1293  if (!isTypeLegal(MVT::ppcf128)) {
1294  if (isTypeLegal(MVT::f64)) {
1295  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1296  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1297  TransformToType[MVT::ppcf128] = MVT::f64;
1298  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1299  } else {
1300  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1301  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1302  TransformToType[MVT::ppcf128] = MVT::i128;
1303  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1304  }
1305  }
1306 
1307  // Decide how to handle f128. If the target does not have native f128 support,
1308  // expand it to i128 and we will be generating soft float library calls.
1309  if (!isTypeLegal(MVT::f128)) {
1310  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1311  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1312  TransformToType[MVT::f128] = MVT::i128;
1313  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1314  }
1315 
1316  // Decide how to handle f64. If the target does not have native f64 support,
1317  // expand it to i64 and we will be generating soft float library calls.
1318  if (!isTypeLegal(MVT::f64)) {
1319  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1320  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1321  TransformToType[MVT::f64] = MVT::i64;
1322  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1323  }
1324 
1325  // Decide how to handle f32. If the target does not have native f32 support,
1326  // expand it to i32 and we will be generating soft float library calls.
1327  if (!isTypeLegal(MVT::f32)) {
1328  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1329  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1330  TransformToType[MVT::f32] = MVT::i32;
1331  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1332  }
1333 
1334  // Decide how to handle f16. If the target does not have native f16 support,
1335  // promote it to f32, because there are no f16 library calls (except for
1336  // conversions).
1337  if (!isTypeLegal(MVT::f16)) {
1338  // Allow targets to control how we legalize half.
1339  if (softPromoteHalfType()) {
1340  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1341  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1342  TransformToType[MVT::f16] = MVT::f32;
1343  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1344  } else {
1345  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1346  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1347  TransformToType[MVT::f16] = MVT::f32;
1348  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1349  }
1350  }
1351 
1352  // Loop over all of the vector value types to see which need transformations.
1353  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1354  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1355  MVT VT = (MVT::SimpleValueType) i;
1356  if (isTypeLegal(VT))
1357  continue;
1358 
1359  MVT EltVT = VT.getVectorElementType();
1361  bool IsLegalWiderType = false;
1362  bool IsScalable = VT.isScalableVector();
1363  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1364  switch (PreferredAction) {
1365  case TypePromoteInteger: {
1366  MVT::SimpleValueType EndVT = IsScalable ?
1369  // Try to promote the elements of integer vectors. If no legal
1370  // promotion was found, fall through to the widen-vector method.
1371  for (unsigned nVT = i + 1;
1372  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1373  MVT SVT = (MVT::SimpleValueType) nVT;
1374  // Promote vectors of integers to vectors with the same number
1375  // of elements, with a wider element type.
1376  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1377  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1378  TransformToType[i] = SVT;
1379  RegisterTypeForVT[i] = SVT;
1380  NumRegistersForVT[i] = 1;
1381  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1382  IsLegalWiderType = true;
1383  break;
1384  }
1385  }
1386  if (IsLegalWiderType)
1387  break;
1389  }
1390 
1391  case TypeWidenVector:
1392  if (isPowerOf2_32(EC.getKnownMinValue())) {
1393  // Try to widen the vector.
1394  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1395  MVT SVT = (MVT::SimpleValueType) nVT;
1396  if (SVT.getVectorElementType() == EltVT &&
1397  SVT.isScalableVector() == IsScalable &&
1399  EC.getKnownMinValue() &&
1400  isTypeLegal(SVT)) {
1401  TransformToType[i] = SVT;
1402  RegisterTypeForVT[i] = SVT;
1403  NumRegistersForVT[i] = 1;
1404  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1405  IsLegalWiderType = true;
1406  break;
1407  }
1408  }
1409  if (IsLegalWiderType)
1410  break;
1411  } else {
1412  // Only widen to the next power of 2 to keep consistency with EVT.
1413  MVT NVT = VT.getPow2VectorType();
1414  if (isTypeLegal(NVT)) {
1415  TransformToType[i] = NVT;
1416  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1417  RegisterTypeForVT[i] = NVT;
1418  NumRegistersForVT[i] = 1;
1419  break;
1420  }
1421  }
1423 
1424  case TypeSplitVector:
1425  case TypeScalarizeVector: {
1426  MVT IntermediateVT;
1427  MVT RegisterVT;
1428  unsigned NumIntermediates;
1429  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1430  NumIntermediates, RegisterVT, this);
1431  NumRegistersForVT[i] = NumRegisters;
1432  assert(NumRegistersForVT[i] == NumRegisters &&
1433  "NumRegistersForVT size cannot represent NumRegisters!");
1434  RegisterTypeForVT[i] = RegisterVT;
1435 
1436  MVT NVT = VT.getPow2VectorType();
1437  if (NVT == VT) {
1438  // Type is already a power of 2. The default action is to split.
1439  TransformToType[i] = MVT::Other;
1440  if (PreferredAction == TypeScalarizeVector)
1441  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1442  else if (PreferredAction == TypeSplitVector)
1443  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1444  else if (EC.getKnownMinValue() > 1)
1445  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1446  else
1447  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1450  } else {
1451  TransformToType[i] = NVT;
1452  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1453  }
1454  break;
1455  }
1456  default:
1457  llvm_unreachable("Unknown vector legalization action!");
1458  }
1459  }
1460 
1461  // Determine the 'representative' register class for each value type.
1462  // An representative register class is the largest (meaning one which is
1463  // not a sub-register class / subreg register class) legal register class for
1464  // a group of value types. For example, on i386, i8, i16, and i32
1465  // representative would be GR32; while on x86_64 it's GR64.
1466  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1467  const TargetRegisterClass* RRC;
1468  uint8_t Cost;
1469  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1470  RepRegClassForVT[i] = RRC;
1471  RepRegClassCostForVT[i] = Cost;
1472  }
1473 }
1474 
1476  EVT VT) const {
1477  assert(!VT.isVector() && "No default SetCC type for vectors!");
1478  return getPointerTy(DL).SimpleTy;
1479 }
1480 
1482  return MVT::i32; // return the default value
1483 }
1484 
1485 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1486 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1487 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1488 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1489 ///
1490 /// This method returns the number of registers needed, and the VT for each
1491 /// register. It also returns the VT and quantity of the intermediate values
1492 /// before they are promoted/expanded.
1494  EVT VT, EVT &IntermediateVT,
1495  unsigned &NumIntermediates,
1496  MVT &RegisterVT) const {
1497  ElementCount EltCnt = VT.getVectorElementCount();
1498 
1499  // If there is a wider vector type with the same element type as this one,
1500  // or a promoted vector type that has the same number of elements which
1501  // are wider, then we should convert to that legal vector type.
1502  // This handles things like <2 x float> -> <4 x float> and
1503  // <4 x i1> -> <4 x i32>.
1505  if (!EltCnt.isScalar() &&
1506  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1507  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1508  if (isTypeLegal(RegisterEVT)) {
1509  IntermediateVT = RegisterEVT;
1510  RegisterVT = RegisterEVT.getSimpleVT();
1511  NumIntermediates = 1;
1512  return 1;
1513  }
1514  }
1515 
1516  // Figure out the right, legal destination reg to copy into.
1517  EVT EltTy = VT.getVectorElementType();
1518 
1519  unsigned NumVectorRegs = 1;
1520 
1521  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1522  // types like done elsewhere in SelectionDAG.
1523  if (EltCnt.isScalable()) {
1524  LegalizeKind LK;
1525  EVT PartVT = VT;
1526  do {
1527  // Iterate until we've found a legal (part) type to hold VT.
1528  LK = getTypeConversion(Context, PartVT);
1529  PartVT = LK.second;
1530  } while (LK.first != TypeLegal);
1531 
1532  if (!PartVT.isVector()) {
1534  "Don't know how to legalize this scalable vector type");
1535  }
1536 
1537  NumIntermediates =
1540  IntermediateVT = PartVT;
1541  RegisterVT = getRegisterType(Context, IntermediateVT);
1542  return NumIntermediates;
1543  }
1544 
1545  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1546  // we could break down into LHS/RHS like LegalizeDAG does.
1547  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1548  NumVectorRegs = EltCnt.getKnownMinValue();
1549  EltCnt = ElementCount::getFixed(1);
1550  }
1551 
1552  // Divide the input until we get to a supported size. This will always
1553  // end with a scalar if the target doesn't support vectors.
1554  while (EltCnt.getKnownMinValue() > 1 &&
1555  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1556  EltCnt = EltCnt.divideCoefficientBy(2);
1557  NumVectorRegs <<= 1;
1558  }
1559 
1560  NumIntermediates = NumVectorRegs;
1561 
1562  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1563  if (!isTypeLegal(NewVT))
1564  NewVT = EltTy;
1565  IntermediateVT = NewVT;
1566 
1567  MVT DestVT = getRegisterType(Context, NewVT);
1568  RegisterVT = DestVT;
1569 
1570  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1571  TypeSize NewVTSize = NewVT.getSizeInBits();
1572  // Convert sizes such as i33 to i64.
1573  if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
1574  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1575  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1576  }
1577 
1578  // Otherwise, promotion or legal types use the same number of registers as
1579  // the vector decimated to the appropriate level.
1580  return NumVectorRegs;
1581 }
1582 
1584  uint64_t NumCases,
1585  uint64_t Range,
1586  ProfileSummaryInfo *PSI,
1587  BlockFrequencyInfo *BFI) const {
1588  // FIXME: This function check the maximum table size and density, but the
1589  // minimum size is not checked. It would be nice if the minimum size is
1590  // also combined within this function. Currently, the minimum size check is
1591  // performed in findJumpTable() in SelectionDAGBuiler and
1592  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1593  const bool OptForSize =
1594  SI->getParent()->getParent()->hasOptSize() ||
1595  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1596  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1597  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1598 
1599  // Check whether the number of cases is small enough and
1600  // the range is dense enough for a jump table.
1601  return (OptForSize || Range <= MaxJumpTableSize) &&
1602  (NumCases * 100 >= Range * MinDensity);
1603 }
1604 
1606  EVT ConditionVT) const {
1607  return getRegisterType(Context, ConditionVT);
1608 }
1609 
1610 /// Get the EVTs and ArgFlags collections that represent the legalized return
1611 /// type of the given function. This does not require a DAG or a return value,
1612 /// and is suitable for use before any DAGs for the function are constructed.
1613 /// TODO: Move this out of TargetLowering.cpp.
1615  AttributeList attr,
1617  const TargetLowering &TLI, const DataLayout &DL) {
1618  SmallVector<EVT, 4> ValueVTs;
1619  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1620  unsigned NumValues = ValueVTs.size();
1621  if (NumValues == 0) return;
1622 
1623  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1624  EVT VT = ValueVTs[j];
1625  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1626 
1627  if (attr.hasRetAttr(Attribute::SExt))
1628  ExtendKind = ISD::SIGN_EXTEND;
1629  else if (attr.hasRetAttr(Attribute::ZExt))
1630  ExtendKind = ISD::ZERO_EXTEND;
1631 
1632  // FIXME: C calling convention requires the return type to be promoted to
1633  // at least 32-bit. But this is not necessary for non-C calling
1634  // conventions. The frontend should mark functions whose return values
1635  // require promoting with signext or zeroext attributes.
1636  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1637  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1638  if (VT.bitsLT(MinVT))
1639  VT = MinVT;
1640  }
1641 
1642  unsigned NumParts =
1643  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1644  MVT PartVT =
1645  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1646 
1647  // 'inreg' on function refers to return value
1648  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1649  if (attr.hasRetAttr(Attribute::InReg))
1650  Flags.setInReg();
1651 
1652  // Propagate extension type if any
1653  if (attr.hasRetAttr(Attribute::SExt))
1654  Flags.setSExt();
1655  else if (attr.hasRetAttr(Attribute::ZExt))
1656  Flags.setZExt();
1657 
1658  for (unsigned i = 0; i < NumParts; ++i)
1659  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1660  }
1661 }
1662 
1663 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1664 /// function arguments in the caller parameter area. This is the actual
1665 /// alignment, not its logarithm.
1667  const DataLayout &DL) const {
1668  return DL.getABITypeAlign(Ty).value();
1669 }
1670 
1672  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1673  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1674  // Check if the specified alignment is sufficient based on the data layout.
1675  // TODO: While using the data layout works in practice, a better solution
1676  // would be to implement this check directly (make this a virtual function).
1677  // For example, the ABI alignment may change based on software platform while
1678  // this function should only be affected by hardware implementation.
1679  Type *Ty = VT.getTypeForEVT(Context);
1680  if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1681  // Assume that an access that meets the ABI-specified alignment is fast.
1682  if (Fast != nullptr)
1683  *Fast = true;
1684  return true;
1685  }
1686 
1687  // This is a misaligned access.
1688  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1689 }
1690 
1692  LLVMContext &Context, const DataLayout &DL, EVT VT,
1693  const MachineMemOperand &MMO, bool *Fast) const {
1695  MMO.getAlign(), MMO.getFlags(), Fast);
1696 }
1697 
1699  const DataLayout &DL, EVT VT,
1700  unsigned AddrSpace, Align Alignment,
1702  bool *Fast) const {
1703  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1704  Flags, Fast);
1705 }
1706 
1708  const DataLayout &DL, EVT VT,
1709  const MachineMemOperand &MMO,
1710  bool *Fast) const {
1711  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1712  MMO.getFlags(), Fast);
1713 }
1714 
1716  const DataLayout &DL, LLT Ty,
1717  const MachineMemOperand &MMO,
1718  bool *Fast) const {
1720  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1721  MMO.getFlags(), Fast);
1722 }
1723 
1724 //===----------------------------------------------------------------------===//
1725 // TargetTransformInfo Helpers
1726 //===----------------------------------------------------------------------===//
1727 
1729  enum InstructionOpcodes {
1730 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1731 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1732 #include "llvm/IR/Instruction.def"
1733  };
1734  switch (static_cast<InstructionOpcodes>(Opcode)) {
1735  case Ret: return 0;
1736  case Br: return 0;
1737  case Switch: return 0;
1738  case IndirectBr: return 0;
1739  case Invoke: return 0;
1740  case CallBr: return 0;
1741  case Resume: return 0;
1742  case Unreachable: return 0;
1743  case CleanupRet: return 0;
1744  case CatchRet: return 0;
1745  case CatchPad: return 0;
1746  case CatchSwitch: return 0;
1747  case CleanupPad: return 0;
1748  case FNeg: return ISD::FNEG;
1749  case Add: return ISD::ADD;
1750  case FAdd: return ISD::FADD;
1751  case Sub: return ISD::SUB;
1752  case FSub: return ISD::FSUB;
1753  case Mul: return ISD::MUL;
1754  case FMul: return ISD::FMUL;
1755  case UDiv: return ISD::UDIV;
1756  case SDiv: return ISD::SDIV;
1757  case FDiv: return ISD::FDIV;
1758  case URem: return ISD::UREM;
1759  case SRem: return ISD::SREM;
1760  case FRem: return ISD::FREM;
1761  case Shl: return ISD::SHL;
1762  case LShr: return ISD::SRL;
1763  case AShr: return ISD::SRA;
1764  case And: return ISD::AND;
1765  case Or: return ISD::OR;
1766  case Xor: return ISD::XOR;
1767  case Alloca: return 0;
1768  case Load: return ISD::LOAD;
1769  case Store: return ISD::STORE;
1770  case GetElementPtr: return 0;
1771  case Fence: return 0;
1772  case AtomicCmpXchg: return 0;
1773  case AtomicRMW: return 0;
1774  case Trunc: return ISD::TRUNCATE;
1775  case ZExt: return ISD::ZERO_EXTEND;
1776  case SExt: return ISD::SIGN_EXTEND;
1777  case FPToUI: return ISD::FP_TO_UINT;
1778  case FPToSI: return ISD::FP_TO_SINT;
1779  case UIToFP: return ISD::UINT_TO_FP;
1780  case SIToFP: return ISD::SINT_TO_FP;
1781  case FPTrunc: return ISD::FP_ROUND;
1782  case FPExt: return ISD::FP_EXTEND;
1783  case PtrToInt: return ISD::BITCAST;
1784  case IntToPtr: return ISD::BITCAST;
1785  case BitCast: return ISD::BITCAST;
1786  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1787  case ICmp: return ISD::SETCC;
1788  case FCmp: return ISD::SETCC;
1789  case PHI: return 0;
1790  case Call: return 0;
1791  case Select: return ISD::SELECT;
1792  case UserOp1: return 0;
1793  case UserOp2: return 0;
1794  case VAArg: return 0;
1795  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1796  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1797  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1798  case ExtractValue: return ISD::MERGE_VALUES;
1799  case InsertValue: return ISD::MERGE_VALUES;
1800  case LandingPad: return 0;
1801  case Freeze: return ISD::FREEZE;
1802  }
1803 
1804  llvm_unreachable("Unknown instruction type encountered!");
1805 }
1806 
1807 std::pair<InstructionCost, MVT>
1809  Type *Ty) const {
1810  LLVMContext &C = Ty->getContext();
1811  EVT MTy = getValueType(DL, Ty);
1812 
1813  InstructionCost Cost = 1;
1814  // We keep legalizing the type until we find a legal kind. We assume that
1815  // the only operation that costs anything is the split. After splitting
1816  // we need to handle two types.
1817  while (true) {
1818  LegalizeKind LK = getTypeConversion(C, MTy);
1819 
1820  if (LK.first == TypeScalarizeScalableVector) {
1821  // Ensure we return a sensible simple VT here, since many callers of this
1822  // function require it.
1823  MVT VT = MTy.isSimple() ? MTy.getSimpleVT() : MVT::i64;
1824  return std::make_pair(InstructionCost::getInvalid(), VT);
1825  }
1826 
1827  if (LK.first == TypeLegal)
1828  return std::make_pair(Cost, MTy.getSimpleVT());
1829 
1830  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1831  Cost *= 2;
1832 
1833  // Do not loop with f128 type.
1834  if (MTy == LK.second)
1835  return std::make_pair(Cost, MTy.getSimpleVT());
1836 
1837  // Keep legalizing the type.
1838  MTy = LK.second;
1839  }
1840 }
1841 
1842 Value *
1844  bool UseTLS) const {
1845  // compiler-rt provides a variable with a magic name. Targets that do not
1846  // link with compiler-rt may also provide such a variable.
1847  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1848  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1849  auto UnsafeStackPtr =
1850  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1851 
1852  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1853 
1854  if (!UnsafeStackPtr) {
1855  auto TLSModel = UseTLS ?
1858  // The global variable is not defined yet, define it ourselves.
1859  // We use the initial-exec TLS model because we do not support the
1860  // variable living anywhere other than in the main executable.
1861  UnsafeStackPtr = new GlobalVariable(
1862  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1863  UnsafeStackPtrVar, nullptr, TLSModel);
1864  } else {
1865  // The variable exists, check its type and attributes.
1866  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1867  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1868  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1869  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1870  (UseTLS ? "" : "not ") + "be thread-local");
1871  }
1872  return UnsafeStackPtr;
1873 }
1874 
1875 Value *
1877  if (!TM.getTargetTriple().isAndroid())
1878  return getDefaultSafeStackPointerLocation(IRB, true);
1879 
1880  // Android provides a libc function to retrieve the address of the current
1881  // thread's unsafe stack pointer.
1882  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1883  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1884  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1885  StackPtrTy->getPointerTo(0));
1886  return IRB.CreateCall(Fn);
1887 }
1888 
1889 //===----------------------------------------------------------------------===//
1890 // Loop Strength Reduction hooks
1891 //===----------------------------------------------------------------------===//
1892 
1893 /// isLegalAddressingMode - Return true if the addressing mode represented
1894 /// by AM is legal for this target, for a load/store of the specified type.
1896  const AddrMode &AM, Type *Ty,
1897  unsigned AS, Instruction *I) const {
1898  // The default implementation of this implements a conservative RISCy, r+r and
1899  // r+i addr mode.
1900 
1901  // Allows a sign-extended 16-bit immediate field.
1902  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1903  return false;
1904 
1905  // No global is ever allowed as a base.
1906  if (AM.BaseGV)
1907  return false;
1908 
1909  // Only support r+r,
1910  switch (AM.Scale) {
1911  case 0: // "r+i" or just "i", depending on HasBaseReg.
1912  break;
1913  case 1:
1914  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1915  return false;
1916  // Otherwise we have r+r or r+i.
1917  break;
1918  case 2:
1919  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1920  return false;
1921  // Allow 2*r as r+r.
1922  break;
1923  default: // Don't allow n * r
1924  return false;
1925  }
1926 
1927  return true;
1928 }
1929 
1930 //===----------------------------------------------------------------------===//
1931 // Stack Protector
1932 //===----------------------------------------------------------------------===//
1933 
1934 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1935 // so that SelectionDAG handle SSP.
1937  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1938  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1939  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1940  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1941  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1942  G->setVisibility(GlobalValue::HiddenVisibility);
1943  return C;
1944  }
1945  return nullptr;
1946 }
1947 
1948 // Currently only support "standard" __stack_chk_guard.
1949 // TODO: add LOAD_STACK_GUARD support.
1951  if (!M.getNamedValue("__stack_chk_guard")) {
1952  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1954  "__stack_chk_guard");
1955 
1956  // FreeBSD has "__stack_chk_guard" defined externally on libc.so
1957  if (TM.getRelocationModel() == Reloc::Static &&
1959  !TM.getTargetTriple().isOSFreeBSD())
1960  GV->setDSOLocal(true);
1961  }
1962 }
1963 
1964 // Currently only support "standard" __stack_chk_guard.
1965 // TODO: add LOAD_STACK_GUARD support.
1967  return M.getNamedValue("__stack_chk_guard");
1968 }
1969 
1971  return nullptr;
1972 }
1973 
1975  return MinimumJumpTableEntries;
1976 }
1977 
1980 }
1981 
1982 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1983  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1984 }
1985 
1987  return MaximumJumpTableSize;
1988 }
1989 
1991  MaximumJumpTableSize = Val;
1992 }
1993 
1996 }
1997 
1999  if (TM.Options.LoopAlignment)
2000  return Align(TM.Options.LoopAlignment);
2001  return PrefLoopAlignment;
2002 }
2003 
2005  MachineBasicBlock *MBB) const {
2006  return MaxBytesForAlignment;
2007 }
2008 
2009 //===----------------------------------------------------------------------===//
2010 // Reciprocal Estimates
2011 //===----------------------------------------------------------------------===//
2012 
2013 /// Get the reciprocal estimate attribute string for a function that will
2014 /// override the target defaults.
2016  const Function &F = MF.getFunction();
2017  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2018 }
2019 
2020 /// Construct a string for the given reciprocal operation of the given type.
2021 /// This string should match the corresponding option to the front-end's
2022 /// "-mrecip" flag assuming those strings have been passed through in an
2023 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2024 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2025  std::string Name = VT.isVector() ? "vec-" : "";
2026 
2027  Name += IsSqrt ? "sqrt" : "div";
2028 
2029  // TODO: Handle other float types?
2030  if (VT.getScalarType() == MVT::f64) {
2031  Name += "d";
2032  } else if (VT.getScalarType() == MVT::f16) {
2033  Name += "h";
2034  } else {
2035  assert(VT.getScalarType() == MVT::f32 &&
2036  "Unexpected FP type for reciprocal estimate");
2037  Name += "f";
2038  }
2039 
2040  return Name;
2041 }
2042 
2043 /// Return the character position and value (a single numeric character) of a
2044 /// customized refinement operation in the input string if it exists. Return
2045 /// false if there is no customized refinement step count.
2046 static bool parseRefinementStep(StringRef In, size_t &Position,
2047  uint8_t &Value) {
2048  const char RefStepToken = ':';
2049  Position = In.find(RefStepToken);
2050  if (Position == StringRef::npos)
2051  return false;
2052 
2053  StringRef RefStepString = In.substr(Position + 1);
2054  // Allow exactly one numeric character for the additional refinement
2055  // step parameter.
2056  if (RefStepString.size() == 1) {
2057  char RefStepChar = RefStepString[0];
2058  if (isDigit(RefStepChar)) {
2059  Value = RefStepChar - '0';
2060  return true;
2061  }
2062  }
2063  report_fatal_error("Invalid refinement step for -recip.");
2064 }
2065 
2066 /// For the input attribute string, return one of the ReciprocalEstimate enum
2067 /// status values (enabled, disabled, or not specified) for this operation on
2068 /// the specified data type.
2069 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2070  if (Override.empty())
2071  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2072 
2073  SmallVector<StringRef, 4> OverrideVector;
2074  Override.split(OverrideVector, ',');
2075  unsigned NumArgs = OverrideVector.size();
2076 
2077  // Check if "all", "none", or "default" was specified.
2078  if (NumArgs == 1) {
2079  // Look for an optional setting of the number of refinement steps needed
2080  // for this type of reciprocal operation.
2081  size_t RefPos;
2082  uint8_t RefSteps;
2083  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2084  // Split the string for further processing.
2085  Override = Override.substr(0, RefPos);
2086  }
2087 
2088  // All reciprocal types are enabled.
2089  if (Override == "all")
2091 
2092  // All reciprocal types are disabled.
2093  if (Override == "none")
2095 
2096  // Target defaults for enablement are used.
2097  if (Override == "default")
2098  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2099  }
2100 
2101  // The attribute string may omit the size suffix ('f'/'d').
2102  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2103  std::string VTNameNoSize = VTName;
2104  VTNameNoSize.pop_back();
2105  static const char DisabledPrefix = '!';
2106 
2107  for (StringRef RecipType : OverrideVector) {
2108  size_t RefPos;
2109  uint8_t RefSteps;
2110  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2111  RecipType = RecipType.substr(0, RefPos);
2112 
2113  // Ignore the disablement token for string matching.
2114  bool IsDisabled = RecipType[0] == DisabledPrefix;
2115  if (IsDisabled)
2116  RecipType = RecipType.substr(1);
2117 
2118  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2121  }
2122 
2123  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2124 }
2125 
2126 /// For the input attribute string, return the customized refinement step count
2127 /// for this operation on the specified data type. If the step count does not
2128 /// exist, return the ReciprocalEstimate enum value for unspecified.
2129 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2130  if (Override.empty())
2131  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2132 
2133  SmallVector<StringRef, 4> OverrideVector;
2134  Override.split(OverrideVector, ',');
2135  unsigned NumArgs = OverrideVector.size();
2136 
2137  // Check if "all", "default", or "none" was specified.
2138  if (NumArgs == 1) {
2139  // Look for an optional setting of the number of refinement steps needed
2140  // for this type of reciprocal operation.
2141  size_t RefPos;
2142  uint8_t RefSteps;
2143  if (!parseRefinementStep(Override, RefPos, RefSteps))
2144  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2145 
2146  // Split the string for further processing.
2147  Override = Override.substr(0, RefPos);
2148  assert(Override != "none" &&
2149  "Disabled reciprocals, but specifed refinement steps?");
2150 
2151  // If this is a general override, return the specified number of steps.
2152  if (Override == "all" || Override == "default")
2153  return RefSteps;
2154  }
2155 
2156  // The attribute string may omit the size suffix ('f'/'d').
2157  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2158  std::string VTNameNoSize = VTName;
2159  VTNameNoSize.pop_back();
2160 
2161  for (StringRef RecipType : OverrideVector) {
2162  size_t RefPos;
2163  uint8_t RefSteps;
2164  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2165  continue;
2166 
2167  RecipType = RecipType.substr(0, RefPos);
2168  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2169  return RefSteps;
2170  }
2171 
2172  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2173 }
2174 
2176  MachineFunction &MF) const {
2177  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2178 }
2179 
2181  MachineFunction &MF) const {
2182  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2183 }
2184 
2186  MachineFunction &MF) const {
2187  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2188 }
2189 
2191  MachineFunction &MF) const {
2192  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2193 }
2194 
2196  MF.getRegInfo().freezeReservedRegs(MF);
2197 }
2198 
2201  const DataLayout &DL) const {
2203  if (LI.isVolatile())
2205 
2206  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2208 
2209  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2211 
2214 
2215  Flags |= getTargetMMOFlags(LI);
2216  return Flags;
2217 }
2218 
2221  const DataLayout &DL) const {
2223 
2224  if (SI.isVolatile())
2226 
2227  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2229 
2230  // FIXME: Not preserving dereferenceable
2231  Flags |= getTargetMMOFlags(SI);
2232  return Flags;
2233 }
2234 
2237  const DataLayout &DL) const {
2239 
2240  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2241  if (RMW->isVolatile())
2243  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2244  if (CmpX->isVolatile())
2246  } else
2247  llvm_unreachable("not an atomic instruction");
2248 
2249  // FIXME: Not preserving dereferenceable
2250  Flags |= getTargetMMOFlags(AI);
2251  return Flags;
2252 }
2253 
2255  Instruction *Inst,
2256  AtomicOrdering Ord) const {
2257  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2258  return Builder.CreateFence(Ord);
2259  else
2260  return nullptr;
2261 }
2262 
2264  Instruction *Inst,
2265  AtomicOrdering Ord) const {
2266  if (isAcquireOrStronger(Ord))
2267  return Builder.CreateFence(Ord);
2268  else
2269  return nullptr;
2270 }
2271 
2272 //===----------------------------------------------------------------------===//
2273 // GlobalISel Hooks
2274 //===----------------------------------------------------------------------===//
2275 
2277  const TargetTransformInfo *TTI) const {
2278  auto &MF = *MI.getMF();
2279  auto &MRI = MF.getRegInfo();
2280  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2281  // this helper function computes the maximum number of uses we should consider
2282  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2283  // break even in terms of code size when the original MI has 2 users vs
2284  // choosing to potentially spill. Any more than 2 users we we have a net code
2285  // size increase. This doesn't take into account register pressure though.
2286  auto maxUses = [](unsigned RematCost) {
2287  // A cost of 1 means remats are basically free.
2288  if (RematCost == 1)
2289  return UINT_MAX;
2290  if (RematCost == 2)
2291  return 2U;
2292 
2293  // Remat is too expensive, only sink if there's one user.
2294  if (RematCost > 2)
2295  return 1U;
2296  llvm_unreachable("Unexpected remat cost");
2297  };
2298 
2299  // Helper to walk through uses and terminate if we've reached a limit. Saves
2300  // us spending time traversing uses if all we want to know is if it's >= min.
2301  auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) {
2302  unsigned NumUses = 0;
2304  for (; UI != UE && NumUses < MaxUses; ++UI) {
2305  NumUses++;
2306  }
2307  // If we haven't reached the end yet then there are more than MaxUses users.
2308  return UI == UE;
2309  };
2310 
2311  switch (MI.getOpcode()) {
2312  default:
2313  return false;
2314  // Constants-like instructions should be close to their users.
2315  // We don't want long live-ranges for them.
2316  case TargetOpcode::G_CONSTANT:
2317  case TargetOpcode::G_FCONSTANT:
2318  case TargetOpcode::G_FRAME_INDEX:
2319  case TargetOpcode::G_INTTOPTR:
2320  return true;
2321  case TargetOpcode::G_GLOBAL_VALUE: {
2322  unsigned RematCost = TTI->getGISelRematGlobalCost();
2323  Register Reg = MI.getOperand(0).getReg();
2324  unsigned MaxUses = maxUses(RematCost);
2325  if (MaxUses == UINT_MAX)
2326  return true; // Remats are "free" so always localize.
2327  bool B = isUsesAtMost(Reg, MaxUses);
2328  return B;
2329  }
2330  }
2331 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:460
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:910
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:2015
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:922
i
i
Definition: README.txt:29
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:1982
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2370
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3318
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::TargetLoweringBase::getByValTypeAlignment
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1666
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:955
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:586
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2411
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1428
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:573
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:191
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:546
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1062
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1621
llvm::TargetLoweringBase::getPreferredSwitchConditionType
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
Definition: TargetLoweringBase.cpp:1605
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:663
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1425
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:291
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1429
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:808
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:322
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:104
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1087
llvm::ElementCount
Definition: TypeSize.h:390
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:936
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:387
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1188
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:59
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:542
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1117
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:48
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1181
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:708
llvm::Triple::x86
@ x86
Definition: Triple.h:85
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:216
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1013
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3316
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:178
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:696
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:839
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1424
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:215
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:1990
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:645
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1160
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:102
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:143
llvm::GlobalVariable
Definition: GlobalVariable.h:39
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:731
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:913
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1876
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:350
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1221
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:543
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::TargetLoweringBase::getPrefLoopAlignment
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
Definition: TargetLoweringBase.cpp:1998
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1059
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:360
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:68
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:118
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::AttributeList
Definition: Attributes.h:408
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:131
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:141
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1583
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1266
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:504
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:1994
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:944
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1808
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3080
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:803
STLExtras.h
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1250
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1843
llvm::TargetLoweringBase::emitTrailingFence
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Definition: TargetLoweringBase.cpp:2263
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:268
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:258
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:208
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1128
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:216
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::EVT::isZeroSized
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:124
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:386
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3339
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2200
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2353
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1182
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:355
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:447
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
Definition: TargetLoweringBase.cpp:879
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::TargetLoweringBase::emitLeadingFence
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: TargetLoweringBase.cpp:2254
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2336
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::ISD::AVGFLOORU
@ AVGFLOORU
Definition: ISDOpcodes.h:644
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3304
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ElementCount::isScalar
bool isScalar() const
Counting predicates.
Definition: TypeSize.h:400
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:334
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:611
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1278
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:923
CommandLine.h
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1088
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:697
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:701
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2276
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2289
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1426
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:227
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:444
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:227
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:101
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:749
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:226
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:792
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2046
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2500
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:265
Twine.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3395
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1066
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:921
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:925
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:943
llvm::TargetLoweringBase::getMaxPermittedBytesForAlignment
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
Definition: TargetLoweringBase.cpp:2004
llvm::NextPowerOf2
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:710
TargetOpcodes.h
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:264
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3354
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:890
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1180
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::Instruction
Definition: Instruction.h:42
llvm::isDereferenceablePointer
bool isDereferenceablePointer(const Value *V, Type *Ty, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Return true if this is always a dereferenceable pointer.
Definition: Loads.cpp:227
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1895
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1187
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1966
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:920
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:919
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1493
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:503
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1432
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3331
llvm::BitVector
Definition: BitVector.h:75
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::RTLIB::getFPLibCall
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Definition: TargetLoweringBase.cpp:216
llvm::ISD::ABDS
@ ABDS
Definition: ISDOpcodes.h:655
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:613
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1950
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1141
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLArrayExtras.h:29
llvm::TargetOptions::LoopAlignment
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
Definition: TargetOptions.h:373
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:475
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:272
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:895
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:907
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:981
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:636
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1264
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3057
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:57
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1481
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3372
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::ISD::AVGCEILU
@ AVGCEILU
Definition: ISDOpcodes.h:649
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3333
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:949
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:1986
llvm::cl::opt< bool >
llvm::ISD::AVGCEILS
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:648
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1974
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1231
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1936
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:305
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:769
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1580
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:307
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:951
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:914
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1267
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:486
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1169
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1185
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:934
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1271
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:282
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:959
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1276
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:209
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:534
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:207
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:491
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2190
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1126
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:314
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:233
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1263
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2236
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1184
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1251
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:926
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:643
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1163
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:341
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1178
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:632
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1475
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1691
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2180
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:261
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3375
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1129
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MVT::all_valuetypes
static auto all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1417
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2220
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:139
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1404
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1273
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:296
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2129
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::isAcquireOrStronger
bool isAcquireOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:128
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Triple.h
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1187
TargetOptions.h
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:950
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1133
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:628
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:176
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:663
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1353
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:716
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:303
llvm::ISD::ABDU
@ ABDU
Definition: ISDOpcodes.h:656
llvm::isReleaseOrStronger
bool isReleaseOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:927
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1179
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2498
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3387
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3368
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:915
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1728
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:368
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:916
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:176
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1275
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:392
llvm::getApproximateEVTForLLT
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
Definition: LowLevelType.cpp:54
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:137
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1177
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:598
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:206
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:846
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:908
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:164
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2175
Attributes.h
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1970
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:420
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1427
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2499
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:937
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:233
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:838
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:611
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2501
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2069
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:257
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1272
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:374
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:344
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1308
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: TargetLoweringBase.cpp:874
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:917
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:173
Enabled
static bool Enabled
Definition: Statistic.cpp:46
llvm::TypeSize
Definition: TypeSize.h:421
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:598
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::LinearPolySize< ElementCount >::getScalable
static ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1274
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:774
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:352
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:421
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:744
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:913
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:210
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2024
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:960
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:214
llvm::InstructionCost::getInvalid
static InstructionCost getInvalid(CostType Val=0)
Definition: InstructionCost.h:73
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:496
llvm::ISD::IS_FPCLASS
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:506
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1698
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:871
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:496
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:391
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1139
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1614
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1671
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:213
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1106
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:814
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:54
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:211
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1248
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1572
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1355
llvm::AttributeList::hasRetAttr
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:749
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1978
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:705
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:165
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1510
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2497
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:437
llvm::TypeSize::getKnownMinSize
ScalarTy getKnownMinSize() const
Definition: TypeSize.h:431
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:662
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:924
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2380
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:401
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:904
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:381
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3243
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3352
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:696
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1183
llvm::MVT::fp_valuetypes
static auto fp_valuetypes()
Definition: MachineValueType.h:1428
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1459
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:51
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1277
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:212
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1279
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2195
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1052
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:181
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:918
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LinearPolySize::divideCoefficientBy
LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:360
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:912
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3366
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2185
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:218
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
TargetRegisterInfo.h
llvm::ISD::AVGFLOORS
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:643
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:51
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2229
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:354
llvm::LinearPolySize::coefficientNextPowerOf2
LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:370
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
llvm::MVT::VALUETYPE_SIZE
@ VALUETYPE_SIZE
Definition: MachineValueType.h:277
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1186
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:708
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:968
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:316
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1168
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393
llvm::LLT
Definition: LowLevelTypeImpl.h:39