LLVM  17.0.0git
TargetLoweringBase.cpp
Go to the documentation of this file.
1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <cstring>
61 #include <iterator>
62 #include <string>
63 #include <tuple>
64 #include <utility>
65 
66 using namespace llvm;
67 
69  "jump-is-expensive", cl::init(false),
70  cl::desc("Do not create extra branches to split comparison logic."),
71  cl::Hidden);
72 
74  ("min-jump-table-entries", cl::init(4), cl::Hidden,
75  cl::desc("Set minimum number of entries to use a jump table."));
76 
78  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79  cl::desc("Set maximum size of jump tables."));
80 
81 /// Minimum jump table density for normal functions.
82 static cl::opt<unsigned>
83  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84  cl::desc("Minimum density for building a jump table in "
85  "a normal function"));
86 
87 /// Minimum jump table density for -Os or -Oz functions.
89  "optsize-jump-table-density", cl::init(40), cl::Hidden,
90  cl::desc("Minimum density for building a jump table in "
91  "an optsize function"));
92 
93 // FIXME: This option is only to test if the strict fp operation processed
94 // correctly by preventing mutating strict fp operation to normal fp operation
95 // during development. When the backend supports strict float operation, this
96 // option will be meaningless.
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98  cl::desc("Don't mutate strict-float node to a legalize node"),
99  cl::init(false), cl::Hidden);
100 
101 static bool darwinHasSinCos(const Triple &TT) {
102  assert(TT.isOSDarwin() && "should be called with darwin triple");
103  // Don't bother with 32 bit x86.
104  if (TT.getArch() == Triple::x86)
105  return false;
106  // Macos < 10.9 has no sincos_stret.
107  if (TT.isMacOSX())
108  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109  // iOS < 7.0 has no sincos_stret.
110  if (TT.isiOS())
111  return !TT.isOSVersionLT(7, 0);
112  // Any other darwin such as WatchOS/TvOS is new enough.
113  return true;
114 }
115 
116 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117 #define HANDLE_LIBCALL(code, name) \
118  setLibcallName(RTLIB::code, name);
119 #include "llvm/IR/RuntimeLibcalls.def"
120 #undef HANDLE_LIBCALL
121  // Initialize calling conventions to their default.
122  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 
125  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
126  if (TT.isPPC()) {
127  setLibcallName(RTLIB::ADD_F128, "__addkf3");
128  setLibcallName(RTLIB::SUB_F128, "__subkf3");
129  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
130  setLibcallName(RTLIB::DIV_F128, "__divkf3");
131  setLibcallName(RTLIB::POWI_F128, "__powikf2");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
139  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
140  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
142  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
143  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
144  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
145  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
146  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
147  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
148  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
149  setLibcallName(RTLIB::UNE_F128, "__nekf2");
150  setLibcallName(RTLIB::OGE_F128, "__gekf2");
151  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
152  setLibcallName(RTLIB::OLE_F128, "__lekf2");
153  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
154  setLibcallName(RTLIB::UO_F128, "__unordkf2");
155  }
156 
157  // A few names are different on particular architectures or environments.
158  if (TT.isOSDarwin()) {
159  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
160  // of the gnueabi-style __gnu_*_ieee.
161  // FIXME: What about other targets?
162  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
163  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
164 
165  // Some darwins have an optimized __bzero/bzero function.
166  switch (TT.getArch()) {
167  case Triple::x86:
168  case Triple::x86_64:
169  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
170  setLibcallName(RTLIB::BZERO, "__bzero");
171  break;
172  case Triple::aarch64:
173  case Triple::aarch64_32:
174  setLibcallName(RTLIB::BZERO, "bzero");
175  break;
176  default:
177  break;
178  }
179 
180  if (darwinHasSinCos(TT)) {
181  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
182  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
183  if (TT.isWatchABI()) {
184  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
186  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
188  }
189  }
190  } else {
191  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
192  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
193  }
194 
195  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
196  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
197  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
198  setLibcallName(RTLIB::SINCOS_F64, "sincos");
199  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
200  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
201  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
202  }
203 
204  if (TT.isPS()) {
205  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
206  setLibcallName(RTLIB::SINCOS_F64, "sincos");
207  }
208 
209  if (TT.isOSOpenBSD()) {
210  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
211  }
212 }
213 
214 /// GetFPLibCall - Helper to return the right libcall for the given floating
215 /// point type, or UNKNOWN_LIBCALL if there is none.
217  RTLIB::Libcall Call_F32,
218  RTLIB::Libcall Call_F64,
219  RTLIB::Libcall Call_F80,
220  RTLIB::Libcall Call_F128,
221  RTLIB::Libcall Call_PPCF128) {
222  return
223  VT == MVT::f32 ? Call_F32 :
224  VT == MVT::f64 ? Call_F64 :
225  VT == MVT::f80 ? Call_F80 :
226  VT == MVT::f128 ? Call_F128 :
227  VT == MVT::ppcf128 ? Call_PPCF128 :
228  RTLIB::UNKNOWN_LIBCALL;
229 }
230 
231 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
234  if (OpVT == MVT::f16) {
235  if (RetVT == MVT::f32)
236  return FPEXT_F16_F32;
237  if (RetVT == MVT::f64)
238  return FPEXT_F16_F64;
239  if (RetVT == MVT::f80)
240  return FPEXT_F16_F80;
241  if (RetVT == MVT::f128)
242  return FPEXT_F16_F128;
243  } else if (OpVT == MVT::f32) {
244  if (RetVT == MVT::f64)
245  return FPEXT_F32_F64;
246  if (RetVT == MVT::f128)
247  return FPEXT_F32_F128;
248  if (RetVT == MVT::ppcf128)
249  return FPEXT_F32_PPCF128;
250  } else if (OpVT == MVT::f64) {
251  if (RetVT == MVT::f128)
252  return FPEXT_F64_F128;
253  else if (RetVT == MVT::ppcf128)
254  return FPEXT_F64_PPCF128;
255  } else if (OpVT == MVT::f80) {
256  if (RetVT == MVT::f128)
257  return FPEXT_F80_F128;
258  }
259 
260  return UNKNOWN_LIBCALL;
261 }
262 
263 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
264 /// UNKNOWN_LIBCALL if there is none.
266  if (RetVT == MVT::f16) {
267  if (OpVT == MVT::f32)
268  return FPROUND_F32_F16;
269  if (OpVT == MVT::f64)
270  return FPROUND_F64_F16;
271  if (OpVT == MVT::f80)
272  return FPROUND_F80_F16;
273  if (OpVT == MVT::f128)
274  return FPROUND_F128_F16;
275  if (OpVT == MVT::ppcf128)
276  return FPROUND_PPCF128_F16;
277  } else if (RetVT == MVT::bf16) {
278  if (OpVT == MVT::f32)
279  return FPROUND_F32_BF16;
280  if (OpVT == MVT::f64)
281  return FPROUND_F64_BF16;
282  } else if (RetVT == MVT::f32) {
283  if (OpVT == MVT::f64)
284  return FPROUND_F64_F32;
285  if (OpVT == MVT::f80)
286  return FPROUND_F80_F32;
287  if (OpVT == MVT::f128)
288  return FPROUND_F128_F32;
289  if (OpVT == MVT::ppcf128)
290  return FPROUND_PPCF128_F32;
291  } else if (RetVT == MVT::f64) {
292  if (OpVT == MVT::f80)
293  return FPROUND_F80_F64;
294  if (OpVT == MVT::f128)
295  return FPROUND_F128_F64;
296  if (OpVT == MVT::ppcf128)
297  return FPROUND_PPCF128_F64;
298  } else if (RetVT == MVT::f80) {
299  if (OpVT == MVT::f128)
300  return FPROUND_F128_F80;
301  }
302 
303  return UNKNOWN_LIBCALL;
304 }
305 
306 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
307 /// UNKNOWN_LIBCALL if there is none.
309  if (OpVT == MVT::f16) {
310  if (RetVT == MVT::i32)
311  return FPTOSINT_F16_I32;
312  if (RetVT == MVT::i64)
313  return FPTOSINT_F16_I64;
314  if (RetVT == MVT::i128)
315  return FPTOSINT_F16_I128;
316  } else if (OpVT == MVT::f32) {
317  if (RetVT == MVT::i32)
318  return FPTOSINT_F32_I32;
319  if (RetVT == MVT::i64)
320  return FPTOSINT_F32_I64;
321  if (RetVT == MVT::i128)
322  return FPTOSINT_F32_I128;
323  } else if (OpVT == MVT::f64) {
324  if (RetVT == MVT::i32)
325  return FPTOSINT_F64_I32;
326  if (RetVT == MVT::i64)
327  return FPTOSINT_F64_I64;
328  if (RetVT == MVT::i128)
329  return FPTOSINT_F64_I128;
330  } else if (OpVT == MVT::f80) {
331  if (RetVT == MVT::i32)
332  return FPTOSINT_F80_I32;
333  if (RetVT == MVT::i64)
334  return FPTOSINT_F80_I64;
335  if (RetVT == MVT::i128)
336  return FPTOSINT_F80_I128;
337  } else if (OpVT == MVT::f128) {
338  if (RetVT == MVT::i32)
339  return FPTOSINT_F128_I32;
340  if (RetVT == MVT::i64)
341  return FPTOSINT_F128_I64;
342  if (RetVT == MVT::i128)
343  return FPTOSINT_F128_I128;
344  } else if (OpVT == MVT::ppcf128) {
345  if (RetVT == MVT::i32)
346  return FPTOSINT_PPCF128_I32;
347  if (RetVT == MVT::i64)
348  return FPTOSINT_PPCF128_I64;
349  if (RetVT == MVT::i128)
350  return FPTOSINT_PPCF128_I128;
351  }
352  return UNKNOWN_LIBCALL;
353 }
354 
355 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
356 /// UNKNOWN_LIBCALL if there is none.
358  if (OpVT == MVT::f16) {
359  if (RetVT == MVT::i32)
360  return FPTOUINT_F16_I32;
361  if (RetVT == MVT::i64)
362  return FPTOUINT_F16_I64;
363  if (RetVT == MVT::i128)
364  return FPTOUINT_F16_I128;
365  } else if (OpVT == MVT::f32) {
366  if (RetVT == MVT::i32)
367  return FPTOUINT_F32_I32;
368  if (RetVT == MVT::i64)
369  return FPTOUINT_F32_I64;
370  if (RetVT == MVT::i128)
371  return FPTOUINT_F32_I128;
372  } else if (OpVT == MVT::f64) {
373  if (RetVT == MVT::i32)
374  return FPTOUINT_F64_I32;
375  if (RetVT == MVT::i64)
376  return FPTOUINT_F64_I64;
377  if (RetVT == MVT::i128)
378  return FPTOUINT_F64_I128;
379  } else if (OpVT == MVT::f80) {
380  if (RetVT == MVT::i32)
381  return FPTOUINT_F80_I32;
382  if (RetVT == MVT::i64)
383  return FPTOUINT_F80_I64;
384  if (RetVT == MVT::i128)
385  return FPTOUINT_F80_I128;
386  } else if (OpVT == MVT::f128) {
387  if (RetVT == MVT::i32)
388  return FPTOUINT_F128_I32;
389  if (RetVT == MVT::i64)
390  return FPTOUINT_F128_I64;
391  if (RetVT == MVT::i128)
392  return FPTOUINT_F128_I128;
393  } else if (OpVT == MVT::ppcf128) {
394  if (RetVT == MVT::i32)
395  return FPTOUINT_PPCF128_I32;
396  if (RetVT == MVT::i64)
397  return FPTOUINT_PPCF128_I64;
398  if (RetVT == MVT::i128)
399  return FPTOUINT_PPCF128_I128;
400  }
401  return UNKNOWN_LIBCALL;
402 }
403 
404 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
405 /// UNKNOWN_LIBCALL if there is none.
407  if (OpVT == MVT::i32) {
408  if (RetVT == MVT::f16)
409  return SINTTOFP_I32_F16;
410  if (RetVT == MVT::f32)
411  return SINTTOFP_I32_F32;
412  if (RetVT == MVT::f64)
413  return SINTTOFP_I32_F64;
414  if (RetVT == MVT::f80)
415  return SINTTOFP_I32_F80;
416  if (RetVT == MVT::f128)
417  return SINTTOFP_I32_F128;
418  if (RetVT == MVT::ppcf128)
419  return SINTTOFP_I32_PPCF128;
420  } else if (OpVT == MVT::i64) {
421  if (RetVT == MVT::f16)
422  return SINTTOFP_I64_F16;
423  if (RetVT == MVT::f32)
424  return SINTTOFP_I64_F32;
425  if (RetVT == MVT::f64)
426  return SINTTOFP_I64_F64;
427  if (RetVT == MVT::f80)
428  return SINTTOFP_I64_F80;
429  if (RetVT == MVT::f128)
430  return SINTTOFP_I64_F128;
431  if (RetVT == MVT::ppcf128)
432  return SINTTOFP_I64_PPCF128;
433  } else if (OpVT == MVT::i128) {
434  if (RetVT == MVT::f16)
435  return SINTTOFP_I128_F16;
436  if (RetVT == MVT::f32)
437  return SINTTOFP_I128_F32;
438  if (RetVT == MVT::f64)
439  return SINTTOFP_I128_F64;
440  if (RetVT == MVT::f80)
441  return SINTTOFP_I128_F80;
442  if (RetVT == MVT::f128)
443  return SINTTOFP_I128_F128;
444  if (RetVT == MVT::ppcf128)
445  return SINTTOFP_I128_PPCF128;
446  }
447  return UNKNOWN_LIBCALL;
448 }
449 
450 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
451 /// UNKNOWN_LIBCALL if there is none.
453  if (OpVT == MVT::i32) {
454  if (RetVT == MVT::f16)
455  return UINTTOFP_I32_F16;
456  if (RetVT == MVT::f32)
457  return UINTTOFP_I32_F32;
458  if (RetVT == MVT::f64)
459  return UINTTOFP_I32_F64;
460  if (RetVT == MVT::f80)
461  return UINTTOFP_I32_F80;
462  if (RetVT == MVT::f128)
463  return UINTTOFP_I32_F128;
464  if (RetVT == MVT::ppcf128)
465  return UINTTOFP_I32_PPCF128;
466  } else if (OpVT == MVT::i64) {
467  if (RetVT == MVT::f16)
468  return UINTTOFP_I64_F16;
469  if (RetVT == MVT::f32)
470  return UINTTOFP_I64_F32;
471  if (RetVT == MVT::f64)
472  return UINTTOFP_I64_F64;
473  if (RetVT == MVT::f80)
474  return UINTTOFP_I64_F80;
475  if (RetVT == MVT::f128)
476  return UINTTOFP_I64_F128;
477  if (RetVT == MVT::ppcf128)
478  return UINTTOFP_I64_PPCF128;
479  } else if (OpVT == MVT::i128) {
480  if (RetVT == MVT::f16)
481  return UINTTOFP_I128_F16;
482  if (RetVT == MVT::f32)
483  return UINTTOFP_I128_F32;
484  if (RetVT == MVT::f64)
485  return UINTTOFP_I128_F64;
486  if (RetVT == MVT::f80)
487  return UINTTOFP_I128_F80;
488  if (RetVT == MVT::f128)
489  return UINTTOFP_I128_F128;
490  if (RetVT == MVT::ppcf128)
491  return UINTTOFP_I128_PPCF128;
492  }
493  return UNKNOWN_LIBCALL;
494 }
495 
497  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
498  POWI_PPCF128);
499 }
500 
502  MVT VT) {
503  unsigned ModeN, ModelN;
504  switch (VT.SimpleTy) {
505  case MVT::i8:
506  ModeN = 0;
507  break;
508  case MVT::i16:
509  ModeN = 1;
510  break;
511  case MVT::i32:
512  ModeN = 2;
513  break;
514  case MVT::i64:
515  ModeN = 3;
516  break;
517  case MVT::i128:
518  ModeN = 4;
519  break;
520  default:
521  return UNKNOWN_LIBCALL;
522  }
523 
524  switch (Order) {
526  ModelN = 0;
527  break;
529  ModelN = 1;
530  break;
532  ModelN = 2;
533  break;
536  ModelN = 3;
537  break;
538  default:
539  return UNKNOWN_LIBCALL;
540  }
541 
542 #define LCALLS(A, B) \
543  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
544 #define LCALL5(A) \
545  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
546  switch (Opc) {
547  case ISD::ATOMIC_CMP_SWAP: {
548  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
549  return LC[ModeN][ModelN];
550  }
551  case ISD::ATOMIC_SWAP: {
552  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
553  return LC[ModeN][ModelN];
554  }
555  case ISD::ATOMIC_LOAD_ADD: {
556  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
557  return LC[ModeN][ModelN];
558  }
559  case ISD::ATOMIC_LOAD_OR: {
560  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
561  return LC[ModeN][ModelN];
562  }
563  case ISD::ATOMIC_LOAD_CLR: {
564  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
565  return LC[ModeN][ModelN];
566  }
567  case ISD::ATOMIC_LOAD_XOR: {
568  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
569  return LC[ModeN][ModelN];
570  }
571  default:
572  return UNKNOWN_LIBCALL;
573  }
574 #undef LCALLS
575 #undef LCALL5
576 }
577 
578 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
579 #define OP_TO_LIBCALL(Name, Enum) \
580  case Name: \
581  switch (VT.SimpleTy) { \
582  default: \
583  return UNKNOWN_LIBCALL; \
584  case MVT::i8: \
585  return Enum##_1; \
586  case MVT::i16: \
587  return Enum##_2; \
588  case MVT::i32: \
589  return Enum##_4; \
590  case MVT::i64: \
591  return Enum##_8; \
592  case MVT::i128: \
593  return Enum##_16; \
594  }
595 
596  switch (Opc) {
597  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
598  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
599  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
600  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
601  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
602  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
603  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
604  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
605  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
606  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
607  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
608  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
609  }
610 
611 #undef OP_TO_LIBCALL
612 
613  return UNKNOWN_LIBCALL;
614 }
615 
617  switch (ElementSize) {
618  case 1:
619  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
620  case 2:
621  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
622  case 4:
623  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
624  case 8:
625  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
626  case 16:
627  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
628  default:
629  return UNKNOWN_LIBCALL;
630  }
631 }
632 
634  switch (ElementSize) {
635  case 1:
636  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
637  case 2:
638  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
639  case 4:
640  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
641  case 8:
642  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
643  case 16:
644  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
645  default:
646  return UNKNOWN_LIBCALL;
647  }
648 }
649 
651  switch (ElementSize) {
652  case 1:
653  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
654  case 2:
655  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
656  case 4:
657  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
658  case 8:
659  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
660  case 16:
661  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
662  default:
663  return UNKNOWN_LIBCALL;
664  }
665 }
666 
667 /// InitCmpLibcallCCs - Set default comparison libcall CC.
668 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
669  std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
670  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
671  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
672  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
673  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
674  CCs[RTLIB::UNE_F32] = ISD::SETNE;
675  CCs[RTLIB::UNE_F64] = ISD::SETNE;
676  CCs[RTLIB::UNE_F128] = ISD::SETNE;
677  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
678  CCs[RTLIB::OGE_F32] = ISD::SETGE;
679  CCs[RTLIB::OGE_F64] = ISD::SETGE;
680  CCs[RTLIB::OGE_F128] = ISD::SETGE;
681  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
682  CCs[RTLIB::OLT_F32] = ISD::SETLT;
683  CCs[RTLIB::OLT_F64] = ISD::SETLT;
684  CCs[RTLIB::OLT_F128] = ISD::SETLT;
685  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
686  CCs[RTLIB::OLE_F32] = ISD::SETLE;
687  CCs[RTLIB::OLE_F64] = ISD::SETLE;
688  CCs[RTLIB::OLE_F128] = ISD::SETLE;
689  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
690  CCs[RTLIB::OGT_F32] = ISD::SETGT;
691  CCs[RTLIB::OGT_F64] = ISD::SETGT;
692  CCs[RTLIB::OGT_F128] = ISD::SETGT;
693  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
694  CCs[RTLIB::UO_F32] = ISD::SETNE;
695  CCs[RTLIB::UO_F64] = ISD::SETNE;
696  CCs[RTLIB::UO_F128] = ISD::SETNE;
697  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
698 }
699 
700 /// NOTE: The TargetMachine owns TLOF.
702  initActions();
703 
704  // Perform these initializations only once.
706  MaxLoadsPerMemcmp = 8;
710  HasMultipleConditionRegisters = false;
711  HasExtractBitsInsn = false;
712  JumpIsExpensive = JumpIsExpensiveOverride;
714  EnableExtLdPromotion = false;
715  StackPointerRegisterToSaveRestore = 0;
716  BooleanContents = UndefinedBooleanContent;
717  BooleanFloatContents = UndefinedBooleanContent;
718  BooleanVectorContents = UndefinedBooleanContent;
719  SchedPreferenceInfo = Sched::ILP;
722  MaxBytesForAlignment = 0;
723  // TODO: the default will be switched to 0 in the next commit, along
724  // with the Target-specific changes necessary.
725  MaxAtomicSizeInBitsSupported = 1024;
726 
727  MaxDivRemBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
728 
729  MaxLargeFPConvertBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
730 
731  MinCmpXchgSizeInBits = 0;
732  SupportsUnalignedAtomics = false;
733 
734  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
735 
736  InitLibcalls(TM.getTargetTriple());
737  InitCmpLibcallCCs(CmpLibcallCCs);
738 }
739 
741  // All operations default to being supported.
742  memset(OpActions, 0, sizeof(OpActions));
743  memset(LoadExtActions, 0, sizeof(LoadExtActions));
744  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
745  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
746  memset(CondCodeActions, 0, sizeof(CondCodeActions));
747  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
748  std::fill(std::begin(TargetDAGCombineArray),
749  std::end(TargetDAGCombineArray), 0);
750 
751  // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
752  // remove this and targets should individually set these types if not legal.
755  for (MVT VT : {MVT::i2, MVT::i4})
756  OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
757  }
758  for (MVT AVT : MVT::all_valuetypes()) {
759  for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
760  setTruncStoreAction(AVT, VT, Expand);
763  }
764  }
765  for (unsigned IM = (unsigned)ISD::PRE_INC;
766  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
767  for (MVT VT : {MVT::i2, MVT::i4}) {
768  setIndexedLoadAction(IM, VT, Expand);
769  setIndexedStoreAction(IM, VT, Expand);
772  }
773  }
774 
775  for (MVT VT : MVT::fp_valuetypes()) {
776  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
777  if (IntVT.isValid()) {
780  }
781  }
782 
783  // Set default actions for various operations.
784  for (MVT VT : MVT::all_valuetypes()) {
785  // Default all indexed load / store to expand.
786  for (unsigned IM = (unsigned)ISD::PRE_INC;
787  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
788  setIndexedLoadAction(IM, VT, Expand);
789  setIndexedStoreAction(IM, VT, Expand);
792  }
793 
794  // Most backends expect to see the node which just returns the value loaded.
796 
797  // These operations default to expand.
815  VT, Expand);
816 
817  // Overflow operations default to expand
820  VT, Expand);
821 
822  // ADDCARRY operations default to expand
825  VT, Expand);
826 
827  // ADDC/ADDE/SUBC/SUBE default to expand.
829  Expand);
830 
831  // Halving adds
834  Expand);
835 
836  // Absolute difference
838 
839  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
841  Expand);
842 
844 
845  // These library functions default to expand.
847 
848  // These operations default to expand for vector types.
849  if (VT.isVector())
854  VT, Expand);
855 
856  // Constrained floating-point operations default to expand.
857 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
858  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
859 #include "llvm/IR/ConstrainedOps.def"
860 
861  // For most targets @llvm.get.dynamic.area.offset just returns 0.
863 
864  // Vector reduction default to expand.
871  VT, Expand);
872 
873  // Named vector shuffles default to expand.
875 
876  // VP_SREM/UREM default to expand.
877  // TODO: Expand all VP intrinsics.
878  setOperationAction(ISD::VP_SREM, VT, Expand);
879  setOperationAction(ISD::VP_UREM, VT, Expand);
880  }
881 
882  // Most targets ignore the @llvm.prefetch intrinsic.
884 
885  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
887 
888  // ConstantFP nodes default to expand. Targets can either change this to
889  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
890  // to optimize expansions for certain constants.
893  Expand);
894 
895  // These library functions default to expand.
901 
902  // Default ISD::TRAP to expand (which turns it into abort).
904 
905  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
906  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
908 
910 }
911 
913  EVT) const {
914  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
915 }
916 
918  bool LegalTypes) const {
919  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
920  if (LHSTy.isVector())
921  return LHSTy;
922  MVT ShiftVT =
923  LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
924  // If any possible shift value won't fit in the prefered type, just use
925  // something safe. Assume it will be legalized when the shift is expanded.
926  if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
927  ShiftVT = MVT::i32;
928  assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
929  "ShiftVT is still too small!");
930  return ShiftVT;
931 }
932 
933 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
934  assert(isTypeLegal(VT));
935  switch (Op) {
936  default:
937  return false;
938  case ISD::SDIV:
939  case ISD::UDIV:
940  case ISD::SREM:
941  case ISD::UREM:
942  return true;
943  }
944 }
945 
947  unsigned DestAS) const {
948  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
949 }
950 
952  // If the command-line option was specified, ignore this request.
954  JumpIsExpensive = isExpensive;
955 }
956 
959  // If this is a simple type, use the ComputeRegisterProp mechanism.
960  if (VT.isSimple()) {
961  MVT SVT = VT.getSimpleVT();
962  assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
963  MVT NVT = TransformToType[SVT.SimpleTy];
964  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
965 
966  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
967  LA == TypeSoftPromoteHalf ||
968  (NVT.isVector() ||
969  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
970  "Promote may not follow Expand or Promote");
971 
972  if (LA == TypeSplitVector)
973  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
974  if (LA == TypeScalarizeVector)
975  return LegalizeKind(LA, SVT.getVectorElementType());
976  return LegalizeKind(LA, NVT);
977  }
978 
979  // Handle Extended Scalar Types.
980  if (!VT.isVector()) {
981  assert(VT.isInteger() && "Float types must be simple");
982  unsigned BitSize = VT.getSizeInBits();
983  // First promote to a power-of-two size, then expand if necessary.
984  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
985  EVT NVT = VT.getRoundIntegerType(Context);
986  assert(NVT != VT && "Unable to round integer VT");
987  LegalizeKind NextStep = getTypeConversion(Context, NVT);
988  // Avoid multi-step promotion.
989  if (NextStep.first == TypePromoteInteger)
990  return NextStep;
991  // Return rounded integer type.
992  return LegalizeKind(TypePromoteInteger, NVT);
993  }
994 
997  }
998 
999  // Handle vector types.
1000  ElementCount NumElts = VT.getVectorElementCount();
1001  EVT EltVT = VT.getVectorElementType();
1002 
1003  // Vectors with only one element are always scalarized.
1004  if (NumElts.isScalar())
1005  return LegalizeKind(TypeScalarizeVector, EltVT);
1006 
1007  // Try to widen vector elements until the element type is a power of two and
1008  // promote it to a legal type later on, for example:
1009  // <3 x i8> -> <4 x i8> -> <4 x i32>
1010  if (EltVT.isInteger()) {
1011  // Vectors with a number of elements that is not a power of two are always
1012  // widened, for example <3 x i8> -> <4 x i8>.
1013  if (!VT.isPow2VectorType()) {
1014  NumElts = NumElts.coefficientNextPowerOf2();
1015  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1016  return LegalizeKind(TypeWidenVector, NVT);
1017  }
1018 
1019  // Examine the element type.
1020  LegalizeKind LK = getTypeConversion(Context, EltVT);
1021 
1022  // If type is to be expanded, split the vector.
1023  // <4 x i140> -> <2 x i140>
1024  if (LK.first == TypeExpandInteger) {
1025  if (VT.getVectorElementCount().isScalable())
1029  }
1030 
1031  // Promote the integer element types until a legal vector type is found
1032  // or until the element integer type is too big. If a legal type was not
1033  // found, fallback to the usual mechanism of widening/splitting the
1034  // vector.
1035  EVT OldEltVT = EltVT;
1036  while (true) {
1037  // Increase the bitwidth of the element to the next pow-of-two
1038  // (which is greater than 8 bits).
1039  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1041 
1042  // Stop trying when getting a non-simple element type.
1043  // Note that vector elements may be greater than legal vector element
1044  // types. Example: X86 XMM registers hold 64bit element on 32bit
1045  // systems.
1046  if (!EltVT.isSimple())
1047  break;
1048 
1049  // Build a new vector type and check if it is legal.
1050  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1051  // Found a legal promoted vector type.
1052  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1054  EVT::getVectorVT(Context, EltVT, NumElts));
1055  }
1056 
1057  // Reset the type to the unexpanded type if we did not find a legal vector
1058  // type with a promoted vector element type.
1059  EltVT = OldEltVT;
1060  }
1061 
1062  // Try to widen the vector until a legal type is found.
1063  // If there is no wider legal type, split the vector.
1064  while (true) {
1065  // Round up to the next power of 2.
1066  NumElts = NumElts.coefficientNextPowerOf2();
1067 
1068  // If there is no simple vector type with this many elements then there
1069  // cannot be a larger legal vector type. Note that this assumes that
1070  // there are no skipped intermediate vector types in the simple types.
1071  if (!EltVT.isSimple())
1072  break;
1073  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1074  if (LargerVector == MVT())
1075  break;
1076 
1077  // If this type is legal then widen the vector.
1078  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1079  return LegalizeKind(TypeWidenVector, LargerVector);
1080  }
1081 
1082  // Widen odd vectors to next power of two.
1083  if (!VT.isPow2VectorType()) {
1084  EVT NVT = VT.getPow2VectorType(Context);
1085  return LegalizeKind(TypeWidenVector, NVT);
1086  }
1087 
1090 
1091  // Vectors with illegal element types are expanded.
1092  EVT NVT = EVT::getVectorVT(Context, EltVT,
1094  return LegalizeKind(TypeSplitVector, NVT);
1095 }
1096 
1097 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1098  unsigned &NumIntermediates,
1099  MVT &RegisterVT,
1100  TargetLoweringBase *TLI) {
1101  // Figure out the right, legal destination reg to copy into.
1103  MVT EltTy = VT.getVectorElementType();
1104 
1105  unsigned NumVectorRegs = 1;
1106 
1107  // Scalable vectors cannot be scalarized, so splitting or widening is
1108  // required.
1109  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1111  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1112 
1113  // FIXME: We don't support non-power-of-2-sized vectors for now.
1114  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1115  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1116  // Split EC to unit size (scalable property is preserved).
1117  NumVectorRegs = EC.getKnownMinValue();
1118  EC = ElementCount::getFixed(1);
1119  }
1120 
1121  // Divide the input until we get to a supported size. This will
1122  // always end up with an EC that represent a scalar or a scalable
1123  // scalar.
1124  while (EC.getKnownMinValue() > 1 &&
1125  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1126  EC = EC.divideCoefficientBy(2);
1127  NumVectorRegs <<= 1;
1128  }
1129 
1130  NumIntermediates = NumVectorRegs;
1131 
1132  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1133  if (!TLI->isTypeLegal(NewVT))
1134  NewVT = EltTy;
1135  IntermediateVT = NewVT;
1136 
1137  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1138 
1139  // Convert sizes such as i33 to i64.
1140  if (!isPowerOf2_32(LaneSizeInBits))
1141  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1142 
1143  MVT DestVT = TLI->getRegisterType(NewVT);
1144  RegisterVT = DestVT;
1145  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1146  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1147 
1148  // Otherwise, promotion or legal types use the same number of registers as
1149  // the vector decimated to the appropriate level.
1150  return NumVectorRegs;
1151 }
1152 
1153 /// isLegalRC - Return true if the value types that can be represented by the
1154 /// specified register class are all legal.
1156  const TargetRegisterClass &RC) const {
1157  for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1158  if (isTypeLegal(*I))
1159  return true;
1160  return false;
1161 }
1162 
1163 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1164 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1167  MachineBasicBlock *MBB) const {
1168  MachineInstr *MI = &InitialMI;
1169  MachineFunction &MF = *MI->getMF();
1170  MachineFrameInfo &MFI = MF.getFrameInfo();
1171 
1172  // We're handling multiple types of operands here:
1173  // PATCHPOINT MetaArgs - live-in, read only, direct
1174  // STATEPOINT Deopt Spill - live-through, read only, indirect
1175  // STATEPOINT Deopt Alloca - live-through, read only, direct
1176  // (We're currently conservative and mark the deopt slots read/write in
1177  // practice.)
1178  // STATEPOINT GC Spill - live-through, read/write, indirect
1179  // STATEPOINT GC Alloca - live-through, read/write, direct
1180  // The live-in vs live-through is handled already (the live through ones are
1181  // all stack slots), but we need to handle the different type of stackmap
1182  // operands and memory effects here.
1183 
1184  if (llvm::none_of(MI->operands(),
1185  [](MachineOperand &Operand) { return Operand.isFI(); }))
1186  return MBB;
1187 
1188  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1189 
1190  // Inherit previous memory operands.
1191  MIB.cloneMemRefs(*MI);
1192 
1193  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1194  MachineOperand &MO = MI->getOperand(i);
1195  if (!MO.isFI()) {
1196  // Index of Def operand this Use it tied to.
1197  // Since Defs are coming before Uses, if Use is tied, then
1198  // index of Def must be smaller that index of that Use.
1199  // Also, Defs preserve their position in new MI.
1200  unsigned TiedTo = i;
1201  if (MO.isReg() && MO.isTied())
1202  TiedTo = MI->findTiedOperandIdx(i);
1203  MIB.add(MO);
1204  if (TiedTo < i)
1205  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1206  continue;
1207  }
1208 
1209  // foldMemoryOperand builds a new MI after replacing a single FI operand
1210  // with the canonical set of five x86 addressing-mode operands.
1211  int FI = MO.getIndex();
1212 
1213  // Add frame index operands recognized by stackmaps.cpp
1214  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1215  // indirect-mem-ref tag, size, #FI, offset.
1216  // Used for spills inserted by StatepointLowering. This codepath is not
1217  // used for patchpoints/stackmaps at all, for these spilling is done via
1218  // foldMemoryOperand callback only.
1219  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1220  MIB.addImm(StackMaps::IndirectMemRefOp);
1221  MIB.addImm(MFI.getObjectSize(FI));
1222  MIB.add(MO);
1223  MIB.addImm(0);
1224  } else {
1225  // direct-mem-ref tag, #FI, offset.
1226  // Used by patchpoint, and direct alloca arguments to statepoints
1227  MIB.addImm(StackMaps::DirectMemRefOp);
1228  MIB.add(MO);
1229  MIB.addImm(0);
1230  }
1231 
1232  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1233 
1234  // Add a new memory operand for this FI.
1235  assert(MFI.getObjectOffset(FI) != -1);
1236 
1237  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1238  // PATCHPOINT should be updated to do the same. (TODO)
1239  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1240  auto Flags = MachineMemOperand::MOLoad;
1242  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1243  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1244  MIB->addMemOperand(MF, MMO);
1245  }
1246  }
1248  MI->eraseFromParent();
1249  return MBB;
1250 }
1251 
1252 /// findRepresentativeClass - Return the largest legal super-reg register class
1253 /// of the register class for the specified type and its associated "cost".
1254 // This function is in TargetLowering because it uses RegClassForVT which would
1255 // need to be moved to TargetRegisterInfo and would necessitate moving
1256 // isTypeLegal over as well - a massive change that would just require
1257 // TargetLowering having a TargetRegisterInfo class member that it would use.
1258 std::pair<const TargetRegisterClass *, uint8_t>
1260  MVT VT) const {
1261  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1262  if (!RC)
1263  return std::make_pair(RC, 0);
1264 
1265  // Compute the set of all super-register classes.
1266  BitVector SuperRegRC(TRI->getNumRegClasses());
1267  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1268  SuperRegRC.setBitsInMask(RCI.getMask());
1269 
1270  // Find the first legal register class with the largest spill size.
1271  const TargetRegisterClass *BestRC = RC;
1272  for (unsigned i : SuperRegRC.set_bits()) {
1273  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1274  // We want the largest possible spill size.
1275  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1276  continue;
1277  if (!isLegalRC(*TRI, *SuperRC))
1278  continue;
1279  BestRC = SuperRC;
1280  }
1281  return std::make_pair(BestRC, 1);
1282 }
1283 
1284 /// computeRegisterProperties - Once all of the register classes are added,
1285 /// this allows us to compute derived properties we expose.
1287  const TargetRegisterInfo *TRI) {
1289  "Too many value types for ValueTypeActions to hold!");
1290 
1291  // Everything defaults to needing one register.
1292  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1293  NumRegistersForVT[i] = 1;
1294  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1295  }
1296  // ...except isVoid, which doesn't need any registers.
1297  NumRegistersForVT[MVT::isVoid] = 0;
1298 
1299  // Find the largest integer register class.
1300  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1301  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1302  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1303 
1304  // Every integer value type larger than this largest register takes twice as
1305  // many registers to represent as the previous ValueType.
1306  for (unsigned ExpandedReg = LargestIntReg + 1;
1307  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1308  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1309  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1310  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1311  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1313  }
1314 
1315  // Inspect all of the ValueType's smaller than the largest integer
1316  // register to see which ones need promotion.
1317  unsigned LegalIntReg = LargestIntReg;
1318  for (unsigned IntReg = LargestIntReg - 1;
1319  IntReg >= (unsigned)MVT::i1; --IntReg) {
1320  MVT IVT = (MVT::SimpleValueType)IntReg;
1321  if (isTypeLegal(IVT)) {
1322  LegalIntReg = IntReg;
1323  } else {
1324  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1325  (MVT::SimpleValueType)LegalIntReg;
1326  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1327  }
1328  }
1329 
1330  // ppcf128 type is really two f64's.
1331  if (!isTypeLegal(MVT::ppcf128)) {
1332  if (isTypeLegal(MVT::f64)) {
1333  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1334  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1335  TransformToType[MVT::ppcf128] = MVT::f64;
1336  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1337  } else {
1338  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1339  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1340  TransformToType[MVT::ppcf128] = MVT::i128;
1341  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1342  }
1343  }
1344 
1345  // Decide how to handle f128. If the target does not have native f128 support,
1346  // expand it to i128 and we will be generating soft float library calls.
1347  if (!isTypeLegal(MVT::f128)) {
1348  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1349  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1350  TransformToType[MVT::f128] = MVT::i128;
1351  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1352  }
1353 
1354  // Decide how to handle f80. If the target does not have native f80 support,
1355  // expand it to i96 and we will be generating soft float library calls.
1356  if (!isTypeLegal(MVT::f80)) {
1357  NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1358  RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1359  TransformToType[MVT::f80] = MVT::i32;
1360  ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
1361  }
1362 
1363  // Decide how to handle f64. If the target does not have native f64 support,
1364  // expand it to i64 and we will be generating soft float library calls.
1365  if (!isTypeLegal(MVT::f64)) {
1366  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1367  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1368  TransformToType[MVT::f64] = MVT::i64;
1369  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1370  }
1371 
1372  // Decide how to handle f32. If the target does not have native f32 support,
1373  // expand it to i32 and we will be generating soft float library calls.
1374  if (!isTypeLegal(MVT::f32)) {
1375  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1376  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1377  TransformToType[MVT::f32] = MVT::i32;
1378  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1379  }
1380 
1381  // Decide how to handle f16. If the target does not have native f16 support,
1382  // promote it to f32, because there are no f16 library calls (except for
1383  // conversions).
1384  if (!isTypeLegal(MVT::f16)) {
1385  // Allow targets to control how we legalize half.
1386  if (softPromoteHalfType()) {
1387  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1388  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1389  TransformToType[MVT::f16] = MVT::f32;
1390  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1391  } else {
1392  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1393  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1394  TransformToType[MVT::f16] = MVT::f32;
1395  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1396  }
1397  }
1398 
1399  // Decide how to handle bf16. If the target does not have native bf16 support,
1400  // promote it to f32, because there are no bf16 library calls (except for
1401  // converting from f32 to bf16).
1402  if (!isTypeLegal(MVT::bf16)) {
1403  NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1404  RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1405  TransformToType[MVT::bf16] = MVT::f32;
1406  ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
1407  }
1408 
1409  // Loop over all of the vector value types to see which need transformations.
1410  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1411  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1412  MVT VT = (MVT::SimpleValueType) i;
1413  if (isTypeLegal(VT))
1414  continue;
1415 
1416  MVT EltVT = VT.getVectorElementType();
1418  bool IsLegalWiderType = false;
1419  bool IsScalable = VT.isScalableVector();
1420  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1421  switch (PreferredAction) {
1422  case TypePromoteInteger: {
1423  MVT::SimpleValueType EndVT = IsScalable ?
1426  // Try to promote the elements of integer vectors. If no legal
1427  // promotion was found, fall through to the widen-vector method.
1428  for (unsigned nVT = i + 1;
1429  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1430  MVT SVT = (MVT::SimpleValueType) nVT;
1431  // Promote vectors of integers to vectors with the same number
1432  // of elements, with a wider element type.
1433  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1434  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1435  TransformToType[i] = SVT;
1436  RegisterTypeForVT[i] = SVT;
1437  NumRegistersForVT[i] = 1;
1438  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1439  IsLegalWiderType = true;
1440  break;
1441  }
1442  }
1443  if (IsLegalWiderType)
1444  break;
1445  [[fallthrough]];
1446  }
1447 
1448  case TypeWidenVector:
1449  if (isPowerOf2_32(EC.getKnownMinValue())) {
1450  // Try to widen the vector.
1451  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1452  MVT SVT = (MVT::SimpleValueType) nVT;
1453  if (SVT.getVectorElementType() == EltVT &&
1454  SVT.isScalableVector() == IsScalable &&
1456  EC.getKnownMinValue() &&
1457  isTypeLegal(SVT)) {
1458  TransformToType[i] = SVT;
1459  RegisterTypeForVT[i] = SVT;
1460  NumRegistersForVT[i] = 1;
1461  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1462  IsLegalWiderType = true;
1463  break;
1464  }
1465  }
1466  if (IsLegalWiderType)
1467  break;
1468  } else {
1469  // Only widen to the next power of 2 to keep consistency with EVT.
1470  MVT NVT = VT.getPow2VectorType();
1471  if (isTypeLegal(NVT)) {
1472  TransformToType[i] = NVT;
1473  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1474  RegisterTypeForVT[i] = NVT;
1475  NumRegistersForVT[i] = 1;
1476  break;
1477  }
1478  }
1479  [[fallthrough]];
1480 
1481  case TypeSplitVector:
1482  case TypeScalarizeVector: {
1483  MVT IntermediateVT;
1484  MVT RegisterVT;
1485  unsigned NumIntermediates;
1486  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1487  NumIntermediates, RegisterVT, this);
1488  NumRegistersForVT[i] = NumRegisters;
1489  assert(NumRegistersForVT[i] == NumRegisters &&
1490  "NumRegistersForVT size cannot represent NumRegisters!");
1491  RegisterTypeForVT[i] = RegisterVT;
1492 
1493  MVT NVT = VT.getPow2VectorType();
1494  if (NVT == VT) {
1495  // Type is already a power of 2. The default action is to split.
1496  TransformToType[i] = MVT::Other;
1497  if (PreferredAction == TypeScalarizeVector)
1498  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1499  else if (PreferredAction == TypeSplitVector)
1500  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1501  else if (EC.getKnownMinValue() > 1)
1502  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1503  else
1504  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1507  } else {
1508  TransformToType[i] = NVT;
1509  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1510  }
1511  break;
1512  }
1513  default:
1514  llvm_unreachable("Unknown vector legalization action!");
1515  }
1516  }
1517 
1518  // Determine the 'representative' register class for each value type.
1519  // An representative register class is the largest (meaning one which is
1520  // not a sub-register class / subreg register class) legal register class for
1521  // a group of value types. For example, on i386, i8, i16, and i32
1522  // representative would be GR32; while on x86_64 it's GR64.
1523  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1524  const TargetRegisterClass* RRC;
1525  uint8_t Cost;
1527  RepRegClassForVT[i] = RRC;
1528  RepRegClassCostForVT[i] = Cost;
1529  }
1530 }
1531 
1533  EVT VT) const {
1534  assert(!VT.isVector() && "No default SetCC type for vectors!");
1535  return getPointerTy(DL).SimpleTy;
1536 }
1537 
1539  return MVT::i32; // return the default value
1540 }
1541 
1542 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1543 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1544 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1545 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1546 ///
1547 /// This method returns the number of registers needed, and the VT for each
1548 /// register. It also returns the VT and quantity of the intermediate values
1549 /// before they are promoted/expanded.
1551  EVT VT, EVT &IntermediateVT,
1552  unsigned &NumIntermediates,
1553  MVT &RegisterVT) const {
1554  ElementCount EltCnt = VT.getVectorElementCount();
1555 
1556  // If there is a wider vector type with the same element type as this one,
1557  // or a promoted vector type that has the same number of elements which
1558  // are wider, then we should convert to that legal vector type.
1559  // This handles things like <2 x float> -> <4 x float> and
1560  // <4 x i1> -> <4 x i32>.
1562  if (!EltCnt.isScalar() &&
1563  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1564  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1565  if (isTypeLegal(RegisterEVT)) {
1566  IntermediateVT = RegisterEVT;
1567  RegisterVT = RegisterEVT.getSimpleVT();
1568  NumIntermediates = 1;
1569  return 1;
1570  }
1571  }
1572 
1573  // Figure out the right, legal destination reg to copy into.
1574  EVT EltTy = VT.getVectorElementType();
1575 
1576  unsigned NumVectorRegs = 1;
1577 
1578  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1579  // types like done elsewhere in SelectionDAG.
1580  if (EltCnt.isScalable()) {
1581  LegalizeKind LK;
1582  EVT PartVT = VT;
1583  do {
1584  // Iterate until we've found a legal (part) type to hold VT.
1585  LK = getTypeConversion(Context, PartVT);
1586  PartVT = LK.second;
1587  } while (LK.first != TypeLegal);
1588 
1589  if (!PartVT.isVector()) {
1591  "Don't know how to legalize this scalable vector type");
1592  }
1593 
1594  NumIntermediates =
1597  IntermediateVT = PartVT;
1598  RegisterVT = getRegisterType(Context, IntermediateVT);
1599  return NumIntermediates;
1600  }
1601 
1602  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1603  // we could break down into LHS/RHS like LegalizeDAG does.
1604  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1605  NumVectorRegs = EltCnt.getKnownMinValue();
1606  EltCnt = ElementCount::getFixed(1);
1607  }
1608 
1609  // Divide the input until we get to a supported size. This will always
1610  // end with a scalar if the target doesn't support vectors.
1611  while (EltCnt.getKnownMinValue() > 1 &&
1612  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1613  EltCnt = EltCnt.divideCoefficientBy(2);
1614  NumVectorRegs <<= 1;
1615  }
1616 
1617  NumIntermediates = NumVectorRegs;
1618 
1619  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1620  if (!isTypeLegal(NewVT))
1621  NewVT = EltTy;
1622  IntermediateVT = NewVT;
1623 
1624  MVT DestVT = getRegisterType(Context, NewVT);
1625  RegisterVT = DestVT;
1626 
1627  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1628  TypeSize NewVTSize = NewVT.getSizeInBits();
1629  // Convert sizes such as i33 to i64.
1630  if (!isPowerOf2_32(NewVTSize.getKnownMinValue()))
1631  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1632  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1633  }
1634 
1635  // Otherwise, promotion or legal types use the same number of registers as
1636  // the vector decimated to the appropriate level.
1637  return NumVectorRegs;
1638 }
1639 
1641  uint64_t NumCases,
1642  uint64_t Range,
1643  ProfileSummaryInfo *PSI,
1644  BlockFrequencyInfo *BFI) const {
1645  // FIXME: This function check the maximum table size and density, but the
1646  // minimum size is not checked. It would be nice if the minimum size is
1647  // also combined within this function. Currently, the minimum size check is
1648  // performed in findJumpTable() in SelectionDAGBuiler and
1649  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1650  const bool OptForSize =
1651  SI->getParent()->getParent()->hasOptSize() ||
1652  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1653  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1654  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1655 
1656  // Check whether the number of cases is small enough and
1657  // the range is dense enough for a jump table.
1658  return (OptForSize || Range <= MaxJumpTableSize) &&
1659  (NumCases * 100 >= Range * MinDensity);
1660 }
1661 
1663  EVT ConditionVT) const {
1664  return getRegisterType(Context, ConditionVT);
1665 }
1666 
1667 /// Get the EVTs and ArgFlags collections that represent the legalized return
1668 /// type of the given function. This does not require a DAG or a return value,
1669 /// and is suitable for use before any DAGs for the function are constructed.
1670 /// TODO: Move this out of TargetLowering.cpp.
1672  AttributeList attr,
1674  const TargetLowering &TLI, const DataLayout &DL) {
1675  SmallVector<EVT, 4> ValueVTs;
1676  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1677  unsigned NumValues = ValueVTs.size();
1678  if (NumValues == 0) return;
1679 
1680  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1681  EVT VT = ValueVTs[j];
1682  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1683 
1684  if (attr.hasRetAttr(Attribute::SExt))
1685  ExtendKind = ISD::SIGN_EXTEND;
1686  else if (attr.hasRetAttr(Attribute::ZExt))
1687  ExtendKind = ISD::ZERO_EXTEND;
1688 
1689  // FIXME: C calling convention requires the return type to be promoted to
1690  // at least 32-bit. But this is not necessary for non-C calling
1691  // conventions. The frontend should mark functions whose return values
1692  // require promoting with signext or zeroext attributes.
1693  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1694  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1695  if (VT.bitsLT(MinVT))
1696  VT = MinVT;
1697  }
1698 
1699  unsigned NumParts =
1700  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1701  MVT PartVT =
1702  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1703 
1704  // 'inreg' on function refers to return value
1705  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1706  if (attr.hasRetAttr(Attribute::InReg))
1707  Flags.setInReg();
1708 
1709  // Propagate extension type if any
1710  if (attr.hasRetAttr(Attribute::SExt))
1711  Flags.setSExt();
1712  else if (attr.hasRetAttr(Attribute::ZExt))
1713  Flags.setZExt();
1714 
1715  for (unsigned i = 0; i < NumParts; ++i)
1716  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1717  }
1718 }
1719 
1720 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1721 /// function arguments in the caller parameter area. This is the actual
1722 /// alignment, not its logarithm.
1724  const DataLayout &DL) const {
1725  return DL.getABITypeAlign(Ty).value();
1726 }
1727 
1729  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1730  Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1731  // Check if the specified alignment is sufficient based on the data layout.
1732  // TODO: While using the data layout works in practice, a better solution
1733  // would be to implement this check directly (make this a virtual function).
1734  // For example, the ABI alignment may change based on software platform while
1735  // this function should only be affected by hardware implementation.
1736  Type *Ty = VT.getTypeForEVT(Context);
1737  if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1738  // Assume that an access that meets the ABI-specified alignment is fast.
1739  if (Fast != nullptr)
1740  *Fast = 1;
1741  return true;
1742  }
1743 
1744  // This is a misaligned access.
1745  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1746 }
1747 
1749  LLVMContext &Context, const DataLayout &DL, EVT VT,
1750  const MachineMemOperand &MMO, unsigned *Fast) const {
1752  MMO.getAlign(), MMO.getFlags(), Fast);
1753 }
1754 
1756  const DataLayout &DL, EVT VT,
1757  unsigned AddrSpace, Align Alignment,
1759  unsigned *Fast) const {
1760  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1761  Flags, Fast);
1762 }
1763 
1765  const DataLayout &DL, EVT VT,
1766  const MachineMemOperand &MMO,
1767  unsigned *Fast) const {
1768  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1769  MMO.getFlags(), Fast);
1770 }
1771 
1773  const DataLayout &DL, LLT Ty,
1774  const MachineMemOperand &MMO,
1775  unsigned *Fast) const {
1777  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1778  MMO.getFlags(), Fast);
1779 }
1780 
1781 //===----------------------------------------------------------------------===//
1782 // TargetTransformInfo Helpers
1783 //===----------------------------------------------------------------------===//
1784 
1786  enum InstructionOpcodes {
1787 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1788 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1789 #include "llvm/IR/Instruction.def"
1790  };
1791  switch (static_cast<InstructionOpcodes>(Opcode)) {
1792  case Ret: return 0;
1793  case Br: return 0;
1794  case Switch: return 0;
1795  case IndirectBr: return 0;
1796  case Invoke: return 0;
1797  case CallBr: return 0;
1798  case Resume: return 0;
1799  case Unreachable: return 0;
1800  case CleanupRet: return 0;
1801  case CatchRet: return 0;
1802  case CatchPad: return 0;
1803  case CatchSwitch: return 0;
1804  case CleanupPad: return 0;
1805  case FNeg: return ISD::FNEG;
1806  case Add: return ISD::ADD;
1807  case FAdd: return ISD::FADD;
1808  case Sub: return ISD::SUB;
1809  case FSub: return ISD::FSUB;
1810  case Mul: return ISD::MUL;
1811  case FMul: return ISD::FMUL;
1812  case UDiv: return ISD::UDIV;
1813  case SDiv: return ISD::SDIV;
1814  case FDiv: return ISD::FDIV;
1815  case URem: return ISD::UREM;
1816  case SRem: return ISD::SREM;
1817  case FRem: return ISD::FREM;
1818  case Shl: return ISD::SHL;
1819  case LShr: return ISD::SRL;
1820  case AShr: return ISD::SRA;
1821  case And: return ISD::AND;
1822  case Or: return ISD::OR;
1823  case Xor: return ISD::XOR;
1824  case Alloca: return 0;
1825  case Load: return ISD::LOAD;
1826  case Store: return ISD::STORE;
1827  case GetElementPtr: return 0;
1828  case Fence: return 0;
1829  case AtomicCmpXchg: return 0;
1830  case AtomicRMW: return 0;
1831  case Trunc: return ISD::TRUNCATE;
1832  case ZExt: return ISD::ZERO_EXTEND;
1833  case SExt: return ISD::SIGN_EXTEND;
1834  case FPToUI: return ISD::FP_TO_UINT;
1835  case FPToSI: return ISD::FP_TO_SINT;
1836  case UIToFP: return ISD::UINT_TO_FP;
1837  case SIToFP: return ISD::SINT_TO_FP;
1838  case FPTrunc: return ISD::FP_ROUND;
1839  case FPExt: return ISD::FP_EXTEND;
1840  case PtrToInt: return ISD::BITCAST;
1841  case IntToPtr: return ISD::BITCAST;
1842  case BitCast: return ISD::BITCAST;
1843  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1844  case ICmp: return ISD::SETCC;
1845  case FCmp: return ISD::SETCC;
1846  case PHI: return 0;
1847  case Call: return 0;
1848  case Select: return ISD::SELECT;
1849  case UserOp1: return 0;
1850  case UserOp2: return 0;
1851  case VAArg: return 0;
1852  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1853  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1854  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1855  case ExtractValue: return ISD::MERGE_VALUES;
1856  case InsertValue: return ISD::MERGE_VALUES;
1857  case LandingPad: return 0;
1858  case Freeze: return ISD::FREEZE;
1859  }
1860 
1861  llvm_unreachable("Unknown instruction type encountered!");
1862 }
1863 
1864 Value *
1866  bool UseTLS) const {
1867  // compiler-rt provides a variable with a magic name. Targets that do not
1868  // link with compiler-rt may also provide such a variable.
1869  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1870  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1871  auto UnsafeStackPtr =
1872  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1873 
1874  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1875 
1876  if (!UnsafeStackPtr) {
1877  auto TLSModel = UseTLS ?
1880  // The global variable is not defined yet, define it ourselves.
1881  // We use the initial-exec TLS model because we do not support the
1882  // variable living anywhere other than in the main executable.
1883  UnsafeStackPtr = new GlobalVariable(
1884  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1885  UnsafeStackPtrVar, nullptr, TLSModel);
1886  } else {
1887  // The variable exists, check its type and attributes.
1888  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1889  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1890  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1891  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1892  (UseTLS ? "" : "not ") + "be thread-local");
1893  }
1894  return UnsafeStackPtr;
1895 }
1896 
1897 Value *
1899  if (!TM.getTargetTriple().isAndroid())
1900  return getDefaultSafeStackPointerLocation(IRB, true);
1901 
1902  // Android provides a libc function to retrieve the address of the current
1903  // thread's unsafe stack pointer.
1904  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1905  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1906  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1907  StackPtrTy->getPointerTo(0));
1908  return IRB.CreateCall(Fn);
1909 }
1910 
1911 //===----------------------------------------------------------------------===//
1912 // Loop Strength Reduction hooks
1913 //===----------------------------------------------------------------------===//
1914 
1915 /// isLegalAddressingMode - Return true if the addressing mode represented
1916 /// by AM is legal for this target, for a load/store of the specified type.
1918  const AddrMode &AM, Type *Ty,
1919  unsigned AS, Instruction *I) const {
1920  // The default implementation of this implements a conservative RISCy, r+r and
1921  // r+i addr mode.
1922 
1923  // Allows a sign-extended 16-bit immediate field.
1924  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1925  return false;
1926 
1927  // No global is ever allowed as a base.
1928  if (AM.BaseGV)
1929  return false;
1930 
1931  // Only support r+r,
1932  switch (AM.Scale) {
1933  case 0: // "r+i" or just "i", depending on HasBaseReg.
1934  break;
1935  case 1:
1936  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1937  return false;
1938  // Otherwise we have r+r or r+i.
1939  break;
1940  case 2:
1941  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1942  return false;
1943  // Allow 2*r as r+r.
1944  break;
1945  default: // Don't allow n * r
1946  return false;
1947  }
1948 
1949  return true;
1950 }
1951 
1952 //===----------------------------------------------------------------------===//
1953 // Stack Protector
1954 //===----------------------------------------------------------------------===//
1955 
1956 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1957 // so that SelectionDAG handle SSP.
1959  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1960  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1961  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1962  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1963  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1964  G->setVisibility(GlobalValue::HiddenVisibility);
1965  return C;
1966  }
1967  return nullptr;
1968 }
1969 
1970 // Currently only support "standard" __stack_chk_guard.
1971 // TODO: add LOAD_STACK_GUARD support.
1973  if (!M.getNamedValue("__stack_chk_guard")) {
1974  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1976  "__stack_chk_guard");
1977 
1978  // FreeBSD has "__stack_chk_guard" defined externally on libc.so
1979  if (TM.getRelocationModel() == Reloc::Static &&
1981  !TM.getTargetTriple().isOSFreeBSD())
1982  GV->setDSOLocal(true);
1983  }
1984 }
1985 
1986 // Currently only support "standard" __stack_chk_guard.
1987 // TODO: add LOAD_STACK_GUARD support.
1989  return M.getNamedValue("__stack_chk_guard");
1990 }
1991 
1993  return nullptr;
1994 }
1995 
1997  return MinimumJumpTableEntries;
1998 }
1999 
2002 }
2003 
2004 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2005  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2006 }
2007 
2009  return MaximumJumpTableSize;
2010 }
2011 
2013  MaximumJumpTableSize = Val;
2014 }
2015 
2018 }
2019 
2021  if (TM.Options.LoopAlignment)
2022  return Align(TM.Options.LoopAlignment);
2023  return PrefLoopAlignment;
2024 }
2025 
2027  MachineBasicBlock *MBB) const {
2028  return MaxBytesForAlignment;
2029 }
2030 
2031 //===----------------------------------------------------------------------===//
2032 // Reciprocal Estimates
2033 //===----------------------------------------------------------------------===//
2034 
2035 /// Get the reciprocal estimate attribute string for a function that will
2036 /// override the target defaults.
2038  const Function &F = MF.getFunction();
2039  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2040 }
2041 
2042 /// Construct a string for the given reciprocal operation of the given type.
2043 /// This string should match the corresponding option to the front-end's
2044 /// "-mrecip" flag assuming those strings have been passed through in an
2045 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2046 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2047  std::string Name = VT.isVector() ? "vec-" : "";
2048 
2049  Name += IsSqrt ? "sqrt" : "div";
2050 
2051  // TODO: Handle other float types?
2052  if (VT.getScalarType() == MVT::f64) {
2053  Name += "d";
2054  } else if (VT.getScalarType() == MVT::f16) {
2055  Name += "h";
2056  } else {
2057  assert(VT.getScalarType() == MVT::f32 &&
2058  "Unexpected FP type for reciprocal estimate");
2059  Name += "f";
2060  }
2061 
2062  return Name;
2063 }
2064 
2065 /// Return the character position and value (a single numeric character) of a
2066 /// customized refinement operation in the input string if it exists. Return
2067 /// false if there is no customized refinement step count.
2068 static bool parseRefinementStep(StringRef In, size_t &Position,
2069  uint8_t &Value) {
2070  const char RefStepToken = ':';
2071  Position = In.find(RefStepToken);
2072  if (Position == StringRef::npos)
2073  return false;
2074 
2075  StringRef RefStepString = In.substr(Position + 1);
2076  // Allow exactly one numeric character for the additional refinement
2077  // step parameter.
2078  if (RefStepString.size() == 1) {
2079  char RefStepChar = RefStepString[0];
2080  if (isDigit(RefStepChar)) {
2081  Value = RefStepChar - '0';
2082  return true;
2083  }
2084  }
2085  report_fatal_error("Invalid refinement step for -recip.");
2086 }
2087 
2088 /// For the input attribute string, return one of the ReciprocalEstimate enum
2089 /// status values (enabled, disabled, or not specified) for this operation on
2090 /// the specified data type.
2091 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2092  if (Override.empty())
2093  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2094 
2095  SmallVector<StringRef, 4> OverrideVector;
2096  Override.split(OverrideVector, ',');
2097  unsigned NumArgs = OverrideVector.size();
2098 
2099  // Check if "all", "none", or "default" was specified.
2100  if (NumArgs == 1) {
2101  // Look for an optional setting of the number of refinement steps needed
2102  // for this type of reciprocal operation.
2103  size_t RefPos;
2104  uint8_t RefSteps;
2105  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2106  // Split the string for further processing.
2107  Override = Override.substr(0, RefPos);
2108  }
2109 
2110  // All reciprocal types are enabled.
2111  if (Override == "all")
2113 
2114  // All reciprocal types are disabled.
2115  if (Override == "none")
2117 
2118  // Target defaults for enablement are used.
2119  if (Override == "default")
2120  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2121  }
2122 
2123  // The attribute string may omit the size suffix ('f'/'d').
2124  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2125  std::string VTNameNoSize = VTName;
2126  VTNameNoSize.pop_back();
2127  static const char DisabledPrefix = '!';
2128 
2129  for (StringRef RecipType : OverrideVector) {
2130  size_t RefPos;
2131  uint8_t RefSteps;
2132  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2133  RecipType = RecipType.substr(0, RefPos);
2134 
2135  // Ignore the disablement token for string matching.
2136  bool IsDisabled = RecipType[0] == DisabledPrefix;
2137  if (IsDisabled)
2138  RecipType = RecipType.substr(1);
2139 
2140  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2143  }
2144 
2145  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2146 }
2147 
2148 /// For the input attribute string, return the customized refinement step count
2149 /// for this operation on the specified data type. If the step count does not
2150 /// exist, return the ReciprocalEstimate enum value for unspecified.
2151 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2152  if (Override.empty())
2153  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2154 
2155  SmallVector<StringRef, 4> OverrideVector;
2156  Override.split(OverrideVector, ',');
2157  unsigned NumArgs = OverrideVector.size();
2158 
2159  // Check if "all", "default", or "none" was specified.
2160  if (NumArgs == 1) {
2161  // Look for an optional setting of the number of refinement steps needed
2162  // for this type of reciprocal operation.
2163  size_t RefPos;
2164  uint8_t RefSteps;
2165  if (!parseRefinementStep(Override, RefPos, RefSteps))
2166  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2167 
2168  // Split the string for further processing.
2169  Override = Override.substr(0, RefPos);
2170  assert(Override != "none" &&
2171  "Disabled reciprocals, but specifed refinement steps?");
2172 
2173  // If this is a general override, return the specified number of steps.
2174  if (Override == "all" || Override == "default")
2175  return RefSteps;
2176  }
2177 
2178  // The attribute string may omit the size suffix ('f'/'d').
2179  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2180  std::string VTNameNoSize = VTName;
2181  VTNameNoSize.pop_back();
2182 
2183  for (StringRef RecipType : OverrideVector) {
2184  size_t RefPos;
2185  uint8_t RefSteps;
2186  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2187  continue;
2188 
2189  RecipType = RecipType.substr(0, RefPos);
2190  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2191  return RefSteps;
2192  }
2193 
2194  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2195 }
2196 
2198  MachineFunction &MF) const {
2199  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2200 }
2201 
2203  MachineFunction &MF) const {
2204  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2205 }
2206 
2208  MachineFunction &MF) const {
2209  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2210 }
2211 
2213  MachineFunction &MF) const {
2214  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2215 }
2216 
2218  EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2219  const MachineMemOperand &MMO) const {
2220  // Single-element vectors are scalarized, so we should generally avoid having
2221  // any memory operations on such types, as they would get scalarized too.
2222  if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2223  BitcastVT.getVectorNumElements() == 1)
2224  return false;
2225 
2226  // Don't do if we could do an indexed load on the original type, but not on
2227  // the new one.
2228  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2229  return true;
2230 
2231  MVT LoadMVT = LoadVT.getSimpleVT();
2232 
2233  // Don't bother doing this if it's just going to be promoted again later, as
2234  // doing so might interfere with other combines.
2235  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
2236  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
2237  return false;
2238 
2239  unsigned Fast = 0;
2240  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
2241  MMO, &Fast) &&
2242  Fast;
2243 }
2244 
2246  MF.getRegInfo().freezeReservedRegs(MF);
2247 }
2248 
2250  const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2251  const TargetLibraryInfo *LibInfo) const {
2253  if (LI.isVolatile())
2255 
2256  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2258 
2259  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2261 
2263  LI.getAlign(), DL, &LI, AC,
2264  /*DT=*/nullptr, LibInfo))
2266 
2267  Flags |= getTargetMMOFlags(LI);
2268  return Flags;
2269 }
2270 
2273  const DataLayout &DL) const {
2275 
2276  if (SI.isVolatile())
2278 
2279  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2281 
2282  // FIXME: Not preserving dereferenceable
2283  Flags |= getTargetMMOFlags(SI);
2284  return Flags;
2285 }
2286 
2289  const DataLayout &DL) const {
2291 
2292  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2293  if (RMW->isVolatile())
2295  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2296  if (CmpX->isVolatile())
2298  } else
2299  llvm_unreachable("not an atomic instruction");
2300 
2301  // FIXME: Not preserving dereferenceable
2302  Flags |= getTargetMMOFlags(AI);
2303  return Flags;
2304 }
2305 
2307  Instruction *Inst,
2308  AtomicOrdering Ord) const {
2309  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2310  return Builder.CreateFence(Ord);
2311  else
2312  return nullptr;
2313 }
2314 
2316  Instruction *Inst,
2317  AtomicOrdering Ord) const {
2318  if (isAcquireOrStronger(Ord))
2319  return Builder.CreateFence(Ord);
2320  else
2321  return nullptr;
2322 }
2323 
2324 //===----------------------------------------------------------------------===//
2325 // GlobalISel Hooks
2326 //===----------------------------------------------------------------------===//
2327 
2329  const TargetTransformInfo *TTI) const {
2330  auto &MF = *MI.getMF();
2331  auto &MRI = MF.getRegInfo();
2332  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2333  // this helper function computes the maximum number of uses we should consider
2334  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2335  // break even in terms of code size when the original MI has 2 users vs
2336  // choosing to potentially spill. Any more than 2 users we we have a net code
2337  // size increase. This doesn't take into account register pressure though.
2338  auto maxUses = [](unsigned RematCost) {
2339  // A cost of 1 means remats are basically free.
2340  if (RematCost == 1)
2342  if (RematCost == 2)
2343  return 2U;
2344 
2345  // Remat is too expensive, only sink if there's one user.
2346  if (RematCost > 2)
2347  return 1U;
2348  llvm_unreachable("Unexpected remat cost");
2349  };
2350 
2351  switch (MI.getOpcode()) {
2352  default:
2353  return false;
2354  // Constants-like instructions should be close to their users.
2355  // We don't want long live-ranges for them.
2356  case TargetOpcode::G_CONSTANT:
2357  case TargetOpcode::G_FCONSTANT:
2358  case TargetOpcode::G_FRAME_INDEX:
2359  case TargetOpcode::G_INTTOPTR:
2360  return true;
2361  case TargetOpcode::G_GLOBAL_VALUE: {
2362  unsigned RematCost = TTI->getGISelRematGlobalCost();
2363  Register Reg = MI.getOperand(0).getReg();
2364  unsigned MaxUses = maxUses(RematCost);
2365  if (MaxUses == UINT_MAX)
2366  return true; // Remats are "free" so always localize.
2367  return MRI.hasAtMostUserInstrs(Reg, MaxUses);
2368  }
2369  }
2370 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:465
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:916
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:2037
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:928
i
i
Definition: README.txt:29
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:2004
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2453
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3433
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::TargetLoweringBase::getByValTypeAlignment
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1723
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:957
llvm::ElementCount::isScalar
constexpr bool isScalar() const
Exactly one element.
Definition: TypeSize.h:302
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:586
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:542
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2494
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1452
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1728
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:578
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:192
llvm::IntegerType::MAX_INT_BITS
@ MAX_INT_BITS
Maximum number of bits that can be specified.
Definition: DerivedTypes.h:52
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1134
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:44
llvm::ElementCount::getScalable
static constexpr ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:294
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1749
llvm::TargetLoweringBase::getPreferredSwitchConditionType
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
Definition: TargetLoweringBase.cpp:1662
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:668
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1449
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:885
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:293
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1453
llvm::TargetLoweringBase::getTypeToTransformTo
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:999
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:322
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:112
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1125
llvm::ElementCount
Definition: TypeSize.h:279
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:942
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:387
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1197
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:61
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:59
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:542
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1155
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:50
llvm::details::FixedOrScalableQuantity::isScalable
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:166
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1190
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:708
llvm::Triple::x86
@ x86
Definition: Triple.h:85
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:217
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3431
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:192
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:696
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:52
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:839
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1448
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:216
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:386
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:2012
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:469
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:650
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1196
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:447
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:103
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::GlobalVariable
Definition: GlobalVariable.h:39
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:740
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:919
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1898
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:350
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1259
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::TargetLoweringBase::getPrefLoopAlignment
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
Definition: TargetLoweringBase.cpp:2020
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:138
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1097
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1755
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:360
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:68
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::AttributeList
Definition: Attributes.h:432
llvm::ElementCount::getFixed
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:291
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:144
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1640
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1279
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:527
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:2016
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:950
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3189
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:803
STLExtras.h
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1408
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1263
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1865
llvm::TargetLoweringBase::emitTrailingFence
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Definition: TargetLoweringBase.cpp:2315
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:264
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:288
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:278
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:209
llvm::MVT::i4
@ i4
Definition: MachineValueType.h:45
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:336
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1166
llvm::LoadInst::getAlign
Align getAlign() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:220
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:216
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::EVT::isZeroSized
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:124
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:386
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3454
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
Definition: TargetLowering.h:1113
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2436
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:481
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1191
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:363
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:452
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
Definition: TargetLoweringBase.cpp:917
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::TargetLoweringBase::emitLeadingFence
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: TargetLoweringBase.cpp:2306
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:393
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2419
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::ISD::AVGFLOORU
@ AVGFLOORU
Definition: ISDOpcodes.h:644
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3419
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:354
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1291
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:929
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1170
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:697
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:682
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:724
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1727
llvm::details::FixedOrScalableQuantity::divideCoefficientBy
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:234
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2328
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
InlinePriorityMode::Cost
@ Cost
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1450
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:444
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:228
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:101
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:244
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:792
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2068
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2595
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
Definition: TargetLoweringBase.cpp:958
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:265
Twine.h
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3510
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1138
llvm::MVT::i2
@ i2
Definition: MachineValueType.h:44
SI
@ SI
Definition: SIInstrInfo.cpp:7993
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:927
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:341
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:931
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:949
llvm::StringRef::substr
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:559
llvm::TargetLoweringBase::getMaxPermittedBytesForAlignment
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
Definition: TargetLoweringBase.cpp:2026
llvm::NextPowerOf2
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:437
TargetOpcodes.h
llvm::ISD::DELETED_NODE
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:284
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3469
llvm::AMDGPU::CPol::NT
@ NT
Definition: SIDefines.h:316
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:889
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1189
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::Instruction
Definition: Instruction.h:41
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1917
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1196
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1988
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:926
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:925
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:401
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1550
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:511
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1456
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3446
llvm::MVT::v64i4
@ v64i4
Definition: MachineValueType.h:82
llvm::BitVector
Definition: BitVector.h:75
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::RTLIB::getFPLibCall
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Definition: TargetLoweringBase.cpp:216
llvm::ISD::ABDS
@ ABDS
Definition: ISDOpcodes.h:655
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:613
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1972
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:214
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1177
llvm::TargetOptions::LoopAlignment
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
Definition: TargetOptions.h:373
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:480
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:272
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:933
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:913
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:386
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1277
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:59
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1538
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3487
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::ISD::AVGCEILU
@ AVGCEILU
Definition: ISDOpcodes.h:649
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::TargetLoweringBase::isLoadBitCastBeneficial
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Definition: TargetLoweringBase.cpp:2217
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2370
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3448
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:955
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:2008
llvm::cl::opt< bool >
llvm::ISD::AVGCEILS
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:648
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1996
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1244
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1958
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:301
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:508
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:285
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1615
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:318
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:953
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:920
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1280
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:778
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:486
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:326
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1178
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1194
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:936
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1284
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:302
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:965
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1289
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:210
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:544
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:208
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:496
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:198
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2212
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1132
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:314
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:233
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1276
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2288
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1193
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1264
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:932
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1172
size
i< reg-> size
Definition: README.txt:166
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:341
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1187
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:632
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
Definition: TargetLoweringBase.cpp:2249
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1408
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:119
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1532
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2202
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:257
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:919
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3490
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:688
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1135
llvm::MVT::all_valuetypes
static auto all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1514
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:693
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2272
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1428
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1286
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2151
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MVT::bf16
@ bf16
Definition: MachineValueType.h:55
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::isAcquireOrStronger
bool isAcquireOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:128
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1263
TargetOptions.h
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:956
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1139
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:633
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:173
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:663
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1377
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:724
Triple.h
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::details::FixedOrScalableQuantity::getKnownMinValue
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:163
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:308
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::ISD::ABDU
@ ABDU
Definition: ISDOpcodes.h:656
llvm::isReleaseOrStronger
bool isReleaseOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:933
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:25
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1188
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2593
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3502
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3483
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:921
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1785
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:368
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2409
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:922
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:433
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:177
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1288
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:392
llvm::getApproximateEVTForLLT
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
Definition: LowLevelType.cpp:54
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1186
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:598
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:337
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:207
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:901
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:946
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:165
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:350
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2197
Attributes.h
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1992
llvm::MachineRegisterInfo::hasAtMostUserInstrs
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
Definition: MachineRegisterInfo.cpp:425
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:420
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1451
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2594
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:943
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2387
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:233
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:638
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:838
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:616
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2596
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2091
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:277
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1285
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:295
llvm::TargetLoweringBase::getTypeToPromoteTo
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition: TargetLowering.h:1462
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:374
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1336
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: TargetLoweringBase.cpp:912
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:923
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:573
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:468
llvm::enum_seq
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
Definition: Sequence.h:327
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:174
Enabled
static bool Enabled
Definition: Statistic.cpp:46
llvm::TypeSize
Definition: TypeSize.h:314
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:111
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:616
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1287
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:776
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:234
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:357
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:424
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:772
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:951
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:211
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3163
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2046
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:966
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:215
llvm::force_iteration_on_noniterable_enum
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
Definition: Sequence.h:108
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:501
llvm::ISD::IS_FPCLASS
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:506
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:870
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:496
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
llvm::MVT::v128i2
@ v128i2
Definition: MachineValueType.h:79
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:391
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:60
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1145
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1671
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:214
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1112
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1044
MachineInstrBuilder.h
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2293
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:199
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:814
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:56
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:212
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1286
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1607
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1379
llvm::AttributeList::hasRetAttr
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:779
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2000
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:127
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:292
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:705
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:165
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1545
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2592
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:437
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:813
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:662
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:930
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2463
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:406
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:910
llvm::details::FixedOrScalableQuantity::coefficientNextPowerOf2
constexpr LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:242
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:381
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3283
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3467
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:701
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1192
llvm::MVT::fp_valuetypes
static auto fp_valuetypes()
Definition: MachineValueType.h:1525
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:53
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1290
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:213
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1292
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2245
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1107
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:195
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:924
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:918
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3481
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2207
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::EVT::isFixedLengthVector
bool isFixedLengthVector() const
Definition: ValueTypes.h:164
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:688
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
TargetRegisterInfo.h
llvm::ISD::AVGFLOORS
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:643
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:51
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:357
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
llvm::MVT::VALUETYPE_SIZE
@ VALUETYPE_SIZE
Definition: MachineValueType.h:297
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1195
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:711
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:986
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:201
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:318
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1240
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:232
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393
llvm::LLT
Definition: LowLevelTypeImpl.h:39