LLVM  13.0.0git
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/Analysis/Loads.h"
22 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalValue.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/Module.h"
47 #include "llvm/IR/Type.h"
48 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/Compiler.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <cstring>
61 #include <iterator>
62 #include <string>
63 #include <tuple>
64 #include <utility>
65 
66 using namespace llvm;
67 
69  "jump-is-expensive", cl::init(false),
70  cl::desc("Do not create extra branches to split comparison logic."),
71  cl::Hidden);
72 
74  ("min-jump-table-entries", cl::init(4), cl::Hidden,
75  cl::desc("Set minimum number of entries to use a jump table."));
76 
78  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79  cl::desc("Set maximum size of jump tables."));
80 
81 /// Minimum jump table density for normal functions.
82 static cl::opt<unsigned>
83  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84  cl::desc("Minimum density for building a jump table in "
85  "a normal function"));
86 
87 /// Minimum jump table density for -Os or -Oz functions.
89  "optsize-jump-table-density", cl::init(40), cl::Hidden,
90  cl::desc("Minimum density for building a jump table in "
91  "an optsize function"));
92 
93 // FIXME: This option is only to test if the strict fp operation processed
94 // correctly by preventing mutating strict fp operation to normal fp operation
95 // during development. When the backend supports strict float operation, this
96 // option will be meaningless.
97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98  cl::desc("Don't mutate strict-float node to a legalize node"),
99  cl::init(false), cl::Hidden);
100 
101 static bool darwinHasSinCos(const Triple &TT) {
102  assert(TT.isOSDarwin() && "should be called with darwin triple");
103  // Don't bother with 32 bit x86.
104  if (TT.getArch() == Triple::x86)
105  return false;
106  // Macos < 10.9 has no sincos_stret.
107  if (TT.isMacOSX())
108  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109  // iOS < 7.0 has no sincos_stret.
110  if (TT.isiOS())
111  return !TT.isOSVersionLT(7, 0);
112  // Any other darwin such as WatchOS/TvOS is new enough.
113  return true;
114 }
115 
116 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117 #define HANDLE_LIBCALL(code, name) \
118  setLibcallName(RTLIB::code, name);
119 #include "llvm/IR/RuntimeLibcalls.def"
120 #undef HANDLE_LIBCALL
121  // Initialize calling conventions to their default.
122  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124 
125  // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
126  if (TT.isPPC()) {
127  setLibcallName(RTLIB::ADD_F128, "__addkf3");
128  setLibcallName(RTLIB::SUB_F128, "__subkf3");
129  setLibcallName(RTLIB::MUL_F128, "__mulkf3");
130  setLibcallName(RTLIB::DIV_F128, "__divkf3");
131  setLibcallName(RTLIB::POWI_F128, "__powikf2");
132  setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
133  setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
134  setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
135  setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
136  setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
137  setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
138  setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
139  setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
140  setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
141  setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
142  setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
143  setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
144  setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
145  setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
146  setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
147  setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
148  setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
149  setLibcallName(RTLIB::UNE_F128, "__nekf2");
150  setLibcallName(RTLIB::OGE_F128, "__gekf2");
151  setLibcallName(RTLIB::OLT_F128, "__ltkf2");
152  setLibcallName(RTLIB::OLE_F128, "__lekf2");
153  setLibcallName(RTLIB::OGT_F128, "__gtkf2");
154  setLibcallName(RTLIB::UO_F128, "__unordkf2");
155  }
156 
157  // A few names are different on particular architectures or environments.
158  if (TT.isOSDarwin()) {
159  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
160  // of the gnueabi-style __gnu_*_ieee.
161  // FIXME: What about other targets?
162  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
163  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
164 
165  // Some darwins have an optimized __bzero/bzero function.
166  switch (TT.getArch()) {
167  case Triple::x86:
168  case Triple::x86_64:
169  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
170  setLibcallName(RTLIB::BZERO, "__bzero");
171  break;
172  case Triple::aarch64:
173  case Triple::aarch64_32:
174  setLibcallName(RTLIB::BZERO, "bzero");
175  break;
176  default:
177  break;
178  }
179 
180  if (darwinHasSinCos(TT)) {
181  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
182  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
183  if (TT.isWatchABI()) {
184  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
186  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
188  }
189  }
190  } else {
191  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
192  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
193  }
194 
195  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
196  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
197  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
198  setLibcallName(RTLIB::SINCOS_F64, "sincos");
199  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
200  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
201  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
202  }
203 
204  if (TT.isPS4CPU()) {
205  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
206  setLibcallName(RTLIB::SINCOS_F64, "sincos");
207  }
208 
209  if (TT.isOSOpenBSD()) {
210  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
211  }
212 }
213 
214 /// GetFPLibCall - Helper to return the right libcall for the given floating
215 /// point type, or UNKNOWN_LIBCALL if there is none.
217  RTLIB::Libcall Call_F32,
218  RTLIB::Libcall Call_F64,
219  RTLIB::Libcall Call_F80,
220  RTLIB::Libcall Call_F128,
221  RTLIB::Libcall Call_PPCF128) {
222  return
223  VT == MVT::f32 ? Call_F32 :
224  VT == MVT::f64 ? Call_F64 :
225  VT == MVT::f80 ? Call_F80 :
226  VT == MVT::f128 ? Call_F128 :
227  VT == MVT::ppcf128 ? Call_PPCF128 :
228  RTLIB::UNKNOWN_LIBCALL;
229 }
230 
231 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
232 /// UNKNOWN_LIBCALL if there is none.
234  if (OpVT == MVT::f16) {
235  if (RetVT == MVT::f32)
236  return FPEXT_F16_F32;
237  if (RetVT == MVT::f64)
238  return FPEXT_F16_F64;
239  if (RetVT == MVT::f128)
240  return FPEXT_F16_F128;
241  } else if (OpVT == MVT::f32) {
242  if (RetVT == MVT::f64)
243  return FPEXT_F32_F64;
244  if (RetVT == MVT::f128)
245  return FPEXT_F32_F128;
246  if (RetVT == MVT::ppcf128)
247  return FPEXT_F32_PPCF128;
248  } else if (OpVT == MVT::f64) {
249  if (RetVT == MVT::f128)
250  return FPEXT_F64_F128;
251  else if (RetVT == MVT::ppcf128)
252  return FPEXT_F64_PPCF128;
253  } else if (OpVT == MVT::f80) {
254  if (RetVT == MVT::f128)
255  return FPEXT_F80_F128;
256  }
257 
258  return UNKNOWN_LIBCALL;
259 }
260 
261 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
262 /// UNKNOWN_LIBCALL if there is none.
264  if (RetVT == MVT::f16) {
265  if (OpVT == MVT::f32)
266  return FPROUND_F32_F16;
267  if (OpVT == MVT::f64)
268  return FPROUND_F64_F16;
269  if (OpVT == MVT::f80)
270  return FPROUND_F80_F16;
271  if (OpVT == MVT::f128)
272  return FPROUND_F128_F16;
273  if (OpVT == MVT::ppcf128)
274  return FPROUND_PPCF128_F16;
275  } else if (RetVT == MVT::f32) {
276  if (OpVT == MVT::f64)
277  return FPROUND_F64_F32;
278  if (OpVT == MVT::f80)
279  return FPROUND_F80_F32;
280  if (OpVT == MVT::f128)
281  return FPROUND_F128_F32;
282  if (OpVT == MVT::ppcf128)
283  return FPROUND_PPCF128_F32;
284  } else if (RetVT == MVT::f64) {
285  if (OpVT == MVT::f80)
286  return FPROUND_F80_F64;
287  if (OpVT == MVT::f128)
288  return FPROUND_F128_F64;
289  if (OpVT == MVT::ppcf128)
290  return FPROUND_PPCF128_F64;
291  } else if (RetVT == MVT::f80) {
292  if (OpVT == MVT::f128)
293  return FPROUND_F128_F80;
294  }
295 
296  return UNKNOWN_LIBCALL;
297 }
298 
299 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
300 /// UNKNOWN_LIBCALL if there is none.
302  if (OpVT == MVT::f16) {
303  if (RetVT == MVT::i32)
304  return FPTOSINT_F16_I32;
305  if (RetVT == MVT::i64)
306  return FPTOSINT_F16_I64;
307  if (RetVT == MVT::i128)
308  return FPTOSINT_F16_I128;
309  } else if (OpVT == MVT::f32) {
310  if (RetVT == MVT::i32)
311  return FPTOSINT_F32_I32;
312  if (RetVT == MVT::i64)
313  return FPTOSINT_F32_I64;
314  if (RetVT == MVT::i128)
315  return FPTOSINT_F32_I128;
316  } else if (OpVT == MVT::f64) {
317  if (RetVT == MVT::i32)
318  return FPTOSINT_F64_I32;
319  if (RetVT == MVT::i64)
320  return FPTOSINT_F64_I64;
321  if (RetVT == MVT::i128)
322  return FPTOSINT_F64_I128;
323  } else if (OpVT == MVT::f80) {
324  if (RetVT == MVT::i32)
325  return FPTOSINT_F80_I32;
326  if (RetVT == MVT::i64)
327  return FPTOSINT_F80_I64;
328  if (RetVT == MVT::i128)
329  return FPTOSINT_F80_I128;
330  } else if (OpVT == MVT::f128) {
331  if (RetVT == MVT::i32)
332  return FPTOSINT_F128_I32;
333  if (RetVT == MVT::i64)
334  return FPTOSINT_F128_I64;
335  if (RetVT == MVT::i128)
336  return FPTOSINT_F128_I128;
337  } else if (OpVT == MVT::ppcf128) {
338  if (RetVT == MVT::i32)
339  return FPTOSINT_PPCF128_I32;
340  if (RetVT == MVT::i64)
341  return FPTOSINT_PPCF128_I64;
342  if (RetVT == MVT::i128)
343  return FPTOSINT_PPCF128_I128;
344  }
345  return UNKNOWN_LIBCALL;
346 }
347 
348 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
349 /// UNKNOWN_LIBCALL if there is none.
351  if (OpVT == MVT::f16) {
352  if (RetVT == MVT::i32)
353  return FPTOUINT_F16_I32;
354  if (RetVT == MVT::i64)
355  return FPTOUINT_F16_I64;
356  if (RetVT == MVT::i128)
357  return FPTOUINT_F16_I128;
358  } else if (OpVT == MVT::f32) {
359  if (RetVT == MVT::i32)
360  return FPTOUINT_F32_I32;
361  if (RetVT == MVT::i64)
362  return FPTOUINT_F32_I64;
363  if (RetVT == MVT::i128)
364  return FPTOUINT_F32_I128;
365  } else if (OpVT == MVT::f64) {
366  if (RetVT == MVT::i32)
367  return FPTOUINT_F64_I32;
368  if (RetVT == MVT::i64)
369  return FPTOUINT_F64_I64;
370  if (RetVT == MVT::i128)
371  return FPTOUINT_F64_I128;
372  } else if (OpVT == MVT::f80) {
373  if (RetVT == MVT::i32)
374  return FPTOUINT_F80_I32;
375  if (RetVT == MVT::i64)
376  return FPTOUINT_F80_I64;
377  if (RetVT == MVT::i128)
378  return FPTOUINT_F80_I128;
379  } else if (OpVT == MVT::f128) {
380  if (RetVT == MVT::i32)
381  return FPTOUINT_F128_I32;
382  if (RetVT == MVT::i64)
383  return FPTOUINT_F128_I64;
384  if (RetVT == MVT::i128)
385  return FPTOUINT_F128_I128;
386  } else if (OpVT == MVT::ppcf128) {
387  if (RetVT == MVT::i32)
388  return FPTOUINT_PPCF128_I32;
389  if (RetVT == MVT::i64)
390  return FPTOUINT_PPCF128_I64;
391  if (RetVT == MVT::i128)
392  return FPTOUINT_PPCF128_I128;
393  }
394  return UNKNOWN_LIBCALL;
395 }
396 
397 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
398 /// UNKNOWN_LIBCALL if there is none.
400  if (OpVT == MVT::i32) {
401  if (RetVT == MVT::f16)
402  return SINTTOFP_I32_F16;
403  if (RetVT == MVT::f32)
404  return SINTTOFP_I32_F32;
405  if (RetVT == MVT::f64)
406  return SINTTOFP_I32_F64;
407  if (RetVT == MVT::f80)
408  return SINTTOFP_I32_F80;
409  if (RetVT == MVT::f128)
410  return SINTTOFP_I32_F128;
411  if (RetVT == MVT::ppcf128)
412  return SINTTOFP_I32_PPCF128;
413  } else if (OpVT == MVT::i64) {
414  if (RetVT == MVT::f16)
415  return SINTTOFP_I64_F16;
416  if (RetVT == MVT::f32)
417  return SINTTOFP_I64_F32;
418  if (RetVT == MVT::f64)
419  return SINTTOFP_I64_F64;
420  if (RetVT == MVT::f80)
421  return SINTTOFP_I64_F80;
422  if (RetVT == MVT::f128)
423  return SINTTOFP_I64_F128;
424  if (RetVT == MVT::ppcf128)
425  return SINTTOFP_I64_PPCF128;
426  } else if (OpVT == MVT::i128) {
427  if (RetVT == MVT::f16)
428  return SINTTOFP_I128_F16;
429  if (RetVT == MVT::f32)
430  return SINTTOFP_I128_F32;
431  if (RetVT == MVT::f64)
432  return SINTTOFP_I128_F64;
433  if (RetVT == MVT::f80)
434  return SINTTOFP_I128_F80;
435  if (RetVT == MVT::f128)
436  return SINTTOFP_I128_F128;
437  if (RetVT == MVT::ppcf128)
438  return SINTTOFP_I128_PPCF128;
439  }
440  return UNKNOWN_LIBCALL;
441 }
442 
443 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
444 /// UNKNOWN_LIBCALL if there is none.
446  if (OpVT == MVT::i32) {
447  if (RetVT == MVT::f16)
448  return UINTTOFP_I32_F16;
449  if (RetVT == MVT::f32)
450  return UINTTOFP_I32_F32;
451  if (RetVT == MVT::f64)
452  return UINTTOFP_I32_F64;
453  if (RetVT == MVT::f80)
454  return UINTTOFP_I32_F80;
455  if (RetVT == MVT::f128)
456  return UINTTOFP_I32_F128;
457  if (RetVT == MVT::ppcf128)
458  return UINTTOFP_I32_PPCF128;
459  } else if (OpVT == MVT::i64) {
460  if (RetVT == MVT::f16)
461  return UINTTOFP_I64_F16;
462  if (RetVT == MVT::f32)
463  return UINTTOFP_I64_F32;
464  if (RetVT == MVT::f64)
465  return UINTTOFP_I64_F64;
466  if (RetVT == MVT::f80)
467  return UINTTOFP_I64_F80;
468  if (RetVT == MVT::f128)
469  return UINTTOFP_I64_F128;
470  if (RetVT == MVT::ppcf128)
471  return UINTTOFP_I64_PPCF128;
472  } else if (OpVT == MVT::i128) {
473  if (RetVT == MVT::f16)
474  return UINTTOFP_I128_F16;
475  if (RetVT == MVT::f32)
476  return UINTTOFP_I128_F32;
477  if (RetVT == MVT::f64)
478  return UINTTOFP_I128_F64;
479  if (RetVT == MVT::f80)
480  return UINTTOFP_I128_F80;
481  if (RetVT == MVT::f128)
482  return UINTTOFP_I128_F128;
483  if (RetVT == MVT::ppcf128)
484  return UINTTOFP_I128_PPCF128;
485  }
486  return UNKNOWN_LIBCALL;
487 }
488 
490  return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
491  POWI_PPCF128);
492 }
493 
495  MVT VT) {
496  unsigned ModeN, ModelN;
497  switch (VT.SimpleTy) {
498  case MVT::i8:
499  ModeN = 0;
500  break;
501  case MVT::i16:
502  ModeN = 1;
503  break;
504  case MVT::i32:
505  ModeN = 2;
506  break;
507  case MVT::i64:
508  ModeN = 3;
509  break;
510  case MVT::i128:
511  ModeN = 4;
512  break;
513  default:
514  return UNKNOWN_LIBCALL;
515  }
516 
517  switch (Order) {
519  ModelN = 0;
520  break;
522  ModelN = 1;
523  break;
525  ModelN = 2;
526  break;
529  ModelN = 3;
530  break;
531  default:
532  return UNKNOWN_LIBCALL;
533  }
534 
535 #define LCALLS(A, B) \
536  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
537 #define LCALL5(A) \
538  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
539  switch (Opc) {
540  case ISD::ATOMIC_CMP_SWAP: {
541  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
542  return LC[ModeN][ModelN];
543  }
544  case ISD::ATOMIC_SWAP: {
545  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
546  return LC[ModeN][ModelN];
547  }
548  case ISD::ATOMIC_LOAD_ADD: {
549  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
550  return LC[ModeN][ModelN];
551  }
552  case ISD::ATOMIC_LOAD_OR: {
553  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
554  return LC[ModeN][ModelN];
555  }
556  case ISD::ATOMIC_LOAD_CLR: {
557  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
558  return LC[ModeN][ModelN];
559  }
560  case ISD::ATOMIC_LOAD_XOR: {
561  const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
562  return LC[ModeN][ModelN];
563  }
564  default:
565  return UNKNOWN_LIBCALL;
566  }
567 #undef LCALLS
568 #undef LCALL5
569 }
570 
571 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
572 #define OP_TO_LIBCALL(Name, Enum) \
573  case Name: \
574  switch (VT.SimpleTy) { \
575  default: \
576  return UNKNOWN_LIBCALL; \
577  case MVT::i8: \
578  return Enum##_1; \
579  case MVT::i16: \
580  return Enum##_2; \
581  case MVT::i32: \
582  return Enum##_4; \
583  case MVT::i64: \
584  return Enum##_8; \
585  case MVT::i128: \
586  return Enum##_16; \
587  }
588 
589  switch (Opc) {
590  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
591  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
592  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
593  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
594  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
595  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
596  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
597  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
598  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
599  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
600  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
601  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
602  }
603 
604 #undef OP_TO_LIBCALL
605 
606  return UNKNOWN_LIBCALL;
607 }
608 
610  switch (ElementSize) {
611  case 1:
612  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
613  case 2:
614  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
615  case 4:
616  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
617  case 8:
618  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
619  case 16:
620  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
621  default:
622  return UNKNOWN_LIBCALL;
623  }
624 }
625 
627  switch (ElementSize) {
628  case 1:
629  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
630  case 2:
631  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
632  case 4:
633  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
634  case 8:
635  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
636  case 16:
637  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
638  default:
639  return UNKNOWN_LIBCALL;
640  }
641 }
642 
644  switch (ElementSize) {
645  case 1:
646  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
647  case 2:
648  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
649  case 4:
650  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
651  case 8:
652  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
653  case 16:
654  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
655  default:
656  return UNKNOWN_LIBCALL;
657  }
658 }
659 
660 /// InitCmpLibcallCCs - Set default comparison libcall CC.
661 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
662  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
663  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
664  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
665  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
666  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
667  CCs[RTLIB::UNE_F32] = ISD::SETNE;
668  CCs[RTLIB::UNE_F64] = ISD::SETNE;
669  CCs[RTLIB::UNE_F128] = ISD::SETNE;
670  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
671  CCs[RTLIB::OGE_F32] = ISD::SETGE;
672  CCs[RTLIB::OGE_F64] = ISD::SETGE;
673  CCs[RTLIB::OGE_F128] = ISD::SETGE;
674  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
675  CCs[RTLIB::OLT_F32] = ISD::SETLT;
676  CCs[RTLIB::OLT_F64] = ISD::SETLT;
677  CCs[RTLIB::OLT_F128] = ISD::SETLT;
678  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
679  CCs[RTLIB::OLE_F32] = ISD::SETLE;
680  CCs[RTLIB::OLE_F64] = ISD::SETLE;
681  CCs[RTLIB::OLE_F128] = ISD::SETLE;
682  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
683  CCs[RTLIB::OGT_F32] = ISD::SETGT;
684  CCs[RTLIB::OGT_F64] = ISD::SETGT;
685  CCs[RTLIB::OGT_F128] = ISD::SETGT;
686  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
687  CCs[RTLIB::UO_F32] = ISD::SETNE;
688  CCs[RTLIB::UO_F64] = ISD::SETNE;
689  CCs[RTLIB::UO_F128] = ISD::SETNE;
690  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
691 }
692 
693 /// NOTE: The TargetMachine owns TLOF.
695  initActions();
696 
697  // Perform these initializations only once.
699  MaxLoadsPerMemcmp = 8;
703  HasMultipleConditionRegisters = false;
704  HasExtractBitsInsn = false;
705  JumpIsExpensive = JumpIsExpensiveOverride;
707  EnableExtLdPromotion = false;
708  StackPointerRegisterToSaveRestore = 0;
709  BooleanContents = UndefinedBooleanContent;
710  BooleanFloatContents = UndefinedBooleanContent;
711  BooleanVectorContents = UndefinedBooleanContent;
712  SchedPreferenceInfo = Sched::ILP;
715  // TODO: the default will be switched to 0 in the next commit, along
716  // with the Target-specific changes necessary.
717  MaxAtomicSizeInBitsSupported = 1024;
718 
719  MinCmpXchgSizeInBits = 0;
720  SupportsUnalignedAtomics = false;
721 
722  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
723 
724  InitLibcalls(TM.getTargetTriple());
725  InitCmpLibcallCCs(CmpLibcallCCs);
726 }
727 
729  // All operations default to being supported.
730  memset(OpActions, 0, sizeof(OpActions));
731  memset(LoadExtActions, 0, sizeof(LoadExtActions));
732  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
733  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
734  memset(CondCodeActions, 0, sizeof(CondCodeActions));
735  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
736  std::fill(std::begin(TargetDAGCombineArray),
737  std::end(TargetDAGCombineArray), 0);
738 
739  for (MVT VT : MVT::fp_valuetypes()) {
740  MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
741  if (IntVT.isValid()) {
744  }
745  }
746 
747  // Set default actions for various operations.
748  for (MVT VT : MVT::all_valuetypes()) {
749  // Default all indexed load / store to expand.
750  for (unsigned IM = (unsigned)ISD::PRE_INC;
751  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
752  setIndexedLoadAction(IM, VT, Expand);
753  setIndexedStoreAction(IM, VT, Expand);
756  }
757 
758  // Most backends expect to see the node which just returns the value loaded.
760 
761  // These operations default to expand.
794 
795  // Overflow operations default to expand
802 
803  // ADDCARRY operations default to expand
809 
810  // ADDC/ADDE/SUBC/SUBE default to expand.
815 
816  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
819 
822 
823  // These library functions default to expand.
827 
828  // These operations default to expand for vector types.
829  if (VT.isVector()) {
836  }
837 
838  // Constrained floating-point operations default to expand.
839 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
840  setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
841 #include "llvm/IR/ConstrainedOps.def"
842 
843  // For most targets @llvm.get.dynamic.area.offset just returns 0.
845 
846  // Vector reduction default to expand.
862 
863  // Named vector shuffles default to expand.
865  }
866 
867  // Most targets ignore the @llvm.prefetch intrinsic.
869 
870  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
872 
873  // ConstantFP nodes default to expand. Targets can either change this to
874  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
875  // to optimize expansions for certain constants.
881 
882  // These library functions default to expand.
883  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
901  }
902 
903  // Default ISD::TRAP to expand (which turns it into abort).
905 
906  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
907  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
909 
911 }
912 
914  EVT) const {
915  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
916 }
917 
919  bool LegalTypes) const {
920  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
921  if (LHSTy.isVector())
922  return LHSTy;
923  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
924  : getPointerTy(DL);
925 }
926 
927 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
928  assert(isTypeLegal(VT));
929  switch (Op) {
930  default:
931  return false;
932  case ISD::SDIV:
933  case ISD::UDIV:
934  case ISD::SREM:
935  case ISD::UREM:
936  return true;
937  }
938 }
939 
941  unsigned DestAS) const {
942  return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
943 }
944 
946  // If the command-line option was specified, ignore this request.
948  JumpIsExpensive = isExpensive;
949 }
950 
952 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
953  // If this is a simple type, use the ComputeRegisterProp mechanism.
954  if (VT.isSimple()) {
955  MVT SVT = VT.getSimpleVT();
956  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
957  MVT NVT = TransformToType[SVT.SimpleTy];
958  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
959 
960  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
961  LA == TypeSoftPromoteHalf ||
962  (NVT.isVector() ||
963  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
964  "Promote may not follow Expand or Promote");
965 
966  if (LA == TypeSplitVector)
967  return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
968  if (LA == TypeScalarizeVector)
969  return LegalizeKind(LA, SVT.getVectorElementType());
970  return LegalizeKind(LA, NVT);
971  }
972 
973  // Handle Extended Scalar Types.
974  if (!VT.isVector()) {
975  assert(VT.isInteger() && "Float types must be simple");
976  unsigned BitSize = VT.getSizeInBits();
977  // First promote to a power-of-two size, then expand if necessary.
978  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
979  EVT NVT = VT.getRoundIntegerType(Context);
980  assert(NVT != VT && "Unable to round integer VT");
981  LegalizeKind NextStep = getTypeConversion(Context, NVT);
982  // Avoid multi-step promotion.
983  if (NextStep.first == TypePromoteInteger)
984  return NextStep;
985  // Return rounded integer type.
986  return LegalizeKind(TypePromoteInteger, NVT);
987  }
988 
991  }
992 
993  // Handle vector types.
994  ElementCount NumElts = VT.getVectorElementCount();
995  EVT EltVT = VT.getVectorElementType();
996 
997  // Vectors with only one element are always scalarized.
998  if (NumElts.isScalar())
999  return LegalizeKind(TypeScalarizeVector, EltVT);
1000 
1001  // Try to widen vector elements until the element type is a power of two and
1002  // promote it to a legal type later on, for example:
1003  // <3 x i8> -> <4 x i8> -> <4 x i32>
1004  if (EltVT.isInteger()) {
1005  // Vectors with a number of elements that is not a power of two are always
1006  // widened, for example <3 x i8> -> <4 x i8>.
1007  if (!VT.isPow2VectorType()) {
1008  NumElts = NumElts.coefficientNextPowerOf2();
1009  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1010  return LegalizeKind(TypeWidenVector, NVT);
1011  }
1012 
1013  // Examine the element type.
1014  LegalizeKind LK = getTypeConversion(Context, EltVT);
1015 
1016  // If type is to be expanded, split the vector.
1017  // <4 x i140> -> <2 x i140>
1018  if (LK.first == TypeExpandInteger) {
1019  if (VT.getVectorElementCount().isScalable())
1023  }
1024 
1025  // Promote the integer element types until a legal vector type is found
1026  // or until the element integer type is too big. If a legal type was not
1027  // found, fallback to the usual mechanism of widening/splitting the
1028  // vector.
1029  EVT OldEltVT = EltVT;
1030  while (true) {
1031  // Increase the bitwidth of the element to the next pow-of-two
1032  // (which is greater than 8 bits).
1033  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1035 
1036  // Stop trying when getting a non-simple element type.
1037  // Note that vector elements may be greater than legal vector element
1038  // types. Example: X86 XMM registers hold 64bit element on 32bit
1039  // systems.
1040  if (!EltVT.isSimple())
1041  break;
1042 
1043  // Build a new vector type and check if it is legal.
1044  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1045  // Found a legal promoted vector type.
1046  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1048  EVT::getVectorVT(Context, EltVT, NumElts));
1049  }
1050 
1051  // Reset the type to the unexpanded type if we did not find a legal vector
1052  // type with a promoted vector element type.
1053  EltVT = OldEltVT;
1054  }
1055 
1056  // Try to widen the vector until a legal type is found.
1057  // If there is no wider legal type, split the vector.
1058  while (true) {
1059  // Round up to the next power of 2.
1060  NumElts = NumElts.coefficientNextPowerOf2();
1061 
1062  // If there is no simple vector type with this many elements then there
1063  // cannot be a larger legal vector type. Note that this assumes that
1064  // there are no skipped intermediate vector types in the simple types.
1065  if (!EltVT.isSimple())
1066  break;
1067  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1068  if (LargerVector == MVT())
1069  break;
1070 
1071  // If this type is legal then widen the vector.
1072  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1073  return LegalizeKind(TypeWidenVector, LargerVector);
1074  }
1075 
1076  // Widen odd vectors to next power of two.
1077  if (!VT.isPow2VectorType()) {
1078  EVT NVT = VT.getPow2VectorType(Context);
1079  return LegalizeKind(TypeWidenVector, NVT);
1080  }
1081 
1084 
1085  // Vectors with illegal element types are expanded.
1086  EVT NVT = EVT::getVectorVT(Context, EltVT,
1088  return LegalizeKind(TypeSplitVector, NVT);
1089 }
1090 
1091 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1092  unsigned &NumIntermediates,
1093  MVT &RegisterVT,
1094  TargetLoweringBase *TLI) {
1095  // Figure out the right, legal destination reg to copy into.
1097  MVT EltTy = VT.getVectorElementType();
1098 
1099  unsigned NumVectorRegs = 1;
1100 
1101  // Scalable vectors cannot be scalarized, so splitting or widening is
1102  // required.
1103  if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1105  "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1106 
1107  // FIXME: We don't support non-power-of-2-sized vectors for now.
1108  // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1109  if (!isPowerOf2_32(EC.getKnownMinValue())) {
1110  // Split EC to unit size (scalable property is preserved).
1111  NumVectorRegs = EC.getKnownMinValue();
1112  EC = ElementCount::getFixed(1);
1113  }
1114 
1115  // Divide the input until we get to a supported size. This will
1116  // always end up with an EC that represent a scalar or a scalable
1117  // scalar.
1118  while (EC.getKnownMinValue() > 1 &&
1119  !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1120  EC = EC.divideCoefficientBy(2);
1121  NumVectorRegs <<= 1;
1122  }
1123 
1124  NumIntermediates = NumVectorRegs;
1125 
1126  MVT NewVT = MVT::getVectorVT(EltTy, EC);
1127  if (!TLI->isTypeLegal(NewVT))
1128  NewVT = EltTy;
1129  IntermediateVT = NewVT;
1130 
1131  unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1132 
1133  // Convert sizes such as i33 to i64.
1134  if (!isPowerOf2_32(LaneSizeInBits))
1135  LaneSizeInBits = NextPowerOf2(LaneSizeInBits);
1136 
1137  MVT DestVT = TLI->getRegisterType(NewVT);
1138  RegisterVT = DestVT;
1139  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1140  return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1141 
1142  // Otherwise, promotion or legal types use the same number of registers as
1143  // the vector decimated to the appropriate level.
1144  return NumVectorRegs;
1145 }
1146 
1147 /// isLegalRC - Return true if the value types that can be represented by the
1148 /// specified register class are all legal.
1150  const TargetRegisterClass &RC) const {
1151  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1152  if (isTypeLegal(*I))
1153  return true;
1154  return false;
1155 }
1156 
1157 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1158 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1161  MachineBasicBlock *MBB) const {
1162  MachineInstr *MI = &InitialMI;
1163  MachineFunction &MF = *MI->getMF();
1164  MachineFrameInfo &MFI = MF.getFrameInfo();
1165 
1166  // We're handling multiple types of operands here:
1167  // PATCHPOINT MetaArgs - live-in, read only, direct
1168  // STATEPOINT Deopt Spill - live-through, read only, indirect
1169  // STATEPOINT Deopt Alloca - live-through, read only, direct
1170  // (We're currently conservative and mark the deopt slots read/write in
1171  // practice.)
1172  // STATEPOINT GC Spill - live-through, read/write, indirect
1173  // STATEPOINT GC Alloca - live-through, read/write, direct
1174  // The live-in vs live-through is handled already (the live through ones are
1175  // all stack slots), but we need to handle the different type of stackmap
1176  // operands and memory effects here.
1177 
1178  if (!llvm::any_of(MI->operands(),
1179  [](MachineOperand &Operand) { return Operand.isFI(); }))
1180  return MBB;
1181 
1182  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1183 
1184  // Inherit previous memory operands.
1185  MIB.cloneMemRefs(*MI);
1186 
1187  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1188  MachineOperand &MO = MI->getOperand(i);
1189  if (!MO.isFI()) {
1190  // Index of Def operand this Use it tied to.
1191  // Since Defs are coming before Uses, if Use is tied, then
1192  // index of Def must be smaller that index of that Use.
1193  // Also, Defs preserve their position in new MI.
1194  unsigned TiedTo = i;
1195  if (MO.isReg() && MO.isTied())
1196  TiedTo = MI->findTiedOperandIdx(i);
1197  MIB.add(MO);
1198  if (TiedTo < i)
1199  MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1200  continue;
1201  }
1202 
1203  // foldMemoryOperand builds a new MI after replacing a single FI operand
1204  // with the canonical set of five x86 addressing-mode operands.
1205  int FI = MO.getIndex();
1206 
1207  // Add frame index operands recognized by stackmaps.cpp
1208  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1209  // indirect-mem-ref tag, size, #FI, offset.
1210  // Used for spills inserted by StatepointLowering. This codepath is not
1211  // used for patchpoints/stackmaps at all, for these spilling is done via
1212  // foldMemoryOperand callback only.
1213  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1214  MIB.addImm(StackMaps::IndirectMemRefOp);
1215  MIB.addImm(MFI.getObjectSize(FI));
1216  MIB.add(MO);
1217  MIB.addImm(0);
1218  } else {
1219  // direct-mem-ref tag, #FI, offset.
1220  // Used by patchpoint, and direct alloca arguments to statepoints
1221  MIB.addImm(StackMaps::DirectMemRefOp);
1222  MIB.add(MO);
1223  MIB.addImm(0);
1224  }
1225 
1226  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1227 
1228  // Add a new memory operand for this FI.
1229  assert(MFI.getObjectOffset(FI) != -1);
1230 
1231  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1232  // PATCHPOINT should be updated to do the same. (TODO)
1233  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1234  auto Flags = MachineMemOperand::MOLoad;
1236  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1237  MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));
1238  MIB->addMemOperand(MF, MMO);
1239  }
1240  }
1242  MI->eraseFromParent();
1243  return MBB;
1244 }
1245 
1246 /// findRepresentativeClass - Return the largest legal super-reg register class
1247 /// of the register class for the specified type and its associated "cost".
1248 // This function is in TargetLowering because it uses RegClassForVT which would
1249 // need to be moved to TargetRegisterInfo and would necessitate moving
1250 // isTypeLegal over as well - a massive change that would just require
1251 // TargetLowering having a TargetRegisterInfo class member that it would use.
1252 std::pair<const TargetRegisterClass *, uint8_t>
1254  MVT VT) const {
1255  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1256  if (!RC)
1257  return std::make_pair(RC, 0);
1258 
1259  // Compute the set of all super-register classes.
1260  BitVector SuperRegRC(TRI->getNumRegClasses());
1261  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1262  SuperRegRC.setBitsInMask(RCI.getMask());
1263 
1264  // Find the first legal register class with the largest spill size.
1265  const TargetRegisterClass *BestRC = RC;
1266  for (unsigned i : SuperRegRC.set_bits()) {
1267  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1268  // We want the largest possible spill size.
1269  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1270  continue;
1271  if (!isLegalRC(*TRI, *SuperRC))
1272  continue;
1273  BestRC = SuperRC;
1274  }
1275  return std::make_pair(BestRC, 1);
1276 }
1277 
1278 /// computeRegisterProperties - Once all of the register classes are added,
1279 /// this allows us to compute derived properties we expose.
1281  const TargetRegisterInfo *TRI) {
1283  "Too many value types for ValueTypeActions to hold!");
1284 
1285  // Everything defaults to needing one register.
1286  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1287  NumRegistersForVT[i] = 1;
1288  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1289  }
1290  // ...except isVoid, which doesn't need any registers.
1291  NumRegistersForVT[MVT::isVoid] = 0;
1292 
1293  // Find the largest integer register class.
1294  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1295  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1296  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1297 
1298  // Every integer value type larger than this largest register takes twice as
1299  // many registers to represent as the previous ValueType.
1300  for (unsigned ExpandedReg = LargestIntReg + 1;
1301  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1302  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1303  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1304  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1305  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1307  }
1308 
1309  // Inspect all of the ValueType's smaller than the largest integer
1310  // register to see which ones need promotion.
1311  unsigned LegalIntReg = LargestIntReg;
1312  for (unsigned IntReg = LargestIntReg - 1;
1313  IntReg >= (unsigned)MVT::i1; --IntReg) {
1314  MVT IVT = (MVT::SimpleValueType)IntReg;
1315  if (isTypeLegal(IVT)) {
1316  LegalIntReg = IntReg;
1317  } else {
1318  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1319  (MVT::SimpleValueType)LegalIntReg;
1320  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1321  }
1322  }
1323 
1324  // ppcf128 type is really two f64's.
1325  if (!isTypeLegal(MVT::ppcf128)) {
1326  if (isTypeLegal(MVT::f64)) {
1327  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1328  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1329  TransformToType[MVT::ppcf128] = MVT::f64;
1330  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1331  } else {
1332  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1333  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1334  TransformToType[MVT::ppcf128] = MVT::i128;
1335  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1336  }
1337  }
1338 
1339  // Decide how to handle f128. If the target does not have native f128 support,
1340  // expand it to i128 and we will be generating soft float library calls.
1341  if (!isTypeLegal(MVT::f128)) {
1342  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1343  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1344  TransformToType[MVT::f128] = MVT::i128;
1345  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1346  }
1347 
1348  // Decide how to handle f64. If the target does not have native f64 support,
1349  // expand it to i64 and we will be generating soft float library calls.
1350  if (!isTypeLegal(MVT::f64)) {
1351  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1352  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1353  TransformToType[MVT::f64] = MVT::i64;
1354  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1355  }
1356 
1357  // Decide how to handle f32. If the target does not have native f32 support,
1358  // expand it to i32 and we will be generating soft float library calls.
1359  if (!isTypeLegal(MVT::f32)) {
1360  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1361  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1362  TransformToType[MVT::f32] = MVT::i32;
1363  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1364  }
1365 
1366  // Decide how to handle f16. If the target does not have native f16 support,
1367  // promote it to f32, because there are no f16 library calls (except for
1368  // conversions).
1369  if (!isTypeLegal(MVT::f16)) {
1370  // Allow targets to control how we legalize half.
1371  if (softPromoteHalfType()) {
1372  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1373  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1374  TransformToType[MVT::f16] = MVT::f32;
1375  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1376  } else {
1377  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1378  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1379  TransformToType[MVT::f16] = MVT::f32;
1380  ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1381  }
1382  }
1383 
1384  // Loop over all of the vector value types to see which need transformations.
1385  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1386  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1387  MVT VT = (MVT::SimpleValueType) i;
1388  if (isTypeLegal(VT))
1389  continue;
1390 
1391  MVT EltVT = VT.getVectorElementType();
1393  bool IsLegalWiderType = false;
1394  bool IsScalable = VT.isScalableVector();
1395  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1396  switch (PreferredAction) {
1397  case TypePromoteInteger: {
1398  MVT::SimpleValueType EndVT = IsScalable ?
1401  // Try to promote the elements of integer vectors. If no legal
1402  // promotion was found, fall through to the widen-vector method.
1403  for (unsigned nVT = i + 1;
1404  (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1405  MVT SVT = (MVT::SimpleValueType) nVT;
1406  // Promote vectors of integers to vectors with the same number
1407  // of elements, with a wider element type.
1408  if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1409  SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1410  TransformToType[i] = SVT;
1411  RegisterTypeForVT[i] = SVT;
1412  NumRegistersForVT[i] = 1;
1413  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1414  IsLegalWiderType = true;
1415  break;
1416  }
1417  }
1418  if (IsLegalWiderType)
1419  break;
1421  }
1422 
1423  case TypeWidenVector:
1424  if (isPowerOf2_32(EC.getKnownMinValue())) {
1425  // Try to widen the vector.
1426  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1427  MVT SVT = (MVT::SimpleValueType) nVT;
1428  if (SVT.getVectorElementType() == EltVT &&
1429  SVT.isScalableVector() == IsScalable &&
1431  EC.getKnownMinValue() &&
1432  isTypeLegal(SVT)) {
1433  TransformToType[i] = SVT;
1434  RegisterTypeForVT[i] = SVT;
1435  NumRegistersForVT[i] = 1;
1436  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1437  IsLegalWiderType = true;
1438  break;
1439  }
1440  }
1441  if (IsLegalWiderType)
1442  break;
1443  } else {
1444  // Only widen to the next power of 2 to keep consistency with EVT.
1445  MVT NVT = VT.getPow2VectorType();
1446  if (isTypeLegal(NVT)) {
1447  TransformToType[i] = NVT;
1448  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1449  RegisterTypeForVT[i] = NVT;
1450  NumRegistersForVT[i] = 1;
1451  break;
1452  }
1453  }
1455 
1456  case TypeSplitVector:
1457  case TypeScalarizeVector: {
1458  MVT IntermediateVT;
1459  MVT RegisterVT;
1460  unsigned NumIntermediates;
1461  unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1462  NumIntermediates, RegisterVT, this);
1463  NumRegistersForVT[i] = NumRegisters;
1464  assert(NumRegistersForVT[i] == NumRegisters &&
1465  "NumRegistersForVT size cannot represent NumRegisters!");
1466  RegisterTypeForVT[i] = RegisterVT;
1467 
1468  MVT NVT = VT.getPow2VectorType();
1469  if (NVT == VT) {
1470  // Type is already a power of 2. The default action is to split.
1471  TransformToType[i] = MVT::Other;
1472  if (PreferredAction == TypeScalarizeVector)
1473  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1474  else if (PreferredAction == TypeSplitVector)
1475  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1476  else if (EC.getKnownMinValue() > 1)
1477  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1478  else
1479  ValueTypeActions.setTypeAction(VT, EC.isScalable()
1482  } else {
1483  TransformToType[i] = NVT;
1484  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1485  }
1486  break;
1487  }
1488  default:
1489  llvm_unreachable("Unknown vector legalization action!");
1490  }
1491  }
1492 
1493  // Determine the 'representative' register class for each value type.
1494  // An representative register class is the largest (meaning one which is
1495  // not a sub-register class / subreg register class) legal register class for
1496  // a group of value types. For example, on i386, i8, i16, and i32
1497  // representative would be GR32; while on x86_64 it's GR64.
1498  for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1499  const TargetRegisterClass* RRC;
1500  uint8_t Cost;
1501  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1502  RepRegClassForVT[i] = RRC;
1503  RepRegClassCostForVT[i] = Cost;
1504  }
1505 }
1506 
1508  EVT VT) const {
1509  assert(!VT.isVector() && "No default SetCC type for vectors!");
1510  return getPointerTy(DL).SimpleTy;
1511 }
1512 
1514  return MVT::i32; // return the default value
1515 }
1516 
1517 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1518 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1519 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1520 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1521 ///
1522 /// This method returns the number of registers needed, and the VT for each
1523 /// register. It also returns the VT and quantity of the intermediate values
1524 /// before they are promoted/expanded.
1526  EVT VT, EVT &IntermediateVT,
1527  unsigned &NumIntermediates,
1528  MVT &RegisterVT) const {
1529  ElementCount EltCnt = VT.getVectorElementCount();
1530 
1531  // If there is a wider vector type with the same element type as this one,
1532  // or a promoted vector type that has the same number of elements which
1533  // are wider, then we should convert to that legal vector type.
1534  // This handles things like <2 x float> -> <4 x float> and
1535  // <4 x i1> -> <4 x i32>.
1537  if (!EltCnt.isScalar() &&
1538  (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1539  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1540  if (isTypeLegal(RegisterEVT)) {
1541  IntermediateVT = RegisterEVT;
1542  RegisterVT = RegisterEVT.getSimpleVT();
1543  NumIntermediates = 1;
1544  return 1;
1545  }
1546  }
1547 
1548  // Figure out the right, legal destination reg to copy into.
1549  EVT EltTy = VT.getVectorElementType();
1550 
1551  unsigned NumVectorRegs = 1;
1552 
1553  // Scalable vectors cannot be scalarized, so handle the legalisation of the
1554  // types like done elsewhere in SelectionDAG.
1555  if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) {
1556  LegalizeKind LK;
1557  EVT PartVT = VT;
1558  do {
1559  // Iterate until we've found a legal (part) type to hold VT.
1560  LK = getTypeConversion(Context, PartVT);
1561  PartVT = LK.second;
1562  } while (LK.first != TypeLegal);
1563 
1564  NumIntermediates = VT.getVectorElementCount().getKnownMinValue() /
1566 
1567  // FIXME: This code needs to be extended to handle more complex vector
1568  // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only
1569  // supported cases are vectors that are broken down into equal parts
1570  // such as nxv6i64 -> 3 x nxv2i64.
1571  assert((PartVT.getVectorElementCount() * NumIntermediates) ==
1572  VT.getVectorElementCount() &&
1573  "Expected an integer multiple of PartVT");
1574  IntermediateVT = PartVT;
1575  RegisterVT = getRegisterType(Context, IntermediateVT);
1576  return NumIntermediates;
1577  }
1578 
1579  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1580  // we could break down into LHS/RHS like LegalizeDAG does.
1581  if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1582  NumVectorRegs = EltCnt.getKnownMinValue();
1583  EltCnt = ElementCount::getFixed(1);
1584  }
1585 
1586  // Divide the input until we get to a supported size. This will always
1587  // end with a scalar if the target doesn't support vectors.
1588  while (EltCnt.getKnownMinValue() > 1 &&
1589  !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1590  EltCnt = EltCnt.divideCoefficientBy(2);
1591  NumVectorRegs <<= 1;
1592  }
1593 
1594  NumIntermediates = NumVectorRegs;
1595 
1596  EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1597  if (!isTypeLegal(NewVT))
1598  NewVT = EltTy;
1599  IntermediateVT = NewVT;
1600 
1601  MVT DestVT = getRegisterType(Context, NewVT);
1602  RegisterVT = DestVT;
1603 
1604  if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1605  TypeSize NewVTSize = NewVT.getSizeInBits();
1606  // Convert sizes such as i33 to i64.
1607  if (!isPowerOf2_32(NewVTSize.getKnownMinSize()))
1608  NewVTSize = NewVTSize.coefficientNextPowerOf2();
1609  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1610  }
1611 
1612  // Otherwise, promotion or legal types use the same number of registers as
1613  // the vector decimated to the appropriate level.
1614  return NumVectorRegs;
1615 }
1616 
1618  uint64_t NumCases,
1619  uint64_t Range,
1620  ProfileSummaryInfo *PSI,
1621  BlockFrequencyInfo *BFI) const {
1622  // FIXME: This function check the maximum table size and density, but the
1623  // minimum size is not checked. It would be nice if the minimum size is
1624  // also combined within this function. Currently, the minimum size check is
1625  // performed in findJumpTable() in SelectionDAGBuiler and
1626  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1627  const bool OptForSize =
1628  SI->getParent()->getParent()->hasOptSize() ||
1629  llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1630  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1631  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1632 
1633  // Check whether the number of cases is small enough and
1634  // the range is dense enough for a jump table.
1635  return (OptForSize || Range <= MaxJumpTableSize) &&
1636  (NumCases * 100 >= Range * MinDensity);
1637 }
1638 
1639 /// Get the EVTs and ArgFlags collections that represent the legalized return
1640 /// type of the given function. This does not require a DAG or a return value,
1641 /// and is suitable for use before any DAGs for the function are constructed.
1642 /// TODO: Move this out of TargetLowering.cpp.
1644  AttributeList attr,
1646  const TargetLowering &TLI, const DataLayout &DL) {
1647  SmallVector<EVT, 4> ValueVTs;
1648  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1649  unsigned NumValues = ValueVTs.size();
1650  if (NumValues == 0) return;
1651 
1652  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1653  EVT VT = ValueVTs[j];
1654  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1655 
1656  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1657  ExtendKind = ISD::SIGN_EXTEND;
1658  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1659  ExtendKind = ISD::ZERO_EXTEND;
1660 
1661  // FIXME: C calling convention requires the return type to be promoted to
1662  // at least 32-bit. But this is not necessary for non-C calling
1663  // conventions. The frontend should mark functions whose return values
1664  // require promoting with signext or zeroext attributes.
1665  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1666  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1667  if (VT.bitsLT(MinVT))
1668  VT = MinVT;
1669  }
1670 
1671  unsigned NumParts =
1672  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1673  MVT PartVT =
1674  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1675 
1676  // 'inreg' on function refers to return value
1677  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1678  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1679  Flags.setInReg();
1680 
1681  // Propagate extension type if any
1682  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1683  Flags.setSExt();
1684  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1685  Flags.setZExt();
1686 
1687  for (unsigned i = 0; i < NumParts; ++i)
1688  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1689  }
1690 }
1691 
1692 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1693 /// function arguments in the caller parameter area. This is the actual
1694 /// alignment, not its logarithm.
1696  const DataLayout &DL) const {
1697  return DL.getABITypeAlign(Ty).value();
1698 }
1699 
1701  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1702  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
1703  // Check if the specified alignment is sufficient based on the data layout.
1704  // TODO: While using the data layout works in practice, a better solution
1705  // would be to implement this check directly (make this a virtual function).
1706  // For example, the ABI alignment may change based on software platform while
1707  // this function should only be affected by hardware implementation.
1708  Type *Ty = VT.getTypeForEVT(Context);
1709  if (Alignment >= DL.getABITypeAlign(Ty)) {
1710  // Assume that an access that meets the ABI-specified alignment is fast.
1711  if (Fast != nullptr)
1712  *Fast = true;
1713  return true;
1714  }
1715 
1716  // This is a misaligned access.
1717  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1718 }
1719 
1721  LLVMContext &Context, const DataLayout &DL, EVT VT,
1722  const MachineMemOperand &MMO, bool *Fast) const {
1724  MMO.getAlign(), MMO.getFlags(), Fast);
1725 }
1726 
1728  const DataLayout &DL, EVT VT,
1729  unsigned AddrSpace, Align Alignment,
1731  bool *Fast) const {
1732  return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1733  Flags, Fast);
1734 }
1735 
1737  const DataLayout &DL, EVT VT,
1738  const MachineMemOperand &MMO,
1739  bool *Fast) const {
1740  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1741  MMO.getFlags(), Fast);
1742 }
1743 
1745  const DataLayout &DL, LLT Ty,
1746  const MachineMemOperand &MMO,
1747  bool *Fast) const {
1749  MMO.getAlign(), MMO.getFlags(), Fast);
1750 }
1751 
1752 //===----------------------------------------------------------------------===//
1753 // TargetTransformInfo Helpers
1754 //===----------------------------------------------------------------------===//
1755 
1757  enum InstructionOpcodes {
1758 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1759 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1760 #include "llvm/IR/Instruction.def"
1761  };
1762  switch (static_cast<InstructionOpcodes>(Opcode)) {
1763  case Ret: return 0;
1764  case Br: return 0;
1765  case Switch: return 0;
1766  case IndirectBr: return 0;
1767  case Invoke: return 0;
1768  case CallBr: return 0;
1769  case Resume: return 0;
1770  case Unreachable: return 0;
1771  case CleanupRet: return 0;
1772  case CatchRet: return 0;
1773  case CatchPad: return 0;
1774  case CatchSwitch: return 0;
1775  case CleanupPad: return 0;
1776  case FNeg: return ISD::FNEG;
1777  case Add: return ISD::ADD;
1778  case FAdd: return ISD::FADD;
1779  case Sub: return ISD::SUB;
1780  case FSub: return ISD::FSUB;
1781  case Mul: return ISD::MUL;
1782  case FMul: return ISD::FMUL;
1783  case UDiv: return ISD::UDIV;
1784  case SDiv: return ISD::SDIV;
1785  case FDiv: return ISD::FDIV;
1786  case URem: return ISD::UREM;
1787  case SRem: return ISD::SREM;
1788  case FRem: return ISD::FREM;
1789  case Shl: return ISD::SHL;
1790  case LShr: return ISD::SRL;
1791  case AShr: return ISD::SRA;
1792  case And: return ISD::AND;
1793  case Or: return ISD::OR;
1794  case Xor: return ISD::XOR;
1795  case Alloca: return 0;
1796  case Load: return ISD::LOAD;
1797  case Store: return ISD::STORE;
1798  case GetElementPtr: return 0;
1799  case Fence: return 0;
1800  case AtomicCmpXchg: return 0;
1801  case AtomicRMW: return 0;
1802  case Trunc: return ISD::TRUNCATE;
1803  case ZExt: return ISD::ZERO_EXTEND;
1804  case SExt: return ISD::SIGN_EXTEND;
1805  case FPToUI: return ISD::FP_TO_UINT;
1806  case FPToSI: return ISD::FP_TO_SINT;
1807  case UIToFP: return ISD::UINT_TO_FP;
1808  case SIToFP: return ISD::SINT_TO_FP;
1809  case FPTrunc: return ISD::FP_ROUND;
1810  case FPExt: return ISD::FP_EXTEND;
1811  case PtrToInt: return ISD::BITCAST;
1812  case IntToPtr: return ISD::BITCAST;
1813  case BitCast: return ISD::BITCAST;
1814  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1815  case ICmp: return ISD::SETCC;
1816  case FCmp: return ISD::SETCC;
1817  case PHI: return 0;
1818  case Call: return 0;
1819  case Select: return ISD::SELECT;
1820  case UserOp1: return 0;
1821  case UserOp2: return 0;
1822  case VAArg: return 0;
1823  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1824  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1825  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1826  case ExtractValue: return ISD::MERGE_VALUES;
1827  case InsertValue: return ISD::MERGE_VALUES;
1828  case LandingPad: return 0;
1829  case Freeze: return ISD::FREEZE;
1830  }
1831 
1832  llvm_unreachable("Unknown instruction type encountered!");
1833 }
1834 
1835 std::pair<InstructionCost, MVT>
1837  Type *Ty) const {
1838  LLVMContext &C = Ty->getContext();
1839  EVT MTy = getValueType(DL, Ty);
1840 
1841  InstructionCost Cost = 1;
1842  // We keep legalizing the type until we find a legal kind. We assume that
1843  // the only operation that costs anything is the split. After splitting
1844  // we need to handle two types.
1845  while (true) {
1846  LegalizeKind LK = getTypeConversion(C, MTy);
1847 
1848  if (LK.first == TypeScalarizeScalableVector)
1849  return std::make_pair(InstructionCost::getInvalid(), MVT::getVT(Ty));
1850 
1851  if (LK.first == TypeLegal)
1852  return std::make_pair(Cost, MTy.getSimpleVT());
1853 
1854  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1855  Cost *= 2;
1856 
1857  // Do not loop with f128 type.
1858  if (MTy == LK.second)
1859  return std::make_pair(Cost, MTy.getSimpleVT());
1860 
1861  // Keep legalizing the type.
1862  MTy = LK.second;
1863  }
1864 }
1865 
1866 Value *
1868  bool UseTLS) const {
1869  // compiler-rt provides a variable with a magic name. Targets that do not
1870  // link with compiler-rt may also provide such a variable.
1871  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1872  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1873  auto UnsafeStackPtr =
1874  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1875 
1876  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1877 
1878  if (!UnsafeStackPtr) {
1879  auto TLSModel = UseTLS ?
1882  // The global variable is not defined yet, define it ourselves.
1883  // We use the initial-exec TLS model because we do not support the
1884  // variable living anywhere other than in the main executable.
1885  UnsafeStackPtr = new GlobalVariable(
1886  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1887  UnsafeStackPtrVar, nullptr, TLSModel);
1888  } else {
1889  // The variable exists, check its type and attributes.
1890  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1891  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1892  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1893  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1894  (UseTLS ? "" : "not ") + "be thread-local");
1895  }
1896  return UnsafeStackPtr;
1897 }
1898 
1899 Value *
1901  if (!TM.getTargetTriple().isAndroid())
1902  return getDefaultSafeStackPointerLocation(IRB, true);
1903 
1904  // Android provides a libc function to retrieve the address of the current
1905  // thread's unsafe stack pointer.
1906  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1907  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1908  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1909  StackPtrTy->getPointerTo(0));
1910  return IRB.CreateCall(Fn);
1911 }
1912 
1913 //===----------------------------------------------------------------------===//
1914 // Loop Strength Reduction hooks
1915 //===----------------------------------------------------------------------===//
1916 
1917 /// isLegalAddressingMode - Return true if the addressing mode represented
1918 /// by AM is legal for this target, for a load/store of the specified type.
1920  const AddrMode &AM, Type *Ty,
1921  unsigned AS, Instruction *I) const {
1922  // The default implementation of this implements a conservative RISCy, r+r and
1923  // r+i addr mode.
1924 
1925  // Allows a sign-extended 16-bit immediate field.
1926  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1927  return false;
1928 
1929  // No global is ever allowed as a base.
1930  if (AM.BaseGV)
1931  return false;
1932 
1933  // Only support r+r,
1934  switch (AM.Scale) {
1935  case 0: // "r+i" or just "i", depending on HasBaseReg.
1936  break;
1937  case 1:
1938  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1939  return false;
1940  // Otherwise we have r+r or r+i.
1941  break;
1942  case 2:
1943  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1944  return false;
1945  // Allow 2*r as r+r.
1946  break;
1947  default: // Don't allow n * r
1948  return false;
1949  }
1950 
1951  return true;
1952 }
1953 
1954 //===----------------------------------------------------------------------===//
1955 // Stack Protector
1956 //===----------------------------------------------------------------------===//
1957 
1958 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1959 // so that SelectionDAG handle SSP.
1961  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1962  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1963  PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
1964  Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
1965  if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
1966  G->setVisibility(GlobalValue::HiddenVisibility);
1967  return C;
1968  }
1969  return nullptr;
1970 }
1971 
1972 // Currently only support "standard" __stack_chk_guard.
1973 // TODO: add LOAD_STACK_GUARD support.
1975  if (!M.getNamedValue("__stack_chk_guard")) {
1976  auto *GV = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1978  "__stack_chk_guard");
1979  if (TM.getRelocationModel() == Reloc::Static &&
1981  GV->setDSOLocal(true);
1982  }
1983 }
1984 
1985 // Currently only support "standard" __stack_chk_guard.
1986 // TODO: add LOAD_STACK_GUARD support.
1988  return M.getNamedValue("__stack_chk_guard");
1989 }
1990 
1992  return nullptr;
1993 }
1994 
1996  return MinimumJumpTableEntries;
1997 }
1998 
2001 }
2002 
2003 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2004  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2005 }
2006 
2008  return MaximumJumpTableSize;
2009 }
2010 
2012  MaximumJumpTableSize = Val;
2013 }
2014 
2017 }
2018 
2019 //===----------------------------------------------------------------------===//
2020 // Reciprocal Estimates
2021 //===----------------------------------------------------------------------===//
2022 
2023 /// Get the reciprocal estimate attribute string for a function that will
2024 /// override the target defaults.
2026  const Function &F = MF.getFunction();
2027  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2028 }
2029 
2030 /// Construct a string for the given reciprocal operation of the given type.
2031 /// This string should match the corresponding option to the front-end's
2032 /// "-mrecip" flag assuming those strings have been passed through in an
2033 /// attribute string. For example, "vec-divf" for a division of a vXf32.
2034 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2035  std::string Name = VT.isVector() ? "vec-" : "";
2036 
2037  Name += IsSqrt ? "sqrt" : "div";
2038 
2039  // TODO: Handle "half" or other float types?
2040  if (VT.getScalarType() == MVT::f64) {
2041  Name += "d";
2042  } else {
2043  assert(VT.getScalarType() == MVT::f32 &&
2044  "Unexpected FP type for reciprocal estimate");
2045  Name += "f";
2046  }
2047 
2048  return Name;
2049 }
2050 
2051 /// Return the character position and value (a single numeric character) of a
2052 /// customized refinement operation in the input string if it exists. Return
2053 /// false if there is no customized refinement step count.
2054 static bool parseRefinementStep(StringRef In, size_t &Position,
2055  uint8_t &Value) {
2056  const char RefStepToken = ':';
2057  Position = In.find(RefStepToken);
2058  if (Position == StringRef::npos)
2059  return false;
2060 
2061  StringRef RefStepString = In.substr(Position + 1);
2062  // Allow exactly one numeric character for the additional refinement
2063  // step parameter.
2064  if (RefStepString.size() == 1) {
2065  char RefStepChar = RefStepString[0];
2066  if (isDigit(RefStepChar)) {
2067  Value = RefStepChar - '0';
2068  return true;
2069  }
2070  }
2071  report_fatal_error("Invalid refinement step for -recip.");
2072 }
2073 
2074 /// For the input attribute string, return one of the ReciprocalEstimate enum
2075 /// status values (enabled, disabled, or not specified) for this operation on
2076 /// the specified data type.
2077 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2078  if (Override.empty())
2079  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2080 
2081  SmallVector<StringRef, 4> OverrideVector;
2082  Override.split(OverrideVector, ',');
2083  unsigned NumArgs = OverrideVector.size();
2084 
2085  // Check if "all", "none", or "default" was specified.
2086  if (NumArgs == 1) {
2087  // Look for an optional setting of the number of refinement steps needed
2088  // for this type of reciprocal operation.
2089  size_t RefPos;
2090  uint8_t RefSteps;
2091  if (parseRefinementStep(Override, RefPos, RefSteps)) {
2092  // Split the string for further processing.
2093  Override = Override.substr(0, RefPos);
2094  }
2095 
2096  // All reciprocal types are enabled.
2097  if (Override == "all")
2099 
2100  // All reciprocal types are disabled.
2101  if (Override == "none")
2103 
2104  // Target defaults for enablement are used.
2105  if (Override == "default")
2106  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2107  }
2108 
2109  // The attribute string may omit the size suffix ('f'/'d').
2110  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2111  std::string VTNameNoSize = VTName;
2112  VTNameNoSize.pop_back();
2113  static const char DisabledPrefix = '!';
2114 
2115  for (StringRef RecipType : OverrideVector) {
2116  size_t RefPos;
2117  uint8_t RefSteps;
2118  if (parseRefinementStep(RecipType, RefPos, RefSteps))
2119  RecipType = RecipType.substr(0, RefPos);
2120 
2121  // Ignore the disablement token for string matching.
2122  bool IsDisabled = RecipType[0] == DisabledPrefix;
2123  if (IsDisabled)
2124  RecipType = RecipType.substr(1);
2125 
2126  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2129  }
2130 
2131  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2132 }
2133 
2134 /// For the input attribute string, return the customized refinement step count
2135 /// for this operation on the specified data type. If the step count does not
2136 /// exist, return the ReciprocalEstimate enum value for unspecified.
2137 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2138  if (Override.empty())
2139  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2140 
2141  SmallVector<StringRef, 4> OverrideVector;
2142  Override.split(OverrideVector, ',');
2143  unsigned NumArgs = OverrideVector.size();
2144 
2145  // Check if "all", "default", or "none" was specified.
2146  if (NumArgs == 1) {
2147  // Look for an optional setting of the number of refinement steps needed
2148  // for this type of reciprocal operation.
2149  size_t RefPos;
2150  uint8_t RefSteps;
2151  if (!parseRefinementStep(Override, RefPos, RefSteps))
2152  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2153 
2154  // Split the string for further processing.
2155  Override = Override.substr(0, RefPos);
2156  assert(Override != "none" &&
2157  "Disabled reciprocals, but specifed refinement steps?");
2158 
2159  // If this is a general override, return the specified number of steps.
2160  if (Override == "all" || Override == "default")
2161  return RefSteps;
2162  }
2163 
2164  // The attribute string may omit the size suffix ('f'/'d').
2165  std::string VTName = getReciprocalOpName(IsSqrt, VT);
2166  std::string VTNameNoSize = VTName;
2167  VTNameNoSize.pop_back();
2168 
2169  for (StringRef RecipType : OverrideVector) {
2170  size_t RefPos;
2171  uint8_t RefSteps;
2172  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2173  continue;
2174 
2175  RecipType = RecipType.substr(0, RefPos);
2176  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2177  return RefSteps;
2178  }
2179 
2180  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2181 }
2182 
2184  MachineFunction &MF) const {
2185  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2186 }
2187 
2189  MachineFunction &MF) const {
2190  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2191 }
2192 
2194  MachineFunction &MF) const {
2195  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2196 }
2197 
2199  MachineFunction &MF) const {
2200  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2201 }
2202 
2204  MF.getRegInfo().freezeReservedRegs(MF);
2205 }
2206 
2209  const DataLayout &DL) const {
2211  if (LI.isVolatile())
2213 
2214  if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2216 
2217  if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2219 
2222 
2223  Flags |= getTargetMMOFlags(LI);
2224  return Flags;
2225 }
2226 
2229  const DataLayout &DL) const {
2231 
2232  if (SI.isVolatile())
2234 
2235  if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2237 
2238  // FIXME: Not preserving dereferenceable
2239  Flags |= getTargetMMOFlags(SI);
2240  return Flags;
2241 }
2242 
2245  const DataLayout &DL) const {
2247 
2248  if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2249  if (RMW->isVolatile())
2251  } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2252  if (CmpX->isVolatile())
2254  } else
2255  llvm_unreachable("not an atomic instruction");
2256 
2257  // FIXME: Not preserving dereferenceable
2258  Flags |= getTargetMMOFlags(AI);
2259  return Flags;
2260 }
2261 
2263  Instruction *Inst,
2264  AtomicOrdering Ord) const {
2265  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2266  return Builder.CreateFence(Ord);
2267  else
2268  return nullptr;
2269 }
2270 
2272  Instruction *Inst,
2273  AtomicOrdering Ord) const {
2274  if (isAcquireOrStronger(Ord))
2275  return Builder.CreateFence(Ord);
2276  else
2277  return nullptr;
2278 }
2279 
2280 //===----------------------------------------------------------------------===//
2281 // GlobalISel Hooks
2282 //===----------------------------------------------------------------------===//
2283 
2285  const TargetTransformInfo *TTI) const {
2286  auto &MF = *MI.getMF();
2287  auto &MRI = MF.getRegInfo();
2288  // Assuming a spill and reload of a value has a cost of 1 instruction each,
2289  // this helper function computes the maximum number of uses we should consider
2290  // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2291  // break even in terms of code size when the original MI has 2 users vs
2292  // choosing to potentially spill. Any more than 2 users we we have a net code
2293  // size increase. This doesn't take into account register pressure though.
2294  auto maxUses = [](unsigned RematCost) {
2295  // A cost of 1 means remats are basically free.
2296  if (RematCost == 1)
2297  return UINT_MAX;
2298  if (RematCost == 2)
2299  return 2U;
2300 
2301  // Remat is too expensive, only sink if there's one user.
2302  if (RematCost > 2)
2303  return 1U;
2304  llvm_unreachable("Unexpected remat cost");
2305  };
2306 
2307  // Helper to walk through uses and terminate if we've reached a limit. Saves
2308  // us spending time traversing uses if all we want to know is if it's >= min.
2309  auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) {
2310  unsigned NumUses = 0;
2312  for (; UI != UE && NumUses < MaxUses; ++UI) {
2313  NumUses++;
2314  }
2315  // If we haven't reached the end yet then there are more than MaxUses users.
2316  return UI == UE;
2317  };
2318 
2319  switch (MI.getOpcode()) {
2320  default:
2321  return false;
2322  // Constants-like instructions should be close to their users.
2323  // We don't want long live-ranges for them.
2324  case TargetOpcode::G_CONSTANT:
2325  case TargetOpcode::G_FCONSTANT:
2326  case TargetOpcode::G_FRAME_INDEX:
2327  case TargetOpcode::G_INTTOPTR:
2328  return true;
2329  case TargetOpcode::G_GLOBAL_VALUE: {
2330  unsigned RematCost = TTI->getGISelRematGlobalCost();
2331  Register Reg = MI.getOperand(0).getReg();
2332  unsigned MaxUses = maxUses(RematCost);
2333  if (MaxUses == UINT_MAX)
2334  return true; // Remats are "free" so always localize.
2335  bool B = isUsesAtMost(Reg, MaxUses);
2336  return B;
2337  }
2338  }
2339 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:438
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:862
getRecipEstimateForFunc
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
Definition: TargetLoweringBase.cpp:2025
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:874
i
i
Definition: README.txt:29
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:683
llvm::TargetLoweringBase::getMinimumJumpTableDensity
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
Definition: TargetLoweringBase.cpp:2003
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetLoweringBase::getByValTypeAlignment
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
Definition: TargetLoweringBase.cpp:1695
llvm::TargetLoweringBase::setIndexedMaskedLoadAction
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
Definition: TargetLowering.h:2222
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3081
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:700
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:916
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:557
MaximumJumpTableSize
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:503
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2256
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1365
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MachineInstr.h
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:312
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::RTLIB::getSYNC
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:571
llvm
Definition: AllocatorList.h:23
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:191
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:538
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1011
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:43
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:623
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
Definition: TargetLoweringBase.cpp:661
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1362
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:838
llvm::RecurKind::FMul
@ FMul
Product of floats.
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:249
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1366
llvm::EVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:315
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1065
llvm::ElementCount
Definition: TypeSize.h:386
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:888
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:368
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1136
Loads.h
llvm::MVT::ppcf128
@ ppcf128
Definition: MachineValueType.h:56
llvm::GlobalValue::HiddenVisibility
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:64
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:513
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
Definition: TargetLoweringBase.cpp:1149
StringRef.h
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:304
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:45
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1129
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:664
llvm::Triple::x86
@ x86
Definition: Triple.h:83
llvm::TargetLoweringBase::TypeScalarizeScalableVector
@ TypeScalarizeScalableVector
Definition: TargetLowering.h:216
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:262
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:994
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3079
llvm::GlobalValue::NotThreadLocal
@ NotThreadLocal
Definition: GlobalValue.h:179
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:652
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1167
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:791
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1361
llvm::TargetLoweringBase::TypeSoftPromoteHalf
@ TypeSoftPromoteHalf
Definition: TargetLowering.h:215
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:350
llvm::TargetLoweringBase::setMaximumJumpTableSize
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
Definition: TargetLoweringBase.cpp:2011
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:643
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1132
SizeOpts.h
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::Sched::ILP
@ ILP
Definition: TargetLowering.h:102
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:361
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::GlobalVariable
Definition: GlobalVariable.h:40
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:132
llvm::CallingConv::ARM_AAPCS_VFP
@ ARM_AAPCS_VFP
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:118
llvm::X86II::TA
@ TA
Definition: X86BaseInfo.h:803
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:728
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:865
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::TargetLoweringBase::getSafeStackPointerLocation
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Definition: TargetLoweringBase.cpp:1900
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:330
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1253
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:775
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:1091
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:340
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::EVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
Definition: ValueTypes.h:155
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:70
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
Module.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::AttributeList
Definition: Attributes.h:385
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
@ LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE
Definition: MachineValueType.h:122
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:692
llvm::TargetLoweringBase::isSuitableForJumpTable
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
Definition: TargetLoweringBase.cpp:1617
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:74
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1214
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition: MachineValueType.h:488
OP_TO_LIBCALL
#define OP_TO_LIBCALL(Name, Enum)
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:2015
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:896
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1836
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2845
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:229
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:759
STLExtras.h
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1198
llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
Definition: TargetLoweringBase.cpp:1867
llvm::TargetLoweringBase::emitTrailingFence
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Definition: TargetLoweringBase.cpp:2271
llvm::LoadInst::getPointerOperand
Value * getPointerOperand()
Definition: Instructions.h:266
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::MVT::LAST_VECTOR_VALUETYPE
@ LAST_VECTOR_VALUETYPE
Definition: MachineValueType.h:245
MinimumJumpTableEntries
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:54
llvm::TargetLoweringBase::TypeExpandInteger
@ TypeExpandInteger
Definition: TargetLowering.h:208
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:331
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
Definition: TargetLoweringBase.cpp:1160
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:209
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::EVT::getRoundIntegerType
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:373
llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
Definition: TargetLowering.h:3102
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:299
llvm::TargetLoweringBase::getLoadMemOperandFlags
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2208
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:617
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1130
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:382
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:445
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:283
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Definition: TargetLoweringBase.cpp:918
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::TargetLoweringBase::emitLeadingFence
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: TargetLoweringBase.cpp:2262
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:357
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::AttributeList::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:1569
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:32
llvm::TargetLoweringBase::GatherAllAliasesMaxDepth
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Definition: TargetLowering.h:3067
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ElementCount::isScalar
bool isScalar() const
Counting predicates.
Definition: TypeSize.h:396
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:318
llvm::StringRef::substr
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:609
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1226
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:875
CommandLine.h
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1039
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:653
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:586
llvm::Triple::isAndroid
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:673
llvm::shouldOptimizeForSize
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
Definition: MachineSizeOpts.cpp:183
GlobalValue.h
llvm::TargetLoweringBase::shouldLocalize
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
Definition: TargetLoweringBase.cpp:2284
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
TargetMachine.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:669
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:354
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:630
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1363
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:218
llvm::EVT::getPow2VectorType
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:431
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition: TargetLowering.h:227
darwinHasSinCos
static bool darwinHasSinCos(const Triple &TT)
Definition: TargetLoweringBase.cpp:101
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
llvm::MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
@ LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE
Definition: MachineValueType.h:213
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:348
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:737
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:748
parseRefinementStep
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
Definition: TargetLoweringBase.cpp:2054
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2340
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:263
Twine.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3158
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1015
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:873
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:725
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:305
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:648
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:877
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:895
TargetOpcodes.h
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:251
llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3117
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:842
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1128
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:139
llvm::Instruction
Definition: Instruction.h:45
llvm::isDereferenceablePointer
bool isDereferenceablePointer(const Value *V, Type *Ty, const DataLayout &DL, const Instruction *CtxI=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Return true if this is always a dereferenceable pointer.
Definition: Loads.cpp:234
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetLoweringBase.cpp:1919
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1135
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2213
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:729
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::TargetLoweringBase::getSDagStackGuard
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
Definition: TargetLoweringBase.cpp:1987
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:872
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:871
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:404
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
Definition: TargetLoweringBase.cpp:1525
BitVector.h
llvm::MachineRegisterInfo::freezeReservedRegs
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Definition: MachineRegisterInfo.cpp:507
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1369
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:492
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3094
llvm::BitVector
Definition: BitVector.h:74
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:311
llvm::RTLIB::getFPLibCall
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Definition: TargetLoweringBase.cpp:216
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:584
llvm::TargetLoweringBase::insertSSPDeclarations
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: TargetLoweringBase.cpp:1974
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1113
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1325
llvm::TargetLoweringBase::softPromoteHalfType
virtual bool softPromoteHalfType() const
Definition: TargetLowering.h:453
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:265
llvm::LinearPolySize< ElementCount >::getFixed
static ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:180
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
Definition: TargetLoweringBase.cpp:927
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:308
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:859
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
Definition: TargetLowering.h:942
Type.h
JumpIsExpensiveOverride
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1212
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::MVT::f80
@ f80
Definition: MachineValueType.h:54
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
Definition: TargetLoweringBase.cpp:1513
llvm::TargetLoweringBase::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
Definition: TargetLowering.h:3135
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:371
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2173
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3096
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:616
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:901
llvm::TargetLoweringBase::getMaximumJumpTableSize
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
Definition: TargetLoweringBase.cpp:2007
llvm::cl::opt< bool >
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1995
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1179
llvm::TargetLoweringBase::getIRStackGuard
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
Definition: TargetLoweringBase.cpp:1960
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:303
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:303
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::TargetLoweringBase::getNumRegistersForCallingConv
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
Definition: TargetLowering.h:1517
llvm::TargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: TargetMachine.h:302
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:912
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:866
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1215
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:737
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:464
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1117
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1133
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
RuntimeLibcalls.h
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:776
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:895
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1219
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:268
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:911
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1224
llvm::TargetLoweringBase::TypeSoftenFloat
@ TypeSoftenFloat
Definition: TargetLowering.h:209
llvm::TargetLoweringBase::TypePromoteInteger
@ TypePromoteInteger
Definition: TargetLowering.h:207
llvm::RTLIB::getPOWI
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:489
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::TargetLoweringBase::getDivRefinementSteps
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
Definition: TargetLoweringBase.cpp:2198
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1078
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:294
llvm::ISD::OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
Definition: TargetCallingConv.h:233
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:505
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1211
llvm::TargetLoweringBase::getAtomicMemOperandFlags
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2244
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:665
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1132
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1199
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:878
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:614
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:465
Analysis.h
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1111
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:321
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1126
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:329
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:470
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:634
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
IRBuilder.h
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
Definition: TargetLoweringBase.cpp:1507
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetLowering.h:1628
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::TargetLoweringBase::getRecipEstimateDivEnabled
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
Definition: TargetLoweringBase.cpp:2188
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::Instruction::hasMetadata
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:264
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:824
llvm::TargetLoweringBase::EnableExtLdPromotion
bool EnableExtLdPromotion
Definition: TargetLowering.h:3138
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:592
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1081
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::TargetLoweringBase::getStoreMemOperandFlags
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
Definition: TargetLoweringBase.cpp:2228
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:367
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1221
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:284
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:297
getOpRefinementSteps
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
Definition: TargetLoweringBase.cpp:2137
llvm::ARM::WinEH::ReturnType
ReturnType
Definition: ARMWinEH.h:25
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::isAcquireOrStronger
bool isAcquireOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:128
Triple.h
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1130
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:902
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1085
llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
Definition: TargetLoweringBase.cpp:626
isDigit
static bool isDigit(const char C)
Definition: RustDemangle.cpp:81
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:149
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:619
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1290
llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Definition: MachineFrameInfo.h:690
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1489
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:301
llvm::isReleaseOrStronger
bool isReleaseOrStronger(AtomicOrdering AO)
Definition: AtomicOrdering.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:237
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:879
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1127
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2338
Compiler.h
llvm::TargetLoweringBase::IsStrictFPEnabled
bool IsStrictFPEnabled
Definition: TargetLowering.h:3150
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3131
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RecurKind::Mul
@ Mul
Product of integers.
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:867
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1756
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:349
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:868
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:418
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1223
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:373
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1125
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:569
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:339
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:728
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:206
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:624
llvm::MVT::getVectorElementCount
ElementCount getVectorElementCount() const
Definition: MachineValueType.h:810
OptsizeJumpTableDensity
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
llvm::TargetLoweringBase::isFreeAddrSpaceCast
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: TargetLoweringBase.cpp:940
llvm::AtomicOrdering::Release
@ Release
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:339
llvm::MVT::all_valuetypes
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Definition: MachineValueType.h:1371
llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
Definition: TargetLoweringBase.cpp:2183
Attributes.h
llvm::TargetLoweringBase::getSSPStackGuardCheck
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Definition: TargetLoweringBase.cpp:1991
j
return j(j<< 16)
llvm::EVT::getHalfNumVectorElementsVT
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:407
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1364
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2339
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:889
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:233
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:542
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:790
llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Definition: TargetLoweringBase.cpp:609
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2204
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:293
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2341
getOpEnabled
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
Definition: TargetLoweringBase.cpp:2077
llvm::MVT::FIRST_VECTOR_VALUETYPE
@ FIRST_VECTOR_VALUETYPE
Definition: MachineValueType.h:244
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1220
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:288
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:355
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1338
MachineFrameInfo.h
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
Definition: TargetLoweringBase.cpp:913
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:869
GlobalVariable.h
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
ISDOpcodes.h
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:687
llvm::IRBuilderBase::GetInsertBlock
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:178
Enabled
static bool Enabled
Definition: Statistic.cpp:50
llvm::TypeSize
Definition: TypeSize.h:417
Casting.h
Function.h
llvm::Triple::isWindowsGNUEnvironment
bool isWindowsGNUEnvironment() const
Definition: Triple.h:574
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:263
llvm::LinearPolySize< ElementCount >::getScalable
static ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1222
llvm::Type::getPointerTo
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:728
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:235
StackMaps.h
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:350
llvm::TargetLoweringBase::getTargetMMOFlags
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: TargetLowering.h:405
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:731
llvm::TargetLoweringBase::setJumpIsExpensive
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
Definition: TargetLoweringBase.cpp:945
llvm::TargetLoweringBase::TypeExpandFloat
@ TypeExpandFloat
Definition: TargetLowering.h:210
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2823
getReciprocalOpName
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
Definition: TargetLoweringBase.cpp:2034
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:912
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:730
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:307
llvm::TargetLoweringBase::TypePromoteFloat
@ TypePromoteFloat
Definition: TargetLowering.h:214
llvm::InstructionCost::getInvalid
static InstructionCost getInvalid(CostType Val=0)
Definition: InstructionCost.h:54
llvm::RTLIB::getOUTLINE_ATOMIC
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Definition: TargetLoweringBase.cpp:494
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::TargetLoweringBase::allowsMemoryAccess
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
Definition: TargetLoweringBase.cpp:1727
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:293
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:823
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:474
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
DisableStrictNodeMutation
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:372
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1091
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1643
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:647
llvm::TargetLoweringBase::allowsMemoryAccessForAlignment
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
Definition: TargetLoweringBase.cpp:1700
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:211
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1058
LCALL5
#define LCALL5(A)
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:375
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
MachineInstrBuilder.h
llvm::getMVTForLLT
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: LowLevelType.cpp:46
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:238
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:770
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:51
llvm::TargetLoweringBase::TypeScalarizeVector
@ TypeScalarizeVector
Definition: TargetLowering.h:211
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1280
llvm::TargetLoweringBase::getRegisterTypeForCallingConv
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: TargetLowering.h:1509
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:660
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:273
llvm::ISD::LAST_INDEXED_MODE
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1292
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1999
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:649
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:123
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:500
TargetTransformInfo.h
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:661
llvm::FunctionCallee
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:164
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1447
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2337
llvm::EVT::isPow2VectorType
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:424
llvm::TypeSize::getKnownMinSize
ScalarTy getKnownMinSize() const
Definition: TypeSize.h:427
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:618
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:876
llvm::TargetLoweringBase::setIndexedMaskedStoreAction
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
Definition: TargetLowering.h:2232
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Definition: TargetLoweringBase.cpp:399
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:856
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:362
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3179
llvm::TargetLoweringBase::MaxLoadsPerMemcmp
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
Definition: TargetLowering.h:3115
llvm::TargetLoweringBase::TargetLoweringBase
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
Definition: TargetLoweringBase.cpp:694
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1131
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1396
llvm::MVT::LAST_INTEGER_VALUETYPE
@ LAST_INTEGER_VALUETYPE
Definition: MachineValueType.h:48
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1225
llvm::TargetLoweringBase::TypeSplitVector
@ TypeSplitVector
Definition: TargetLowering.h:212
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1227
llvm::TargetLoweringBase::finalizeLowering
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
Definition: TargetLoweringBase.cpp:2203
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1099
llvm::GlobalValue::InitialExecTLSModel
@ InitialExecTLSModel
Definition: GlobalValue.h:182
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:870
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LinearPolySize::divideCoefficientBy
LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:361
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:494
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:864
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
Definition: TargetLowering.h:3129
llvm::TargetLoweringBase::getSqrtRefinementSteps
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
Definition: TargetLoweringBase.cpp:2193
JumpTableDensity
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:272
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:804
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:209
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
TargetRegisterInfo.h
llvm::Triple::aarch64
@ aarch64
Definition: Triple.h:52
llvm::IRBuilderBase::CreateCall
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2352
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::LinearPolySize::coefficientNextPowerOf2
LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:366
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:320
llvm::MVT::VALUETYPE_SIZE
@ VALUETYPE_SIZE
Definition: MachineValueType.h:263
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1134
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:701
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
Definition: TargetLowering.h:929
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:313
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1111
llvm::MVT::fp_valuetypes
static mvt_range fp_valuetypes()
Definition: MachineValueType.h:1381
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:374
llvm::LLT
Definition: LowLevelTypeImpl.h:40