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SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer comparisons. There are three operands: the two values
54  // to compare, and an integer of type SystemZICMP.
56 
57  // Floating-point comparisons. The two operands are the values to compare.
59 
60  // Test under mask. The first operand is ANDed with the second operand
61  // and the condition codes are set on the result. The third operand is
62  // a boolean that is true if the condition codes need to distinguish
63  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
64  // register forms do but the memory forms don't).
65  TM,
66 
67  // Branches if a condition is true. Operand 0 is the chain operand;
68  // operand 1 is the 4-bit condition-code mask, with bit N in
69  // big-endian order meaning "branch if CC=N"; operand 2 is the
70  // target block and operand 3 is the flag operand.
72 
73  // Selects between operand 0 and operand 1. Operand 2 is the
74  // mask of condition-code values for which operand 0 should be
75  // chosen over operand 1; it has the same form as BR_CCMASK.
76  // Operand 3 is the flag operand.
78 
79  // Evaluates to the gap between the stack pointer and the
80  // base of the dynamically-allocatable area.
82 
83  // For allocating stack space when using stack clash protector.
84  // Allocation is performed by block, and each block is probed.
86 
87  // Count number of bits set in operand 0 per byte.
89 
90  // Wrappers around the ISD opcodes of the same name. The output is GR128.
91  // Input operands may be GR64 or GR32, depending on the instruction.
96 
97  // Add/subtract with overflow/carry. These have the same operands as
98  // the corresponding standard operations, except with the carry flag
99  // replaced by a condition code value.
101 
102  // Set the condition code from a boolean value in operand 0.
103  // Operand 1 is a mask of all condition-code values that may result of this
104  // operation, operand 2 is a mask of condition-code values that may result
105  // if the boolean is true.
106  // Note that this operation is always optimized away, we will never
107  // generate any code for it.
109 
110  // Use a series of MVCs to copy bytes from one memory location to another.
111  // The operands are:
112  // - the target address
113  // - the source address
114  // - the constant length
115  //
116  // This isn't a memory opcode because we'd need to attach two
117  // MachineMemOperands rather than one.
119 
120  // Similar to MVC, but for logic operations (AND, OR, XOR).
121  NC,
122  OC,
123  XC,
124 
125  // Use CLC to compare two blocks of memory, with the same comments
126  // as for MVC.
128 
129  // Use an MVST-based sequence to implement stpcpy().
131 
132  // Use a CLST-based sequence to implement strcmp(). The two input operands
133  // are the addresses of the strings to compare.
135 
136  // Use an SRST-based sequence to search a block of memory. The first
137  // operand is the end address, the second is the start, and the third
138  // is the character to search for. CC is set to 1 on success and 2
139  // on failure.
141 
142  // Store the CC value in bits 29 and 28 of an integer.
144 
145  // Compiler barrier only; generate a no-op.
147 
148  // Transaction begin. The first operand is the chain, the second
149  // the TDB pointer, and the third the immediate control field.
150  // Returns CC value and chain.
153 
154  // Transaction end. Just the chain operand. Returns CC value and chain.
156 
157  // Create a vector constant by filling byte N of the result with bit
158  // 15-N of the single operand.
160 
161  // Create a vector constant by replicating an element-sized RISBG-style mask.
162  // The first operand specifies the starting set bit and the second operand
163  // specifies the ending set bit. Both operands count from the MSB of the
164  // element.
166 
167  // Replicate a GPR scalar value into all elements of a vector.
169 
170  // Create a vector from two i64 GPRs.
172 
173  // Replicate one element of a vector into all elements. The first operand
174  // is the vector and the second is the index of the element to replicate.
176 
177  // Interleave elements from the high half of operand 0 and the high half
178  // of operand 1.
180 
181  // Likewise for the low halves.
183 
184  // Concatenate the vectors in the first two operands, shift them left
185  // by the third operand, and take the first half of the result.
187 
188  // Take one element of the first v2i64 operand and the one element of
189  // the second v2i64 operand and concatenate them to form a v2i64 result.
190  // The third operand is a 4-bit value of the form 0A0B, where A and B
191  // are the element selectors for the first operand and second operands
192  // respectively.
194 
195  // Perform a general vector permute on vector operands 0 and 1.
196  // Each byte of operand 2 controls the corresponding byte of the result,
197  // in the same way as a byte-level VECTOR_SHUFFLE mask.
199 
200  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
202 
203  // Likewise, but saturate the result and set CC. PACKS_CC does signed
204  // saturation and PACKLS_CC does unsigned saturation.
207 
208  // Unpack the first half of vector operand 0 into double-sized elements.
209  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
212 
213  // Likewise for the second half.
216 
217  // Shift each element of vector operand 0 by the number of bits specified
218  // by scalar operand 1.
222 
223  // For each element of the output type, sum across all sub-elements of
224  // operand 0 belonging to the corresponding element, and add in the
225  // rightmost sub-element of the corresponding element of operand 1.
227 
228  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
229  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
230  // and VICMPHL for "unsigned greater than".
234 
235  // Likewise, but also set the condition codes on the result.
239 
240  // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
241  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
242  // greater than" and VFCMPHE for "ordered and greater than or equal to".
246 
247  // Likewise, but also set the condition codes on the result.
251 
252  // Test floating-point data class for vectors.
254 
255  // Extend the even f32 elements of vector operand 0 to produce a vector
256  // of f64 elements.
258 
259  // Round the f64 elements of vector operand 0 to f32s and store them in the
260  // even elements of the result.
262 
263  // AND the two vector operands together and set CC based on the result.
265 
266  // String operations that set CC as a side-effect.
278 
279  // Test Data Class.
280  //
281  // Operand 0: the value to test
282  // Operand 1: the bit mask
284 
285  // Strict variants of scalar floating-point comparisons.
286  // Quiet and signaling versions.
289 
290  // Strict variants of vector floating-point comparisons.
291  // Quiet and signaling versions.
298 
299  // Strict variants of VEXTEND and VROUND.
302 
303  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
304  // ATOMIC_LOAD_<op>.
305  //
306  // Operand 0: the address of the containing 32-bit-aligned field
307  // Operand 1: the second operand of <op>, in the high bits of an i32
308  // for everything except ATOMIC_SWAPW
309  // Operand 2: how many bits to rotate the i32 left to bring the first
310  // operand into the high bits
311  // Operand 3: the negative of operand 2, for rotating the other way
312  // Operand 4: the width of the field in bits (8 or 16)
324 
325  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
326  //
327  // Operand 0: the address of the containing 32-bit-aligned field
328  // Operand 1: the compare value, in the low bits of an i32
329  // Operand 2: the swap value, in the low bits of an i32
330  // Operand 3: how many bits to rotate the i32 left to bring the first
331  // operand into the high bits
332  // Operand 4: the negative of operand 2, for rotating the other way
333  // Operand 5: the width of the field in bits (8 or 16)
335 
336  // Atomic compare-and-swap returning CC value.
337  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
339 
340  // 128-bit atomic load.
341  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
343 
344  // 128-bit atomic store.
345  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
347 
348  // 128-bit atomic compare-and-swap.
349  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
351 
352  // Byte swapping load/store. Same operands as regular load/store.
354 
355  // Element swapping load/store. Same operands as regular load/store.
357 
358  // Prefetch from the second operand using the 4-bit control code in
359  // the first operand. The code is 1 for a load prefetch and 2 for
360  // a store prefetch.
362 };
363 
364 // Return true if OPCODE is some kind of PC-relative address.
365 inline bool isPCREL(unsigned Opcode) {
366  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
367 }
368 } // end namespace SystemZISD
369 
370 namespace SystemZICMP {
371 // Describes whether an integer comparison needs to be signed or unsigned,
372 // or whether either type is OK.
373 enum {
377 };
378 } // end namespace SystemZICMP
379 
380 class SystemZSubtarget;
381 class SystemZTargetMachine;
382 
384 public:
385  explicit SystemZTargetLowering(const TargetMachine &TM,
386  const SystemZSubtarget &STI);
387 
388  bool useSoftFloat() const override;
389 
390  // Override TargetLowering.
391  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
392  return MVT::i32;
393  }
394  MVT getVectorIdxTy(const DataLayout &DL) const override {
395  // Only the lower 12 bits of an element index are used, so we don't
396  // want to clobber the upper 32 bits of a GPR unnecessarily.
397  return MVT::i32;
398  }
400  const override {
401  // Widen subvectors to the full width rather than promoting integer
402  // elements. This is better because:
403  //
404  // (a) it means that we can handle the ABI for passing and returning
405  // sub-128 vectors without having to handle them as legal types.
406  //
407  // (b) we don't have instructions to extend on load and truncate on store,
408  // so promoting the integers is less efficient.
409  //
410  // (c) there are no multiplication instructions for the widest integer
411  // type (v2i64).
412  if (VT.getScalarSizeInBits() % 8 == 0)
413  return TypeWidenVector;
415  }
416  unsigned
418  Optional<MVT> RegisterVT) const override {
419  // i128 inline assembly operand.
420  if (VT == MVT::i128 &&
421  RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped)
422  return 1;
424  }
425  bool isCheapToSpeculateCtlz() const override { return true; }
426  bool preferZeroCompareBranch() const override { return true; }
427  bool hasBitPreservingFPLogic(EVT VT) const override {
428  EVT ScVT = VT.getScalarType();
429  return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
430  }
431  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
432  ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
433  return Mask && Mask->getValue().isIntN(16);
434  }
435  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
436  return VT.isScalarInteger();
437  }
439  EVT) const override;
441  EVT VT) const override;
442  bool isFPImmLegal(const APFloat &Imm, EVT VT,
443  bool ForCodeSize) const override;
444  bool hasInlineStackProbe(MachineFunction &MF) const override;
445  bool isLegalICmpImmediate(int64_t Imm) const override;
446  bool isLegalAddImmediate(int64_t Imm) const override;
447  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
448  unsigned AS,
449  Instruction *I = nullptr) const override;
450  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
452  bool *Fast) const override;
453  bool isTruncateFree(Type *, Type *) const override;
454  bool isTruncateFree(EVT, EVT) const override;
455 
456  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
457  bool MathUsed) const override {
458  // Form add and sub with overflow intrinsics regardless of any extra
459  // users of the math result.
460  return VT == MVT::i32 || VT == MVT::i64;
461  }
462 
463  const char *getTargetNodeName(unsigned Opcode) const override;
464  std::pair<unsigned, const TargetRegisterClass *>
466  StringRef Constraint, MVT VT) const override;
468  getConstraintType(StringRef Constraint) const override;
470  getSingleConstraintMatchWeight(AsmOperandInfo &info,
471  const char *constraint) const override;
473  std::string &Constraint,
474  std::vector<SDValue> &Ops,
475  SelectionDAG &DAG) const override;
476 
477  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
478  if (ConstraintCode.size() == 1) {
479  switch(ConstraintCode[0]) {
480  default:
481  break;
482  case 'o':
484  case 'Q':
486  case 'R':
488  case 'S':
490  case 'T':
492  }
493  }
494  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
495  }
496 
497  Register getRegisterByName(const char *RegName, LLT VT,
498  const MachineFunction &MF) const override;
499 
500  /// If a physical register, this returns the register that receives the
501  /// exception address on entry to an EH pad.
502  Register
503  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
504  return SystemZ::R6D;
505  }
506 
507  /// If a physical register, this returns the register that receives the
508  /// exception typeid on entry to a landing pad.
509  Register
510  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
511  return SystemZ::R7D;
512  }
513 
514  /// Override to support customized stack guard loading.
515  bool useLoadStackGuardNode() const override {
516  return true;
517  }
518  void insertSSPDeclarations(Module &M) const override {
519  }
520 
523  MachineBasicBlock *BB) const override;
524  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
526  SelectionDAG &DAG) const override;
528  SelectionDAG &DAG) const override;
529  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
530  bool allowTruncateForTailCall(Type *, Type *) const override;
531  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
533  SDValue Val, SDValue *Parts,
534  unsigned NumParts, MVT PartVT,
535  Optional<CallingConv::ID> CC) const override;
536  SDValue
538  const SDValue *Parts, unsigned NumParts,
539  MVT PartVT, EVT ValueVT,
540  Optional<CallingConv::ID> CC) const override;
542  bool isVarArg,
544  const SDLoc &DL, SelectionDAG &DAG,
545  SmallVectorImpl<SDValue> &InVals) const override;
546  SDValue LowerCall(CallLoweringInfo &CLI,
547  SmallVectorImpl<SDValue> &InVals) const override;
548 
550  bool isVarArg,
552  LLVMContext &Context) const override;
553  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
555  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
556  SelectionDAG &DAG) const override;
557  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
558 
559  /// Determine which of the bits specified in Mask are known to be either
560  /// zero or one and return them in the KnownZero/KnownOne bitsets.
562  KnownBits &Known,
563  const APInt &DemandedElts,
564  const SelectionDAG &DAG,
565  unsigned Depth = 0) const override;
566 
567  /// Determine the number of bits in the operation that are sign bits.
569  const APInt &DemandedElts,
570  const SelectionDAG &DAG,
571  unsigned Depth) const override;
572 
574  return ISD::ANY_EXTEND;
575  }
577  return ISD::ZERO_EXTEND;
578  }
579 
580  bool supportSwiftError() const override {
581  return true;
582  }
583 
584  unsigned getStackProbeSize(MachineFunction &MF) const;
585 
586 private:
587  const SystemZSubtarget &Subtarget;
588 
589  // Implement LowerOperation for individual opcodes.
590  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
591  const SDLoc &DL, EVT VT,
592  SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
593  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
594  EVT VT, ISD::CondCode CC,
595  SDValue CmpOp0, SDValue CmpOp1,
596  SDValue Chain = SDValue(),
597  bool IsSignaling = false) const;
598  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
599  SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
600  bool IsSignaling) const;
601  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
602  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
603  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
604  SelectionDAG &DAG) const;
605  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
606  SelectionDAG &DAG, unsigned Opcode,
607  SDValue GOTOffset) const;
608  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
609  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
610  SelectionDAG &DAG) const;
611  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
612  SelectionDAG &DAG) const;
613  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
614  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
615  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
616  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
617  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
618  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
619  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
620  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
621  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
622  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
623  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
624  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
625  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
626  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
627  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
628  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
629  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
630  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
631  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
634  unsigned Opcode) const;
635  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
636  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
637  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
638  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
641  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
642  bool isVectorElementLoad(SDValue Op) const;
643  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
644  SmallVectorImpl<SDValue> &Elems) const;
645  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
646  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
647  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
653 
654  bool canTreatAsByteVector(EVT VT) const;
655  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
656  unsigned Index, DAGCombinerInfo &DCI,
657  bool Force) const;
658  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
659  DAGCombinerInfo &DCI) const;
660  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
661  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
662  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
663  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
664  bool canLoadStoreByteSwapped(EVT VT) const;
665  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
666  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
667  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
668  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
669  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
670  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
671  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
672  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
673  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
674  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
675  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
676  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
677  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
678  SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
679 
680  SDValue unwrapAddress(SDValue N) const override;
681 
682  // If the last instruction before MBBI in MBB was some form of COMPARE,
683  // try to replace it with a COMPARE AND BRANCH just before MBBI.
684  // CCMask and Target are the BRC-like operands for the branch.
685  // Return true if the change was made.
686  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
688  unsigned CCMask,
689  MachineBasicBlock *Target) const;
690 
691  // Implement EmitInstrWithCustomInserter for individual operation types.
692  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
694  unsigned StoreOpcode, unsigned STOCOpcode,
695  bool Invert) const;
696  MachineBasicBlock *emitPair128(MachineInstr &MI,
697  MachineBasicBlock *MBB) const;
699  bool ClearEven) const;
700  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
702  unsigned BinOpcode, unsigned BitSize,
703  bool Invert = false) const;
704  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
706  unsigned CompareOpcode,
707  unsigned KeepOldMask,
708  unsigned BitSize) const;
709  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
710  MachineBasicBlock *BB) const;
711  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
712  unsigned Opcode) const;
713  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
714  unsigned Opcode) const;
715  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
717  unsigned Opcode, bool NoFloat) const;
718  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
720  unsigned Opcode) const;
721  MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
722  MachineBasicBlock *MBB) const;
723 
724  SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
725 
727  getTargetMMOFlags(const Instruction &I) const override;
728  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
729 };
730 
732 private:
733  APInt IntBits; // The 128 bits as an integer.
734  APInt SplatBits; // Smallest splat value.
735  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
736  unsigned SplatBitSize = 0;
737  bool isFP128 = false;
738 
739 public:
740  unsigned Opcode = 0;
745  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
746 };
747 
748 } // end namespace llvm
749 
750 #endif
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:452
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SystemZISelLowering.cpp:5674
llvm::SystemZISD::UADDO
@ UADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::SELECT_CCMASK
@ SELECT_CCMASK
Definition: SystemZISelLowering.h:77
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SystemZISelLowering.cpp:1235
llvm::SystemZISD::SDIVREM
@ SDIVREM
Definition: SystemZISelLowering.h:94
llvm::SystemZISD::ATOMIC_LOADW_SUB
@ ATOMIC_LOADW_SUB
Definition: SystemZISelLowering.h:315
llvm::SystemZISD::SUBCARRY
@ SUBCARRY
Definition: SystemZISelLowering.h:100
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::SystemZISD::ATOMIC_LOAD_128
@ ATOMIC_LOAD_128
Definition: SystemZISelLowering.h:342
llvm::SystemZISD::USUBO
@ USUBO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::RET_FLAG
@ RET_FLAG
Definition: SystemZISelLowering.h:29
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: SystemZISelLowering.cpp:993
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition: SystemZISelLowering.h:417
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1085
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4222
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition: SystemZISelLowering.cpp:690
llvm::SystemZISD::ICMP
@ ICMP
Definition: SystemZISelLowering.h:55
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SystemZISelLowering.cpp:1298
llvm::SystemZISD::GET_CCMASK
@ GET_CCMASK
Definition: SystemZISelLowering.h:108
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:48
llvm::SystemZISD::VICMPH
@ VICMPH
Definition: SystemZISelLowering.h:232
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:383
llvm::SmallVector< unsigned, 2 >
llvm::SystemZISD::PACKLS_CC
@ PACKLS_CC
Definition: SystemZISelLowering.h:206
llvm::SystemZISD::CLC
@ CLC
Definition: SystemZISelLowering.h:127
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SystemZISelLowering.cpp:5467
llvm::SystemZISD::ATOMIC_CMP_SWAPW
@ ATOMIC_CMP_SWAPW
Definition: SystemZISelLowering.h:334
llvm::SystemZISD::VICMPHLS
@ VICMPHLS
Definition: SystemZISelLowering.h:238
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SystemZISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SystemZISelLowering.h:26
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
MachineBasicBlock.h
llvm::SystemZISD::ROTATE_MASK
@ ROTATE_MASK
Definition: SystemZISelLowering.h:165
llvm::SystemZISD::VFENEZ_CC
@ VFENEZ_CC
Definition: SystemZISelLowering.h:272
llvm::SystemZISD::VFAE_CC
@ VFAE_CC
Definition: SystemZISelLowering.h:267
llvm::SystemZISD::VSTRS_CC
@ VSTRS_CC
Definition: SystemZISelLowering.h:276
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: SystemZISelLowering.cpp:1293
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SystemZISD::PREFETCH
@ PREFETCH
Definition: SystemZISelLowering.h:361
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SystemZISelLowering.cpp:1606
llvm::SystemZICMP::Any
@ Any
Definition: SystemZISelLowering.h:374
llvm::SystemZISD::VSTER
@ VSTER
Definition: SystemZISelLowering.h:356
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition: SystemZISelLowering.cpp:80
llvm::Optional
Definition: APInt.h:33
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: SystemZISelLowering.h:426
llvm::SystemZICMP::SignedOnly
@ SignedOnly
Definition: SystemZISelLowering.h:376
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: SystemZISelLowering.h:576
llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: SystemZISelLowering.h:435
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SystemZISelLowering.cpp:1223
llvm::SystemZISD::STRICT_VEXTEND
@ STRICT_VEXTEND
Definition: SystemZISelLowering.h:300
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: SystemZISelLowering.cpp:7120
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SystemZISelLowering.cpp:1014
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SystemZISelLowering.cpp:1047
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2148
llvm::SystemZISD::VICMPHL
@ VICMPHL
Definition: SystemZISelLowering.h:233
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SystemZISD::VSHL_BY_SCALAR
@ VSHL_BY_SCALAR
Definition: SystemZISelLowering.h:219
llvm::SystemZISD::PERMUTE_DWORDS
@ PERMUTE_DWORDS
Definition: SystemZISelLowering.h:193
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::SystemZTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SystemZISelLowering.h:427
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SystemZISelLowering.h:518
llvm::SystemZISD::TEND
@ TEND
Definition: SystemZISelLowering.h:155
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SystemZISelLowering.cpp:1851
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: SystemZISelLowering.cpp:7065
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:288
llvm::SystemZISD::ATOMIC_SWAPW
@ ATOMIC_SWAPW
Definition: SystemZISelLowering.h:313
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::SystemZTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: SystemZISelLowering.h:394
llvm::SystemZISD::ATOMIC_LOADW_UMAX
@ ATOMIC_LOADW_UMAX
Definition: SystemZISelLowering.h:323
llvm::InlineAsm::Constraint_T
@ Constraint_T
Definition: InlineAsm.h:254
llvm::SystemZISD::BR_CCMASK
@ BR_CCMASK
Definition: SystemZISelLowering.h:71
llvm::SystemZISD::UNPACK_HIGH
@ UNPACK_HIGH
Definition: SystemZISelLowering.h:210
llvm::SystemZISD::ATOMIC_LOADW_ADD
@ ATOMIC_LOADW_ADD
Definition: SystemZISelLowering.h:314
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
SystemZInstrInfo.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:40
llvm::SystemZISD::VSRA_BY_SCALAR
@ VSRA_BY_SCALAR
Definition: SystemZISelLowering.h:221
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:39
llvm::SystemZISD::VFEEZ_CC
@ VFEEZ_CC
Definition: SystemZISelLowering.h:270
llvm::SystemZISD::ATOMIC_LOADW_UMIN
@ ATOMIC_LOADW_UMIN
Definition: SystemZISelLowering.h:322
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SystemZISelLowering.h:503
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: SystemZISelLowering.cpp:850
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1820
llvm::SystemZISD::SIBCALL
@ SIBCALL
Definition: SystemZISelLowering.h:35
llvm::SystemZISD::JOIN_DWORDS
@ JOIN_DWORDS
Definition: SystemZISelLowering.h:171
llvm::SystemZISD::VSTRCZ_CC
@ VSTRCZ_CC
Definition: SystemZISelLowering.h:275
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SystemZISelLowering.cpp:8394
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::SystemZISD::VSRL_BY_SCALAR
@ VSRL_BY_SCALAR
Definition: SystemZISelLowering.h:220
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: SystemZISelLowering.h:573
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1062
llvm::SystemZISD::UNPACKL_HIGH
@ UNPACKL_HIGH
Definition: SystemZISelLowering.h:211
llvm::SystemZISD::STRICT_VFCMPHES
@ STRICT_VFCMPHES
Definition: SystemZISelLowering.h:297
llvm::SystemZISD::VFCMPHES
@ VFCMPHES
Definition: SystemZISelLowering.h:250
llvm::SystemZISD::CALL
@ CALL
Definition: SystemZISelLowering.h:34
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SystemZISD::ATOMIC_LOADW_AND
@ ATOMIC_LOADW_AND
Definition: SystemZISelLowering.h:316
llvm::SystemZTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: SystemZISelLowering.h:431
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:45
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition: SystemZISelLowering.cpp:719
llvm::SystemZISD::STRCMP
@ STRCMP
Definition: SystemZISelLowering.h:134
llvm::SystemZISD::STRICT_VROUND
@ STRICT_VROUND
Definition: SystemZISelLowering.h:301
llvm::SystemZICMP::UnsignedOnly
@ UnsignedOnly
Definition: SystemZISelLowering.h:375
llvm::SystemZISD::VFEE_CC
@ VFEE_CC
Definition: SystemZISelLowering.h:269
SystemZ.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:214
llvm::SystemZISD::VSUM
@ VSUM
Definition: SystemZISelLowering.h:226
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZISD::FCMP
@ FCMP
Definition: SystemZISelLowering.h:58
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: SystemZISelLowering.h:580
llvm::SystemZISD::VFCMPE
@ VFCMPE
Definition: SystemZISelLowering.h:243
llvm::SystemZISD::UDIVREM
@ UDIVREM
Definition: SystemZISelLowering.h:95
llvm::SystemZISD::SSUBO
@ SSUBO
Definition: SystemZISelLowering.h:100
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SystemZISD::VTM
@ VTM
Definition: SystemZISelLowering.h:264
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SystemZTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SystemZISelLowering.cpp:686
llvm::SystemZISD::ATOMIC_LOADW_NAND
@ ATOMIC_LOADW_NAND
Definition: SystemZISelLowering.h:319
llvm::SystemZISD::SMUL_LOHI
@ SMUL_LOHI
Definition: SystemZISelLowering.h:92
llvm::SystemZISD::VFCMPHE
@ VFCMPHE
Definition: SystemZISelLowering.h:245
llvm::SystemZVectorConstantInfo::Opcode
unsigned Opcode
Definition: SystemZISelLowering.h:740
llvm::SystemZISD::UMUL_LOHI
@ UMUL_LOHI
Definition: SystemZISelLowering.h:93
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SystemZISelLowering.cpp:6799
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:248
llvm::SystemZISD::TBEGIN_NOFLOAT
@ TBEGIN_NOFLOAT
Definition: SystemZISelLowering.h:152
llvm::APFloat
Definition: APFloat.h:701
llvm::SystemZISD::TDC
@ TDC
Definition: SystemZISelLowering.h:283
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SystemZISelLowering.cpp:6947
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SystemZISD::VICMPHS
@ VICMPHS
Definition: SystemZISelLowering.h:237
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SystemZVectorConstantInfo
Definition: SystemZISelLowering.h:731
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1255
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:118
llvm::SystemZISD::SHL_DOUBLE
@ SHL_DOUBLE
Definition: SystemZISelLowering.h:186
llvm::SystemZISD::MERGE_HIGH
@ MERGE_HIGH
Definition: SystemZISelLowering.h:179
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: SystemZISelLowering.cpp:860
llvm::SystemZISD::LRV
@ LRV
Definition: SystemZISelLowering.h:353
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: SystemZISelLowering.cpp:855
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SystemZISelLowering.cpp:1831
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SystemZISelLowering.h:510
llvm::SystemZISD::VEXTEND
@ VEXTEND
Definition: SystemZISelLowering.h:257
llvm::SystemZISD::STRICT_VFCMPHS
@ STRICT_VFCMPHS
Definition: SystemZISelLowering.h:296
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::SystemZISD::VSTRC_CC
@ VSTRC_CC
Definition: SystemZISelLowering.h:274
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:122
llvm::SystemZISD::SEARCH_STRING
@ SEARCH_STRING
Definition: SystemZISelLowering.h:140
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: SystemZISelLowering.h:425
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1366
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SystemZISD::VFCMPES
@ VFCMPES
Definition: SystemZISelLowering.h:248
llvm::SystemZISD::VFCMPH
@ VFCMPH
Definition: SystemZISelLowering.h:244
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::SystemZISD::ATOMIC_LOADW_XOR
@ ATOMIC_LOADW_XOR
Definition: SystemZISelLowering.h:318
llvm::SystemZISD::VFCMPHS
@ VFCMPHS
Definition: SystemZISelLowering.h:249
llvm::SystemZISD::STRICT_VFCMPH
@ STRICT_VFCMPH
Definition: SystemZISelLowering.h:293
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: SystemZISelLowering.cpp:842
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1841
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition: SelectionDAGNodes.h:1946
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SystemZISelLowering.cpp:967
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZISD::VFENE_CC
@ VFENE_CC
Definition: SystemZISelLowering.h:271
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: SystemZISelLowering.h:477
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::SystemZISD::REPLICATE
@ REPLICATE
Definition: SystemZISelLowering.h:168
Node
Definition: ItaniumDemangle.h:235
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SystemZISelLowering.h:399
llvm::SystemZISD::ATOMIC_LOADW_MIN
@ ATOMIC_LOADW_MIN
Definition: SystemZISelLowering.h:320
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZISD::VROUND
@ VROUND
Definition: SystemZISelLowering.h:261
llvm::SystemZISD::ATOMIC_LOADW_OR
@ ATOMIC_LOADW_OR
Definition: SystemZISelLowering.h:317
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SystemZISelLowering.h:391
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::SystemZISD::STRICT_FCMP
@ STRICT_FCMP
Definition: SystemZISelLowering.h:287
llvm::SystemZISD::SADDO
@ SADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: SystemZISelLowering.h:288
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1717
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:146
llvm::SystemZISD::PACKS_CC
@ PACKS_CC
Definition: SystemZISelLowering.h:205
uint16_t
llvm::SystemZTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SystemZISelLowering.cpp:5680
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:296
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4231
llvm::SystemZISD::ATOMIC_CMP_SWAP_128
@ ATOMIC_CMP_SWAP_128
Definition: SystemZISelLowering.h:350
llvm::SystemZISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: SystemZISelLowering.h:85
llvm::SystemZISD::VICMPES
@ VICMPES
Definition: SystemZISelLowering.h:236
llvm::SystemZISD::VICMPE
@ VICMPE
Definition: SystemZISelLowering.h:231
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:201
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::SystemZTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: SystemZISelLowering.cpp:832
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::SystemZISD::NC
@ NC
Definition: SystemZISelLowering.h:121
llvm::InlineAsm::Constraint_S
@ Constraint_S
Definition: InlineAsm.h:253
llvm::SystemZISD::PCREL_WRAPPER
@ PCREL_WRAPPER
Definition: SystemZISelLowering.h:44
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: SystemZISelLowering.cpp:1403
llvm::SystemZISD::PCREL_OFFSET
@ PCREL_OFFSET
Definition: SystemZISelLowering.h:51
llvm::SystemZISD::VISTR_CC
@ VISTR_CC
Definition: SystemZISelLowering.h:273
llvm::SystemZISD::VFAEZ_CC
@ VFAEZ_CC
Definition: SystemZISelLowering.h:268
llvm::SystemZISD::MERGE_LOW
@ MERGE_LOW
Definition: SystemZISelLowering.h:182
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SystemZISelLowering.h:515
llvm::SystemZISD::STRICT_VFCMPHE
@ STRICT_VFCMPHE
Definition: SystemZISelLowering.h:294
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: SystemZISelLowering.h:456
llvm::SystemZISD::UNPACK_LOW
@ UNPACK_LOW
Definition: SystemZISelLowering.h:214
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: SystemZISelLowering.cpp:1419
llvm::SystemZISD::VLER
@ VLER
Definition: SystemZISelLowering.h:356
llvm::SystemZISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: SystemZISelLowering.h:81
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1261
N
#define N
llvm::SystemZISD::ATOMIC_STORE_128
@ ATOMIC_STORE_128
Definition: SystemZISelLowering.h:346
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4323
llvm::SystemZISD::UNPACKL_LOW
@ UNPACKL_LOW
Definition: SystemZISelLowering.h:215
llvm::SystemZISD::VFTCI
@ VFTCI
Definition: SystemZISelLowering.h:253
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:266
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SystemZISD::isPCREL
bool isPCREL(unsigned Opcode)
Definition: SystemZISelLowering.h:365
llvm::SystemZISD::ATOMIC_LOADW_MAX
@ ATOMIC_LOADW_MAX
Definition: SystemZISelLowering.h:321
RegName
#define RegName(no)
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1515
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SystemZISD::SPLAT
@ SPLAT
Definition: SystemZISelLowering.h:175
llvm::SystemZISD::STRICT_VFCMPE
@ STRICT_VFCMPE
Definition: SystemZISelLowering.h:292
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1469
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SystemZISD::STPCPY
@ STPCPY
Definition: SystemZISelLowering.h:130
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: SystemZISelLowering.cpp:1286
llvm::SystemZISD::ADDCARRY
@ ADDCARRY
Definition: SystemZISelLowering.h:100
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APFloat FPImm)
Definition: SystemZISelLowering.cpp:795
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SystemZISelLowering.cpp:1432
llvm::SystemZISD::VSTRSZ_CC
@ VSTRSZ_CC
Definition: SystemZISelLowering.h:277
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:156
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::SystemZISD::PERMUTE
@ PERMUTE
Definition: SystemZISelLowering.h:198
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition: SystemZISelLowering.h:741
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SystemZISelLowering.cpp:697
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:252
llvm::SystemZISD::IPM
@ IPM
Definition: SystemZISelLowering.h:143
llvm::SystemZISD::TBEGIN
@ TBEGIN
Definition: SystemZISelLowering.h:151
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SystemZISelLowering.cpp:1132
llvm::SystemZVectorConstantInfo::VecVT
MVT VecVT
Definition: SystemZISelLowering.h:742
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SystemZISelLowering.cpp:5592
llvm::SystemZISD::POPCNT
@ POPCNT
Definition: SystemZISelLowering.h:88
llvm::SystemZISD::STRV
@ STRV
Definition: SystemZISelLowering.h:353
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
llvm::SystemZISD::STRICT_VFCMPES
@ STRICT_VFCMPES
Definition: SystemZISelLowering.h:295
llvm::SystemZISD::BYTE_MASK
@ BYTE_MASK
Definition: SystemZISelLowering.h:159
llvm::SystemZISD::NodeType
NodeType
Definition: SystemZISelLowering.h:25
llvm::SystemZISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: SystemZISelLowering.h:338
llvm::LLT
Definition: LowLevelTypeImpl.h:40