LLVM 17.0.0git
SystemZISelLowering.h
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1
2//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that SystemZ uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17
18#include "SystemZ.h"
19#include "SystemZInstrInfo.h"
23#include <optional>
24
25namespace llvm {
26namespace SystemZISD {
27enum NodeType : unsigned {
29
30 // Return with a glue operand. Operand 0 is the chain operand.
32
33 // Calls a function. Operand 0 is the chain operand and operand 1
34 // is the target address. The arguments start at operand 2.
35 // There is an optional glue operand at the end.
38
39 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
40 // (The call target is implicitly __tls_get_offset.)
43
44 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
45 // accesses (LARL). Operand 0 is the address.
47
48 // Used in cases where an offset is applied to a TargetGlobalAddress.
49 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
50 // PCREL_WRAPPER for an anchor point. This is used so that we can
51 // cheaply refer to either the full address or the anchor point
52 // as a register base.
54
55 // Integer comparisons. There are three operands: the two values
56 // to compare, and an integer of type SystemZICMP.
58
59 // Floating-point comparisons. The two operands are the values to compare.
61
62 // Test under mask. The first operand is ANDed with the second operand
63 // and the condition codes are set on the result. The third operand is
64 // a boolean that is true if the condition codes need to distinguish
65 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
66 // register forms do but the memory forms don't).
68
69 // Branches if a condition is true. Operand 0 is the chain operand;
70 // operand 1 is the 4-bit condition-code mask, with bit N in
71 // big-endian order meaning "branch if CC=N"; operand 2 is the
72 // target block and operand 3 is the flag operand.
74
75 // Selects between operand 0 and operand 1. Operand 2 is the
76 // mask of condition-code values for which operand 0 should be
77 // chosen over operand 1; it has the same form as BR_CCMASK.
78 // Operand 3 is the flag operand.
80
81 // Evaluates to the gap between the stack pointer and the
82 // base of the dynamically-allocatable area.
84
85 // For allocating stack space when using stack clash protector.
86 // Allocation is performed by block, and each block is probed.
88
89 // Count number of bits set in operand 0 per byte.
91
92 // Wrappers around the ISD opcodes of the same name. The output is GR128.
93 // Input operands may be GR64 or GR32, depending on the instruction.
98
99 // Add/subtract with overflow/carry. These have the same operands as
100 // the corresponding standard operations, except with the carry flag
101 // replaced by a condition code value.
103
104 // Set the condition code from a boolean value in operand 0.
105 // Operand 1 is a mask of all condition-code values that may result of this
106 // operation, operand 2 is a mask of condition-code values that may result
107 // if the boolean is true.
108 // Note that this operation is always optimized away, we will never
109 // generate any code for it.
111
112 // Use a series of MVCs to copy bytes from one memory location to another.
113 // The operands are:
114 // - the target address
115 // - the source address
116 // - the constant length
117 //
118 // This isn't a memory opcode because we'd need to attach two
119 // MachineMemOperands rather than one.
121
122 // Similar to MVC, but for logic operations (AND, OR, XOR).
126
127 // Use CLC to compare two blocks of memory, with the same comments
128 // as for MVC.
130
131 // Use MVC to set a block of memory after storing the first byte.
133
134 // Use an MVST-based sequence to implement stpcpy().
136
137 // Use a CLST-based sequence to implement strcmp(). The two input operands
138 // are the addresses of the strings to compare.
140
141 // Use an SRST-based sequence to search a block of memory. The first
142 // operand is the end address, the second is the start, and the third
143 // is the character to search for. CC is set to 1 on success and 2
144 // on failure.
146
147 // Store the CC value in bits 29 and 28 of an integer.
149
150 // Transaction begin. The first operand is the chain, the second
151 // the TDB pointer, and the third the immediate control field.
152 // Returns CC value and chain.
155
156 // Transaction end. Just the chain operand. Returns CC value and chain.
158
159 // Create a vector constant by filling byte N of the result with bit
160 // 15-N of the single operand.
162
163 // Create a vector constant by replicating an element-sized RISBG-style mask.
164 // The first operand specifies the starting set bit and the second operand
165 // specifies the ending set bit. Both operands count from the MSB of the
166 // element.
168
169 // Replicate a GPR scalar value into all elements of a vector.
171
172 // Create a vector from two i64 GPRs.
174
175 // Replicate one element of a vector into all elements. The first operand
176 // is the vector and the second is the index of the element to replicate.
178
179 // Interleave elements from the high half of operand 0 and the high half
180 // of operand 1.
182
183 // Likewise for the low halves.
185
186 // Concatenate the vectors in the first two operands, shift them left
187 // by the third operand, and take the first half of the result.
189
190 // Take one element of the first v2i64 operand and the one element of
191 // the second v2i64 operand and concatenate them to form a v2i64 result.
192 // The third operand is a 4-bit value of the form 0A0B, where A and B
193 // are the element selectors for the first operand and second operands
194 // respectively.
196
197 // Perform a general vector permute on vector operands 0 and 1.
198 // Each byte of operand 2 controls the corresponding byte of the result,
199 // in the same way as a byte-level VECTOR_SHUFFLE mask.
201
202 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
204
205 // Likewise, but saturate the result and set CC. PACKS_CC does signed
206 // saturation and PACKLS_CC does unsigned saturation.
209
210 // Unpack the first half of vector operand 0 into double-sized elements.
211 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
214
215 // Likewise for the second half.
218
219 // Shift each element of vector operand 0 by the number of bits specified
220 // by scalar operand 1.
224
225 // For each element of the output type, sum across all sub-elements of
226 // operand 0 belonging to the corresponding element, and add in the
227 // rightmost sub-element of the corresponding element of operand 1.
229
230 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
231 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
232 // and VICMPHL for "unsigned greater than".
236
237 // Likewise, but also set the condition codes on the result.
241
242 // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
243 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
244 // greater than" and VFCMPHE for "ordered and greater than or equal to".
248
249 // Likewise, but also set the condition codes on the result.
253
254 // Test floating-point data class for vectors.
256
257 // Extend the even f32 elements of vector operand 0 to produce a vector
258 // of f64 elements.
260
261 // Round the f64 elements of vector operand 0 to f32s and store them in the
262 // even elements of the result.
264
265 // AND the two vector operands together and set CC based on the result.
267
268 // String operations that set CC as a side-effect.
280
281 // Test Data Class.
282 //
283 // Operand 0: the value to test
284 // Operand 1: the bit mask
286
287 // Strict variants of scalar floating-point comparisons.
288 // Quiet and signaling versions.
291
292 // Strict variants of vector floating-point comparisons.
293 // Quiet and signaling versions.
300
301 // Strict variants of VEXTEND and VROUND.
304
305 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
306 // ATOMIC_LOAD_<op>.
307 //
308 // Operand 0: the address of the containing 32-bit-aligned field
309 // Operand 1: the second operand of <op>, in the high bits of an i32
310 // for everything except ATOMIC_SWAPW
311 // Operand 2: how many bits to rotate the i32 left to bring the first
312 // operand into the high bits
313 // Operand 3: the negative of operand 2, for rotating the other way
314 // Operand 4: the width of the field in bits (8 or 16)
326
327 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
328 //
329 // Operand 0: the address of the containing 32-bit-aligned field
330 // Operand 1: the compare value, in the low bits of an i32
331 // Operand 2: the swap value, in the low bits of an i32
332 // Operand 3: how many bits to rotate the i32 left to bring the first
333 // operand into the high bits
334 // Operand 4: the negative of operand 2, for rotating the other way
335 // Operand 5: the width of the field in bits (8 or 16)
337
338 // Atomic compare-and-swap returning CC value.
339 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
341
342 // 128-bit atomic load.
343 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
345
346 // 128-bit atomic store.
347 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
349
350 // 128-bit atomic compare-and-swap.
351 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
353
354 // Byte swapping load/store. Same operands as regular load/store.
356
357 // Element swapping load/store. Same operands as regular load/store.
359
360 // Prefetch from the second operand using the 4-bit control code in
361 // the first operand. The code is 1 for a load prefetch and 2 for
362 // a store prefetch.
365
366// Return true if OPCODE is some kind of PC-relative address.
367inline bool isPCREL(unsigned Opcode) {
368 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
369}
370} // end namespace SystemZISD
371
372namespace SystemZICMP {
373// Describes whether an integer comparison needs to be signed or unsigned,
374// or whether either type is OK.
375enum {
380} // end namespace SystemZICMP
381
382class SystemZSubtarget;
383
385public:
386 explicit SystemZTargetLowering(const TargetMachine &TM,
387 const SystemZSubtarget &STI);
388
389 bool useSoftFloat() const override;
390
391 // Override TargetLowering.
392 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
393 return MVT::i32;
394 }
395 MVT getVectorIdxTy(const DataLayout &DL) const override {
396 // Only the lower 12 bits of an element index are used, so we don't
397 // want to clobber the upper 32 bits of a GPR unnecessarily.
398 return MVT::i32;
399 }
401 const override {
402 // Widen subvectors to the full width rather than promoting integer
403 // elements. This is better because:
404 //
405 // (a) it means that we can handle the ABI for passing and returning
406 // sub-128 vectors without having to handle them as legal types.
407 //
408 // (b) we don't have instructions to extend on load and truncate on store,
409 // so promoting the integers is less efficient.
410 //
411 // (c) there are no multiplication instructions for the widest integer
412 // type (v2i64).
413 if (VT.getScalarSizeInBits() % 8 == 0)
414 return TypeWidenVector;
416 }
417 unsigned
419 std::optional<MVT> RegisterVT) const override {
420 // i128 inline assembly operand.
421 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
422 return 1;
424 }
425 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
426 bool preferZeroCompareBranch() const override { return true; }
427 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override {
428 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1));
429 return Mask && Mask->getValue().isIntN(16);
430 }
431 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
432 return VT.isScalarInteger();
433 }
435 EVT) const override;
437 EVT VT) const override;
438 bool isFPImmLegal(const APFloat &Imm, EVT VT,
439 bool ForCodeSize) const override;
440 bool ShouldShrinkFPConstant(EVT VT) const override {
441 // Do not shrink 64-bit FP constpool entries since LDEB is slower than
442 // LD, and having the full constant in memory enables reg/mem opcodes.
443 return VT != MVT::f64;
444 }
445 bool hasInlineStackProbe(const MachineFunction &MF) const override;
446 bool isLegalICmpImmediate(int64_t Imm) const override;
447 bool isLegalAddImmediate(int64_t Imm) const override;
448 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
449 unsigned AS,
450 Instruction *I = nullptr) const override;
451 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
453 unsigned *Fast) const override;
454 bool
455 findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit,
456 const MemOp &Op, unsigned DstAS, unsigned SrcAS,
457 const AttributeList &FuncAttributes) const override;
458 EVT getOptimalMemOpType(const MemOp &Op,
459 const AttributeList &FuncAttributes) const override;
460 bool isTruncateFree(Type *, Type *) const override;
461 bool isTruncateFree(EVT, EVT) const override;
462
463 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
464 bool MathUsed) const override {
465 // Form add and sub with overflow intrinsics regardless of any extra
466 // users of the math result.
467 return VT == MVT::i32 || VT == MVT::i64;
468 }
469
470 bool shouldConsiderGEPOffsetSplit() const override { return true; }
471
472 const char *getTargetNodeName(unsigned Opcode) const override;
473 std::pair<unsigned, const TargetRegisterClass *>
475 StringRef Constraint, MVT VT) const override;
477 getConstraintType(StringRef Constraint) const override;
479 getSingleConstraintMatchWeight(AsmOperandInfo &info,
480 const char *constraint) const override;
482 std::string &Constraint,
483 std::vector<SDValue> &Ops,
484 SelectionDAG &DAG) const override;
485
486 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
487 if (ConstraintCode.size() == 1) {
488 switch(ConstraintCode[0]) {
489 default:
490 break;
491 case 'o':
493 case 'Q':
495 case 'R':
497 case 'S':
499 case 'T':
501 }
502 } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') {
503 switch (ConstraintCode[1]) {
504 default:
505 break;
506 case 'Q':
508 case 'R':
510 case 'S':
512 case 'T':
514 }
515 }
516 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
517 }
518
519 Register getRegisterByName(const char *RegName, LLT VT,
520 const MachineFunction &MF) const override;
521
522 /// If a physical register, this returns the register that receives the
523 /// exception address on entry to an EH pad.
525 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
526 return SystemZ::R6D;
527 }
528
529 /// If a physical register, this returns the register that receives the
530 /// exception typeid on entry to a landing pad.
532 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
533 return SystemZ::R7D;
534 }
535
536 /// Override to support customized stack guard loading.
537 bool useLoadStackGuardNode() const override {
538 return true;
539 }
540 void insertSSPDeclarations(Module &M) const override {
541 }
542
545 MachineBasicBlock *BB) const override;
546 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
548 SelectionDAG &DAG) const override;
550 SelectionDAG &DAG) const override;
551 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
552 bool allowTruncateForTailCall(Type *, Type *) const override;
553 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
555 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
556 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
557 const override;
559 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
560 unsigned NumParts, MVT PartVT, EVT ValueVT,
561 std::optional<CallingConv::ID> CC) const override;
563 bool isVarArg,
565 const SDLoc &DL, SelectionDAG &DAG,
566 SmallVectorImpl<SDValue> &InVals) const override;
567 SDValue LowerCall(CallLoweringInfo &CLI,
568 SmallVectorImpl<SDValue> &InVals) const override;
569
570 std::pair<SDValue, SDValue>
571 makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName,
572 EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv,
573 bool IsSigned, SDLoc DL, bool DoesNotReturn,
574 bool IsReturnValueUsed) const;
575
577 bool isVarArg,
579 LLVMContext &Context) const override;
580 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
582 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
583 SelectionDAG &DAG) const override;
584 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
585
586 /// Determine which of the bits specified in Mask are known to be either
587 /// zero or one and return them in the KnownZero/KnownOne bitsets.
589 KnownBits &Known,
590 const APInt &DemandedElts,
591 const SelectionDAG &DAG,
592 unsigned Depth = 0) const override;
593
594 /// Determine the number of bits in the operation that are sign bits.
596 const APInt &DemandedElts,
597 const SelectionDAG &DAG,
598 unsigned Depth) const override;
599
601 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
602 bool PoisonOnly, unsigned Depth) const override;
603
605 return ISD::ANY_EXTEND;
606 }
608 return ISD::ZERO_EXTEND;
609 }
610
611 bool supportSwiftError() const override {
612 return true;
613 }
614
615 unsigned getStackProbeSize(const MachineFunction &MF) const;
616
617private:
618 const SystemZSubtarget &Subtarget;
619
620 // Implement LowerOperation for individual opcodes.
621 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
622 const SDLoc &DL, EVT VT,
623 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
624 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
625 EVT VT, ISD::CondCode CC,
626 SDValue CmpOp0, SDValue CmpOp1,
627 SDValue Chain = SDValue(),
628 bool IsSignaling = false) const;
629 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
630 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
631 bool IsSignaling) const;
632 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
633 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
634 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
635 SelectionDAG &DAG) const;
636 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
637 SelectionDAG &DAG, unsigned Opcode,
638 SDValue GOTOffset) const;
639 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
640 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
641 SelectionDAG &DAG) const;
642 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
643 SelectionDAG &DAG) const;
644 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
645 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
646 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
647 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
648 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
649 SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const;
650 SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const;
651 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
652 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
653 SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const;
654 SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const;
655 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
656 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
657 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
658 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
659 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
660 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
661 SDValue lowerUADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
662 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
663 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
664 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
665 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
666 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
667 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
668 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
669 unsigned Opcode) const;
670 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
671 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
672 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
673 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
674 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
675 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
676 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
677 bool isVectorElementLoad(SDValue Op) const;
678 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
679 SmallVectorImpl<SDValue> &Elems) const;
680 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
681 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
682 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
683 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
684 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
685 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
686 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
687 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
688 SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
689 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
690
691 bool canTreatAsByteVector(EVT VT) const;
692 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
693 unsigned Index, DAGCombinerInfo &DCI,
694 bool Force) const;
695 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
696 DAGCombinerInfo &DCI) const;
697 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
698 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
699 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
700 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
701 bool canLoadStoreByteSwapped(EVT VT) const;
702 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
703 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
704 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
705 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
706 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
707 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
708 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
709 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
710 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
711 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
712 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
713 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
714 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
715 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
716
717 SDValue unwrapAddress(SDValue N) const override;
718
719 // If the last instruction before MBBI in MBB was some form of COMPARE,
720 // try to replace it with a COMPARE AND BRANCH just before MBBI.
721 // CCMask and Target are the BRC-like operands for the branch.
722 // Return true if the change was made.
723 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
725 unsigned CCMask,
727
728 // Implement EmitInstrWithCustomInserter for individual operation types.
729 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
731 unsigned StoreOpcode, unsigned STOCOpcode,
732 bool Invert) const;
733 MachineBasicBlock *emitPair128(MachineInstr &MI,
734 MachineBasicBlock *MBB) const;
736 bool ClearEven) const;
737 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
739 unsigned BinOpcode, unsigned BitSize,
740 bool Invert = false) const;
741 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
743 unsigned CompareOpcode,
744 unsigned KeepOldMask,
745 unsigned BitSize) const;
746 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
747 MachineBasicBlock *BB) const;
748 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
749 unsigned Opcode,
750 bool IsMemset = false) const;
751 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
752 unsigned Opcode) const;
753 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
755 unsigned Opcode, bool NoFloat) const;
756 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
758 unsigned Opcode) const;
759 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
760 MachineBasicBlock *MBB) const;
761
762 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
763
765 getTargetMMOFlags(const Instruction &I) const override;
766 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
767};
768
770private:
771 APInt IntBits; // The 128 bits as an integer.
772 APInt SplatBits; // Smallest splat value.
773 APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
774 unsigned SplatBitSize = 0;
775 bool isFP128 = false;
776public:
777 unsigned Opcode = 0;
782 : SystemZVectorConstantInfo(FPImm.bitcastToAPInt()) {
783 isFP128 = (&FPImm.getSemantics() == &APFloat::IEEEquad());
784 }
786 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
787};
788
789} // end namespace llvm
790
791#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
LLVMContext & Context
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
@ Flags
Definition: TextStubV5.cpp:93
const fltSemantics & getSemantics() const
Definition: APFloat.h:1277
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A "pseudo-class" with methods for operating on BUILD_VECTORs.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
uint64_t getScalarSizeInBits() const
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
bool useSoftFloat() const override
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
bool shouldConsiderGEPOffsetSplit() const override
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const override
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
unsigned getStackProbeSize(const MachineFunction &MF) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Value * getOperand(unsigned i) const
Definition: User.h:169
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:779
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1348
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:776
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1360
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1354
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1471
bool isPCREL(unsigned Opcode)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
static const fltSemantics & IEEEquad() LLVM_READNONE
Definition: APFloat.cpp:246
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
SmallVector< unsigned, 2 > OpVals
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)