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SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 
17 #include "SystemZ.h"
18 #include "SystemZInstrInfo.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer comparisons. There are three operands: the two values
54  // to compare, and an integer of type SystemZICMP.
56 
57  // Floating-point comparisons. The two operands are the values to compare.
59 
60  // Test under mask. The first operand is ANDed with the second operand
61  // and the condition codes are set on the result. The third operand is
62  // a boolean that is true if the condition codes need to distinguish
63  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
64  // register forms do but the memory forms don't).
65  TM,
66 
67  // Branches if a condition is true. Operand 0 is the chain operand;
68  // operand 1 is the 4-bit condition-code mask, with bit N in
69  // big-endian order meaning "branch if CC=N"; operand 2 is the
70  // target block and operand 3 is the flag operand.
72 
73  // Selects between operand 0 and operand 1. Operand 2 is the
74  // mask of condition-code values for which operand 0 should be
75  // chosen over operand 1; it has the same form as BR_CCMASK.
76  // Operand 3 is the flag operand.
78 
79  // Evaluates to the gap between the stack pointer and the
80  // base of the dynamically-allocatable area.
82 
83  // For allocating stack space when using stack clash protector.
84  // Allocation is performed by block, and each block is probed.
86 
87  // Count number of bits set in operand 0 per byte.
89 
90  // Wrappers around the ISD opcodes of the same name. The output is GR128.
91  // Input operands may be GR64 or GR32, depending on the instruction.
96 
97  // Add/subtract with overflow/carry. These have the same operands as
98  // the corresponding standard operations, except with the carry flag
99  // replaced by a condition code value.
101 
102  // Set the condition code from a boolean value in operand 0.
103  // Operand 1 is a mask of all condition-code values that may result of this
104  // operation, operand 2 is a mask of condition-code values that may result
105  // if the boolean is true.
106  // Note that this operation is always optimized away, we will never
107  // generate any code for it.
109 
110  // Use a series of MVCs to copy bytes from one memory location to another.
111  // The operands are:
112  // - the target address
113  // - the source address
114  // - the constant length
115  //
116  // This isn't a memory opcode because we'd need to attach two
117  // MachineMemOperands rather than one.
119 
120  // Like MVC, but implemented as a loop that handles X*256 bytes
121  // followed by straight-line code to handle the rest (if any).
122  // The value of X is passed as an additional operand.
124 
125  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
126  NC,
128  OC,
130  XC,
132 
133  // Use CLC to compare two blocks of memory, with the same comments
134  // as for MVC and MVC_LOOP.
137 
138  // Use an MVST-based sequence to implement stpcpy().
140 
141  // Use a CLST-based sequence to implement strcmp(). The two input operands
142  // are the addresses of the strings to compare.
144 
145  // Use an SRST-based sequence to search a block of memory. The first
146  // operand is the end address, the second is the start, and the third
147  // is the character to search for. CC is set to 1 on success and 2
148  // on failure.
150 
151  // Store the CC value in bits 29 and 28 of an integer.
153 
154  // Compiler barrier only; generate a no-op.
156 
157  // Transaction begin. The first operand is the chain, the second
158  // the TDB pointer, and the third the immediate control field.
159  // Returns CC value and chain.
162 
163  // Transaction end. Just the chain operand. Returns CC value and chain.
165 
166  // Create a vector constant by filling byte N of the result with bit
167  // 15-N of the single operand.
169 
170  // Create a vector constant by replicating an element-sized RISBG-style mask.
171  // The first operand specifies the starting set bit and the second operand
172  // specifies the ending set bit. Both operands count from the MSB of the
173  // element.
175 
176  // Replicate a GPR scalar value into all elements of a vector.
178 
179  // Create a vector from two i64 GPRs.
181 
182  // Replicate one element of a vector into all elements. The first operand
183  // is the vector and the second is the index of the element to replicate.
185 
186  // Interleave elements from the high half of operand 0 and the high half
187  // of operand 1.
189 
190  // Likewise for the low halves.
192 
193  // Concatenate the vectors in the first two operands, shift them left
194  // by the third operand, and take the first half of the result.
196 
197  // Take one element of the first v2i64 operand and the one element of
198  // the second v2i64 operand and concatenate them to form a v2i64 result.
199  // The third operand is a 4-bit value of the form 0A0B, where A and B
200  // are the element selectors for the first operand and second operands
201  // respectively.
203 
204  // Perform a general vector permute on vector operands 0 and 1.
205  // Each byte of operand 2 controls the corresponding byte of the result,
206  // in the same way as a byte-level VECTOR_SHUFFLE mask.
208 
209  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
211 
212  // Likewise, but saturate the result and set CC. PACKS_CC does signed
213  // saturation and PACKLS_CC does unsigned saturation.
216 
217  // Unpack the first half of vector operand 0 into double-sized elements.
218  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
221 
222  // Likewise for the second half.
225 
226  // Shift each element of vector operand 0 by the number of bits specified
227  // by scalar operand 1.
231 
232  // For each element of the output type, sum across all sub-elements of
233  // operand 0 belonging to the corresponding element, and add in the
234  // rightmost sub-element of the corresponding element of operand 1.
236 
237  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
238  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
239  // and VICMPHL for "unsigned greater than".
243 
244  // Likewise, but also set the condition codes on the result.
248 
249  // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
250  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
251  // greater than" and VFCMPHE for "ordered and greater than or equal to".
255 
256  // Likewise, but also set the condition codes on the result.
260 
261  // Test floating-point data class for vectors.
263 
264  // Extend the even f32 elements of vector operand 0 to produce a vector
265  // of f64 elements.
267 
268  // Round the f64 elements of vector operand 0 to f32s and store them in the
269  // even elements of the result.
271 
272  // AND the two vector operands together and set CC based on the result.
274 
275  // String operations that set CC as a side-effect.
287 
288  // Test Data Class.
289  //
290  // Operand 0: the value to test
291  // Operand 1: the bit mask
293 
294  // Strict variants of scalar floating-point comparisons.
295  // Quiet and signaling versions.
298 
299  // Strict variants of vector floating-point comparisons.
300  // Quiet and signaling versions.
307 
308  // Strict variants of VEXTEND and VROUND.
311 
312  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
313  // ATOMIC_LOAD_<op>.
314  //
315  // Operand 0: the address of the containing 32-bit-aligned field
316  // Operand 1: the second operand of <op>, in the high bits of an i32
317  // for everything except ATOMIC_SWAPW
318  // Operand 2: how many bits to rotate the i32 left to bring the first
319  // operand into the high bits
320  // Operand 3: the negative of operand 2, for rotating the other way
321  // Operand 4: the width of the field in bits (8 or 16)
333 
334  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
335  //
336  // Operand 0: the address of the containing 32-bit-aligned field
337  // Operand 1: the compare value, in the low bits of an i32
338  // Operand 2: the swap value, in the low bits of an i32
339  // Operand 3: how many bits to rotate the i32 left to bring the first
340  // operand into the high bits
341  // Operand 4: the negative of operand 2, for rotating the other way
342  // Operand 5: the width of the field in bits (8 or 16)
344 
345  // Atomic compare-and-swap returning CC value.
346  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
348 
349  // 128-bit atomic load.
350  // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
352 
353  // 128-bit atomic store.
354  // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
356 
357  // 128-bit atomic compare-and-swap.
358  // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
360 
361  // Byte swapping load/store. Same operands as regular load/store.
363 
364  // Element swapping load/store. Same operands as regular load/store.
366 
367  // Prefetch from the second operand using the 4-bit control code in
368  // the first operand. The code is 1 for a load prefetch and 2 for
369  // a store prefetch.
371 };
372 
373 // Return true if OPCODE is some kind of PC-relative address.
374 inline bool isPCREL(unsigned Opcode) {
375  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
376 }
377 } // end namespace SystemZISD
378 
379 namespace SystemZICMP {
380 // Describes whether an integer comparison needs to be signed or unsigned,
381 // or whether either type is OK.
382 enum {
386 };
387 } // end namespace SystemZICMP
388 
389 class SystemZSubtarget;
390 class SystemZTargetMachine;
391 
393 public:
394  explicit SystemZTargetLowering(const TargetMachine &TM,
395  const SystemZSubtarget &STI);
396 
397  bool useSoftFloat() const override;
398 
399  // Override TargetLowering.
400  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
401  return MVT::i32;
402  }
403  MVT getVectorIdxTy(const DataLayout &DL) const override {
404  // Only the lower 12 bits of an element index are used, so we don't
405  // want to clobber the upper 32 bits of a GPR unnecessarily.
406  return MVT::i32;
407  }
409  const override {
410  // Widen subvectors to the full width rather than promoting integer
411  // elements. This is better because:
412  //
413  // (a) it means that we can handle the ABI for passing and returning
414  // sub-128 vectors without having to handle them as legal types.
415  //
416  // (b) we don't have instructions to extend on load and truncate on store,
417  // so promoting the integers is less efficient.
418  //
419  // (c) there are no multiplication instructions for the widest integer
420  // type (v2i64).
421  if (VT.getScalarSizeInBits() % 8 == 0)
422  return TypeWidenVector;
424  }
425  unsigned
427  Optional<MVT> RegisterVT) const override {
428  // i128 inline assembly operand.
429  if (VT == MVT::i128 &&
430  RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped)
431  return 1;
433  }
434  bool isCheapToSpeculateCtlz() const override { return true; }
435  bool preferZeroCompareBranch() const override { return true; }
436  bool hasBitPreservingFPLogic(EVT VT) const override {
437  EVT ScVT = VT.getScalarType();
438  return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128;
439  }
441  EVT) const override;
443  EVT VT) const override;
444  bool isFPImmLegal(const APFloat &Imm, EVT VT,
445  bool ForCodeSize) const override;
446  bool hasInlineStackProbe(MachineFunction &MF) const override;
447  bool isLegalICmpImmediate(int64_t Imm) const override;
448  bool isLegalAddImmediate(int64_t Imm) const override;
449  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
450  unsigned AS,
451  Instruction *I = nullptr) const override;
452  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
454  bool *Fast) const override;
455  bool isTruncateFree(Type *, Type *) const override;
456  bool isTruncateFree(EVT, EVT) const override;
457 
458  bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
459  bool MathUsed) const override {
460  // Form add and sub with overflow intrinsics regardless of any extra
461  // users of the math result.
462  return VT == MVT::i32 || VT == MVT::i64;
463  }
464 
465  const char *getTargetNodeName(unsigned Opcode) const override;
466  std::pair<unsigned, const TargetRegisterClass *>
468  StringRef Constraint, MVT VT) const override;
470  getConstraintType(StringRef Constraint) const override;
472  getSingleConstraintMatchWeight(AsmOperandInfo &info,
473  const char *constraint) const override;
475  std::string &Constraint,
476  std::vector<SDValue> &Ops,
477  SelectionDAG &DAG) const override;
478 
479  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
480  if (ConstraintCode.size() == 1) {
481  switch(ConstraintCode[0]) {
482  default:
483  break;
484  case 'o':
486  case 'Q':
488  case 'R':
490  case 'S':
492  case 'T':
494  }
495  }
496  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
497  }
498 
499  Register getRegisterByName(const char *RegName, LLT VT,
500  const MachineFunction &MF) const override;
501 
502  /// If a physical register, this returns the register that receives the
503  /// exception address on entry to an EH pad.
504  Register
505  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
506  return SystemZ::R6D;
507  }
508 
509  /// If a physical register, this returns the register that receives the
510  /// exception typeid on entry to a landing pad.
511  Register
512  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
513  return SystemZ::R7D;
514  }
515 
516  /// Override to support customized stack guard loading.
517  bool useLoadStackGuardNode() const override {
518  return true;
519  }
520  void insertSSPDeclarations(Module &M) const override {
521  }
522 
525  MachineBasicBlock *BB) const override;
526  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
528  SelectionDAG &DAG) const override;
530  SelectionDAG &DAG) const override;
531  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
532  bool allowTruncateForTailCall(Type *, Type *) const override;
533  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
535  SDValue Val, SDValue *Parts,
536  unsigned NumParts, MVT PartVT,
537  Optional<CallingConv::ID> CC) const override;
538  SDValue
540  const SDValue *Parts, unsigned NumParts,
541  MVT PartVT, EVT ValueVT,
542  Optional<CallingConv::ID> CC) const override;
544  bool isVarArg,
546  const SDLoc &DL, SelectionDAG &DAG,
547  SmallVectorImpl<SDValue> &InVals) const override;
548  SDValue LowerCall(CallLoweringInfo &CLI,
549  SmallVectorImpl<SDValue> &InVals) const override;
550 
552  bool isVarArg,
554  LLVMContext &Context) const override;
555  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
557  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
558  SelectionDAG &DAG) const override;
559  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
560 
561  /// Determine which of the bits specified in Mask are known to be either
562  /// zero or one and return them in the KnownZero/KnownOne bitsets.
564  KnownBits &Known,
565  const APInt &DemandedElts,
566  const SelectionDAG &DAG,
567  unsigned Depth = 0) const override;
568 
569  /// Determine the number of bits in the operation that are sign bits.
571  const APInt &DemandedElts,
572  const SelectionDAG &DAG,
573  unsigned Depth) const override;
574 
576  return ISD::ANY_EXTEND;
577  }
579  return ISD::ZERO_EXTEND;
580  }
581 
582  bool supportSwiftError() const override {
583  return true;
584  }
585 
586  unsigned getStackProbeSize(MachineFunction &MF) const;
587 
588 private:
589  const SystemZSubtarget &Subtarget;
590 
591  // Implement LowerOperation for individual opcodes.
592  SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
593  const SDLoc &DL, EVT VT,
594  SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const;
595  SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
596  EVT VT, ISD::CondCode CC,
597  SDValue CmpOp0, SDValue CmpOp1,
598  SDValue Chain = SDValue(),
599  bool IsSignaling = false) const;
600  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
601  SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG,
602  bool IsSignaling) const;
603  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
604  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
605  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
606  SelectionDAG &DAG) const;
607  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
608  SelectionDAG &DAG, unsigned Opcode,
609  SDValue GOTOffset) const;
610  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
611  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
612  SelectionDAG &DAG) const;
613  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
614  SelectionDAG &DAG) const;
615  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
616  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
617  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
618  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
619  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
620  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
621  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
622  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
623  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
624  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
625  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
626  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
627  SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
628  SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
629  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
630  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
631  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
634  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
636  unsigned Opcode) const;
637  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
638  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
641  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
642  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
643  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
644  bool isVectorElementLoad(SDValue Op) const;
645  SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
646  SmallVectorImpl<SDValue> &Elems) const;
647  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
653  SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
654  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
655 
656  bool canTreatAsByteVector(EVT VT) const;
657  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
658  unsigned Index, DAGCombinerInfo &DCI,
659  bool Force) const;
660  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
661  DAGCombinerInfo &DCI) const;
662  SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
663  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
664  SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
665  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
666  bool canLoadStoreByteSwapped(EVT VT) const;
667  SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const;
668  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
669  SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const;
670  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
671  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
672  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
673  SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
674  SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const;
675  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
676  SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
677  SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
678  SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
679  SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const;
680  SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const;
681 
682  SDValue unwrapAddress(SDValue N) const override;
683 
684  // If the last instruction before MBBI in MBB was some form of COMPARE,
685  // try to replace it with a COMPARE AND BRANCH just before MBBI.
686  // CCMask and Target are the BRC-like operands for the branch.
687  // Return true if the change was made.
688  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
690  unsigned CCMask,
691  MachineBasicBlock *Target) const;
692 
693  // Implement EmitInstrWithCustomInserter for individual operation types.
694  MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
696  unsigned StoreOpcode, unsigned STOCOpcode,
697  bool Invert) const;
698  MachineBasicBlock *emitPair128(MachineInstr &MI,
699  MachineBasicBlock *MBB) const;
701  bool ClearEven) const;
702  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
704  unsigned BinOpcode, unsigned BitSize,
705  bool Invert = false) const;
706  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
708  unsigned CompareOpcode,
709  unsigned KeepOldMask,
710  unsigned BitSize) const;
711  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
712  MachineBasicBlock *BB) const;
713  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
714  unsigned Opcode) const;
715  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
716  unsigned Opcode) const;
717  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
719  unsigned Opcode, bool NoFloat) const;
720  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
722  unsigned Opcode) const;
723  MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
724  MachineBasicBlock *MBB) const;
725 
726  SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const;
727 
729  getTargetMMOFlags(const Instruction &I) const override;
730  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
731 };
732 
734 private:
735  APInt IntBits; // The 128 bits as an integer.
736  APInt SplatBits; // Smallest splat value.
737  APInt SplatUndef; // Bits correspoding to undef operands of the BVN.
738  unsigned SplatBitSize = 0;
739  bool isFP128 = false;
740 
741 public:
742  unsigned Opcode = 0;
747  bool isVectorConstantLegal(const SystemZSubtarget &Subtarget);
748 };
749 
750 } // end namespace llvm
751 
752 #endif
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:438
llvm::InlineAsm::Constraint_S
@ Constraint_S
Definition: InlineAsm.h:253
llvm::SystemZTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SystemZISelLowering.cpp:5598
llvm::SystemZISD::UADDO
@ UADDO
Definition: SystemZISelLowering.h:100
llvm::InlineAsm::Constraint_T
@ Constraint_T
Definition: InlineAsm.h:254
llvm::SystemZISD::SELECT_CCMASK
@ SELECT_CCMASK
Definition: SystemZISelLowering.h:77
llvm::SystemZTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SystemZISelLowering.cpp:1230
llvm::SystemZISD::SDIVREM
@ SDIVREM
Definition: SystemZISelLowering.h:94
llvm::SystemZISD::ATOMIC_LOADW_SUB
@ ATOMIC_LOADW_SUB
Definition: SystemZISelLowering.h:324
llvm::SystemZISD::SUBCARRY
@ SUBCARRY
Definition: SystemZISelLowering.h:100
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
Definition: AllocatorList.h:23
llvm::SystemZISD::ATOMIC_LOAD_128
@ ATOMIC_LOAD_128
Definition: SystemZISelLowering.h:351
llvm::SystemZISD::USUBO
@ USUBO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::RET_FLAG
@ RET_FLAG
Definition: SystemZISelLowering.h:29
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::SystemZTargetLowering::isTruncateFree
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: SystemZISelLowering.cpp:988
llvm::SystemZTargetLowering::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT) const override
Return the number of registers that this ValueType will eventually require.
Definition: SystemZISelLowering.h:426
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4118
llvm::SystemZTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
Definition: SystemZISelLowering.cpp:685
llvm::SystemZISD::ICMP
@ ICMP
Definition: SystemZISelLowering.h:55
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SystemZTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SystemZISelLowering.cpp:1293
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:251
llvm::SystemZISD::GET_CCMASK
@ GET_CCMASK
Definition: SystemZISelLowering.h:108
llvm::MVT::i128
@ i128
Definition: MachineValueType.h:45
llvm::SystemZISD::VICMPH
@ VICMPH
Definition: SystemZISelLowering.h:241
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:125
llvm::SystemZTargetLowering
Definition: SystemZISelLowering.h:392
llvm::SmallVector< unsigned, 2 >
llvm::SystemZISD::PACKLS_CC
@ PACKLS_CC
Definition: SystemZISelLowering.h:215
llvm::SystemZISD::CLC
@ CLC
Definition: SystemZISelLowering.h:135
llvm::SystemZTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SystemZISelLowering.cpp:5417
llvm::SystemZISD::ATOMIC_CMP_SWAPW
@ ATOMIC_CMP_SWAPW
Definition: SystemZISelLowering.h:343
llvm::SystemZISD::VICMPHLS
@ VICMPHLS
Definition: SystemZISelLowering.h:247
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::SystemZISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SystemZISelLowering.h:26
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
MachineBasicBlock.h
llvm::SystemZISD::ROTATE_MASK
@ ROTATE_MASK
Definition: SystemZISelLowering.h:174
llvm::SystemZISD::VFENEZ_CC
@ VFENEZ_CC
Definition: SystemZISelLowering.h:281
llvm::SystemZISD::VFAE_CC
@ VFAE_CC
Definition: SystemZISelLowering.h:276
llvm::SystemZISD::VSTRS_CC
@ VSTRS_CC
Definition: SystemZISelLowering.h:285
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::SystemZTargetLowering::allowTruncateForTailCall
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
Definition: SystemZISelLowering.cpp:1288
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::SystemZISD::PREFETCH
@ PREFETCH
Definition: SystemZISelLowering.h:370
llvm::SystemZTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SystemZISelLowering.cpp:1588
llvm::SystemZISD::VSTER
@ VSTER
Definition: SystemZISelLowering.h:365
llvm::SystemZTargetLowering::SystemZTargetLowering
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
Definition: SystemZISelLowering.cpp:80
llvm::Optional
Definition: APInt.h:33
llvm::SystemZTargetLowering::preferZeroCompareBranch
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Definition: SystemZISelLowering.h:435
llvm::SystemZTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: SystemZISelLowering.h:578
llvm::SystemZTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SystemZISelLowering.cpp:1218
llvm::SystemZISD::STRICT_VEXTEND
@ STRICT_VEXTEND
Definition: SystemZISelLowering.h:309
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::SystemZTargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: SystemZISelLowering.cpp:7049
llvm::SystemZTargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SystemZISelLowering.cpp:1009
llvm::SystemZTargetLowering::getSingleConstraintMatchWeight
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SystemZISelLowering.cpp:1042
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2107
llvm::SystemZISD::VICMPHL
@ VICMPHL
Definition: SystemZISelLowering.h:242
SelectionDAG.h
llvm::SystemZISD::VSHL_BY_SCALAR
@ VSHL_BY_SCALAR
Definition: SystemZISelLowering.h:228
llvm::SystemZISD::PERMUTE_DWORDS
@ PERMUTE_DWORDS
Definition: SystemZISelLowering.h:202
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SystemZTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SystemZISelLowering.h:436
llvm::SystemZTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SystemZISelLowering.h:520
llvm::SystemZISD::TEND
@ TEND
Definition: SystemZISelLowering.h:164
llvm::SystemZTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SystemZISelLowering.cpp:1802
llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
Definition: SystemZISelLowering.cpp:6994
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:288
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::SystemZISD::ATOMIC_SWAPW
@ ATOMIC_SWAPW
Definition: SystemZISelLowering.h:322
TargetLowering.h
llvm::SystemZTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: SystemZISelLowering.h:403
llvm::SystemZISD::ATOMIC_LOADW_UMAX
@ ATOMIC_LOADW_UMAX
Definition: SystemZISelLowering.h:332
llvm::SystemZISD::BR_CCMASK
@ BR_CCMASK
Definition: SystemZISelLowering.h:71
llvm::SystemZISD::UNPACK_HIGH
@ UNPACK_HIGH
Definition: SystemZISelLowering.h:219
llvm::SystemZISD::ATOMIC_LOADW_ADD
@ ATOMIC_LOADW_ADD
Definition: SystemZISelLowering.h:323
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
SystemZInstrInfo.h
llvm::SystemZISD::TLS_LDCALL
@ TLS_LDCALL
Definition: SystemZISelLowering.h:40
llvm::SystemZISD::VSRA_BY_SCALAR
@ VSRA_BY_SCALAR
Definition: SystemZISelLowering.h:230
llvm::SystemZISD::TLS_GDCALL
@ TLS_GDCALL
Definition: SystemZISelLowering.h:39
llvm::SystemZISD::VFEEZ_CC
@ VFEEZ_CC
Definition: SystemZISelLowering.h:279
llvm::SystemZISD::ATOMIC_LOADW_UMIN
@ ATOMIC_LOADW_UMIN
Definition: SystemZISelLowering.h:331
llvm::SystemZTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SystemZISelLowering.h:505
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::SystemZTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: SystemZISelLowering.cpp:845
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1796
llvm::SystemZISD::SIBCALL
@ SIBCALL
Definition: SystemZISelLowering.h:35
llvm::SystemZISD::JOIN_DWORDS
@ JOIN_DWORDS
Definition: SystemZISelLowering.h:180
llvm::SystemZISD::VSTRCZ_CC
@ VSTRCZ_CC
Definition: SystemZISelLowering.h:284
llvm::SystemZTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SystemZISelLowering.cpp:8199
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3158
llvm::SystemZISD::VSRL_BY_SCALAR
@ VSRL_BY_SCALAR
Definition: SystemZISelLowering.h:229
llvm::SystemZTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: SystemZISelLowering.h:575
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1015
llvm::SystemZISD::UNPACKL_HIGH
@ UNPACKL_HIGH
Definition: SystemZISelLowering.h:220
llvm::SystemZISD::STRICT_VFCMPHES
@ STRICT_VFCMPHES
Definition: SystemZISelLowering.h:306
llvm::SystemZISD::VFCMPHES
@ VFCMPHES
Definition: SystemZISelLowering.h:259
llvm::SystemZISD::CALL
@ CALL
Definition: SystemZISelLowering.h:34
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SystemZISD::MVC_LOOP
@ MVC_LOOP
Definition: SystemZISelLowering.h:123
llvm::SystemZISD::ATOMIC_LOADW_AND
@ ATOMIC_LOADW_AND
Definition: SystemZISelLowering.h:325
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:45
llvm::SystemZICMP::Any
@ Any
Definition: SystemZISelLowering.h:383
llvm::SystemZVectorConstantInfo::isVectorConstantLegal
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
Definition: SystemZISelLowering.cpp:714
llvm::SystemZISD::STRCMP
@ STRCMP
Definition: SystemZISelLowering.h:143
llvm::SystemZISD::STRICT_VROUND
@ STRICT_VROUND
Definition: SystemZISelLowering.h:310
llvm::SystemZISD::VFEE_CC
@ VFEE_CC
Definition: SystemZISelLowering.h:278
SystemZ.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::SystemZISD::VSUM
@ VSUM
Definition: SystemZISelLowering.h:235
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SystemZISD::FCMP
@ FCMP
Definition: SystemZISelLowering.h:58
llvm::SystemZTargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: SystemZISelLowering.h:582
llvm::SystemZISD::VFCMPE
@ VFCMPE
Definition: SystemZISelLowering.h:252
llvm::SystemZISD::UDIVREM
@ UDIVREM
Definition: SystemZISelLowering.h:95
llvm::SystemZISD::SSUBO
@ SSUBO
Definition: SystemZISelLowering.h:100
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::SystemZISD::VTM
@ VTM
Definition: SystemZISelLowering.h:273
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SystemZTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SystemZISelLowering.cpp:681
llvm::SystemZISD::ATOMIC_LOADW_NAND
@ ATOMIC_LOADW_NAND
Definition: SystemZISelLowering.h:328
llvm::SystemZISD::SMUL_LOHI
@ SMUL_LOHI
Definition: SystemZISelLowering.h:92
llvm::SystemZISD::VFCMPHE
@ VFCMPHE
Definition: SystemZISelLowering.h:254
llvm::SystemZVectorConstantInfo::Opcode
unsigned Opcode
Definition: SystemZISelLowering.h:742
llvm::SystemZICMP::SignedOnly
@ SignedOnly
Definition: SystemZISelLowering.h:385
llvm::InlineAsm::Constraint_R
@ Constraint_R
Definition: InlineAsm.h:252
llvm::SystemZISD::UMUL_LOHI
@ UMUL_LOHI
Definition: SystemZISelLowering.h:93
llvm::SystemZTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SystemZISelLowering.cpp:6728
llvm::SystemZISD::TBEGIN_NOFLOAT
@ TBEGIN_NOFLOAT
Definition: SystemZISelLowering.h:161
llvm::APFloat
Definition: APFloat.h:701
llvm::SystemZISD::TDC
@ TDC
Definition: SystemZISelLowering.h:292
llvm::SystemZTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SystemZISelLowering.cpp:6876
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SystemZISD::VICMPHS
@ VICMPHS
Definition: SystemZISelLowering.h:246
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SystemZVectorConstantInfo
Definition: SystemZISelLowering.h:733
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1241
llvm::SystemZISD::MVC
@ MVC
Definition: SystemZISelLowering.h:118
llvm::SystemZISD::SHL_DOUBLE
@ SHL_DOUBLE
Definition: SystemZISelLowering.h:195
llvm::SystemZISD::MERGE_HIGH
@ MERGE_HIGH
Definition: SystemZISelLowering.h:188
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SystemZTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
Definition: SystemZISelLowering.cpp:855
llvm::SystemZISD::LRV
@ LRV
Definition: SystemZISelLowering.h:362
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:130
llvm::SystemZTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: SystemZISelLowering.cpp:850
llvm::SystemZTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SystemZISelLowering.cpp:1782
llvm::SystemZTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SystemZISelLowering.h:512
llvm::SystemZISD::VEXTEND
@ VEXTEND
Definition: SystemZISelLowering.h:266
llvm::SystemZISD::CLC_LOOP
@ CLC_LOOP
Definition: SystemZISelLowering.h:136
llvm::SystemZISD::STRICT_VFCMPHS
@ STRICT_VFCMPHS
Definition: SystemZISelLowering.h:305
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::SystemZISD::VSTRC_CC
@ VSTRC_CC
Definition: SystemZISelLowering.h:283
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SystemZISD::OC
@ OC
Definition: SystemZISelLowering.h:128
llvm::SystemZISD::SEARCH_STRING
@ SEARCH_STRING
Definition: SystemZISelLowering.h:149
llvm::SystemZTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: SystemZISelLowering.h:434
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1341
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::SystemZISD::VFCMPES
@ VFCMPES
Definition: SystemZISelLowering.h:257
llvm::SystemZISD::VFCMPH
@ VFCMPH
Definition: SystemZISelLowering.h:253
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::SystemZISD::ATOMIC_LOADW_XOR
@ ATOMIC_LOADW_XOR
Definition: SystemZISelLowering.h:327
llvm::SystemZISD::VFCMPHS
@ VFCMPHS
Definition: SystemZISelLowering.h:258
llvm::SystemZISD::STRICT_VFCMPH
@ STRICT_VFCMPH
Definition: SystemZISelLowering.h:302
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::SystemZTargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: SystemZISelLowering.cpp:837
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1817
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::BuildVectorSDNode
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Definition: SelectionDAGNodes.h:1922
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::SystemZTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SystemZISelLowering.cpp:962
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SystemZISD::VFENE_CC
@ VFENE_CC
Definition: SystemZISelLowering.h:280
llvm::SystemZTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: SystemZISelLowering.h:479
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::SystemZISD::REPLICATE
@ REPLICATE
Definition: SystemZISelLowering.h:177
Node
Definition: ItaniumDemangle.h:114
llvm::SystemZTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SystemZISelLowering.h:408
llvm::SystemZISD::ATOMIC_LOADW_MIN
@ ATOMIC_LOADW_MIN
Definition: SystemZISelLowering.h:329
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SystemZISD::VROUND
@ VROUND
Definition: SystemZISelLowering.h:270
llvm::SystemZISD::ATOMIC_LOADW_OR
@ ATOMIC_LOADW_OR
Definition: SystemZISelLowering.h:326
llvm::SystemZTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: SystemZISelLowering.h:400
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::SystemZISD::STRICT_FCMP
@ STRICT_FCMP
Definition: SystemZISelLowering.h:296
llvm::SystemZISD::SADDO
@ SADDO
Definition: SystemZISelLowering.h:100
llvm::SystemZISD::NC_LOOP
@ NC_LOOP
Definition: SystemZISelLowering.h:127
llvm::SystemZISD::STRICT_FCMPS
@ STRICT_FCMPS
Definition: SystemZISelLowering.h:297
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1693
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:155
llvm::SystemZISD::PACKS_CC
@ PACKS_CC
Definition: SystemZISelLowering.h:214
uint16_t
llvm::SystemZTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SystemZISelLowering.cpp:5604
llvm::EVT::getScalarType
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:288
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4127
llvm::SystemZISD::ATOMIC_CMP_SWAP_128
@ ATOMIC_CMP_SWAP_128
Definition: SystemZISelLowering.h:359
llvm::SystemZISD::PROBED_ALLOCA
@ PROBED_ALLOCA
Definition: SystemZISelLowering.h:85
llvm::SystemZISD::VICMPES
@ VICMPES
Definition: SystemZISelLowering.h:245
llvm::SystemZISD::VICMPE
@ VICMPE
Definition: SystemZISelLowering.h:240
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::SystemZISD::PACK
@ PACK
Definition: SystemZISelLowering.h:210
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SystemZTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: SystemZISelLowering.cpp:827
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::InlineAsm::Constraint_o
@ Constraint_o
Definition: InlineAsm.h:248
llvm::SystemZISD::NC
@ NC
Definition: SystemZISelLowering.h:126
llvm::SystemZISD::PCREL_WRAPPER
@ PCREL_WRAPPER
Definition: SystemZISelLowering.h:44
llvm::SystemZTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: SystemZISelLowering.cpp:1391
llvm::SystemZISD::PCREL_OFFSET
@ PCREL_OFFSET
Definition: SystemZISelLowering.h:51
llvm::SystemZISD::VISTR_CC
@ VISTR_CC
Definition: SystemZISelLowering.h:282
llvm::SystemZISD::OC_LOOP
@ OC_LOOP
Definition: SystemZISelLowering.h:129
llvm::SystemZISD::VFAEZ_CC
@ VFAEZ_CC
Definition: SystemZISelLowering.h:277
llvm::SystemZISD::MERGE_LOW
@ MERGE_LOW
Definition: SystemZISelLowering.h:191
llvm::SystemZTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SystemZISelLowering.h:517
llvm::SystemZISD::STRICT_VFCMPHE
@ STRICT_VFCMPHE
Definition: SystemZISelLowering.h:303
llvm::SystemZISD::XC_LOOP
@ XC_LOOP
Definition: SystemZISelLowering.h:131
llvm::SystemZTargetLowering::shouldFormOverflowOp
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Definition: SystemZISelLowering.h:458
llvm::SystemZISD::UNPACK_LOW
@ UNPACK_LOW
Definition: SystemZISelLowering.h:223
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:55
llvm::SystemZTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: SystemZISelLowering.cpp:1407
llvm::SystemZISD::VLER
@ VLER
Definition: SystemZISelLowering.h:365
llvm::SystemZISD::ADJDYNALLOC
@ ADJDYNALLOC
Definition: SystemZISelLowering.h:81
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1247
N
#define N
llvm::SystemZISD::ATOMIC_STORE_128
@ ATOMIC_STORE_128
Definition: SystemZISelLowering.h:355
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4219
llvm::SystemZISD::UNPACKL_LOW
@ UNPACKL_LOW
Definition: SystemZISelLowering.h:224
llvm::SystemZISD::VFTCI
@ VFTCI
Definition: SystemZISelLowering.h:262
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:253
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::SystemZISD::isPCREL
bool isPCREL(unsigned Opcode)
Definition: SystemZISelLowering.h:374
llvm::SystemZISD::ATOMIC_LOADW_MAX
@ ATOMIC_LOADW_MAX
Definition: SystemZISelLowering.h:330
RegName
#define RegName(no)
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1485
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SystemZISD::SPLAT
@ SPLAT
Definition: SystemZISelLowering.h:184
llvm::SystemZISD::STRICT_VFCMPE
@ STRICT_VFCMPE
Definition: SystemZISelLowering.h:301
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SystemZISD::STPCPY
@ STPCPY
Definition: SystemZISelLowering.h:139
llvm::SystemZTargetLowering::getScratchRegisters
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: SystemZISelLowering.cpp:1281
llvm::SystemZISD::ADDCARRY
@ ADDCARRY
Definition: SystemZISelLowering.h:100
llvm::SystemZVectorConstantInfo::SystemZVectorConstantInfo
SystemZVectorConstantInfo(APFloat FPImm)
Definition: SystemZISelLowering.cpp:790
llvm::SystemZTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SystemZISelLowering.cpp:1420
llvm::SystemZISD::VSTRSZ_CC
@ VSTRSZ_CC
Definition: SystemZISelLowering.h:286
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:52
llvm::SystemZISD::PERMUTE
@ PERMUTE
Definition: SystemZISelLowering.h:207
llvm::SystemZICMP::UnsignedOnly
@ UnsignedOnly
Definition: SystemZISelLowering.h:384
llvm::SystemZVectorConstantInfo::OpVals
SmallVector< unsigned, 2 > OpVals
Definition: SystemZISelLowering.h:743
llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SystemZISelLowering.cpp:692
llvm::SystemZISD::IPM
@ IPM
Definition: SystemZISelLowering.h:152
llvm::SystemZISD::TBEGIN
@ TBEGIN
Definition: SystemZISelLowering.h:160
llvm::SystemZTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SystemZISelLowering.cpp:1127
llvm::SystemZVectorConstantInfo::VecVT
MVT VecVT
Definition: SystemZISelLowering.h:744
llvm::SystemZTargetLowering::LowerOperationWrapper
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SystemZISelLowering.cpp:5542
llvm::SystemZISD::POPCNT
@ POPCNT
Definition: SystemZISelLowering.h:88
llvm::SystemZISD::STRV
@ STRV
Definition: SystemZISelLowering.h:362
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
llvm::SystemZISD::STRICT_VFCMPES
@ STRICT_VFCMPES
Definition: SystemZISelLowering.h:304
llvm::SystemZISD::BYTE_MASK
@ BYTE_MASK
Definition: SystemZISelLowering.h:168
llvm::SystemZISD::NodeType
NodeType
Definition: SystemZISelLowering.h:25
llvm::SystemZISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: SystemZISelLowering.h:347
llvm::LLT
Definition: LowLevelTypeImpl.h:40