36 #define DEBUG_TYPE "ve-asmparser"
48 #define GET_ASSEMBLER_HEADER
49 #include "VEGenAsmMatcher.inc"
54 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
57 bool MatchingInlineAsm)
override;
58 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
59 int parseRegisterName(
unsigned (*matchFn)(
StringRef));
61 SMLoc &EndLoc)
override;
64 bool ParseDirective(
AsmToken DirectiveID)
override;
67 unsigned Kind)
override;
82 bool parseExpression(
const MCExpr *&EVal);
88 bool parseLiteralValues(
unsigned Size,
SMLoc L);
95 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
102 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
103 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
104 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
105 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
106 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
107 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
108 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
109 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
110 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
114 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
115 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
116 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
117 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
118 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
119 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
120 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
121 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
122 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
127 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
128 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
129 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
132 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
135 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
136 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
137 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
138 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
139 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
140 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
141 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
142 VE::PMC12, VE::PMC13, VE::PMC14};
168 SMLoc StartLoc, EndLoc;
214 VEOperand(KindTy K) :
Kind(K) {}
216 bool isToken()
const override {
return Kind == k_Token; }
217 bool isReg()
const override {
return Kind == k_Register; }
218 bool isImm()
const override {
return Kind == k_Immediate; }
219 bool isMem()
const override {
220 return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||
223 bool isMEMrri()
const {
return Kind == k_MemoryRegRegImm; }
224 bool isMEMrii()
const {
return Kind == k_MemoryRegImmImm; }
225 bool isMEMzri()
const {
return Kind == k_MemoryZeroRegImm; }
226 bool isMEMzii()
const {
return Kind == k_MemoryZeroImmImm; }
227 bool isMEMri()
const {
return Kind == k_MemoryRegImm; }
228 bool isMEMzi()
const {
return Kind == k_MemoryZeroImm; }
229 bool isCCOp()
const {
return Kind == k_CCOp; }
230 bool isRDOp()
const {
return Kind == k_RDOp; }
236 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
237 int64_t
Value = ConstExpr->getValue();
247 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
248 int64_t
Value = ConstExpr->getValue();
258 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
259 int64_t
Value = ConstExpr->getValue();
260 return isUInt<1>(
Value);
269 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
270 int64_t
Value = ConstExpr->getValue();
271 return isUInt<2>(
Value);
280 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
281 int64_t
Value = ConstExpr->getValue();
282 return isUInt<3>(
Value);
291 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
292 int64_t
Value = ConstExpr->getValue();
293 return isUInt<4>(
Value);
302 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
303 int64_t
Value = ConstExpr->getValue();
304 return isUInt<6>(
Value);
313 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
314 int64_t
Value = ConstExpr->getValue();
315 return isUInt<7>(
Value);
324 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
325 int64_t
Value = ConstExpr->getValue();
326 return isInt<7>(
Value);
330 bool isMImm()
const {
331 if (
Kind != k_MImmOp)
335 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
336 int64_t
Value = ConstExpr->getValue();
337 return isUInt<6>(
Value);
347 unsigned getReg()
const override {
348 assert((
Kind == k_Register) &&
"Invalid access!");
352 const MCExpr *getImm()
const {
353 assert((
Kind == k_Immediate) &&
"Invalid access!");
357 unsigned getMemBase()
const {
359 Kind == k_MemoryRegImm) &&
364 unsigned getMemIndexReg()
const {
365 assert((
Kind == k_MemoryRegRegImm ||
Kind == k_MemoryZeroRegImm) &&
370 const MCExpr *getMemIndex()
const {
371 assert((
Kind == k_MemoryRegImmImm ||
Kind == k_MemoryZeroImmImm) &&
376 const MCExpr *getMemOffset()
const {
378 Kind == k_MemoryZeroImmImm ||
Kind == k_MemoryZeroRegImm ||
379 Kind == k_MemoryRegImm ||
Kind == k_MemoryZeroImm) &&
384 void setMemOffset(
const MCExpr *off) {
386 Kind == k_MemoryZeroImmImm ||
Kind == k_MemoryZeroRegImm ||
387 Kind == k_MemoryRegImm ||
Kind == k_MemoryZeroImm) &&
392 unsigned getCCVal()
const {
393 assert((
Kind == k_CCOp) &&
"Invalid access!");
397 unsigned getRDVal()
const {
398 assert((
Kind == k_RDOp) &&
"Invalid access!");
402 const MCExpr *getMImmVal()
const {
403 assert((
Kind == k_MImmOp) &&
"Invalid access!");
406 bool getM0Flag()
const {
407 assert((
Kind == k_MImmOp) &&
"Invalid access!");
412 SMLoc getStartLoc()
const override {
return StartLoc; }
414 SMLoc getEndLoc()
const override {
return EndLoc; }
419 OS <<
"Token: " << getToken() <<
"\n";
422 OS <<
"Reg: #" <<
getReg() <<
"\n";
425 OS <<
"Imm: " << getImm() <<
"\n";
427 case k_MemoryRegRegImm:
428 assert(getMemOffset() !=
nullptr);
429 OS <<
"Mem: #" << getMemBase() <<
"+#" << getMemIndexReg() <<
"+"
430 << *getMemOffset() <<
"\n";
432 case k_MemoryRegImmImm:
433 assert(getMemIndex() !=
nullptr && getMemOffset() !=
nullptr);
434 OS <<
"Mem: #" << getMemBase() <<
"+" << *getMemIndex() <<
"+"
435 << *getMemOffset() <<
"\n";
437 case k_MemoryZeroRegImm:
438 assert(getMemOffset() !=
nullptr);
439 OS <<
"Mem: 0+#" << getMemIndexReg() <<
"+" << *getMemOffset() <<
"\n";
441 case k_MemoryZeroImmImm:
442 assert(getMemIndex() !=
nullptr && getMemOffset() !=
nullptr);
443 OS <<
"Mem: 0+" << *getMemIndex() <<
"+" << *getMemOffset() <<
"\n";
446 assert(getMemOffset() !=
nullptr);
447 OS <<
"Mem: #" << getMemBase() <<
"+" << *getMemOffset() <<
"\n";
449 case k_MemoryZeroImm:
450 assert(getMemOffset() !=
nullptr);
451 OS <<
"Mem: 0+" << *getMemOffset() <<
"\n";
454 OS <<
"CCOp: " << getCCVal() <<
"\n";
457 OS <<
"RDOp: " << getRDVal() <<
"\n";
460 OS <<
"MImm: (" << getMImmVal() << (getM0Flag() ?
")0" :
")1") <<
"\n";
465 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
466 assert(
N == 1 &&
"Invalid number of operands!");
470 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
471 assert(
N == 1 &&
"Invalid number of operands!");
472 const MCExpr *Expr = getImm();
476 void addZeroOperands(
MCInst &Inst,
unsigned N)
const {
477 addImmOperands(Inst,
N);
480 void addUImm0to2Operands(
MCInst &Inst,
unsigned N)
const {
481 addImmOperands(Inst,
N);
484 void addUImm1Operands(
MCInst &Inst,
unsigned N)
const {
485 addImmOperands(Inst,
N);
488 void addUImm2Operands(
MCInst &Inst,
unsigned N)
const {
489 addImmOperands(Inst,
N);
492 void addUImm3Operands(
MCInst &Inst,
unsigned N)
const {
493 addImmOperands(Inst,
N);
496 void addUImm4Operands(
MCInst &Inst,
unsigned N)
const {
497 addImmOperands(Inst,
N);
500 void addUImm6Operands(
MCInst &Inst,
unsigned N)
const {
501 addImmOperands(Inst,
N);
504 void addUImm7Operands(
MCInst &Inst,
unsigned N)
const {
505 addImmOperands(Inst,
N);
508 void addSImm7Operands(
MCInst &Inst,
unsigned N)
const {
509 addImmOperands(Inst,
N);
516 else if (
const auto *CE = dyn_cast<MCConstantExpr>(Expr))
522 void addMEMrriOperands(
MCInst &Inst,
unsigned N)
const {
523 assert(
N == 3 &&
"Invalid number of operands!");
527 addExpr(Inst, getMemOffset());
530 void addMEMriiOperands(
MCInst &Inst,
unsigned N)
const {
531 assert(
N == 3 &&
"Invalid number of operands!");
534 addExpr(Inst, getMemIndex());
535 addExpr(Inst, getMemOffset());
538 void addMEMzriOperands(
MCInst &Inst,
unsigned N)
const {
539 assert(
N == 3 &&
"Invalid number of operands!");
543 addExpr(Inst, getMemOffset());
546 void addMEMziiOperands(
MCInst &Inst,
unsigned N)
const {
547 assert(
N == 3 &&
"Invalid number of operands!");
550 addExpr(Inst, getMemIndex());
551 addExpr(Inst, getMemOffset());
554 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
555 assert(
N == 2 &&
"Invalid number of operands!");
558 addExpr(Inst, getMemOffset());
561 void addMEMziOperands(
MCInst &Inst,
unsigned N)
const {
562 assert(
N == 2 &&
"Invalid number of operands!");
565 addExpr(Inst, getMemOffset());
568 void addCCOpOperands(
MCInst &Inst,
unsigned N)
const {
569 assert(
N == 1 &&
"Invalid number of operands!");
574 void addRDOpOperands(
MCInst &Inst,
unsigned N)
const {
575 assert(
N == 1 &&
"Invalid number of operands!");
580 void addMImmOperands(
MCInst &Inst,
unsigned N)
const {
581 assert(
N == 1 &&
"Invalid number of operands!");
582 const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());
583 assert(ConstExpr &&
"Null operands!");
584 int64_t
Value = ConstExpr->getValue();
590 static std::unique_ptr<VEOperand> CreateToken(
StringRef Str,
SMLoc S) {
591 auto Op = std::make_unique<VEOperand>(k_Token);
592 Op->Tok.Data = Str.data();
593 Op->Tok.Length = Str.size();
599 static std::unique_ptr<VEOperand> CreateReg(
unsigned RegNum,
SMLoc S,
601 auto Op = std::make_unique<VEOperand>(k_Register);
602 Op->Reg.RegNum = RegNum;
608 static std::unique_ptr<VEOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
610 auto Op = std::make_unique<VEOperand>(k_Immediate);
617 static std::unique_ptr<VEOperand> CreateCCOp(
unsigned CCVal,
SMLoc S,
619 auto Op = std::make_unique<VEOperand>(k_CCOp);
620 Op->CC.CCVal = CCVal;
626 static std::unique_ptr<VEOperand> CreateRDOp(
unsigned RDVal,
SMLoc S,
628 auto Op = std::make_unique<VEOperand>(k_RDOp);
629 Op->RD.RDVal = RDVal;
635 static std::unique_ptr<VEOperand> CreateMImm(
const MCExpr *Val,
bool Flag,
637 auto Op = std::make_unique<VEOperand>(k_MImmOp);
645 static bool MorphToI32Reg(VEOperand &
Op) {
646 unsigned Reg =
Op.getReg();
647 unsigned regIdx =
Reg - VE::SX0;
654 static bool MorphToF32Reg(VEOperand &
Op) {
655 unsigned Reg =
Op.getReg();
656 unsigned regIdx =
Reg - VE::SX0;
663 static bool MorphToF128Reg(VEOperand &
Op) {
664 unsigned Reg =
Op.getReg();
665 unsigned regIdx =
Reg - VE::SX0;
666 if (regIdx % 2 || regIdx > 63)
672 static bool MorphToVM512Reg(VEOperand &
Op) {
673 unsigned Reg =
Op.getReg();
674 unsigned regIdx =
Reg - VE::VM0;
675 if (regIdx % 2 || regIdx > 15)
681 static bool MorphToMISCReg(VEOperand &
Op) {
682 const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Op.getImm());
685 unsigned regIdx = ConstExpr->getValue();
686 if (regIdx > 31 ||
MISCRegs[regIdx] == VE::NoRegister)
688 Op.Kind = k_Register;
693 static std::unique_ptr<VEOperand>
694 MorphToMEMri(
unsigned Base, std::unique_ptr<VEOperand>
Op) {
696 Op->Kind = k_MemoryRegImm;
698 Op->Mem.IndexReg = 0;
699 Op->Mem.Index =
nullptr;
700 Op->Mem.Offset = Imm;
704 static std::unique_ptr<VEOperand>
705 MorphToMEMzi(std::unique_ptr<VEOperand>
Op) {
707 Op->Kind = k_MemoryZeroImm;
709 Op->Mem.IndexReg = 0;
710 Op->Mem.Index =
nullptr;
711 Op->Mem.Offset = Imm;
715 static std::unique_ptr<VEOperand>
716 MorphToMEMrri(
unsigned Base,
unsigned Index, std::unique_ptr<VEOperand>
Op) {
718 Op->Kind = k_MemoryRegRegImm;
721 Op->Mem.Index =
nullptr;
722 Op->Mem.Offset = Imm;
726 static std::unique_ptr<VEOperand>
728 std::unique_ptr<VEOperand>
Op) {
730 Op->Kind = k_MemoryRegImmImm;
732 Op->Mem.IndexReg = 0;
734 Op->Mem.Offset = Imm;
738 static std::unique_ptr<VEOperand>
739 MorphToMEMzri(
unsigned Index, std::unique_ptr<VEOperand>
Op) {
741 Op->Kind = k_MemoryZeroRegImm;
744 Op->Mem.Index =
nullptr;
745 Op->Mem.Offset = Imm;
749 static std::unique_ptr<VEOperand>
750 MorphToMEMzii(
const MCExpr *
Index, std::unique_ptr<VEOperand>
Op) {
752 Op->Kind = k_MemoryZeroImmImm;
754 Op->Mem.IndexReg = 0;
756 Op->Mem.Offset = Imm;
763 bool VEAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
766 bool MatchingInlineAsm) {
768 unsigned MatchResult =
770 switch (MatchResult) {
776 case Match_MissingFeature:
778 "instruction requires a CPU feature not currently enabled");
780 case Match_InvalidOperand: {
781 SMLoc ErrorLoc = IDLoc;
784 return Error(IDLoc,
"too few operands for instruction");
787 if (ErrorLoc ==
SMLoc())
791 return Error(ErrorLoc,
"invalid operand for instruction");
793 case Match_MnemonicFail:
794 return Error(IDLoc,
"invalid instruction mnemonic");
799 bool VEAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
802 return Error(StartLoc,
"invalid register name");
808 int VEAsmParser::parseRegisterName(
unsigned (*matchFn)(
StringRef)) {
811 int RegNum = matchFn(
Name);
815 if (RegNum == VE::NoRegister) {
816 RegNum = matchFn(
Name.lower());
831 VEAsmParser::tryParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
841 if (RegNo == VE::NoRegister)
844 if (RegNo != VE::NoRegister) {
849 getLexer().UnLex(Tok);
854 bool IntegerCC,
bool OmitCC,
SMLoc NameLoc,
868 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
874 if (!SuffixStr.
empty())
875 Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));
877 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
892 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
901 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
913 if (
Name[0] ==
'b') {
916 size_t Next =
Name.find(
'.');
918 if (
Name.size() > 1 &&
Name[1] ==
'r')
922 if (Next + 1 <
Name.size() &&
923 (
Name[Next + 1] ==
'd' ||
Name[Next + 1] ==
's'))
926 }
else if (
Name.startswith(
"cmov.l.") ||
Name.startswith(
"cmov.w.") ||
927 Name.startswith(
"cmov.d.") ||
Name.startswith(
"cmov.s.")) {
928 bool ICC =
Name[5] ==
'l' ||
Name[5] ==
'w';
930 }
else if (
Name.startswith(
"cvt.w.d.sx") ||
Name.startswith(
"cvt.w.d.zx") ||
931 Name.startswith(
"cvt.w.s.sx") ||
Name.startswith(
"cvt.w.s.zx")) {
933 }
else if (
Name.startswith(
"cvt.l.d")) {
935 }
else if (
Name.startswith(
"vcvt.w.d.sx") ||
Name.startswith(
"vcvt.w.d.zx") ||
936 Name.startswith(
"vcvt.w.s.sx") ||
Name.startswith(
"vcvt.w.s.zx")) {
938 }
else if (
Name.startswith(
"vcvt.l.d")) {
940 }
else if (
Name.startswith(
"pvcvt.w.s.lo") ||
941 Name.startswith(
"pvcvt.w.s.up")) {
943 }
else if (
Name.startswith(
"pvcvt.w.s")) {
945 }
else if (
Name.startswith(
"vfmk.l.") ||
Name.startswith(
"vfmk.w.") ||
946 Name.startswith(
"vfmk.d.") ||
Name.startswith(
"vfmk.s.")) {
947 bool ICC =
Name[5] ==
'l' ||
Name[5] ==
'w' ?
true :
false;
949 }
else if (
Name.startswith(
"pvfmk.w.lo.") ||
Name.startswith(
"pvfmk.w.up.") ||
950 Name.startswith(
"pvfmk.s.lo.") ||
Name.startswith(
"pvfmk.s.up.")) {
951 bool ICC =
Name[6] ==
'l' ||
Name[6] ==
'w' ?
true :
false;
954 Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));
978 SMLoc Loc = getLexer().getLoc();
979 return Error(Loc,
"unexpected token");
986 SMLoc Loc = getLexer().getLoc();
987 return Error(Loc,
"unexpected token");
992 SMLoc Loc = getLexer().getLoc();
993 return Error(Loc,
"unexpected token");
999 bool VEAsmParser::ParseDirective(
AsmToken DirectiveID) {
1007 if (IDVal ==
".word")
1008 return parseLiteralValues(4, DirectiveID.
getLoc());
1011 if (IDVal ==
".long")
1012 return parseLiteralValues(8, DirectiveID.
getLoc());
1015 if (IDVal ==
".llong")
1016 return parseLiteralValues(8, DirectiveID.
getLoc());
1026 bool VEAsmParser::parseLiteralValues(
unsigned Size,
SMLoc L) {
1027 auto parseOne = [&]() ->
bool {
1029 if (getParser().parseExpression(
Value))
1031 getParser().getStreamer().emitValue(
Value,
Size, L);
1034 return (parseMany(parseOne));
1044 VEAsmParser::extractModifierFromExpr(
const MCExpr *
E,
1049 switch (
E->getKind()) {
1122 const MCExpr *
LHS = extractModifierFromExpr(BE->
getLHS(), LHSVariant);
1123 const MCExpr *
RHS = extractModifierFromExpr(BE->
getRHS(), RHSVariant);
1137 else if (LHSVariant == RHSVariant)
1149 const MCExpr *VEAsmParser::fixupVariantKind(
const MCExpr *
E) {
1152 switch (
E->getKind()) {
1181 bool VEAsmParser::parseExpression(
const MCExpr *&EVal) {
1183 if (getParser().parseExpression(EVal))
1187 EVal = fixupVariantKind(EVal);
1189 const MCExpr *
E = extractModifierFromExpr(EVal, Variant);
1210 std::unique_ptr<VEOperand>
Offset;
1211 switch (getLexer().getKind()) {
1220 if (!parseExpression(EVal))
1221 Offset = VEOperand::CreateImm(EVal,
S,
E);
1234 switch (getLexer().getKind()) {
1239 Operands.push_back(VEOperand::MorphToMEMzii(
1248 const MCExpr *IndexValue =
nullptr;
1249 unsigned IndexReg = 0;
1251 switch (getLexer().getKind()) {
1253 if (ParseRegister(IndexReg,
S,
E))
1260 if (getParser().parseExpression(IndexValue,
E))
1270 switch (getLexer().getKind()) {
1286 unsigned BaseReg = 0;
1287 if (ParseRegister(BaseReg,
S,
E))
1316 unsigned BaseReg = VE::NoRegister;
1317 std::unique_ptr<VEOperand>
Offset;
1318 switch (getLexer().getKind()) {
1327 if (!parseExpression(EVal))
1328 Offset = VEOperand::CreateImm(EVal,
S,
E);
1335 if (ParseRegister(BaseReg,
S,
E))
1348 switch (getLexer().getKind()) {
1354 Operands.push_back(BaseReg != VE::NoRegister
1360 if (BaseReg != VE::NoRegister)
1366 switch (getLexer().getKind()) {
1368 if (ParseRegister(BaseReg,
S,
E))
1374 if (ParseRegister(BaseReg,
S,
E))
1386 Operands.push_back(BaseReg != VE::NoRegister
1407 getLexer().UnLex(Tok1);
1413 getLexer().UnLex(Tok2);
1414 getLexer().UnLex(Tok1);
1421 if (Suffix !=
"1" && Suffix !=
"0") {
1422 getLexer().UnLex(Tok3);
1423 getLexer().UnLex(Tok2);
1424 getLexer().UnLex(Tok1);
1430 VEOperand::CreateMImm(EVal, Suffix ==
"0", Tok1.
getLoc(), EndLoc));
1445 switch (getLexer().getKind()) {
1454 getLexer().UnLex(Tok1);
1471 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1));
1472 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2));
1479 std::unique_ptr<VEOperand>
Op;
1480 ResTy = parseVEAsmOperand(
Op);
1491 std::unique_ptr<VEOperand> Op1 = VEOperand::CreateToken(
1495 std::unique_ptr<VEOperand> Op2;
1496 ResTy = parseVEAsmOperand(Op2);
1516 VEAsmParser::parseVEAsmOperand(std::unique_ptr<VEOperand> &
Op) {
1523 switch (getLexer().getKind()) {
1530 Op = VEOperand::CreateReg(RegNo,
S,
E);
1537 if (!parseExpression(EVal))
1538 Op = VEOperand::CreateImm(EVal,
S,
E);
1549 #define GET_REGISTER_MATCHER
1550 #define GET_MATCHER_IMPLEMENTATION
1551 #include "VEGenAsmMatcher.inc"
1555 VEOperand &
Op = (VEOperand &)GOp;
1564 if (
Op.isReg() && VEOperand::MorphToF32Reg(
Op))
1568 if (
Op.isReg() && VEOperand::MorphToI32Reg(
Op))
1572 if (
Op.isReg() && VEOperand::MorphToF128Reg(
Op))
1576 if (
Op.isReg() && VEOperand::MorphToVM512Reg(
Op))
1580 if (
Op.isImm() && VEOperand::MorphToMISCReg(
Op))
1584 return Match_InvalidOperand;