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VEISelLowering.cpp
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1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that VE uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "VEISelLowering.h"
15 #include "MCTargetDesc/VEMCExpr.h"
16 #include "VECustomDAG.h"
17 #include "VEInstrBuilder.h"
18 #include "VEMachineFunctionInfo.h"
19 #include "VERegisterInfo.h"
20 #include "VETargetMachine.h"
21 #include "llvm/ADT/StringSwitch.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/Module.h"
36 #include "llvm/Support/KnownBits.h"
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "ve-lower"
40 
41 //===----------------------------------------------------------------------===//
42 // Calling Convention Implementation
43 //===----------------------------------------------------------------------===//
44 
45 #include "VEGenCallingConv.inc"
46 
48  switch (CallConv) {
49  default:
50  return RetCC_VE_C;
51  case CallingConv::Fast:
52  return RetCC_VE_Fast;
53  }
54 }
55 
56 CCAssignFn *getParamCC(CallingConv::ID CallConv, bool IsVarArg) {
57  if (IsVarArg)
58  return CC_VE2;
59  switch (CallConv) {
60  default:
61  return CC_VE_C;
62  case CallingConv::Fast:
63  return CC_VE_Fast;
64  }
65 }
66 
68  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
70  CCAssignFn *RetCC = getReturnCC(CallConv);
72  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
73  return CCInfo.CheckReturn(Outs, RetCC);
74 }
75 
78 
79 static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
80 
82 
83 void VETargetLowering::initRegisterClasses() {
84  // Set up the register classes.
85  addRegisterClass(MVT::i32, &VE::I32RegClass);
86  addRegisterClass(MVT::i64, &VE::I64RegClass);
87  addRegisterClass(MVT::f32, &VE::F32RegClass);
88  addRegisterClass(MVT::f64, &VE::I64RegClass);
89  addRegisterClass(MVT::f128, &VE::F128RegClass);
90 
91  if (Subtarget->enableVPU()) {
92  for (MVT VecVT : AllVectorVTs)
93  addRegisterClass(VecVT, &VE::V64RegClass);
94  addRegisterClass(MVT::v256i1, &VE::VMRegClass);
95  addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
96  }
97 }
98 
99 void VETargetLowering::initSPUActions() {
100  const auto &TM = getTargetMachine();
101  /// Load & Store {
102 
103  // VE doesn't have i1 sign extending load.
104  for (MVT VT : MVT::integer_valuetypes()) {
109  }
110 
111  // VE doesn't have floating point extload/truncstore, so expand them.
112  for (MVT FPVT : MVT::fp_valuetypes()) {
113  for (MVT OtherFPVT : MVT::fp_valuetypes()) {
114  setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
115  setTruncStoreAction(FPVT, OtherFPVT, Expand);
116  }
117  }
118 
119  // VE doesn't have fp128 load/store, so expand them in custom lower.
122 
123  /// } Load & Store
124 
125  // Custom legalize address nodes into LO/HI parts.
126  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
132 
133  /// VAARG handling {
135  // VAARG needs to be lowered to access with 8 bytes alignment.
137  // Use the default implementation.
140  /// } VAARG handling
141 
142  /// Stack {
145 
146  // Use the default implementation.
149  /// } Stack
150 
151  /// Branch {
152 
153  // VE doesn't have BRCOND
155 
156  // BR_JT is not implemented yet.
158 
159  /// } Branch
160 
161  /// Int Ops {
162  for (MVT IntVT : {MVT::i32, MVT::i64}) {
163  // VE has no REM or DIVREM operations.
168 
169  // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
173 
174  // VE has no MULHU/S or U/SMUL_LOHI operations.
175  // TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
180 
181  // VE has no CTTZ, ROTL, ROTR operations.
185 
186  // VE has 64 bits instruction which works as i64 BSWAP operation. This
187  // instruction works fine as i32 BSWAP operation with an additional
188  // parameter. Use isel patterns to lower BSWAP.
190 
191  // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
192  // operations. Use isel patterns for i64, promote for i32.
193  LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
194  setOperationAction(ISD::BITREVERSE, IntVT, Act);
195  setOperationAction(ISD::CTLZ, IntVT, Act);
197  setOperationAction(ISD::CTPOP, IntVT, Act);
198 
199  // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
200  // Use isel patterns for i64, promote for i32.
201  setOperationAction(ISD::AND, IntVT, Act);
202  setOperationAction(ISD::OR, IntVT, Act);
203  setOperationAction(ISD::XOR, IntVT, Act);
204  }
205  /// } Int Ops
206 
207  /// Conversion {
208  // VE doesn't have instructions for fp<->uint, so expand them by llvm
213 
214  // fp16 not supported
215  for (MVT FPVT : MVT::fp_valuetypes()) {
218  }
219  /// } Conversion
220 
221  /// Floating-point Ops {
222  /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
223  /// and fcmp.
224 
225  // VE doesn't have following floating point operations.
226  for (MVT VT : MVT::fp_valuetypes()) {
229  }
230 
231  // VE doesn't have fdiv of f128.
233 
234  for (MVT FPVT : {MVT::f32, MVT::f64}) {
235  // f32 and f64 uses ConstantFP. f128 uses ConstantPool.
237  }
238  /// } Floating-point Ops
239 
240  /// Floating-point math functions {
241 
242  // VE doesn't have following floating point math functions.
243  for (MVT VT : MVT::fp_valuetypes()) {
249  }
250 
251  /// } Floating-point math functions
252 
253  /// Atomic instructions {
254 
258 
259  // Use custom inserter for ATOMIC_FENCE.
261 
262  // Other atomic instructions.
263  for (MVT VT : MVT::integer_valuetypes()) {
264  // Support i8/i16 atomic swap.
266 
267  // FIXME: Support "atmam" instructions.
272 
273  // VE doesn't have follwing instructions.
282  }
283 
284  /// } Atomic instructions
285 
286  /// SJLJ instructions {
290  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
291  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
292  /// } SJLJ instructions
293 
294  // Intrinsic instructions
296 }
297 
298 void VETargetLowering::initVPUActions() {
299  for (MVT LegalMaskVT : AllMaskVTs)
301 
302  for (unsigned Opc : {ISD::AND, ISD::OR, ISD::XOR})
304 
305  for (MVT LegalVecVT : AllVectorVTs) {
309  // Translate all vector instructions with legal element types to VVP_*
310  // nodes.
311  // TODO We will custom-widen into VVP_* nodes in the future. While we are
312  // buildling the infrastructure for this, we only do this for legal vector
313  // VTs.
314 #define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
315  setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
316 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
317  setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
318  setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, LegalVecVT, Custom);
319  setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, LegalVecVT, Custom);
320 #include "VVPNodes.def"
321  }
322 
323  for (MVT LegalPackedVT : AllPackedVTs) {
326  }
327 
328  // vNt32, vNt64 ops (legal element types)
329  for (MVT VT : MVT::vector_valuetypes()) {
330  MVT ElemVT = VT.getVectorElementType();
331  unsigned ElemBits = ElemVT.getScalarSizeInBits();
332  if (ElemBits != 32 && ElemBits != 64)
333  continue;
334 
335  for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE})
336  setOperationAction(MemOpc, VT, Custom);
337 
338  const ISD::NodeType IntReductionOCs[] = {
342 
343  for (unsigned IntRedOpc : IntReductionOCs)
344  setOperationAction(IntRedOpc, VT, Custom);
345  }
346 }
347 
348 SDValue
350  bool IsVarArg,
352  const SmallVectorImpl<SDValue> &OutVals,
353  const SDLoc &DL, SelectionDAG &DAG) const {
354  // CCValAssign - represent the assignment of the return value to locations.
356 
357  // CCState - Info about the registers and stack slot.
358  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
359  *DAG.getContext());
360 
361  // Analyze return values.
362  CCInfo.AnalyzeReturn(Outs, getReturnCC(CallConv));
363 
364  SDValue Flag;
365  SmallVector<SDValue, 4> RetOps(1, Chain);
366 
367  // Copy the result values into the output registers.
368  for (unsigned i = 0; i != RVLocs.size(); ++i) {
369  CCValAssign &VA = RVLocs[i];
370  assert(VA.isRegLoc() && "Can only return in registers!");
371  assert(!VA.needsCustom() && "Unexpected custom lowering");
372  SDValue OutVal = OutVals[i];
373 
374  // Integer return values must be sign or zero extended by the callee.
375  switch (VA.getLocInfo()) {
376  case CCValAssign::Full:
377  break;
378  case CCValAssign::SExt:
379  OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
380  break;
381  case CCValAssign::ZExt:
382  OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
383  break;
384  case CCValAssign::AExt:
385  OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
386  break;
387  case CCValAssign::BCvt: {
388  // Convert a float return value to i64 with padding.
389  // 63 31 0
390  // +------+------+
391  // | float| 0 |
392  // +------+------+
393  assert(VA.getLocVT() == MVT::i64);
394  assert(VA.getValVT() == MVT::f32);
396  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
397  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
398  OutVal = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
399  MVT::i64, Undef, OutVal, Sub_f32),
400  0);
401  break;
402  }
403  default:
404  llvm_unreachable("Unknown loc info!");
405  }
406 
407  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
408 
409  // Guarantee that all emitted copies are stuck together with flags.
410  Flag = Chain.getValue(1);
411  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
412  }
413 
414  RetOps[0] = Chain; // Update chain.
415 
416  // Add the flag if we have it.
417  if (Flag.getNode())
418  RetOps.push_back(Flag);
419 
420  return DAG.getNode(VEISD::RET_FLAG, DL, MVT::Other, RetOps);
421 }
422 
424  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
426  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
428 
429  // Get the base offset of the incoming arguments stack space.
430  unsigned ArgsBaseOffset = Subtarget->getRsaSize();
431  // Get the size of the preserved arguments area
432  unsigned ArgsPreserved = 64;
433 
434  // Analyze arguments according to CC_VE.
436  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
437  *DAG.getContext());
438  // Allocate the preserved area first.
439  CCInfo.AllocateStack(ArgsPreserved, Align(8));
440  // We already allocated the preserved area, so the stack offset computed
441  // by CC_VE would be correct now.
442  CCInfo.AnalyzeFormalArguments(Ins, getParamCC(CallConv, false));
443 
444  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
445  CCValAssign &VA = ArgLocs[i];
446  assert(!VA.needsCustom() && "Unexpected custom lowering");
447  if (VA.isRegLoc()) {
448  // This argument is passed in a register.
449  // All integer register arguments are promoted by the caller to i64.
450 
451  // Create a virtual register for the promoted live-in value.
452  Register VReg =
453  MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));
454  SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
455 
456  // The caller promoted the argument, so insert an Assert?ext SDNode so we
457  // won't promote the value again in this function.
458  switch (VA.getLocInfo()) {
459  case CCValAssign::SExt:
460  Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
461  DAG.getValueType(VA.getValVT()));
462  break;
463  case CCValAssign::ZExt:
464  Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
465  DAG.getValueType(VA.getValVT()));
466  break;
467  case CCValAssign::BCvt: {
468  // Extract a float argument from i64 with padding.
469  // 63 31 0
470  // +------+------+
471  // | float| 0 |
472  // +------+------+
473  assert(VA.getLocVT() == MVT::i64);
474  assert(VA.getValVT() == MVT::f32);
475  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
476  Arg = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
477  MVT::f32, Arg, Sub_f32),
478  0);
479  break;
480  }
481  default:
482  break;
483  }
484 
485  // Truncate the register down to the argument type.
486  if (VA.isExtInLoc())
487  Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
488 
489  InVals.push_back(Arg);
490  continue;
491  }
492 
493  // The registers are exhausted. This argument was passed on the stack.
494  assert(VA.isMemLoc());
495  // The CC_VE_Full/Half functions compute stack offsets relative to the
496  // beginning of the arguments area at %fp + the size of reserved area.
497  unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
498  unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
499 
500  // Adjust offset for a float argument by adding 4 since the argument is
501  // stored in 8 bytes buffer with offset like below. LLVM generates
502  // 4 bytes load instruction, so need to adjust offset here. This
503  // adjustment is required in only LowerFormalArguments. In LowerCall,
504  // a float argument is converted to i64 first, and stored as 8 bytes
505  // data, which is required by ABI, so no need for adjustment.
506  // 0 4
507  // +------+------+
508  // | empty| float|
509  // +------+------+
510  if (VA.getValVT() == MVT::f32)
511  Offset += 4;
512 
513  int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
514  InVals.push_back(
515  DAG.getLoad(VA.getValVT(), DL, Chain,
518  }
519 
520  if (!IsVarArg)
521  return Chain;
522 
523  // This function takes variable arguments, some of which may have been passed
524  // in registers %s0-%s8.
525  //
526  // The va_start intrinsic needs to know the offset to the first variable
527  // argument.
528  // TODO: need to calculate offset correctly once we support f128.
529  unsigned ArgOffset = ArgLocs.size() * 8;
531  // Skip the reserved area at the top of stack.
532  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset);
533 
534  return Chain;
535 }
536 
537 // FIXME? Maybe this could be a TableGen attribute on some registers and
538 // this table could be generated automatically from RegInfo.
540  const MachineFunction &MF) const {
542  .Case("sp", VE::SX11) // Stack pointer
543  .Case("fp", VE::SX9) // Frame pointer
544  .Case("sl", VE::SX8) // Stack limit
545  .Case("lr", VE::SX10) // Link register
546  .Case("tp", VE::SX14) // Thread pointer
547  .Case("outer", VE::SX12) // Outer regiser
548  .Case("info", VE::SX17) // Info area register
549  .Case("got", VE::SX15) // Global offset table register
550  .Case("plt", VE::SX16) // Procedure linkage table register
551  .Default(0);
552 
553  if (Reg)
554  return Reg;
555 
556  report_fatal_error("Invalid register name global variable");
557 }
558 
559 //===----------------------------------------------------------------------===//
560 // TargetLowering Implementation
561 //===----------------------------------------------------------------------===//
562 
564  SmallVectorImpl<SDValue> &InVals) const {
565  SelectionDAG &DAG = CLI.DAG;
566  SDLoc DL = CLI.DL;
567  SDValue Chain = CLI.Chain;
568  auto PtrVT = getPointerTy(DAG.getDataLayout());
569 
570  // VE target does not yet support tail call optimization.
571  CLI.IsTailCall = false;
572 
573  // Get the base offset of the outgoing arguments stack space.
574  unsigned ArgsBaseOffset = Subtarget->getRsaSize();
575  // Get the size of the preserved arguments area
576  unsigned ArgsPreserved = 8 * 8u;
577 
578  // Analyze operands of the call, assigning locations to each operand.
580  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
581  *DAG.getContext());
582  // Allocate the preserved area first.
583  CCInfo.AllocateStack(ArgsPreserved, Align(8));
584  // We already allocated the preserved area, so the stack offset computed
585  // by CC_VE would be correct now.
586  CCInfo.AnalyzeCallOperands(CLI.Outs, getParamCC(CLI.CallConv, false));
587 
588  // VE requires to use both register and stack for varargs or no-prototyped
589  // functions.
590  bool UseBoth = CLI.IsVarArg;
591 
592  // Analyze operands again if it is required to store BOTH.
594  CCState CCInfo2(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
595  ArgLocs2, *DAG.getContext());
596  if (UseBoth)
597  CCInfo2.AnalyzeCallOperands(CLI.Outs, getParamCC(CLI.CallConv, true));
598 
599  // Get the size of the outgoing arguments stack space requirement.
600  unsigned ArgsSize = CCInfo.getNextStackOffset();
601 
602  // Keep stack frames 16-byte aligned.
603  ArgsSize = alignTo(ArgsSize, 16);
604 
605  // Adjust the stack pointer to make room for the arguments.
606  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
607  // with more than 6 arguments.
608  Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
609 
610  // Collect the set of registers to pass to the function and their values.
611  // This will be emitted as a sequence of CopyToReg nodes glued to the call
612  // instruction.
614 
615  // Collect chains from all the memory opeations that copy arguments to the
616  // stack. They must follow the stack pointer adjustment above and precede the
617  // call instruction itself.
618  SmallVector<SDValue, 8> MemOpChains;
619 
620  // VE needs to get address of callee function in a register
621  // So, prepare to copy it to SX12 here.
622 
623  // If the callee is a GlobalAddress node (quite common, every direct call is)
624  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
625  // Likewise ExternalSymbol -> TargetExternalSymbol.
626  SDValue Callee = CLI.Callee;
627 
628  bool IsPICCall = isPositionIndependent();
629 
630  // PC-relative references to external symbols should go through $stub.
631  // If so, we need to prepare GlobalBaseReg first.
632  const TargetMachine &TM = DAG.getTarget();
634  const GlobalValue *GV = nullptr;
635  auto *CalleeG = dyn_cast<GlobalAddressSDNode>(Callee);
636  if (CalleeG)
637  GV = CalleeG->getGlobal();
638  bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
639  bool UsePlt = !Local;
641 
642  // Turn GlobalAddress/ExternalSymbol node into a value node
643  // containing the address of them here.
644  if (CalleeG) {
645  if (IsPICCall) {
646  if (UsePlt)
647  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
648  Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
649  Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
650  } else {
651  Callee =
653  }
654  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
655  if (IsPICCall) {
656  if (UsePlt)
657  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
658  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
659  Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
660  } else {
661  Callee =
663  }
664  }
665 
666  RegsToPass.push_back(std::make_pair(VE::SX12, Callee));
667 
668  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
669  CCValAssign &VA = ArgLocs[i];
670  SDValue Arg = CLI.OutVals[i];
671 
672  // Promote the value if needed.
673  switch (VA.getLocInfo()) {
674  default:
675  llvm_unreachable("Unknown location info!");
676  case CCValAssign::Full:
677  break;
678  case CCValAssign::SExt:
679  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
680  break;
681  case CCValAssign::ZExt:
682  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
683  break;
684  case CCValAssign::AExt:
685  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
686  break;
687  case CCValAssign::BCvt: {
688  // Convert a float argument to i64 with padding.
689  // 63 31 0
690  // +------+------+
691  // | float| 0 |
692  // +------+------+
693  assert(VA.getLocVT() == MVT::i64);
694  assert(VA.getValVT() == MVT::f32);
696  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
697  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
698  Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
699  MVT::i64, Undef, Arg, Sub_f32),
700  0);
701  break;
702  }
703  }
704 
705  if (VA.isRegLoc()) {
706  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
707  if (!UseBoth)
708  continue;
709  VA = ArgLocs2[i];
710  }
711 
712  assert(VA.isMemLoc());
713 
714  // Create a store off the stack pointer for this argument.
715  SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT);
716  // The argument area starts at %fp/%sp + the size of reserved area.
717  SDValue PtrOff =
718  DAG.getIntPtrConstant(VA.getLocMemOffset() + ArgsBaseOffset, DL);
719  PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
720  MemOpChains.push_back(
721  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
722  }
723 
724  // Emit all stores, make sure they occur before the call.
725  if (!MemOpChains.empty())
726  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
727 
728  // Build a sequence of CopyToReg nodes glued together with token chain and
729  // glue operands which copy the outgoing args into registers. The InGlue is
730  // necessary since all emitted instructions must be stuck together in order
731  // to pass the live physical registers.
732  SDValue InGlue;
733  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
734  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
735  RegsToPass[i].second, InGlue);
736  InGlue = Chain.getValue(1);
737  }
738 
739  // Build the operands for the call instruction itself.
741  Ops.push_back(Chain);
742  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
743  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
744  RegsToPass[i].second.getValueType()));
745 
746  // Add a register mask operand representing the call-preserved registers.
747  const VERegisterInfo *TRI = Subtarget->getRegisterInfo();
748  const uint32_t *Mask =
750  assert(Mask && "Missing call preserved mask for calling convention");
751  Ops.push_back(DAG.getRegisterMask(Mask));
752 
753  // Make sure the CopyToReg nodes are glued to the call instruction which
754  // consumes the registers.
755  if (InGlue.getNode())
756  Ops.push_back(InGlue);
757 
758  // Now the call itself.
759  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
760  Chain = DAG.getNode(VEISD::CALL, DL, NodeTys, Ops);
761  InGlue = Chain.getValue(1);
762 
763  // Revert the stack pointer immediately after the call.
764  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
765  DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
766  InGlue = Chain.getValue(1);
767 
768  // Now extract the return values. This is more or less the same as
769  // LowerFormalArguments.
770 
771  // Assign locations to each value returned by this call.
773  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
774  *DAG.getContext());
775 
776  // Set inreg flag manually for codegen generated library calls that
777  // return float.
778  if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
779  CLI.Ins[0].Flags.setInReg();
780 
781  RVInfo.AnalyzeCallResult(CLI.Ins, getReturnCC(CLI.CallConv));
782 
783  // Copy all of the result registers out of their specified physreg.
784  for (unsigned i = 0; i != RVLocs.size(); ++i) {
785  CCValAssign &VA = RVLocs[i];
786  assert(!VA.needsCustom() && "Unexpected custom lowering");
787  Register Reg = VA.getLocReg();
788 
789  // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
790  // reside in the same register in the high and low bits. Reuse the
791  // CopyFromReg previous node to avoid duplicate copies.
792  SDValue RV;
793  if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
794  if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
795  RV = Chain.getValue(0);
796 
797  // But usually we'll create a new CopyFromReg for a different register.
798  if (!RV.getNode()) {
799  RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
800  Chain = RV.getValue(1);
801  InGlue = Chain.getValue(2);
802  }
803 
804  // The callee promoted the return value, so insert an Assert?ext SDNode so
805  // we won't promote the value again in this function.
806  switch (VA.getLocInfo()) {
807  case CCValAssign::SExt:
808  RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
809  DAG.getValueType(VA.getValVT()));
810  break;
811  case CCValAssign::ZExt:
812  RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
813  DAG.getValueType(VA.getValVT()));
814  break;
815  case CCValAssign::BCvt: {
816  // Extract a float return value from i64 with padding.
817  // 63 31 0
818  // +------+------+
819  // | float| 0 |
820  // +------+------+
821  assert(VA.getLocVT() == MVT::i64);
822  assert(VA.getValVT() == MVT::f32);
823  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
824  RV = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
825  MVT::f32, RV, Sub_f32),
826  0);
827  break;
828  }
829  default:
830  break;
831  }
832 
833  // Truncate the register down to the return value type.
834  if (VA.isExtInLoc())
835  RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
836 
837  InVals.push_back(RV);
838  }
839 
840  return Chain;
841 }
842 
844  const GlobalAddressSDNode *GA) const {
845  // VE uses 64 bit addressing, so we need multiple instructions to generate
846  // an address. Folding address with offset increases the number of
847  // instructions, so that we disable it here. Offsets will be folded in
848  // the DAG combine later if it worth to do so.
849  return false;
850 }
851 
852 /// isFPImmLegal - Returns true if the target can instruction select the
853 /// specified FP immediate natively. If false, the legalizer will
854 /// materialize the FP immediate as a load from a constant pool.
856  bool ForCodeSize) const {
857  return VT == MVT::f32 || VT == MVT::f64;
858 }
859 
860 /// Determine if the target supports unaligned memory accesses.
861 ///
862 /// This function returns true if the target allows unaligned memory accesses
863 /// of the specified type in the given address space. If true, it also returns
864 /// whether the unaligned memory access is "fast" in the last argument by
865 /// reference. This is used, for example, in situations where an array
866 /// copy/move/set is converted to a sequence of store operations. Its use
867 /// helps to ensure that such replacements don't generate code that causes an
868 /// alignment error (trap) on the target machine.
870  unsigned AddrSpace,
871  Align A,
873  bool *Fast) const {
874  if (Fast) {
875  // It's fast anytime on VE
876  *Fast = true;
877  }
878  return true;
879 }
880 
882  const VESubtarget &STI)
883  : TargetLowering(TM), Subtarget(&STI) {
884  // Instructions which use registers as conditionals examine all the
885  // bits (as does the pseudo SELECT_CC expansion). I don't think it
886  // matters much whether it's ZeroOrOneBooleanContent, or
887  // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
888  // former.
891 
892  initRegisterClasses();
893  initSPUActions();
894  initVPUActions();
895 
897 
898  // We have target-specific dag combine patterns for the following nodes:
900 
901  // Set function alignment to 16 bytes
903 
904  // VE stores all argument by 8 bytes alignment
906 
908 }
909 
910 const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
911 #define TARGET_NODE_CASE(NAME) \
912  case VEISD::NAME: \
913  return "VEISD::" #NAME;
914  switch ((VEISD::NodeType)Opcode) {
915  case VEISD::FIRST_NUMBER:
916  break;
925  TARGET_NODE_CASE(Hi)
926  TARGET_NODE_CASE(Lo)
936 
938 
939  // Register the VVP_* SDNodes.
940 #define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
941 #include "VVPNodes.def"
942  }
943 #undef TARGET_NODE_CASE
944  return nullptr;
945 }
946 
948  EVT VT) const {
949  return MVT::i32;
950 }
951 
952 // Convert to a target node and set target flags.
954  SelectionDAG &DAG) const {
955  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
956  return DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA),
957  GA->getValueType(0), GA->getOffset(), TF);
958 
959  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
960  return DAG.getTargetBlockAddress(BA->getBlockAddress(), Op.getValueType(),
961  0, TF);
962 
963  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
964  return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0),
965  CP->getAlign(), CP->getOffset(), TF);
966 
967  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
968  return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0),
969  TF);
970 
971  if (const JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op))
972  return DAG.getTargetJumpTable(JT->getIndex(), JT->getValueType(0), TF);
973 
974  llvm_unreachable("Unhandled address SDNode");
975 }
976 
977 // Split Op into high and low parts according to HiTF and LoTF.
978 // Return an ADD node combining the parts.
979 SDValue VETargetLowering::makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
980  SelectionDAG &DAG) const {
981  SDLoc DL(Op);
982  EVT VT = Op.getValueType();
983  SDValue Hi = DAG.getNode(VEISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
984  SDValue Lo = DAG.getNode(VEISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
985  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
986 }
987 
988 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
989 // or ExternalSymbol SDNode.
991  SDLoc DL(Op);
992  EVT PtrVT = Op.getValueType();
993 
994  // Handle PIC mode first. VE needs a got load for every variable!
995  if (isPositionIndependent()) {
996  auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
997 
998  if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
999  (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
1000  // Create following instructions for local linkage PIC code.
1001  // lea %reg, label@gotoff_lo
1002  // and %reg, %reg, (32)0
1003  // lea.sl %reg, label@gotoff_hi(%reg, %got)
1006  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT);
1007  return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo);
1008  }
1009  // Create following instructions for not local linkage PIC code.
1010  // lea %reg, label@got_lo
1011  // and %reg, %reg, (32)0
1012  // lea.sl %reg, label@got_hi(%reg)
1013  // ld %reg, (%reg, %got)
1016  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT);
1017  SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo);
1018  return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), AbsAddr,
1020  }
1021 
1022  // This is one of the absolute code models.
1023  switch (getTargetMachine().getCodeModel()) {
1024  default:
1025  llvm_unreachable("Unsupported absolute code model");
1026  case CodeModel::Small:
1027  case CodeModel::Medium:
1028  case CodeModel::Large:
1029  // abs64.
1031  }
1032 }
1033 
1034 /// Custom Lower {
1035 
1036 // The mappings for emitLeading/TrailingFence for VE is designed by following
1037 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
1039  Instruction *Inst,
1040  AtomicOrdering Ord) const {
1041  switch (Ord) {
1044  llvm_unreachable("Invalid fence: unordered/non-atomic");
1047  return nullptr; // Nothing to do
1050  return Builder.CreateFence(AtomicOrdering::Release);
1052  if (!Inst->hasAtomicStore())
1053  return nullptr; // Nothing to do
1054  return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
1055  }
1056  llvm_unreachable("Unknown fence ordering in emitLeadingFence");
1057 }
1058 
1060  Instruction *Inst,
1061  AtomicOrdering Ord) const {
1062  switch (Ord) {
1065  llvm_unreachable("Invalid fence: unordered/not-atomic");
1068  return nullptr; // Nothing to do
1071  return Builder.CreateFence(AtomicOrdering::Acquire);
1073  return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
1074  }
1075  llvm_unreachable("Unknown fence ordering in emitTrailingFence");
1076 }
1077 
1079  SelectionDAG &DAG) const {
1080  SDLoc DL(Op);
1081  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
1082  cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
1083  SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
1084  cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
1085 
1086  // VE uses Release consistency, so need a fence instruction if it is a
1087  // cross-thread fence.
1088  if (FenceSSID == SyncScope::System) {
1089  switch (FenceOrdering) {
1093  // No need to generate fencem instruction here.
1094  break;
1096  // Generate "fencem 2" as acquire fence.
1097  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1098  DAG.getTargetConstant(2, DL, MVT::i32),
1099  Op.getOperand(0)),
1100  0);
1102  // Generate "fencem 1" as release fence.
1103  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1104  DAG.getTargetConstant(1, DL, MVT::i32),
1105  Op.getOperand(0)),
1106  0);
1109  // Generate "fencem 3" as acq_rel and seq_cst fence.
1110  // FIXME: "fencem 3" doesn't wait for for PCIe deveices accesses,
1111  // so seq_cst may require more instruction for them.
1112  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1113  DAG.getTargetConstant(3, DL, MVT::i32),
1114  Op.getOperand(0)),
1115  0);
1116  }
1117  }
1118 
1119  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
1120  return DAG.getNode(VEISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
1121 }
1122 
1125  // We have TS1AM implementation for i8/i16/i32/i64, so use it.
1126  if (AI->getOperation() == AtomicRMWInst::Xchg) {
1128  }
1129  // FIXME: Support "ATMAM" instruction for LOAD_ADD/SUB/AND/OR.
1130 
1131  // Otherwise, expand it using compare and exchange instruction to not call
1132  // __sync_fetch_and_* functions.
1134 }
1135 
1137  SDValue &Bits) {
1138  SDLoc DL(Op);
1139  AtomicSDNode *N = cast<AtomicSDNode>(Op);
1140  SDValue Ptr = N->getOperand(1);
1141  SDValue Val = N->getOperand(2);
1142  EVT PtrVT = Ptr.getValueType();
1143  bool Byte = N->getMemoryVT() == MVT::i8;
1144  // Remainder = AND Ptr, 3
1145  // Flag = 1 << Remainder ; If Byte is true (1 byte swap flag)
1146  // Flag = 3 << Remainder ; If Byte is false (2 bytes swap flag)
1147  // Bits = Remainder << 3
1148  // NewVal = Val << Bits
1149  SDValue Const3 = DAG.getConstant(3, DL, PtrVT);
1150  SDValue Remainder = DAG.getNode(ISD::AND, DL, PtrVT, {Ptr, Const3});
1151  SDValue Mask = Byte ? DAG.getConstant(1, DL, MVT::i32)
1152  : DAG.getConstant(3, DL, MVT::i32);
1153  Flag = DAG.getNode(ISD::SHL, DL, MVT::i32, {Mask, Remainder});
1154  Bits = DAG.getNode(ISD::SHL, DL, PtrVT, {Remainder, Const3});
1155  return DAG.getNode(ISD::SHL, DL, Val.getValueType(), {Val, Bits});
1156 }
1157 
1159  SDValue Bits) {
1160  SDLoc DL(Op);
1161  EVT VT = Data.getValueType();
1162  bool Byte = cast<AtomicSDNode>(Op)->getMemoryVT() == MVT::i8;
1163  // NewData = Data >> Bits
1164  // Result = NewData & 0xff ; If Byte is true (1 byte)
1165  // Result = NewData & 0xffff ; If Byte is false (2 bytes)
1166 
1167  SDValue NewData = DAG.getNode(ISD::SRL, DL, VT, Data, Bits);
1168  return DAG.getNode(ISD::AND, DL, VT,
1169  {NewData, DAG.getConstant(Byte ? 0xff : 0xffff, DL, VT)});
1170 }
1171 
1173  SelectionDAG &DAG) const {
1174  SDLoc DL(Op);
1175  AtomicSDNode *N = cast<AtomicSDNode>(Op);
1176 
1177  if (N->getMemoryVT() == MVT::i8) {
1178  // For i8, use "ts1am"
1179  // Input:
1180  // ATOMIC_SWAP Ptr, Val, Order
1181  //
1182  // Output:
1183  // Remainder = AND Ptr, 3
1184  // Flag = 1 << Remainder ; 1 byte swap flag for TS1AM inst.
1185  // Bits = Remainder << 3
1186  // NewVal = Val << Bits
1187  //
1188  // Aligned = AND Ptr, -4
1189  // Data = TS1AM Aligned, Flag, NewVal
1190  //
1191  // NewData = Data >> Bits
1192  // Result = NewData & 0xff ; 1 byte result
1193  SDValue Flag;
1194  SDValue Bits;
1195  SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1196 
1197  SDValue Ptr = N->getOperand(1);
1198  SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1199  {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1200  SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
1201  DAG.getVTList(Op.getNode()->getValueType(0),
1202  Op.getNode()->getValueType(1)),
1203  {N->getChain(), Aligned, Flag, NewVal},
1204  N->getMemOperand());
1205 
1206  SDValue Result = finalizeTS1AM(Op, DAG, TS1AM, Bits);
1207  SDValue Chain = TS1AM.getValue(1);
1208  return DAG.getMergeValues({Result, Chain}, DL);
1209  }
1210  if (N->getMemoryVT() == MVT::i16) {
1211  // For i16, use "ts1am"
1212  SDValue Flag;
1213  SDValue Bits;
1214  SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1215 
1216  SDValue Ptr = N->getOperand(1);
1217  SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1218  {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1219  SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
1220  DAG.getVTList(Op.getNode()->getValueType(0),
1221  Op.getNode()->getValueType(1)),
1222  {N->getChain(), Aligned, Flag, NewVal},
1223  N->getMemOperand());
1224 
1225  SDValue Result = finalizeTS1AM(Op, DAG, TS1AM, Bits);
1226  SDValue Chain = TS1AM.getValue(1);
1227  return DAG.getMergeValues({Result, Chain}, DL);
1228  }
1229  // Otherwise, let llvm legalize it.
1230  return Op;
1231 }
1232 
1234  SelectionDAG &DAG) const {
1235  return makeAddress(Op, DAG);
1236 }
1237 
1239  SelectionDAG &DAG) const {
1240  return makeAddress(Op, DAG);
1241 }
1242 
1244  SelectionDAG &DAG) const {
1245  return makeAddress(Op, DAG);
1246 }
1247 
1248 SDValue
1250  SelectionDAG &DAG) const {
1251  SDLoc DL(Op);
1252 
1253  // Generate the following code:
1254  // t1: ch,glue = callseq_start t0, 0, 0
1255  // t2: i64,ch,glue = VEISD::GETTLSADDR t1, label, t1:1
1256  // t3: ch,glue = callseq_end t2, 0, 0, t2:2
1257  // t4: i64,ch,glue = CopyFromReg t3, Register:i64 $sx0, t3:1
1258  SDValue Label = withTargetFlags(Op, 0, DAG);
1259  EVT PtrVT = Op.getValueType();
1260 
1261  // Lowering the machine isd will make sure everything is in the right
1262  // location.
1263  SDValue Chain = DAG.getEntryNode();
1264  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1265  const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1267  Chain = DAG.getCALLSEQ_START(Chain, 64, 0, DL);
1268  SDValue Args[] = {Chain, Label, DAG.getRegisterMask(Mask), Chain.getValue(1)};
1269  Chain = DAG.getNode(VEISD::GETTLSADDR, DL, NodeTys, Args);
1270  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(64, DL, true),
1271  DAG.getIntPtrConstant(0, DL, true),
1272  Chain.getValue(1), DL);
1273  Chain = DAG.getCopyFromReg(Chain, DL, VE::SX0, PtrVT, Chain.getValue(1));
1274 
1275  // GETTLSADDR will be codegen'ed as call. Inform MFI that function has calls.
1277  MFI.setHasCalls(true);
1278 
1279  // Also generate code to prepare a GOT register if it is PIC.
1280  if (isPositionIndependent()) {
1281  MachineFunction &MF = DAG.getMachineFunction();
1282  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
1283  }
1284 
1285  return Chain;
1286 }
1287 
1289  SelectionDAG &DAG) const {
1290  // The current implementation of nld (2.26) doesn't allow local exec model
1291  // code described in VE-tls_v1.1.pdf (*1) as its input. Instead, we always
1292  // generate the general dynamic model code sequence.
1293  //
1294  // *1: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-tls_v1.1.pdf
1295  return lowerToTLSGeneralDynamicModel(Op, DAG);
1296 }
1297 
1299  return makeAddress(Op, DAG);
1300 }
1301 
1302 // Lower a f128 load into two f64 loads.
1304  SDLoc DL(Op);
1305  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
1306  assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type");
1307  unsigned Alignment = LdNode->getAlign().value();
1308  if (Alignment > 8)
1309  Alignment = 8;
1310 
1311  SDValue Lo64 =
1312  DAG.getLoad(MVT::f64, DL, LdNode->getChain(), LdNode->getBasePtr(),
1313  LdNode->getPointerInfo(), Alignment,
1316  EVT AddrVT = LdNode->getBasePtr().getValueType();
1317  SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, LdNode->getBasePtr(),
1318  DAG.getConstant(8, DL, AddrVT));
1319  SDValue Hi64 =
1320  DAG.getLoad(MVT::f64, DL, LdNode->getChain(), HiPtr,
1321  LdNode->getPointerInfo(), Alignment,
1324 
1325  SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32);
1326  SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32);
1327 
1328  // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1329  SDNode *InFP128 =
1330  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f128);
1331  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1332  SDValue(InFP128, 0), Hi64, SubRegEven);
1333  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1334  SDValue(InFP128, 0), Lo64, SubRegOdd);
1335  SDValue OutChains[2] = {SDValue(Lo64.getNode(), 1),
1336  SDValue(Hi64.getNode(), 1)};
1337  SDValue OutChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1338  SDValue Ops[2] = {SDValue(InFP128, 0), OutChain};
1339  return DAG.getMergeValues(Ops, DL);
1340 }
1341 
1343  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
1344 
1345  EVT MemVT = LdNode->getMemoryVT();
1346 
1347  // Dispatch to vector isel.
1348  if (MemVT.isVector() && !isMaskType(MemVT))
1349  return lowerToVVP(Op, DAG);
1350 
1351  SDValue BasePtr = LdNode->getBasePtr();
1352  if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1353  // Do not expand store instruction with frame index here because of
1354  // dependency problems. We expand it later in eliminateFrameIndex().
1355  return Op;
1356  }
1357 
1358  if (MemVT == MVT::f128)
1359  return lowerLoadF128(Op, DAG);
1360 
1361  return Op;
1362 }
1363 
1364 // Lower a f128 store into two f64 stores.
1366  SDLoc DL(Op);
1367  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
1368  assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1369 
1370  SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32);
1371  SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32);
1372 
1373  SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64,
1374  StNode->getValue(), SubRegEven);
1375  SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64,
1376  StNode->getValue(), SubRegOdd);
1377 
1378  unsigned Alignment = StNode->getAlign().value();
1379  if (Alignment > 8)
1380  Alignment = 8;
1381 
1382  // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1383  SDValue OutChains[2];
1384  OutChains[0] =
1385  DAG.getStore(StNode->getChain(), DL, SDValue(Lo64, 0),
1386  StNode->getBasePtr(), MachinePointerInfo(), Alignment,
1389  EVT AddrVT = StNode->getBasePtr().getValueType();
1390  SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, StNode->getBasePtr(),
1391  DAG.getConstant(8, DL, AddrVT));
1392  OutChains[1] =
1393  DAG.getStore(StNode->getChain(), DL, SDValue(Hi64, 0), HiPtr,
1394  MachinePointerInfo(), Alignment,
1397  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1398 }
1399 
1401  StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
1402  assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1403 
1404  // always expand non-mask vector loads to VVP
1405  EVT MemVT = StNode->getMemoryVT();
1406  if (MemVT.isVector() && !isMaskType(MemVT))
1407  return lowerToVVP(Op, DAG);
1408 
1409  SDValue BasePtr = StNode->getBasePtr();
1410  if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1411  // Do not expand store instruction with frame index here because of
1412  // dependency problems. We expand it later in eliminateFrameIndex().
1413  return Op;
1414  }
1415 
1416  if (MemVT == MVT::f128)
1417  return lowerStoreF128(Op, DAG);
1418 
1419  // Otherwise, ask llvm to expand it.
1420  return SDValue();
1421 }
1422 
1424  MachineFunction &MF = DAG.getMachineFunction();
1426  auto PtrVT = getPointerTy(DAG.getDataLayout());
1427 
1428  // Need frame address to find the address of VarArgsFrameIndex.
1430 
1431  // vastart just stores the address of the VarArgsFrameIndex slot into the
1432  // memory location argument.
1433  SDLoc DL(Op);
1434  SDValue Offset =
1435  DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT),
1436  DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
1437  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1438  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
1439  MachinePointerInfo(SV));
1440 }
1441 
1443  SDNode *Node = Op.getNode();
1444  EVT VT = Node->getValueType(0);
1445  SDValue InChain = Node->getOperand(0);
1446  SDValue VAListPtr = Node->getOperand(1);
1447  EVT PtrVT = VAListPtr.getValueType();
1448  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1449  SDLoc DL(Node);
1450  SDValue VAList =
1451  DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
1452  SDValue Chain = VAList.getValue(1);
1453  SDValue NextPtr;
1454 
1455  if (VT == MVT::f128) {
1456  // VE f128 values must be stored with 16 bytes alignment. We doesn't
1457  // know the actual alignment of VAList, so we take alignment of it
1458  // dyanmically.
1459  int Align = 16;
1460  VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1461  DAG.getConstant(Align - 1, DL, PtrVT));
1462  VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
1463  DAG.getConstant(-Align, DL, PtrVT));
1464  // Increment the pointer, VAList, by 16 to the next vaarg.
1465  NextPtr =
1466  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(16, DL));
1467  } else if (VT == MVT::f32) {
1468  // float --> need special handling like below.
1469  // 0 4
1470  // +------+------+
1471  // | empty| float|
1472  // +------+------+
1473  // Increment the pointer, VAList, by 8 to the next vaarg.
1474  NextPtr =
1475  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
1476  // Then, adjust VAList.
1477  unsigned InternalOffset = 4;
1478  VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1479  DAG.getConstant(InternalOffset, DL, PtrVT));
1480  } else {
1481  // Increment the pointer, VAList, by 8 to the next vaarg.
1482  NextPtr =
1483  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
1484  }
1485 
1486  // Store the incremented VAList to the legalized pointer.
1487  InChain = DAG.getStore(Chain, DL, NextPtr, VAListPtr, MachinePointerInfo(SV));
1488 
1489  // Load the actual argument out of the pointer VAList.
1490  // We can't count on greater alignment than the word size.
1491  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
1492  std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8);
1493 }
1494 
1496  SelectionDAG &DAG) const {
1497  // Generate following code.
1498  // (void)__llvm_grow_stack(size);
1499  // ret = GETSTACKTOP; // pseudo instruction
1500  SDLoc DL(Op);
1501 
1502  // Get the inputs.
1503  SDNode *Node = Op.getNode();
1504  SDValue Chain = Op.getOperand(0);
1505  SDValue Size = Op.getOperand(1);
1506  MaybeAlign Alignment(Op.getConstantOperandVal(2));
1507  EVT VT = Node->getValueType(0);
1508 
1509  // Chain the dynamic stack allocation so that it doesn't modify the stack
1510  // pointer when other instructions are using the stack.
1511  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
1512 
1513  const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
1514  Align StackAlign = TFI.getStackAlign();
1515  bool NeedsAlign = Alignment.valueOrOne() > StackAlign;
1516 
1517  // Prepare arguments
1520  Entry.Node = Size;
1521  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1522  Args.push_back(Entry);
1523  if (NeedsAlign) {
1524  Entry.Node = DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT);
1525  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1526  Args.push_back(Entry);
1527  }
1528  Type *RetTy = Type::getVoidTy(*DAG.getContext());
1529 
1530  EVT PtrVT = Op.getValueType();
1531  SDValue Callee;
1532  if (NeedsAlign) {
1533  Callee = DAG.getTargetExternalSymbol("__ve_grow_stack_align", PtrVT, 0);
1534  } else {
1535  Callee = DAG.getTargetExternalSymbol("__ve_grow_stack", PtrVT, 0);
1536  }
1537 
1539  CLI.setDebugLoc(DL)
1540  .setChain(Chain)
1542  .setDiscardResult(true);
1543  std::pair<SDValue, SDValue> pair = LowerCallTo(CLI);
1544  Chain = pair.second;
1545  SDValue Result = DAG.getNode(VEISD::GETSTACKTOP, DL, VT, Chain);
1546  if (NeedsAlign) {
1547  Result = DAG.getNode(ISD::ADD, DL, VT, Result,
1548  DAG.getConstant((Alignment->value() - 1ULL), DL, VT));
1549  Result = DAG.getNode(ISD::AND, DL, VT, Result,
1550  DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT));
1551  }
1552  // Chain = Result.getValue(1);
1553  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
1554  DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
1555 
1556  SDValue Ops[2] = {Result, Chain};
1557  return DAG.getMergeValues(Ops, DL);
1558 }
1559 
1561  SelectionDAG &DAG) const {
1562  SDLoc DL(Op);
1563  return DAG.getNode(VEISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0),
1564  Op.getOperand(1));
1565 }
1566 
1568  SelectionDAG &DAG) const {
1569  SDLoc DL(Op);
1570  return DAG.getNode(VEISD::EH_SJLJ_SETJMP, DL,
1571  DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
1572  Op.getOperand(1));
1573 }
1574 
1576  SelectionDAG &DAG) const {
1577  SDLoc DL(Op);
1579  Op.getOperand(0));
1580 }
1581 
1583  const VETargetLowering &TLI,
1584  const VESubtarget *Subtarget) {
1585  SDLoc DL(Op);
1586  MachineFunction &MF = DAG.getMachineFunction();
1587  EVT PtrVT = TLI.getPointerTy(MF.getDataLayout());
1588 
1589  MachineFrameInfo &MFI = MF.getFrameInfo();
1590  MFI.setFrameAddressIsTaken(true);
1591 
1592  unsigned Depth = Op.getConstantOperandVal(0);
1593  const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
1594  Register FrameReg = RegInfo->getFrameRegister(MF);
1595  SDValue FrameAddr =
1596  DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT);
1597  while (Depth--)
1598  FrameAddr = DAG.getLoad(Op.getValueType(), DL, DAG.getEntryNode(),
1599  FrameAddr, MachinePointerInfo());
1600  return FrameAddr;
1601 }
1602 
1604  const VETargetLowering &TLI,
1605  const VESubtarget *Subtarget) {
1606  MachineFunction &MF = DAG.getMachineFunction();
1607  MachineFrameInfo &MFI = MF.getFrameInfo();
1608  MFI.setReturnAddressIsTaken(true);
1609 
1611  return SDValue();
1612 
1613  SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
1614 
1615  SDLoc DL(Op);
1616  EVT VT = Op.getValueType();
1617  SDValue Offset = DAG.getConstant(8, DL, VT);
1618  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1619  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
1620  MachinePointerInfo());
1621 }
1622 
1624  SelectionDAG &DAG) const {
1625  SDLoc DL(Op);
1626  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1627  switch (IntNo) {
1628  default: // Don't custom lower most intrinsics.
1629  return SDValue();
1630  case Intrinsic::eh_sjlj_lsda: {
1631  MachineFunction &MF = DAG.getMachineFunction();
1632  MVT VT = Op.getSimpleValueType();
1633  const VETargetMachine *TM =
1634  static_cast<const VETargetMachine *>(&DAG.getTarget());
1635 
1636  // Create GCC_except_tableXX string. The real symbol for that will be
1637  // generated in EHStreamer::emitExceptionTable() later. So, we just
1638  // borrow it's name here.
1639  TM->getStrList()->push_back(std::string(
1640  (Twine("GCC_except_table") + Twine(MF.getFunctionNumber())).str()));
1641  SDValue Addr =
1642  DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);
1643  if (isPositionIndependent()) {
1646  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, VT);
1647  return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);
1648  }
1650  }
1651  }
1652 }
1653 
1654 static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx) {
1655  if (!isa<BuildVectorSDNode>(N))
1656  return false;
1657  const auto *BVN = cast<BuildVectorSDNode>(N);
1658 
1659  // Find first non-undef insertion.
1660  unsigned Idx;
1661  for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
1662  auto ElemV = BVN->getOperand(Idx);
1663  if (!ElemV->isUndef())
1664  break;
1665  }
1666  // Catch the (hypothetical) all-undef case.
1667  if (Idx == BVN->getNumOperands())
1668  return false;
1669  // Remember insertion.
1670  UniqueIdx = Idx++;
1671  // Verify that all other insertions are undef.
1672  for (; Idx < BVN->getNumOperands(); ++Idx) {
1673  auto ElemV = BVN->getOperand(Idx);
1674  if (!ElemV->isUndef())
1675  return false;
1676  }
1677  return true;
1678 }
1679 
1681  if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
1682  return BuildVec->getSplatValue();
1683  }
1684  return SDValue();
1685 }
1686 
1688  SelectionDAG &DAG) const {
1689  VECustomDAG CDAG(DAG, Op);
1690  MVT ResultVT = Op.getSimpleValueType();
1691 
1692  // If there is just one element, expand to INSERT_VECTOR_ELT.
1693  unsigned UniqueIdx;
1694  if (getUniqueInsertion(Op.getNode(), UniqueIdx)) {
1695  SDValue AccuV = CDAG.getUNDEF(Op.getValueType());
1696  auto ElemV = Op->getOperand(UniqueIdx);
1697  SDValue IdxV = CDAG.getConstant(UniqueIdx, MVT::i64);
1698  return CDAG.getNode(ISD::INSERT_VECTOR_ELT, ResultVT, {AccuV, ElemV, IdxV});
1699  }
1700 
1701  // Else emit a broadcast.
1702  if (SDValue ScalarV = getSplatValue(Op.getNode())) {
1703  unsigned NumEls = ResultVT.getVectorNumElements();
1704  auto AVL = CDAG.getConstant(NumEls, MVT::i32);
1705  return CDAG.getBroadcast(ResultVT, ScalarV, AVL);
1706  }
1707 
1708  // Expand
1709  return SDValue();
1710 }
1711 
1714  // Custom legalization on VVP_* and VEC_* opcodes is required to pack-legalize
1715  // these operations (transform nodes such that their AVL parameter refers to
1716  // packs of 64bit, instead of number of elements.
1717 
1718  // Packing opcodes are created with a pack-legal AVL (LEGALAVL). No need to
1719  // re-visit them.
1720  if (isPackingSupportOpcode(Op.getOpcode()))
1721  return Legal;
1722 
1723  // Custom lower to legalize AVL for packed mode.
1724  if (isVVPOrVEC(Op.getOpcode()))
1725  return Custom;
1726  return Legal;
1727 }
1728 
1730  LLVM_DEBUG(dbgs() << "::LowerOperation"; Op->print(dbgs()););
1731  unsigned Opcode = Op.getOpcode();
1732 
1733  /// Scalar isel.
1734  switch (Opcode) {
1735  case ISD::ATOMIC_FENCE:
1736  return lowerATOMIC_FENCE(Op, DAG);
1737  case ISD::ATOMIC_SWAP:
1738  return lowerATOMIC_SWAP(Op, DAG);
1739  case ISD::BlockAddress:
1740  return lowerBlockAddress(Op, DAG);
1741  case ISD::ConstantPool:
1742  return lowerConstantPool(Op, DAG);
1744  return lowerDYNAMIC_STACKALLOC(Op, DAG);
1745  case ISD::EH_SJLJ_LONGJMP:
1746  return lowerEH_SJLJ_LONGJMP(Op, DAG);
1747  case ISD::EH_SJLJ_SETJMP:
1748  return lowerEH_SJLJ_SETJMP(Op, DAG);
1750  return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
1751  case ISD::FRAMEADDR:
1752  return lowerFRAMEADDR(Op, DAG, *this, Subtarget);
1753  case ISD::GlobalAddress:
1754  return lowerGlobalAddress(Op, DAG);
1755  case ISD::GlobalTLSAddress:
1756  return lowerGlobalTLSAddress(Op, DAG);
1758  return lowerINTRINSIC_WO_CHAIN(Op, DAG);
1759  case ISD::JumpTable:
1760  return lowerJumpTable(Op, DAG);
1761  case ISD::LOAD:
1762  return lowerLOAD(Op, DAG);
1763  case ISD::RETURNADDR:
1764  return lowerRETURNADDR(Op, DAG, *this, Subtarget);
1765  case ISD::BUILD_VECTOR:
1766  return lowerBUILD_VECTOR(Op, DAG);
1767  case ISD::STORE:
1768  return lowerSTORE(Op, DAG);
1769  case ISD::VASTART:
1770  return lowerVASTART(Op, DAG);
1771  case ISD::VAARG:
1772  return lowerVAARG(Op, DAG);
1773 
1775  return lowerINSERT_VECTOR_ELT(Op, DAG);
1777  return lowerEXTRACT_VECTOR_ELT(Op, DAG);
1778  }
1779 
1780  /// Vector isel.
1781  LLVM_DEBUG(dbgs() << "::LowerOperation_VVP"; Op->print(dbgs()););
1782  if (ISD::isVPOpcode(Opcode))
1783  return lowerToVVP(Op, DAG);
1784 
1785  switch (Opcode) {
1786  default:
1787  llvm_unreachable("Should not custom lower this!");
1788 
1789  // Legalize the AVL of this internal node.
1790  case VEISD::VEC_BROADCAST:
1791 #define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1792 #include "VVPNodes.def"
1793  // AVL already legalized.
1794  if (getAnnotatedNodeAVL(Op).second)
1795  return Op;
1796  return legalizeInternalVectorOp(Op, DAG);
1797 
1798  // Translate into a VEC_*/VVP_* layer operation.
1799  case ISD::MLOAD:
1800  case ISD::MSTORE:
1801 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1802 #include "VVPNodes.def"
1803  if (isMaskArithmetic(Op) && isPackedVectorType(Op.getValueType()))
1804  return splitMaskArithmetic(Op, DAG);
1805  return lowerToVVP(Op, DAG);
1806  }
1807 }
1808 /// } Custom Lower
1809 
1812  SelectionDAG &DAG) const {
1813  switch (N->getOpcode()) {
1814  case ISD::ATOMIC_SWAP:
1815  // Let LLVM expand atomic swap instruction through LowerOperation.
1816  return;
1817  default:
1818  LLVM_DEBUG(N->dumpr(&DAG));
1819  llvm_unreachable("Do not know how to custom type legalize this operation!");
1820  }
1821 }
1822 
1823 /// JumpTable for VE.
1824 ///
1825 /// VE cannot generate relocatable symbol in jump table. VE cannot
1826 /// generate expressions using symbols in both text segment and data
1827 /// segment like below.
1828 /// .4byte .LBB0_2-.LJTI0_0
1829 /// So, we generate offset from the top of function like below as
1830 /// a custom label.
1831 /// .4byte .LBB0_2-<function name>
1832 
1834  // Use custom label for PIC.
1835  if (isPositionIndependent())
1837 
1838  // Otherwise, use the normal jump table encoding heuristics.
1840 }
1841 
1843  const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
1844  unsigned Uid, MCContext &Ctx) const {
1846 
1847  // Generate custom label for PIC like below.
1848  // .4bytes .LBB0_2-<function name>
1849  const auto *Value = MCSymbolRefExpr::create(MBB->getSymbol(), Ctx);
1850  MCSymbol *Sym = Ctx.getOrCreateSymbol(MBB->getParent()->getName().data());
1851  const auto *Base = MCSymbolRefExpr::create(Sym, Ctx);
1852  return MCBinaryExpr::createSub(Value, Base, Ctx);
1853 }
1854 
1856  SelectionDAG &DAG) const {
1858  SDLoc DL(Table);
1860  assert(Function != nullptr);
1861  auto PtrTy = getPointerTy(DAG.getDataLayout(), Function->getAddressSpace());
1862 
1863  // In the jump table, we have following values in PIC mode.
1864  // .4bytes .LBB0_2-<function name>
1865  // We need to add this value and the address of this function to generate
1866  // .LBB0_2 label correctly under PIC mode. So, we want to generate following
1867  // instructions:
1868  // lea %reg, fun@gotoff_lo
1869  // and %reg, %reg, (32)0
1870  // lea.sl %reg, fun@gotoff_hi(%reg, %got)
1871  // In order to do so, we need to genarate correctly marked DAG node using
1872  // makeHiLoPair.
1873  SDValue Op = DAG.getGlobalAddress(Function, DL, PtrTy);
1876  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrTy);
1877  return DAG.getNode(ISD::ADD, DL, PtrTy, GlobalBase, HiLo);
1878 }
1879 
1882  MachineBasicBlock *TargetBB,
1883  const DebugLoc &DL) const {
1884  MachineFunction *MF = MBB.getParent();
1886  const VEInstrInfo *TII = Subtarget->getInstrInfo();
1887 
1888  const TargetRegisterClass *RC = &VE::I64RegClass;
1889  Register Tmp1 = MRI.createVirtualRegister(RC);
1890  Register Tmp2 = MRI.createVirtualRegister(RC);
1891  Register Result = MRI.createVirtualRegister(RC);
1892 
1893  if (isPositionIndependent()) {
1894  // Create following instructions for local linkage PIC code.
1895  // lea %Tmp1, TargetBB@gotoff_lo
1896  // and %Tmp2, %Tmp1, (32)0
1897  // lea.sl %Result, TargetBB@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1898  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
1899  .addImm(0)
1900  .addImm(0)
1901  .addMBB(TargetBB, VEMCExpr::VK_VE_GOTOFF_LO32);
1902  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1903  .addReg(Tmp1, getKillRegState(true))
1904  .addImm(M0(32));
1905  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result)
1906  .addReg(VE::SX15)
1907  .addReg(Tmp2, getKillRegState(true))
1908  .addMBB(TargetBB, VEMCExpr::VK_VE_GOTOFF_HI32);
1909  } else {
1910  // Create following instructions for non-PIC code.
1911  // lea %Tmp1, TargetBB@lo
1912  // and %Tmp2, %Tmp1, (32)0
1913  // lea.sl %Result, TargetBB@hi(%Tmp2)
1914  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
1915  .addImm(0)
1916  .addImm(0)
1917  .addMBB(TargetBB, VEMCExpr::VK_VE_LO32);
1918  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1919  .addReg(Tmp1, getKillRegState(true))
1920  .addImm(M0(32));
1921  BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result)
1922  .addReg(Tmp2, getKillRegState(true))
1923  .addImm(0)
1924  .addMBB(TargetBB, VEMCExpr::VK_VE_HI32);
1925  }
1926  return Result;
1927 }
1928 
1931  StringRef Symbol, const DebugLoc &DL,
1932  bool IsLocal = false,
1933  bool IsCall = false) const {
1934  MachineFunction *MF = MBB.getParent();
1936  const VEInstrInfo *TII = Subtarget->getInstrInfo();
1937 
1938  const TargetRegisterClass *RC = &VE::I64RegClass;
1939  Register Result = MRI.createVirtualRegister(RC);
1940 
1941  if (isPositionIndependent()) {
1942  if (IsCall && !IsLocal) {
1943  // Create following instructions for non-local linkage PIC code function
1944  // calls. These instructions uses IC and magic number -24, so we expand
1945  // them in VEAsmPrinter.cpp from GETFUNPLT pseudo instruction.
1946  // lea %Reg, Symbol@plt_lo(-24)
1947  // and %Reg, %Reg, (32)0
1948  // sic %s16
1949  // lea.sl %Result, Symbol@plt_hi(%Reg, %s16) ; %s16 is PLT
1950  BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result)
1951  .addExternalSymbol("abort");
1952  } else if (IsLocal) {
1953  Register Tmp1 = MRI.createVirtualRegister(RC);
1954  Register Tmp2 = MRI.createVirtualRegister(RC);
1955  // Create following instructions for local linkage PIC code.
1956  // lea %Tmp1, Symbol@gotoff_lo
1957  // and %Tmp2, %Tmp1, (32)0
1958  // lea.sl %Result, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1959  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
1960  .addImm(0)
1961  .addImm(0)
1963  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1964  .addReg(Tmp1, getKillRegState(true))
1965  .addImm(M0(32));
1966  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result)
1967  .addReg(VE::SX15)
1968  .addReg(Tmp2, getKillRegState(true))
1970  } else {
1971  Register Tmp1 = MRI.createVirtualRegister(RC);
1972  Register Tmp2 = MRI.createVirtualRegister(RC);
1973  // Create following instructions for not local linkage PIC code.
1974  // lea %Tmp1, Symbol@got_lo
1975  // and %Tmp2, %Tmp1, (32)0
1976  // lea.sl %Tmp3, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1977  // ld %Result, 0(%Tmp3)
1978  Register Tmp3 = MRI.createVirtualRegister(RC);
1979  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
1980  .addImm(0)
1981  .addImm(0)
1983  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
1984  .addReg(Tmp1, getKillRegState(true))
1985  .addImm(M0(32));
1986  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3)
1987  .addReg(VE::SX15)
1988  .addReg(Tmp2, getKillRegState(true))
1990  BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result)
1991  .addReg(Tmp3, getKillRegState(true))
1992  .addImm(0)
1993  .addImm(0);
1994  }
1995  } else {
1996  Register Tmp1 = MRI.createVirtualRegister(RC);
1997  Register Tmp2 = MRI.createVirtualRegister(RC);
1998  // Create following instructions for non-PIC code.
1999  // lea %Tmp1, Symbol@lo
2000  // and %Tmp2, %Tmp1, (32)0
2001  // lea.sl %Result, Symbol@hi(%Tmp2)
2002  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2003  .addImm(0)
2004  .addImm(0)
2006  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2007  .addReg(Tmp1, getKillRegState(true))
2008  .addImm(M0(32));
2009  BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result)
2010  .addReg(Tmp2, getKillRegState(true))
2011  .addImm(0)
2013  }
2014  return Result;
2015 }
2016 
2019  MachineBasicBlock *DispatchBB,
2020  int FI, int Offset) const {
2021  DebugLoc DL = MI.getDebugLoc();
2022  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2023 
2024  Register LabelReg =
2025  prepareMBB(*MBB, MachineBasicBlock::iterator(MI), DispatchBB, DL);
2026 
2027  // Store an address of DispatchBB to a given jmpbuf[1] where has next IC
2028  // referenced by longjmp (throw) later.
2029  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2030  addFrameReference(MIB, FI, Offset); // jmpbuf[1]
2031  MIB.addReg(LabelReg, getKillRegState(true));
2032 }
2033 
2036  MachineBasicBlock *MBB) const {
2037  DebugLoc DL = MI.getDebugLoc();
2038  MachineFunction *MF = MBB->getParent();
2039  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2040  const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
2042 
2043  const BasicBlock *BB = MBB->getBasicBlock();
2045 
2046  // Memory Reference.
2047  SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands_begin(),
2048  MI.memoperands_end());
2049  Register BufReg = MI.getOperand(1).getReg();
2050 
2051  Register DstReg;
2052 
2053  DstReg = MI.getOperand(0).getReg();
2054  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
2055  assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
2056  (void)TRI;
2057  Register MainDestReg = MRI.createVirtualRegister(RC);
2058  Register RestoreDestReg = MRI.createVirtualRegister(RC);
2059 
2060  // For `v = call @llvm.eh.sjlj.setjmp(buf)`, we generate following
2061  // instructions. SP/FP must be saved in jmpbuf before `llvm.eh.sjlj.setjmp`.
2062  //
2063  // ThisMBB:
2064  // buf[3] = %s17 iff %s17 is used as BP
2065  // buf[1] = RestoreMBB as IC after longjmp
2066  // # SjLjSetup RestoreMBB
2067  //
2068  // MainMBB:
2069  // v_main = 0
2070  //
2071  // SinkMBB:
2072  // v = phi(v_main, MainMBB, v_restore, RestoreMBB)
2073  // ...
2074  //
2075  // RestoreMBB:
2076  // %s17 = buf[3] = iff %s17 is used as BP
2077  // v_restore = 1
2078  // goto SinkMBB
2079 
2080  MachineBasicBlock *ThisMBB = MBB;
2083  MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
2084  MF->insert(I, MainMBB);
2085  MF->insert(I, SinkMBB);
2086  MF->push_back(RestoreMBB);
2087  RestoreMBB->setHasAddressTaken();
2088 
2089  // Transfer the remainder of BB and its successor edges to SinkMBB.
2090  SinkMBB->splice(SinkMBB->begin(), MBB,
2091  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2093 
2094  // ThisMBB:
2095  Register LabelReg =
2096  prepareMBB(*MBB, MachineBasicBlock::iterator(MI), RestoreMBB, DL);
2097 
2098  // Store BP in buf[3] iff this function is using BP.
2099  const VEFrameLowering *TFI = Subtarget->getFrameLowering();
2100  if (TFI->hasBP(*MF)) {
2101  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2102  MIB.addReg(BufReg);
2103  MIB.addImm(0);
2104  MIB.addImm(24);
2105  MIB.addReg(VE::SX17);
2106  MIB.setMemRefs(MMOs);
2107  }
2108 
2109  // Store IP in buf[1].
2110  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2111  MIB.add(MI.getOperand(1)); // we can preserve the kill flags here.
2112  MIB.addImm(0);
2113  MIB.addImm(8);
2114  MIB.addReg(LabelReg, getKillRegState(true));
2115  MIB.setMemRefs(MMOs);
2116 
2117  // SP/FP are already stored in jmpbuf before `llvm.eh.sjlj.setjmp`.
2118 
2119  // Insert setup.
2120  MIB =
2121  BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB);
2122 
2123  const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2124  MIB.addRegMask(RegInfo->getNoPreservedMask());
2125  ThisMBB->addSuccessor(MainMBB);
2126  ThisMBB->addSuccessor(RestoreMBB);
2127 
2128  // MainMBB:
2129  BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg)
2130  .addImm(0)
2131  .addImm(0)
2132  .addImm(0);
2133  MainMBB->addSuccessor(SinkMBB);
2134 
2135  // SinkMBB:
2136  BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg)
2137  .addReg(MainDestReg)
2138  .addMBB(MainMBB)
2139  .addReg(RestoreDestReg)
2140  .addMBB(RestoreMBB);
2141 
2142  // RestoreMBB:
2143  // Restore BP from buf[3] iff this function is using BP. The address of
2144  // buf is in SX10.
2145  // FIXME: Better to not use SX10 here
2146  if (TFI->hasBP(*MF)) {
2147  MachineInstrBuilder MIB =
2148  BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17);
2149  MIB.addReg(VE::SX10);
2150  MIB.addImm(0);
2151  MIB.addImm(24);
2152  MIB.setMemRefs(MMOs);
2153  }
2154  BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg)
2155  .addImm(0)
2156  .addImm(0)
2157  .addImm(1);
2158  BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB);
2159  RestoreMBB->addSuccessor(SinkMBB);
2160 
2161  MI.eraseFromParent();
2162  return SinkMBB;
2163 }
2164 
2167  MachineBasicBlock *MBB) const {
2168  DebugLoc DL = MI.getDebugLoc();
2169  MachineFunction *MF = MBB->getParent();
2170  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2172 
2173  // Memory Reference.
2174  SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands_begin(),
2175  MI.memoperands_end());
2176  Register BufReg = MI.getOperand(0).getReg();
2177 
2178  Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass);
2179  // Since FP is only updated here but NOT referenced, it's treated as GPR.
2180  Register FP = VE::SX9;
2181  Register SP = VE::SX11;
2182 
2183  MachineInstrBuilder MIB;
2184 
2185  MachineBasicBlock *ThisMBB = MBB;
2186 
2187  // For `call @llvm.eh.sjlj.longjmp(buf)`, we generate following instructions.
2188  //
2189  // ThisMBB:
2190  // %fp = load buf[0]
2191  // %jmp = load buf[1]
2192  // %s10 = buf ; Store an address of buf to SX10 for RestoreMBB
2193  // %sp = load buf[2] ; generated by llvm.eh.sjlj.setjmp.
2194  // jmp %jmp
2195 
2196  // Reload FP.
2197  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP);
2198  MIB.addReg(BufReg);
2199  MIB.addImm(0);
2200  MIB.addImm(0);
2201  MIB.setMemRefs(MMOs);
2202 
2203  // Reload IP.
2204  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp);
2205  MIB.addReg(BufReg);
2206  MIB.addImm(0);
2207  MIB.addImm(8);
2208  MIB.setMemRefs(MMOs);
2209 
2210  // Copy BufReg to SX10 for later use in setjmp.
2211  // FIXME: Better to not use SX10 here
2212  BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10)
2213  .addReg(BufReg)
2214  .addImm(0);
2215 
2216  // Reload SP.
2217  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP);
2218  MIB.add(MI.getOperand(0)); // we can preserve the kill flags here.
2219  MIB.addImm(0);
2220  MIB.addImm(16);
2221  MIB.setMemRefs(MMOs);
2222 
2223  // Jump.
2224  BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t))
2225  .addReg(Tmp, getKillRegState(true))
2226  .addImm(0);
2227 
2228  MI.eraseFromParent();
2229  return ThisMBB;
2230 }
2231 
2234  MachineBasicBlock *BB) const {
2235  DebugLoc DL = MI.getDebugLoc();
2236  MachineFunction *MF = BB->getParent();
2237  MachineFrameInfo &MFI = MF->getFrameInfo();
2239  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2240  int FI = MFI.getFunctionContextIndex();
2241 
2242  // Get a mapping of the call site numbers to all of the landing pads they're
2243  // associated with.
2245  unsigned MaxCSNum = 0;
2246  for (auto &MBB : *MF) {
2247  if (!MBB.isEHPad())
2248  continue;
2249 
2250  MCSymbol *Sym = nullptr;
2251  for (const auto &MI : MBB) {
2252  if (MI.isDebugInstr())
2253  continue;
2254 
2255  assert(MI.isEHLabel() && "expected EH_LABEL");
2256  Sym = MI.getOperand(0).getMCSymbol();
2257  break;
2258  }
2259 
2260  if (!MF->hasCallSiteLandingPad(Sym))
2261  continue;
2262 
2263  for (unsigned CSI : MF->getCallSiteLandingPad(Sym)) {
2264  CallSiteNumToLPad[CSI].push_back(&MBB);
2265  MaxCSNum = std::max(MaxCSNum, CSI);
2266  }
2267  }
2268 
2269  // Get an ordered list of the machine basic blocks for the jump table.
2270  std::vector<MachineBasicBlock *> LPadList;
2272  LPadList.reserve(CallSiteNumToLPad.size());
2273 
2274  for (unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2275  for (auto &LP : CallSiteNumToLPad[CSI]) {
2276  LPadList.push_back(LP);
2277  InvokeBBs.insert(LP->pred_begin(), LP->pred_end());
2278  }
2279  }
2280 
2281  assert(!LPadList.empty() &&
2282  "No landing pad destinations for the dispatch jump table!");
2283 
2284  // The %fn_context is allocated like below (from --print-after=sjljehprepare):
2285  // %fn_context = alloca { i8*, i64, [4 x i64], i8*, i8*, [5 x i8*] }
2286  //
2287  // This `[5 x i8*]` is jmpbuf, so jmpbuf[1] is FI+72.
2288  // First `i64` is callsite, so callsite is FI+8.
2289  static const int OffsetIC = 72;
2290  static const int OffsetCS = 8;
2291 
2292  // Create the MBBs for the dispatch code like following:
2293  //
2294  // ThisMBB:
2295  // Prepare DispatchBB address and store it to buf[1].
2296  // ...
2297  //
2298  // DispatchBB:
2299  // %s15 = GETGOT iff isPositionIndependent
2300  // %callsite = load callsite
2301  // brgt.l.t #size of callsites, %callsite, DispContBB
2302  //
2303  // TrapBB:
2304  // Call abort.
2305  //
2306  // DispContBB:
2307  // %breg = address of jump table
2308  // %pc = load and calculate next pc from %breg and %callsite
2309  // jmp %pc
2310 
2311  // Shove the dispatch's address into the return slot in the function context.
2312  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
2313  DispatchBB->setIsEHPad(true);
2314 
2315  // Trap BB will causes trap like `assert(0)`.
2316  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
2317  DispatchBB->addSuccessor(TrapBB);
2318 
2319  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
2320  DispatchBB->addSuccessor(DispContBB);
2321 
2322  // Insert MBBs.
2323  MF->push_back(DispatchBB);
2324  MF->push_back(DispContBB);
2325  MF->push_back(TrapBB);
2326 
2327  // Insert code to call abort in the TrapBB.
2328  Register Abort = prepareSymbol(*TrapBB, TrapBB->end(), "abort", DL,
2329  /* Local */ false, /* Call */ true);
2330  BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10)
2331  .addReg(Abort, getKillRegState(true))
2332  .addImm(0)
2333  .addImm(0);
2334 
2335  // Insert code into the entry block that creates and registers the function
2336  // context.
2337  setupEntryBlockForSjLj(MI, BB, DispatchBB, FI, OffsetIC);
2338 
2339  // Create the jump table and associated information
2340  unsigned JTE = getJumpTableEncoding();
2341  MachineJumpTableInfo *JTI = MF->getOrCreateJumpTableInfo(JTE);
2342  unsigned MJTI = JTI->createJumpTableIndex(LPadList);
2343 
2344  const VERegisterInfo &RI = TII->getRegisterInfo();
2345  // Add a register mask with no preserved registers. This results in all
2346  // registers being marked as clobbered.
2347  BuildMI(DispatchBB, DL, TII->get(VE::NOP))
2349 
2350  if (isPositionIndependent()) {
2351  // Force to generate GETGOT, since current implementation doesn't store GOT
2352  // register.
2353  BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15);
2354  }
2355 
2356  // IReg is used as an index in a memory operand and therefore can't be SP
2357  const TargetRegisterClass *RC = &VE::I64RegClass;
2358  Register IReg = MRI.createVirtualRegister(RC);
2359  addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI,
2360  OffsetCS);
2361  if (LPadList.size() < 64) {
2362  BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t))
2364  .addImm(LPadList.size())
2365  .addReg(IReg)
2366  .addMBB(TrapBB);
2367  } else {
2368  assert(LPadList.size() <= 0x7FFFFFFF && "Too large Landing Pad!");
2369  Register TmpReg = MRI.createVirtualRegister(RC);
2370  BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg)
2371  .addImm(0)
2372  .addImm(0)
2373  .addImm(LPadList.size());
2374  BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t))
2376  .addReg(TmpReg, getKillRegState(true))
2377  .addReg(IReg)
2378  .addMBB(TrapBB);
2379  }
2380 
2381  Register BReg = MRI.createVirtualRegister(RC);
2382  Register Tmp1 = MRI.createVirtualRegister(RC);
2383  Register Tmp2 = MRI.createVirtualRegister(RC);
2384 
2385  if (isPositionIndependent()) {
2386  // Create following instructions for local linkage PIC code.
2387  // lea %Tmp1, .LJTI0_0@gotoff_lo
2388  // and %Tmp2, %Tmp1, (32)0
2389  // lea.sl %BReg, .LJTI0_0@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2390  BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2391  .addImm(0)
2392  .addImm(0)
2394  BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2395  .addReg(Tmp1, getKillRegState(true))
2396  .addImm(M0(32));
2397  BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg)
2398  .addReg(VE::SX15)
2399  .addReg(Tmp2, getKillRegState(true))
2401  } else {
2402  // Create following instructions for non-PIC code.
2403  // lea %Tmp1, .LJTI0_0@lo
2404  // and %Tmp2, %Tmp1, (32)0
2405  // lea.sl %BReg, .LJTI0_0@hi(%Tmp2)
2406  BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2407  .addImm(0)
2408  .addImm(0)
2410  BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2411  .addReg(Tmp1, getKillRegState(true))
2412  .addImm(M0(32));
2413  BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg)
2414  .addReg(Tmp2, getKillRegState(true))
2415  .addImm(0)
2417  }
2418 
2419  switch (JTE) {
2421  // Generate simple block address code for no-PIC model.
2422  // sll %Tmp1, %IReg, 3
2423  // lds %TReg, 0(%Tmp1, %BReg)
2424  // bcfla %TReg
2425 
2426  Register TReg = MRI.createVirtualRegister(RC);
2427  Register Tmp1 = MRI.createVirtualRegister(RC);
2428 
2429  BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2430  .addReg(IReg, getKillRegState(true))
2431  .addImm(3);
2432  BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg)
2433  .addReg(BReg, getKillRegState(true))
2434  .addReg(Tmp1, getKillRegState(true))
2435  .addImm(0);
2436  BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2437  .addReg(TReg, getKillRegState(true))
2438  .addImm(0);
2439  break;
2440  }
2442  // Generate block address code using differences from the function pointer
2443  // for PIC model.
2444  // sll %Tmp1, %IReg, 2
2445  // ldl.zx %OReg, 0(%Tmp1, %BReg)
2446  // Prepare function address in BReg2.
2447  // adds.l %TReg, %BReg2, %OReg
2448  // bcfla %TReg
2449 
2451  Register OReg = MRI.createVirtualRegister(RC);
2452  Register TReg = MRI.createVirtualRegister(RC);
2453  Register Tmp1 = MRI.createVirtualRegister(RC);
2454 
2455  BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2456  .addReg(IReg, getKillRegState(true))
2457  .addImm(2);
2458  BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg)
2459  .addReg(BReg, getKillRegState(true))
2460  .addReg(Tmp1, getKillRegState(true))
2461  .addImm(0);
2462  Register BReg2 =
2463  prepareSymbol(*DispContBB, DispContBB->end(),
2464  DispContBB->getParent()->getName(), DL, /* Local */ true);
2465  BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg)
2466  .addReg(OReg, getKillRegState(true))
2467  .addReg(BReg2, getKillRegState(true));
2468  BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2469  .addReg(TReg, getKillRegState(true))
2470  .addImm(0);
2471  break;
2472  }
2473  default:
2474  llvm_unreachable("Unexpected jump table encoding");
2475  }
2476 
2477  // Add the jump table entries as successors to the MBB.
2479  for (auto &LP : LPadList)
2480  if (SeenMBBs.insert(LP).second)
2481  DispContBB->addSuccessor(LP);
2482 
2483  // N.B. the order the invoke BBs are processed in doesn't matter here.
2485  const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
2486  for (MachineBasicBlock *MBB : InvokeBBs) {
2487  // Remove the landing pad successor from the invoke block and replace it
2488  // with the new dispatch block.
2489  // Keep a copy of Successors since it's modified inside the loop.
2491  MBB->succ_rend());
2492  // FIXME: Avoid quadratic complexity.
2493  for (auto MBBS : Successors) {
2494  if (MBBS->isEHPad()) {
2495  MBB->removeSuccessor(MBBS);
2496  MBBLPads.push_back(MBBS);
2497  }
2498  }
2499 
2500  MBB->addSuccessor(DispatchBB);
2501 
2502  // Find the invoke call and mark all of the callee-saved registers as
2503  // 'implicit defined' so that they're spilled. This prevents code from
2504  // moving instructions to before the EH block, where they will never be
2505  // executed.
2506  for (auto &II : reverse(*MBB)) {
2507  if (!II.isCall())
2508  continue;
2509 
2510  DenseMap<Register, bool> DefRegs;
2511  for (auto &MOp : II.operands())
2512  if (MOp.isReg())
2513  DefRegs[MOp.getReg()] = true;
2514 
2515  MachineInstrBuilder MIB(*MF, &II);
2516  for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
2517  Register Reg = SavedRegs[RI];
2518  if (!DefRegs[Reg])
2520  }
2521 
2522  break;
2523  }
2524  }
2525 
2526  // Mark all former landing pads as non-landing pads. The dispatch is the only
2527  // landing pad now.
2528  for (auto &LP : MBBLPads)
2529  LP->setIsEHPad(false);
2530 
2531  // The instruction is gone now.
2532  MI.eraseFromParent();
2533  return BB;
2534 }
2535 
2538  MachineBasicBlock *BB) const {
2539  switch (MI.getOpcode()) {
2540  default:
2541  llvm_unreachable("Unknown Custom Instruction!");
2542  case VE::EH_SjLj_LongJmp:
2543  return emitEHSjLjLongJmp(MI, BB);
2544  case VE::EH_SjLj_SetJmp:
2545  return emitEHSjLjSetJmp(MI, BB);
2546  case VE::EH_SjLj_Setup_Dispatch:
2547  return emitSjLjDispatchBlock(MI, BB);
2548  }
2549 }
2550 
2551 static bool isI32Insn(const SDNode *User, const SDNode *N) {
2552  switch (User->getOpcode()) {
2553  default:
2554  return false;
2555  case ISD::ADD:
2556  case ISD::SUB:
2557  case ISD::MUL:
2558  case ISD::SDIV:
2559  case ISD::UDIV:
2560  case ISD::SETCC:
2561  case ISD::SMIN:
2562  case ISD::SMAX:
2563  case ISD::SHL:
2564  case ISD::SRA:
2565  case ISD::BSWAP:
2566  case ISD::SINT_TO_FP:
2567  case ISD::UINT_TO_FP:
2568  case ISD::BR_CC:
2569  case ISD::BITCAST:
2570  case ISD::ATOMIC_CMP_SWAP:
2571  case ISD::ATOMIC_SWAP:
2572  return true;
2573  case ISD::SRL:
2574  if (N->getOperand(0).getOpcode() != ISD::SRL)
2575  return true;
2576  // (srl (trunc (srl ...))) may be optimized by combining srl, so
2577  // doesn't optimize trunc now.
2578  return false;
2579  case ISD::SELECT_CC:
2580  if (User->getOperand(2).getNode() != N &&
2581  User->getOperand(3).getNode() != N)
2582  return true;
2584  case ISD::AND:
2585  case ISD::OR:
2586  case ISD::XOR:
2587  case ISD::SELECT:
2588  case ISD::CopyToReg:
2589  // Check all use of selections, bit operations, and copies. If all of them
2590  // are safe, optimize truncate to extract_subreg.
2591  for (const SDNode *U : User->uses()) {
2592  switch (U->getOpcode()) {
2593  default:
2594  // If the use is an instruction which treats the source operand as i32,
2595  // it is safe to avoid truncate here.
2596  if (isI32Insn(U, N))
2597  continue;
2598  break;
2599  case ISD::ANY_EXTEND:
2600  case ISD::SIGN_EXTEND:
2601  case ISD::ZERO_EXTEND: {
2602  // Special optimizations to the combination of ext and trunc.
2603  // (ext ... (select ... (trunc ...))) is safe to avoid truncate here
2604  // since this truncate instruction clears higher 32 bits which is filled
2605  // by one of ext instructions later.
2606  assert(N->getValueType(0) == MVT::i32 &&
2607  "find truncate to not i32 integer");
2608  if (User->getOpcode() == ISD::SELECT_CC ||
2609  User->getOpcode() == ISD::SELECT)
2610  continue;
2611  break;
2612  }
2613  }
2614  return false;
2615  }
2616  return true;
2617  }
2618 }
2619 
2620 // Optimize TRUNCATE in DAG combining. Optimizing it in CUSTOM lower is
2621 // sometime too early. Optimizing it in DAG pattern matching in VEInstrInfo.td
2622 // is sometime too late. So, doing it at here.
2624  DAGCombinerInfo &DCI) const {
2625  assert(N->getOpcode() == ISD::TRUNCATE &&
2626  "Should be called with a TRUNCATE node");
2627 
2628  SelectionDAG &DAG = DCI.DAG;
2629  SDLoc DL(N);
2630  EVT VT = N->getValueType(0);
2631 
2632  // We prefer to do this when all types are legal.
2633  if (!DCI.isAfterLegalizeDAG())
2634  return SDValue();
2635 
2636  // Skip combine TRUNCATE atm if the operand of TRUNCATE might be a constant.
2637  if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC &&
2638  isa<ConstantSDNode>(N->getOperand(0)->getOperand(0)) &&
2639  isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
2640  return SDValue();
2641 
2642  // Check all use of this TRUNCATE.
2643  for (const SDNode *User : N->uses()) {
2644  // Make sure that we're not going to replace TRUNCATE for non i32
2645  // instructions.
2646  //
2647  // FIXME: Although we could sometimes handle this, and it does occur in
2648  // practice that one of the condition inputs to the select is also one of
2649  // the outputs, we currently can't deal with this.
2650  if (isI32Insn(User, N))
2651  continue;
2652 
2653  return SDValue();
2654  }
2655 
2656  SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
2657  return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT,
2658  N->getOperand(0), SubI32),
2659  0);
2660 }
2661 
2663  DAGCombinerInfo &DCI) const {
2664  switch (N->getOpcode()) {
2665  default:
2666  break;
2667  case ISD::TRUNCATE:
2668  return combineTRUNCATE(N, DCI);
2669  }
2670 
2671  return SDValue();
2672 }
2673 
2674 //===----------------------------------------------------------------------===//
2675 // VE Inline Assembly Support
2676 //===----------------------------------------------------------------------===//
2677 
2680  if (Constraint.size() == 1) {
2681  switch (Constraint[0]) {
2682  default:
2683  break;
2684  case 'v': // vector registers
2685  return C_RegisterClass;
2686  }
2687  }
2688  return TargetLowering::getConstraintType(Constraint);
2689 }
2690 
2691 std::pair<unsigned, const TargetRegisterClass *>
2693  StringRef Constraint,
2694  MVT VT) const {
2695  const TargetRegisterClass *RC = nullptr;
2696  if (Constraint.size() == 1) {
2697  switch (Constraint[0]) {
2698  default:
2699  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2700  case 'r':
2701  RC = &VE::I64RegClass;
2702  break;
2703  case 'v':
2704  RC = &VE::V64RegClass;
2705  break;
2706  }
2707  return std::make_pair(0U, RC);
2708  }
2709 
2710  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2711 }
2712 
2713 //===----------------------------------------------------------------------===//
2714 // VE Target Optimization Support
2715 //===----------------------------------------------------------------------===//
2716 
2718  // Specify 8 for PIC model to relieve the impact of PIC load instructions.
2719  if (isJumpTableRelative())
2720  return 8;
2721 
2723 }
2724 
2726  EVT VT = Y.getValueType();
2727 
2728  // VE doesn't have vector and not instruction.
2729  if (VT.isVector())
2730  return false;
2731 
2732  // VE allows different immediate values for X and Y where ~X & Y.
2733  // Only simm7 works for X, and only mimm works for Y on VE. However, this
2734  // function is used to check whether an immediate value is OK for and-not
2735  // instruction as both X and Y. Generating additional instruction to
2736  // retrieve an immediate value is no good since the purpose of this
2737  // function is to convert a series of 3 instructions to another series of
2738  // 3 instructions with better parallelism. Therefore, we return false
2739  // for all immediate values now.
2740  // FIXME: Change hasAndNot function to have two operands to make it work
2741  // correctly with Aurora VE.
2742  if (isa<ConstantSDNode>(Y))
2743  return false;
2744 
2745  // It's ok for generic registers.
2746  return true;
2747 }
2748 
2750  SelectionDAG &DAG) const {
2751  assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
2752  MVT VT = Op.getOperand(0).getSimpleValueType();
2753 
2754  // Special treatment for packed V64 types.
2755  assert(VT == MVT::v512i32 || VT == MVT::v512f32);
2756  (void)VT;
2757  // Example of codes:
2758  // %packed_v = extractelt %vr, %idx / 2
2759  // %v = %packed_v >> (%idx % 2 * 32)
2760  // %res = %v & 0xffffffff
2761 
2762  SDValue Vec = Op.getOperand(0);
2763  SDValue Idx = Op.getOperand(1);
2764  SDLoc DL(Op);
2765  SDValue Result = Op;
2766  if (false /* Idx->isConstant() */) {
2767  // TODO: optimized implementation using constant values
2768  } else {
2769  SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
2770  SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
2771  SDValue PackedElt =
2772  SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0);
2773  SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
2774  SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
2775  SDValue Const5 = DAG.getConstant(5, DL, MVT::i64);
2776  Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, {Shift, Const5});
2777  PackedElt = DAG.getNode(ISD::SRL, DL, MVT::i64, {PackedElt, Shift});
2778  SDValue Mask = DAG.getConstant(0xFFFFFFFFL, DL, MVT::i64);
2779  PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
2780  SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
2781  Result = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
2782  MVT::i32, PackedElt, SubI32),
2783  0);
2784 
2785  if (Op.getSimpleValueType() == MVT::f32) {
2786  Result = DAG.getBitcast(MVT::f32, Result);
2787  } else {
2788  assert(Op.getSimpleValueType() == MVT::i32);
2789  }
2790  }
2791  return Result;
2792 }
2793 
2795  SelectionDAG &DAG) const {
2796  assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
2797  MVT VT = Op.getOperand(0).getSimpleValueType();
2798 
2799  // Special treatment for packed V64 types.
2800  assert(VT == MVT::v512i32 || VT == MVT::v512f32);
2801  (void)VT;
2802  // The v512i32 and v512f32 starts from upper bits (0..31). This "upper
2803  // bits" required `val << 32` from C implementation's point of view.
2804  //
2805  // Example of codes:
2806  // %packed_elt = extractelt %vr, (%idx >> 1)
2807  // %shift = ((%idx & 1) ^ 1) << 5
2808  // %packed_elt &= 0xffffffff00000000 >> shift
2809  // %packed_elt |= (zext %val) << shift
2810  // %vr = insertelt %vr, %packed_elt, (%idx >> 1)
2811 
2812  SDLoc DL(Op);
2813  SDValue Vec = Op.getOperand(0);
2814  SDValue Val = Op.getOperand(1);
2815  SDValue Idx = Op.getOperand(2);
2816  if (Idx.getSimpleValueType() == MVT::i32)
2817  Idx = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Idx);
2818  if (Val.getSimpleValueType() == MVT::f32)
2819  Val = DAG.getBitcast(MVT::i32, Val);
2821  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
2822 
2823  SDValue Result = Op;
2824  if (false /* Idx->isConstant()*/) {
2825  // TODO: optimized implementation using constant values
2826  } else {
2827  SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
2828  SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
2829  SDValue PackedElt =
2830  SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0);
2831  SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
2832  SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
2833  SDValue Const5 = DAG.getConstant(5, DL, MVT::i64);
2834  Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, {Shift, Const5});
2835  SDValue Mask = DAG.getConstant(0xFFFFFFFF00000000L, DL, MVT::i64);
2836  Mask = DAG.getNode(ISD::SRL, DL, MVT::i64, {Mask, Shift});
2837  PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
2838  Val = DAG.getNode(ISD::SHL, DL, MVT::i64, {Val, Shift});
2839  PackedElt = DAG.getNode(ISD::OR, DL, MVT::i64, {PackedElt, Val});
2840  Result =
2841  SDValue(DAG.getMachineNode(VE::LSVrr_v, DL, Vec.getSimpleValueType(),
2842  {HalfIdx, PackedElt, Vec}),
2843  0);
2844  }
2845  return Result;
2846 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
lowerLoadF128
static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG)
Definition: VEISelLowering.cpp:1303
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
i
i
Definition: README.txt:29
llvm::VETargetLowering::legalizeInternalVectorOp
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:323
VECustomDAG.h
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::LoadSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2334
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
CmpMode::FP
@ FP
llvm::VETargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: VEISelLowering.cpp:2692
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2131
llvm::StoreSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2364
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
llvm::VETargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:979
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:940
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::VETargetLowering::prepareSymbol
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition: VEISelLowering.cpp:1929
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::VETargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: VEISelLowering.cpp:349
llvm::VEISD::REPL_F32
@ REPL_F32
Definition: VEISelLowering.h:50
llvm::VERegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: VERegisterInfo.cpp:60
llvm::VETargetLowering::lowerBUILD_VECTOR
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1687
llvm::VEISD::REPL_I32
@ REPL_I32
Definition: VEISelLowering.h:49
llvm::VETargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2035
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::MachineJumpTableInfo::createJumpTableIndex
unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
createJumpTableIndex - Create a new jump table.
Definition: MachineFunction.cpp:1329
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:205
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:377
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4394
llvm::VEISD::NodeType
NodeType
Definition: VEISelLowering.h:24
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:984
llvm::TargetLowering::CallLoweringInfo::setChain
CallLoweringInfo & setChain(SDValue InChain)
Definition: TargetLowering.h:4028
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:747
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1188
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::VESubtarget::getRsaSize
unsigned getRsaSize() const
Get the size of RSA, return address, and frame pointer as described in VEFrameLowering....
Definition: VESubtarget.h:79
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::VERegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:198
llvm::VEISD::CALL
@ CALL
Definition: VEISelLowering.h:27
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:969
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1181
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1798
llvm::isPackedVectorType
bool isPackedVectorType(EVT SomeVT)
Definition: VECustomDAG.cpp:22
llvm::ISD::MLOAD
@ MLOAD
Definition: ISDOpcodes.h:1198
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::AtomicRMWInst::getOperation
BinOp getOperation() const
Definition: Instructions.h:805
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::TargetLoweringBase::setMinCmpXchgSizeInBits
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition: TargetLowering.h:2464
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1679
llvm::VESubtarget::enableVPU
bool enableVPU() const
Definition: VESubtarget.h:65
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::VETargetLowering::lowerATOMIC_SWAP
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1172
llvm::VEISD::Hi
@ Hi
Definition: VEISelLowering.h:36
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1050
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9055
llvm::VETargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: VEISelLowering.cpp:1855
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
ErrorHandling.h
llvm::isMaskArithmetic
bool isMaskArithmetic(SDValue Op)
Definition: VECustomDAG.cpp:50
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1341
llvm::MachineFunction::getFunctionNumber
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
Definition: MachineFunction.h:615
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1364
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::MVT::v512i32
@ v512i32
Definition: MachineValueType.h:113
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3787
llvm::VEMachineFunctionInfo::getVarArgsFrameOffset
int getVarArgsFrameOffset() const
Definition: VEMachineFunctionInfo.h:39
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2314
llvm::TargetLowering::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
Definition: TargetLowering.h:4047
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::VETargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: VEISelLowering.cpp:1059
llvm::VESubtarget::getRegisterInfo
const VERegisterInfo * getRegisterInfo() const override
Definition: VESubtarget.h:55
Shift
bool Shift
Definition: README.txt:468
MachineJumpTableInfo.h
llvm::CCState::AnalyzeFormalArguments
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Definition: CallingConvLower.cpp:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::VETargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition: VEISelLowering.cpp:2679
Module.h
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2469
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7756
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:841
llvm::VETargetLowering::lowerToTLSGeneralDynamicModel
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1249
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::MachineJumpTableInfo::EK_BlockAddress
@ EK_BlockAddress
EK_BlockAddress - Each entry is a plain address of block, e.g.
Definition: MachineJumpTableInfo.h:49
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:4011
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2432
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9686
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::VETargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: VEISelLowering.cpp:1124
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:1994
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::VETargetLowering::lowerATOMIC_FENCE
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1078
AllPackedVTs
static const MVT AllPackedVTs[]
Definition: VEISelLowering.cpp:81
AllVectorVTs
static const MVT AllVectorVTs[]
Definition: VEISelLowering.cpp:76
llvm::VEISD::GETFUNPLT
@ GETFUNPLT
Definition: VEISelLowering.h:31
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1079
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::MVT::v256i32
@ v256i32
Definition: MachineValueType.h:112
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:33
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
VEISelLowering.h
SelectionDAG.h
llvm::MachineJumpTableInfo::EK_Custom32
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Definition: MachineJumpTableInfo.h:76
llvm::VETargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition: VEISelLowering.cpp:953
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::VEISD::LEGALAVL
@ LEGALAVL
Definition: VEISelLowering.h:55
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::CCState::AnalyzeCallOperands
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
Definition: CallingConvLower.cpp:123
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:459
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1182
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:905
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:994
llvm::ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:141
MachineRegisterInfo.h
llvm::MachineBasicBlock::succ_rbegin
succ_reverse_iterator succ_rbegin()
Definition: MachineBasicBlock.h:345
KnownBits.h
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::VEISD::VEC_UNPACK_LO
@ VEC_UNPACK_LO
Definition: VEISelLowering.h:41
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::VEInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
Definition: VEInstrInfo.cpp:724
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2424
llvm::ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:147
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1278
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1422
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:747
llvm::VETargetLowering::prepareMBB
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition: VEISelLowering.cpp:1880
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:57
llvm::VETargetLowering::VETargetLowering
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition: VEISelLowering.cpp:881
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::VETargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: VEISelLowering.cpp:563
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7706
llvm::MVT::v256f32
@ v256f32
Definition: MachineValueType.h:166
llvm::VEMCExpr::VK_VE_GOT_LO32
@ VK_VE_GOT_LO32
Definition: VEMCExpr.h:33
llvm::VETargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: VEISelLowering.cpp:910
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:632
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3989
llvm::ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:151
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:204
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:154
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::VEISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: VEISelLowering.h:35
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2749
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::VETargetLowering::lowerGlobalAddress
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1233
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2288
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:742
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:68
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::VETargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1567
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
llvm::VEISD::VEC_BROADCAST
@ VEC_BROADCAST
Definition: VEISelLowering.h:47
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::VETargetLowering::splitMaskArithmetic
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:21
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3394
llvm::VETargetLowering::lowerVAARG
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1442
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1066
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::VETargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: VEISelLowering.cpp:855
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::VETargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: VEISelLowering.cpp:423
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3781
llvm::CCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Definition: CallingConvLower.cpp:110
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::Value::uses
iterator_range< use_iterator > uses()
Definition: Value.h:376
llvm::VETargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: VEISelLowering.cpp:2725
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::VEISD::VEC_UNPACK_HI
@ VEC_UNPACK_HI
Definition: VEISelLowering.h:42
llvm::TargetLowering::CallLoweringInfo::setDebugLoc
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
Definition: TargetLowering.h:4023
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1015
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2271
llvm::MVT::v256f64
@ v256f64
Definition: MachineValueType.h:180
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::VECustomDAG::getBroadcast
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
Definition: VECustomDAG.cpp:451
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1180
llvm::StoreSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2365
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:370
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::VEFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: VEFrameLowering.cpp:430
llvm::CallingConv::PreserveAll
@ PreserveAll
Definition: CallingConv.h:70
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1187
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::ISD::FP16_TO_FP
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:896
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::VEMCExpr::VK_VE_LO32
@ VK_VE_LO32
Definition: VEMCExpr.h:29
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::VETargetLowering::emitSjLjDispatchBlock
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: VEISelLowering.cpp:2233
llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1575
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2219
llvm::AtomicRMWInst::Xchg
@ Xchg
*p = v
Definition: Instructions.h:741
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::VEInstrInfo
Definition: VEInstrInfo.h:51
llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1495
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::MemSDNode::isVolatile
bool isVolatile() const
Definition: SelectionDAGNodes.h:1300
isI32Insn
static bool isI32Insn(const SDNode *User, const SDNode *N)
Definition: VEISelLowering.cpp:2551
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VETargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition: VEISelLowering.cpp:1842
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:695
llvm::getAnnotatedNodeAVL
std::pair< SDValue, bool > getAnnotatedNodeAVL(SDValue Op)
Definition: VECustomDAG.cpp:395
llvm::VETargetLowering::lowerBlockAddress
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1238
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(ArrayRef< RTLIB::Libcall > Calls, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3056
llvm::VEISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: VEISelLowering.h:29
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::isPackingSupportOpcode
bool isPackingSupportOpcode(unsigned Opc)
Definition: VECustomDAG.cpp:116
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::VEMCExpr::VK_VE_GOT_HI32
@ VK_VE_GOT_HI32
Definition: VEMCExpr.h:32
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4012
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::APFloat
Definition: APFloat.h:700
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1974
llvm::MachineFunction::push_back
void push_back(MachineBasicBlock *MBB)
Definition: MachineFunction.h:839
llvm::ISD::isVPOpcode
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
Definition: SelectionDAG.cpp:417
getParamCC
CCAssignFn * getParamCC(CallingConv::ID CallConv, bool IsVarArg)
Definition: VEISelLowering.cpp:56
llvm::VETargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1400
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::VETargetLowering::getMinimumJumpTableEntries
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition: VEISelLowering.cpp:2717
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1148
llvm::VEMCExpr::VK_VE_GOTOFF_LO32
@ VK_VE_GOTOFF_LO32
Definition: VEMCExpr.h:35
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1169
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1185
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:6447
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1271
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:959
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1276
llvm::VEISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: VEISelLowering.h:25
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
lowerStoreF128
static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG)
Definition: VEISelLowering.cpp:1365
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:3985
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1572
llvm::MachineBasicBlock::setIsEHPad
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Definition: MachineBasicBlock.h:552
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::TargetLowering::getJumpTableEncoding
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Definition: TargetLowering.cpp:439
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
VEInstrBuilder.h
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:716
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:773
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4006
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2237
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1184
llvm::AtomicOrdering::Unordered
@ Unordered
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:643
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8790
llvm::ISD::FP_TO_FP16
@ FP_TO_FP16
Definition: ISDOpcodes.h:897
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1163
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1178
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4010
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
VERegisterInfo.h
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:441
llvm::VETargetLowering::lowerJumpTable
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1298
llvm::VECustomDAG::getUNDEF
SDValue getUNDEF(EVT VT) const
Definition: VECustomDAG.h:180
llvm::VEMachineFunctionInfo::setVarArgsFrameOffset
void setVarArgsFrameOffset(int Offset)
Definition: VEMachineFunctionInfo.h:40
llvm::VETargetLowering::lowerConstantPool
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1243
llvm::VEISD::MEMBARRIER
@ MEMBARRIER
Definition: VEISelLowering.h:38
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:850
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
llvm::ISD::MSTORE
@ MSTORE
Definition: ISDOpcodes.h:1199
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2342
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3984
IRBuilder.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SelectionDAG::getAtomic
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition: SelectionDAG.cpp:7431
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1623
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::VETargetLowering::lowerGlobalTLSAddress
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1288
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineBasicBlock::succ_rend
succ_reverse_iterator succ_rend()
Definition: MachineBasicBlock.h:349
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:282
llvm::MachineBasicBlock::setHasAddressTaken
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
Definition: MachineBasicBlock.h:224
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::VEFrameLowering
Definition: VEFrameLowering.h:23
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::VETargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1342
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9493
MachineModuleInfo.h
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1273
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2164
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
lowerFRAMEADDR
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition: VEISelLowering.cpp:1582
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::VETargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:990
llvm::MVT::v256i1
@ v256i1
Definition: MachineValueType.h:72
llvm::StoreSDNode::getValue
const SDValue & getValue() const
Definition: SelectionDAGNodes.h:2363
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1080
llvm::VESubtarget::getFrameLowering
const VEFrameLowering * getFrameLowering() const override
Definition: VESubtarget.h:52
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::SelectionDAG::getGlobalAddress
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1646
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:952
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::VETargetLowering::lowerVASTART
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1423
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4014
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4009
llvm::VETargetLowering::getCustomOperationAction
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1713
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:711
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MachineFrameInfo::setHasCalls
void setHasCalls(bool V)
Definition: MachineFrameInfo.h:606
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:548
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
lowerRETURNADDR
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition: VEISelLowering.cpp:1603
llvm::VEISD::GETTLSADDR
@ GETTLSADDR
Definition: VEISelLowering.h:32
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::VETargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2166
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG
bool isAfterLegalizeDAG() const
Definition: TargetLowering.h:3794
llvm::VECustomDAG
Definition: VECustomDAG.h:142
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1179
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:294
llvm::VETargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: VEISelLowering.cpp:947
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
uint32_t
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1133
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VEMachineFunctionInfo
Definition: VEMachineFunctionInfo.h:19
llvm::isVVPOrVEC
bool isVVPOrVEC(unsigned Opcode)
Definition: VECustomDAG.cpp:126
llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1560
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
getReturnCC
CCAssignFn * getReturnCC(CallingConv::ID CallConv)
Definition: VEISelLowering.cpp:47
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5049
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2325
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:182
llvm::CCState::CheckReturn
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Definition: CallingConvLower.cpp:96
llvm::TargetLoweringBase::setMinStackArgumentAlignment
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
Definition: TargetLowering.h:2451
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1275
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:137
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1177
llvm::MVT::v512i1
@ v512i1
Definition: MachineValueType.h:73
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4396
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::INTRINSIC_WO_CHAIN
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:184
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::VETargetMachine
Definition: VETargetMachine.h:22
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:312
llvm::LoadSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2333
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:705
llvm::VEISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: VEISelLowering.h:28
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
llvm::MVT::v256i64
@ v256i64
Definition: MachineValueType.h:126
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::AtomicOrdering::Release
@ Release
llvm::AtomicSDNode
This is an SDNode representing atomic operations.
Definition: SelectionDAGNodes.h:1426
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:906
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4000
llvm::CCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
Definition: CallingConvLower.cpp:159
llvm::VEISD::VEC_PACK
@ VEC_PACK
Definition: VEISelLowering.h:44
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
VEMCExpr.h
llvm::VESubtarget::getInstrInfo
const VEInstrInfo * getInstrInfo() const override
Definition: VESubtarget.h:51
llvm::VETargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: VEISelLowering.cpp:843
llvm::VEISD::RET_FLAG
@ RET_FLAG
Definition: VEISelLowering.h:39
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:149
VEMachineFunctionInfo.h
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::VETargetLowering::setupEntryBlockForSjLj
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition: VEISelLowering.cpp:2017
uint16_t
CallingConvLower.h
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:785
llvm::VEISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: VEISelLowering.h:30
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1272
AllMaskVTs
static const MVT AllMaskVTs[]
Definition: VEISelLowering.cpp:79
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::VETargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1038
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:909
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:528
llvm::TargetLowering::CallLoweringInfo::setDiscardResult
CallLoweringInfo & setDiscardResult(bool Value=true)
Definition: TargetLowering.h:4103
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:908
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:452
llvm::VECustomDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
Definition: VECustomDAG.cpp:404
llvm::ISD::BUILD_VECTOR
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:514
llvm::VERegisterInfo
Definition: VERegisterInfo.h:22
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::VEISD::TS1AM
@ TS1AM
Definition: VEISelLowering.h:40
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size
unsigned size() const
Definition: DenseMap.h:101
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1829
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1274
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
llvm::VEISD::Lo
@ Lo
Definition: VEISelLowering.h:37
llvm::VETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: VEISelLowering.cpp:869
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
StringSwitch.h
llvm::VETargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
JumpTable for VE.
Definition: VEISelLowering.cpp:1833
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:960
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1075
llvm::MVT::v512f32
@ v512f32
Definition: MachineValueType.h:167
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::SDValue::isUndef
bool isUndef() const
Definition: SelectionDAGNodes.h:1161
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:117
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::VETargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: VEISelLowering.cpp:67
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::MemSDNode::getAlign
Align getAlign() const
Definition: SelectionDAGNodes.h:1277
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:222
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2205
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
getUniqueInsertion
static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx)
Definition: VEISelLowering.cpp:1654
llvm::VECustomDAG::getNode
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef< SDValue > OpV, Optional< SDNodeFlags > Flags=None) const
getNode {
Definition: VECustomDAG.h:156
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
llvm::VETargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
Definition: VEISelLowering.cpp:1810
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::VETargetLowering::lowerINSERT_VECTOR_ELT
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:2794
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::VETargetLowering::combineTRUNCATE
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2623
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::VESubtarget
Definition: VESubtarget.h:31
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1248
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Definition: TargetLowering.h:2459
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::MVT::vector_valuetypes
static auto vector_valuetypes()
Definition: MachineValueType.h:1433
finalizeTS1AM
static SDValue finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data, SDValue Bits)
Definition: VEISelLowering.cpp:1158
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2076
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:891
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::StringRef::data
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:149
llvm::TargetLoweringBase::AtomicExpansionKind::None
@ None
llvm::VETargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
Definition: VEISelLowering.cpp:2537
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:4013
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:886
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:649
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2303
DerivedTypes.h
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:4007
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
VETargetMachine.h
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:904
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::VERegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: VERegisterInfo.cpp:48
llvm::VETargetLowering
Definition: VEISelLowering.h:65
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1070
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:371
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::VETargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: VEISelLowering.cpp:1729
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1183
Mod
Module * Mod
Definition: PassBuilderBindings.cpp:54
llvm::MVT::fp_valuetypes
static auto fp_valuetypes()
Definition: MachineValueType.h:1428
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1277
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::VEMCExpr::VK_VE_HI32
@ VK_VE_HI32
Definition: VEMCExpr.h:28
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1279
llvm::VETargetLowering::lowerToVVP
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
Definition: VVPISelLowering.cpp:38
MachineFunction.h
llvm::TargetLoweringBase::AtomicExpansionKind::CmpXChg
@ CmpXChg
llvm::MachineInstrBundleIterator< MachineInstr >
prepareTS1AM
static SDValue prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag, SDValue &Bits)
Definition: VEISelLowering.cpp:1136
llvm::VECC::CC_ILE
@ CC_ILE
Definition: VE.h:48
llvm::isMaskType
bool isMaskType(EVT SomeVT)
Definition: VECustomDAG.cpp:44
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:523
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:131
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1046
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::codegen::getCodeModel
CodeModel::Model getCodeModel()
llvm::VEMCExpr::VK_VE_GOTOFF_HI32
@ VK_VE_GOTOFF_HI32
Definition: VEMCExpr.h:34
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:453
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::VETargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
Definition: VEISelLowering.cpp:2662
llvm::MemSDNode::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: SelectionDAGNodes.h:1347
llvm::CCValAssign::needsCustom
bool needsCustom() const
Definition: CallingConvLower.h:146
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4910
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:354
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::VETargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: VEISelLowering.cpp:539
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1186
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::MachineFrameInfo::getFunctionContextIndex
int getFunctionContextIndex() const
Return the index for the function context object.
Definition: MachineFrameInfo.h:363
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7470
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1168
TARGET_NODE_CASE
#define TARGET_NODE_CASE(NAME)
TargetLoweringObjectFileImpl.h
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393
llvm::LLT
Definition: LowLevelTypeImpl.h:39