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29 #define GET_REGINFO_TARGET_DESC
30 #include "AVRGenRegisterInfo.inc"
40 if (STI.hasTinyEncoding())
42 : CSR_NormalTiny_SaveList;
45 : CSR_Normal_SaveList;
52 return STI.
hasTinyEncoding() ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask;
61 Reserved.
set(AVR::R0);
62 Reserved.
set(AVR::R1);
63 Reserved.
set(AVR::R1R0);
66 Reserved.
set(AVR::SPL);
67 Reserved.
set(AVR::SPH);
68 Reserved.
set(AVR::SP);
76 for (
unsigned Reg = AVR::R3R2;
Reg <= AVR::R18R17;
Reg++)
89 Reserved.
set(AVR::R28);
90 Reserved.
set(AVR::R29);
91 Reserved.
set(AVR::R29R28);
101 return &AVR::DREGSRegClass;
105 return &AVR::GPR8RegClass;
115 int Opcode =
MI.getOpcode();
118 if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
124 if (DstReg !=
MI.getOperand(0).getReg()) {
131 Offset += -
MI.getOperand(2).getImm();
134 Offset +=
MI.getOperand(2).getImm();
140 MI.eraseFromParent();
144 int SPAdj,
unsigned FIOperandNum,
146 assert(SPAdj == 0 &&
"Unexpected SPAdj value");
157 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
163 Offset +=
MI.getOperand(FIOperandNum + 1).getImm();
168 if (
MI.getOpcode() == AVR::FRMIDX) {
169 MI.setDesc(
TII.get(AVR::MOVWRdRr));
170 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28,
false);
173 assert(Offset > 0 &&
"Invalid offset");
178 assert(DstReg != AVR::R29R28 &&
"Dest reg cannot be the frame pointer");
198 if (isUInt<6>(Offset)) {
199 Opcode = AVR::ADIWRdK;
206 Opcode = AVR::SUBIWRdK;
215 New->getOperand(3).setIsDead();
225 unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
226 int AddOffset = Offset - 63 + 1;
229 if ((Offset - 63 + 1) > 63) {
230 AddOpc = AVR::SUBIWRdK;
231 SubOpc = AVR::SUBIWRdK;
232 AddOffset = -AddOffset;
245 New->getOperand(3).setIsDead();
254 BuildMI(
MBB, std::next(II), dl,
TII.get(SubOpc), AVR::R29R28)
261 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28,
false);
262 assert(isUInt<6>(Offset) &&
"Offset is out of range");
263 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
268 if (TFI->
hasFP(MF)) {
278 unsigned Kind)
const {
282 return &AVR::PTRDISPREGSRegClass;
289 LoReg = getSubReg(
Reg, AVR::sub_lo);
290 HiReg = getSubReg(
Reg, AVR::sub_hi);
297 if (this->
getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Information about stack frame layout on the target.
bool hasTinyEncoding() const
return AArch64::GPR64RegClass contains(Reg)
A generic AVR implementation.
Reg
All possible values of the reg field in the ModR/M byte.
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
TargetInstrInfo - Interface to description of machine instruction set.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
A specific AVR target MCU.
@ Kill
The last use of a register.
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Register getFrameRegister(const MachineFunction &MF) const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
BitVector getReservedRegs(const MachineFunction &MF) const override
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, Register DstReg)
Fold a frame offset shared between two add instructions into a single one.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getIORegSREG(void) const
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Wrapper class representing virtual and physical registers.
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
virtual const TargetFrameLowering * getFrameLowering() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
void splitReg(Register Reg, Register &LoReg, Register &HiReg) const
Splits a 16-bit DREGS register into the lo/hi register pair.
bool isInterruptOrSignalHandler() const
Checks if the function is some form of interrupt service routine.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Contains AVR-specific information for each MachineFunction.
const char LLVMTargetMachineRef TM
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override