LLVM  14.0.0git
AVRRegisterInfo.cpp
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1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRRegisterInfo.h"
14 
15 #include "llvm/ADT/BitVector.h"
21 #include "llvm/IR/Function.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRMachineFunctionInfo.h"
26 #include "AVRTargetMachine.h"
28 
29 #define GET_REGINFO_TARGET_DESC
30 #include "AVRGenRegisterInfo.inc"
31 
32 namespace llvm {
33 
35 
36 const uint16_t *
39 
40  return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList
41  : CSR_Normal_SaveList;
42 }
43 
44 const uint32_t *
46  CallingConv::ID CC) const {
47  return CSR_Normal_RegMask;
48 }
49 
51  BitVector Reserved(getNumRegs());
52 
53  // Reserve the intermediate result registers r1 and r2
54  // The result of instructions like 'mul' is always stored here.
55  Reserved.set(AVR::R0);
56  Reserved.set(AVR::R1);
57  Reserved.set(AVR::R1R0);
58 
59  // Reserve the stack pointer.
60  Reserved.set(AVR::SPL);
61  Reserved.set(AVR::SPH);
62  Reserved.set(AVR::SP);
63 
64  // We tenatively reserve the frame pointer register r29:r28 because the
65  // function may require one, but we cannot tell until register allocation
66  // is complete, which can be too late.
67  //
68  // Instead we just unconditionally reserve the Y register.
69  //
70  // TODO: Write a pass to enumerate functions which reserved the Y register
71  // but didn't end up needing a frame pointer. In these, we can
72  // convert one or two of the spills inside to use the Y register.
73  Reserved.set(AVR::R28);
74  Reserved.set(AVR::R29);
75  Reserved.set(AVR::R29R28);
76 
77  return Reserved;
78 }
79 
80 const TargetRegisterClass *
82  const MachineFunction &MF) const {
84  if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
85  return &AVR::DREGSRegClass;
86  }
87 
88  if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
89  return &AVR::GPR8RegClass;
90  }
91 
92  llvm_unreachable("Invalid register size");
93 }
94 
95 /// Fold a frame offset shared between two add instructions into a single one.
97  Register DstReg) {
98  MachineInstr &MI = *II;
99  int Opcode = MI.getOpcode();
100 
101  // Don't bother trying if the next instruction is not an add or a sub.
102  if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
103  return;
104  }
105 
106  // Check that DstReg matches with next instruction, otherwise the instruction
107  // is not related to stack address manipulation.
108  if (DstReg != MI.getOperand(0).getReg()) {
109  return;
110  }
111 
112  // Add the offset in the next instruction to our offset.
113  switch (Opcode) {
114  case AVR::SUBIWRdK:
115  Offset += -MI.getOperand(2).getImm();
116  break;
117  case AVR::ADIWRdK:
118  Offset += MI.getOperand(2).getImm();
119  break;
120  }
121 
122  // Finally remove the instruction.
123  II++;
124  MI.eraseFromParent();
125 }
126 
128  int SPAdj, unsigned FIOperandNum,
129  RegScavenger *RS) const {
130  assert(SPAdj == 0 && "Unexpected SPAdj value");
131 
132  MachineInstr &MI = *II;
133  DebugLoc dl = MI.getDebugLoc();
134  MachineBasicBlock &MBB = *MI.getParent();
135  const MachineFunction &MF = *MBB.getParent();
136  const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
137  const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
138  const MachineFrameInfo &MFI = MF.getFrameInfo();
139  const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
140  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
141  int Offset = MFI.getObjectOffset(FrameIndex);
142 
143  // Add one to the offset because SP points to an empty slot.
144  Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
145  // Fold incoming offset.
146  Offset += MI.getOperand(FIOperandNum + 1).getImm();
147 
148  // This is actually "load effective address" of the stack slot
149  // instruction. We have only two-address instructions, thus we need to
150  // expand it into move + add.
151  if (MI.getOpcode() == AVR::FRMIDX) {
152  MI.setDesc(TII.get(AVR::MOVWRdRr));
153  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
154  MI.RemoveOperand(2);
155 
156  assert(Offset > 0 && "Invalid offset");
157 
158  // We need to materialize the offset via an add instruction.
159  unsigned Opcode;
160  Register DstReg = MI.getOperand(0).getReg();
161  assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
162 
163  II++; // Skip over the FRMIDX (and now MOVW) instruction.
164 
165  // Generally, to load a frame address two add instructions are emitted that
166  // could get folded into a single one:
167  // movw r31:r30, r29:r28
168  // adiw r31:r30, 29
169  // adiw r31:r30, 16
170  // to:
171  // movw r31:r30, r29:r28
172  // adiw r31:r30, 45
173  if (II != MBB.end())
174  foldFrameOffset(II, Offset, DstReg);
175 
176  // Select the best opcode based on DstReg and the offset size.
177  switch (DstReg) {
178  case AVR::R25R24:
179  case AVR::R27R26:
180  case AVR::R31R30: {
181  if (isUInt<6>(Offset)) {
182  Opcode = AVR::ADIWRdK;
183  break;
184  }
186  }
187  default: {
188  // This opcode will get expanded into a pair of subi/sbci.
189  Opcode = AVR::SUBIWRdK;
190  Offset = -Offset;
191  break;
192  }
193  }
194 
195  MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
196  .addReg(DstReg, RegState::Kill)
197  .addImm(Offset);
198  New->getOperand(3).setIsDead();
199 
200  return;
201  }
202 
203  // If the offset is too big we have to adjust and restore the frame pointer
204  // to materialize a valid load/store with displacement.
205  //: TODO: consider using only one adiw/sbiw chain for more than one frame
206  //: index
207  if (Offset > 62) {
208  unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
209  int AddOffset = Offset - 63 + 1;
210 
211  // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
212  if ((Offset - 63 + 1) > 63) {
213  AddOpc = AVR::SUBIWRdK;
214  SubOpc = AVR::SUBIWRdK;
215  AddOffset = -AddOffset;
216  }
217 
218  // It is possible that the spiller places this frame instruction in between
219  // a compare and branch, invalidating the contents of SREG set by the
220  // compare instruction because of the add/sub pairs. Conservatively save and
221  // restore SREG before and after each add/sub pair.
222  BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
223 
224  MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
225  .addReg(AVR::R29R28, RegState::Kill)
226  .addImm(AddOffset);
227  New->getOperand(3).setIsDead();
228 
229  // Restore SREG.
230  BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
231  .addImm(0x3f)
232  .addReg(AVR::R0, RegState::Kill);
233 
234  // No need to set SREG as dead here otherwise if the next instruction is a
235  // cond branch it will be using a dead register.
236  BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
237  .addReg(AVR::R29R28, RegState::Kill)
238  .addImm(Offset - 63 + 1);
239 
240  Offset = 62;
241  }
242 
243  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
244  assert(isUInt<6>(Offset) && "Offset is out of range");
245  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
246 }
247 
250  if (TFI->hasFP(MF)) {
251  // The Y pointer register
252  return AVR::R28;
253  }
254 
255  return AVR::SP;
256 }
257 
258 const TargetRegisterClass *
260  unsigned Kind) const {
261  // FIXME: Currently we're using avr-gcc as reference, so we restrict
262  // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
263  // of memory constraint, so we can fix it and bit avr-gcc here ;-)
264  return &AVR::PTRDISPREGSRegClass;
265 }
266 
268  Register &HiReg) const {
269  assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
270 
271  LoReg = getSubReg(Reg, AVR::sub_lo);
272  HiReg = getSubReg(Reg, AVR::sub_hi);
273 }
274 
276  MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
277  const TargetRegisterClass *DstRC, unsigned DstSubReg,
278  const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
279  if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
280  return false;
281  }
282 
283  return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
284  NewRC, LIS);
285 }
286 
287 } // end of namespace llvm
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AVRRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: AVRRegisterInfo.cpp:275
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
MachineRegisterInfo.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::AVRRegisterInfo::AVRRegisterInfo
AVRRegisterInfo()
Definition: AVRRegisterInfo.cpp:34
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
llvm::AVRRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: AVRRegisterInfo.cpp:248
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::BitVector
Definition: BitVector.h:74
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::AVRRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: AVRRegisterInfo.cpp:50
AVRGenRegisterInfo
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegScavenger
Definition: RegisterScavenging.h:34
AVRTargetMachine.h
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AVRRegisterInfo::getCalleeSavedRegs
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=nullptr) const override
Definition: AVRRegisterInfo.cpp:37
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
AVRMCTargetDesc.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::foldFrameOffset
static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, Register DstReg)
Fold a frame offset shared between two add instructions into a single one.
Definition: AVRRegisterInfo.cpp:96
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AVRRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: AVRRegisterInfo.cpp:45
AVRRegisterInfo.h
llvm::TargetRegisterInfo::shouldCoalesce
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition: TargetRegisterInfo.h:1025
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
AVRMachineFunctionInfo.h
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
MachineFrameInfo.h
Function.h
llvm::AVRRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: AVRRegisterInfo.cpp:81
llvm::AVRRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
Definition: AVRRegisterInfo.cpp:127
llvm::AVRRegisterInfo::splitReg
void splitReg(Register Reg, Register &LoReg, Register &HiReg) const
Splits a 16-bit DREGS register into the lo/hi register pair.
Definition: AVRRegisterInfo.cpp:267
getRegClass
static int getRegClass(RegisterKind Is, unsigned RegWidth)
Definition: AMDGPUAsmParser.cpp:2207
llvm::LiveIntervals
Definition: LiveIntervals.h:54
AVR.h
llvm::AVRMachineFunctionInfo::isInterruptOrSignalHandler
bool isInterruptOrSignalHandler() const
Checks if the function is some form of interrupt service routine.
Definition: AVRMachineFunctionInfo.h:74
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::AVRMachineFunctionInfo
Contains AVR-specific information for each MachineFunction.
Definition: AVRMachineFunctionInfo.h:21
AVRInstrInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AVRRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: AVRRegisterInfo.cpp:259