LLVM 22.0.0git
Macros | Enumerations | Functions | Variables
AArch64InstrInfo.cpp File Reference
#include "AArch64InstrInfo.h"
#include "AArch64ExpandImm.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PointerAuth.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/CFIInstBuilder.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"

Go to the source code of this file.

Macros

#define GET_INSTRINFO_CTOR_DTOR
#define DEBUG_TYPE   "AArch64InstrInfo"
#define GET_INSTRINFO_HELPERS
#define GET_INSTRMAP_INFO

Enumerations

enum  AccessKind { AK_Write = 0x01 , AK_Read = 0x10 , AK_All = 0x11 }
enum class  FMAInstKind { Default , Indexed , Accumulator }
enum  MachineOutlinerClass {
  MachineOutlinerDefault , MachineOutlinerTailCall , MachineOutlinerNoLRSave , MachineOutlinerThunk ,
  MachineOutlinerRegSave
}
 Constants defining how certain sequences should be outlined. More...
enum  MachineOutlinerMBBFlags { LRUnavailableSomewhere = 0x2 , HasCalls = 0x4 , UnsafeRegsDead = 0x8 }

Functions

 STATISTIC (NumCopyInstrs, "Number of COPY instructions expanded")
 STATISTIC (NumZCRegMoveInstrsGPR, "Number of zero-cycle GPR register move " "instructions expanded from canonical COPY")
 STATISTIC (NumZCRegMoveInstrsFPR, "Number of zero-cycle FPR register move " "instructions expanded from canonical COPY")
 STATISTIC (NumZCZeroingInstrsGPR, "Number of zero-cycle GPR zeroing " "instructions expanded from canonical COPY")
static void parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned getBranchDisplacementBits (unsigned Opc)
static unsigned removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
static unsigned canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewReg=nullptr)
static bool isCheapImmediate (const MachineInstr &MI, unsigned BitSize)
static bool isCheapCopy (const MachineInstr &MI, const AArch64RegisterInfo &RI)
static bool UpdateOperandRegClass (MachineInstr &Instr)
static unsigned convertToNonFlagSettingOpc (const MachineInstr &MI)
 Return the opcode that does not set flags when possible - otherwise return the original opcode.
static bool areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
 True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.
static unsigned sForm (MachineInstr &Instr)
 Get opcode of S version of Instr.
static bool areCFlagsAliveInSuccessors (const MachineBasicBlock *MBB)
 Check if AArch64::NZCV should be alive in successors of MBB.
static int findCondCodeUseOperandIdxForBranchOrSelect (const MachineInstr &Instr)
static AArch64CC::CondCode findCondCodeUsedByInstr (const MachineInstr &Instr)
 Find a condition code used by the instruction.
static UsedNZCV getUsedNZCV (AArch64CC::CondCode CC)
static bool isADDSRegImm (unsigned Opcode)
static bool isSUBSRegImm (unsigned Opcode)
static bool isANDOpcode (MachineInstr &MI)
static bool canInstrSubstituteCmpInstr (MachineInstr &MI, MachineInstr &CmpInstr, const TargetRegisterInfo &TRI)
 Check if CmpInstr can be substituted by MI.
static bool canCmpInstrBeRemoved (MachineInstr &MI, MachineInstr &CmpInstr, int CmpValue, const TargetRegisterInfo &TRI, SmallVectorImpl< MachineInstr * > &CCUseInstrs, bool &IsInvertCC)
static bool isFrameLoadOpcode (int Opcode)
static bool isFrameStoreOpcode (int Opcode)
static unsigned regOffsetOpcode (unsigned Opcode)
unsigned scaledOffsetOpcode (unsigned Opcode, unsigned &Scale)
unsigned unscaledOffsetOpcode (unsigned Opcode)
static unsigned offsetExtendOpcode (unsigned Opcode)
static bool isPostIndexLdStOpcode (unsigned Opcode)
 Return true if the opcode is a post-index ld/st instruction, which really loads from base+0.
static const TargetRegisterClass * getRegClass (const MachineInstr &MI, Register Reg)
static bool scaleOffset (unsigned Opc, int64_t &Offset)
static bool canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
static bool shouldClusterFI (const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2)
static const MachineInstrBuilder & AddSubReg (const MachineInstrBuilder &MIB, MCRegister Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
static bool forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static bool isInStreamingCallSiteRegion (MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
 Returns true if the instruction at I is in a streaming call site region, within a single basic block.
static bool mustAvoidNeonAtMBBI (const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
 Returns true if in a streaming call site region without SME-FA64.
static void storeRegPairToStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void loadRegPairFromStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, Register DestReg, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void appendConstantExpr (SmallVectorImpl< char > &Expr, int64_t Constant, dwarf::LocationAtom Operation)
static void appendReadRegExpr (SmallVectorImpl< char > &Expr, unsigned RegNum)
static void appendLoadRegExpr (SmallVectorImpl< char > &Expr, int64_t OffsetFromDefCFA)
static void appendOffsetComment (int NumBytes, llvm::raw_string_ostream &Comment, StringRef RegScale={})
static MCCFIInstruction createDefCFAExpression (const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
static void emitFrameOffsetAdj (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int64_t Offset, unsigned Opc, const TargetInstrInfo *TII, MachineInstr::MIFlag Flag, bool NeedsWinCFI, bool *HasWinCFI, bool EmitCFAOffset, StackOffset CFAOffset, unsigned FrameReg)
static bool isCombineInstrSettingFlag (unsigned Opc)
static bool isCombineInstrCandidate32 (unsigned Opc)
static bool isCombineInstrCandidate64 (unsigned Opc)
static bool isCombineInstrCandidateFP (const MachineInstr &Inst)
static bool isCombineInstrCandidate (unsigned Opc)
static bool canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
static bool canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
static bool canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
static bool getMaddPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
 Find instructions that can be turned into madd.
static bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
 Floating-Point Support.
static bool getFMULPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static bool getFNEGPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
static bool getMiscPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
 Find other MI combine patterns.
static bool getGatherLanePattern (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, unsigned LoadLaneOpCode, unsigned NumLanes)
 Check if the given instruction forms a gather load pattern that can be optimized for better Memory-Level Parallelism (MLP).
static bool getLoadPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns)
 Search for patterns of LD instructions we can optimize.
static void generateGatherLanePattern (MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned Pattern, unsigned NumLanes)
 Generate optimized instruction sequence for gather load patterns to improve Memory-Level Parallelism (MLP).
static MachineInstr * genFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default, const Register *ReplacedAddend=nullptr)
 genFusedMultiply - Generate fused multiply instructions.
static MachineInstr * genFNegatedMAD (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs)
static MachineInstr * genIndexedMultiply (MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxDupOp, unsigned MulOpc, const TargetRegisterClass *RC, MachineRegisterInfo &MRI)
 Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)
static MachineInstr * genFusedMultiplyAcc (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
 genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.
static Register genNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned MnegOpc, const TargetRegisterClass *RC)
 genNeg - Helper to generate an intermediate negation of the second operand of Root
static MachineInstr * genFusedMultiplyAccNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
 genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr * genFusedMultiplyIdx (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC)
 genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.
static MachineInstr * genFusedMultiplyIdxNeg (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg, unsigned IdxMulOpd, unsigned MaddOpc, unsigned MnegOpc, const TargetRegisterClass *RC)
 genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator
static MachineInstr * genMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
 genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V
static void genSubAdd2SubSub (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, unsigned IdxOpd1, DenseMap< Register, unsigned > &InstrIdxForVirtReg)
 Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.
static bool outliningCandidatesSigningScopeConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool outliningCandidatesSigningKeyConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static bool outliningCandidatesV8_3OpsConsensus (const outliner::Candidate &a, const outliner::Candidate &b)
static void signOutlinedFunction (MachineFunction &MF, MachineBasicBlock &MBB, const AArch64InstrInfo *TII, bool ShouldSignReturnAddr)
static std::optional< ParamLoadedValue > describeORRLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then, if possible, describe the value in terms of the source register.
static Register cloneInstr (const MachineInstr *MI, unsigned ReplaceOprNum, Register ReplaceReg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertTo)
 Clone an instruction from MI.
static void extractPhiReg (const MachineInstr &Phi, const MachineBasicBlock *MBB, Register &RegMBB, Register &RegOther)
static bool isDefinedOutside (Register Reg, const MachineBasicBlock *BB)
static bool getIndVarInfo (Register Reg, const MachineBasicBlock *LoopBB, MachineInstr *&UpdateInst, unsigned &UpdateCounterOprNum, Register &InitReg, bool &IsUpdatePriorComp)
 If Reg is an induction variable, return true and set some parameters.

Variables

static cl::opt< unsigned > CBDisplacementBits ("aarch64-cb-offset-bits", cl::Hidden, cl::init(9), cl::desc("Restrict range of CB instructions (DEBUG)"))
static cl::opt< unsigned > TBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned > CBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned > BCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
static cl::opt< unsigned > BDisplacementBits ("aarch64-b-offset-bits", cl::Hidden, cl::init(26), cl::desc("Restrict range of B instructions (DEBUG)"))
static cl::opt< unsigned > GatherOptSearchLimit ("aarch64-search-limit", cl::Hidden, cl::init(2048), cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization"))

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "AArch64InstrInfo"

Definition at line 69 of file AArch64InstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 66 of file AArch64InstrInfo.cpp.

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 11755 of file AArch64InstrInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 11756 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

◆ AccessKind

enum AccessKind
Enumerator
AK_Write 
AK_Read 
AK_All 

Definition at line 1669 of file AArch64InstrInfo.cpp.

◆ FMAInstKind

enum class FMAInstKind
strong
Enumerator
Default 
Indexed 
Accumulator 

Definition at line 8292 of file AArch64InstrInfo.cpp.

◆ MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

  • Call construction overhead: 3 (save + BL + restore)
  • Frame construction overhead: 1 (ret)
  • Requires stack fixups? Yes

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 --> B OUTLINED_FUNCTION I1 RET I2 RET

  • Call construction overhead: 1 (B)
  • Frame construction overhead: 0 (Return included in sequence)
  • Requires stack fixups? No

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 I2 I3 RET

  • Call construction overhead: 1 (BL)
  • Frame construction overhead: 1 (RET)
  • Requires stack fixups? No

MachineOutlinerThunk implies that the function is being created from a sequence of instructions ending in a call. The outlined function is called with a BL instruction, and the outlined function tail-calls the original call destination.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 BL f I2 B f

  • Call construction overhead: 1 (BL)
  • Frame construction overhead: 0
  • Requires stack fixups? No

MachineOutlinerRegSave implies that the function should be called with a save and restore of LR to an available register. This allows us to avoid stack fixups. Note that this outlining variant is compatible with the NoLRSave case.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

  • Call construction overhead: 3 (save + BL + restore)
  • Frame construction overhead: 1 (ret)
  • Requires stack fixups? No
Enumerator
MachineOutlinerDefault 
MachineOutlinerTailCall 

Emit a save, restore, call, and return.

MachineOutlinerNoLRSave 

Only emit a branch.

MachineOutlinerThunk 

Emit a call and return.

MachineOutlinerRegSave 

Emit a call and tail-call.

Same as default, but save to a register.

Definition at line 9879 of file AArch64InstrInfo.cpp.

◆ MachineOutlinerMBBFlags

enum MachineOutlinerMBBFlags
Enumerator
LRUnavailableSomewhere 
HasCalls 
UnsafeRegsDead 

Definition at line 9887 of file AArch64InstrInfo.cpp.

Function Documentation

◆ AddSubReg()

const MachineInstrBuilder & AddSubReg ( const MachineInstrBuilder & MIB,
MCRegister Reg,
unsigned SubIdx,
unsigned State,
const TargetRegisterInfo * TRI )
static

Definition at line 5321 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), Reg, and TRI.

Referenced by llvm::AArch64InstrInfo::copyGPRRegTuple(), and llvm::AArch64InstrInfo::copyPhysRegTuple().

◆ appendConstantExpr()

void appendConstantExpr ( SmallVectorImpl< char > & Expr,
int64_t Constant,
dwarf::LocationAtom Operation )
static

Definition at line 6368 of file AArch64InstrInfo.cpp.

References llvm::appendLEB128(), Operation, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by appendLoadRegExpr(), llvm::createCFAOffset(), and createDefCFAExpression().

◆ appendLoadRegExpr()

void appendLoadRegExpr ( SmallVectorImpl< char > & Expr,
int64_t OffsetFromDefCFA )
static

Definition at line 6394 of file AArch64InstrInfo.cpp.

References appendConstantExpr(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::createCFAOffset().

◆ appendOffsetComment()

void appendOffsetComment ( int NumBytes,
llvm::raw_string_ostream & Comment,
StringRef RegScale = {} )
static

Definition at line 6406 of file AArch64InstrInfo.cpp.

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

◆ appendReadRegExpr()

void appendReadRegExpr ( SmallVectorImpl< char > & Expr,
unsigned RegNum )
static

Definition at line 6386 of file AArch64InstrInfo.cpp.

References llvm::appendLEB128(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::createCFAOffset(), and createDefCFAExpression().

◆ areCFlagsAccessedBetweenInstrs()

bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock::iterator From,
MachineBasicBlock::iterator To,
const TargetRegisterInfo * TRI,
const AccessKind AccessToCheck = AK_All )
static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 1676 of file AArch64InstrInfo.cpp.

References AK_All, AK_Read, AK_Write, assert(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::instructionsWithoutDebug(), MI, and TRI.

Referenced by canCmpInstrBeRemoved(), canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

◆ areCFlagsAliveInSuccessors()

bool areCFlagsAliveInSuccessors ( const MachineBasicBlock * MBB)
static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 2040 of file AArch64InstrInfo.cpp.

References MBB.

Referenced by llvm::examineCFlagsUse().

◆ canCmpInstrBeRemoved()

bool canCmpInstrBeRemoved ( MachineInstr & MI,
MachineInstr & CmpInstr,
int CmpValue,
const TargetRegisterInfo & TRI,
SmallVectorImpl< MachineInstr * > & CCUseInstrs,
bool & IsInvertCC )
static
Returns
True if CmpInstr can be removed.

IsInvertCC is true if, after removing CmpInstr, condition codes used in CCUseInstrs must be inverted.

Definition at line 2274 of file AArch64InstrInfo.cpp.

References AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::UsedNZCV::C, llvm::AArch64CC::EQ, llvm::examineCFlagsUse(), findCondCodeUsedByInstr(), llvm::MachineInstr::getOpcode(), getUsedNZCV(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), MI, llvm::UsedNZCV::N, llvm::AArch64CC::NE, llvm::AArch64CC::PL, TRI, llvm::UsedNZCV::V, and llvm::UsedNZCV::Z.

◆ canCombine()

bool canCombine ( MachineBasicBlock & MBB,
MachineOperand & MO,
unsigned CombineOpc,
unsigned ZeroReg = 0,
bool CheckZeroReg = false )
static

Definition at line 7141 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, and MRI.

◆ canCombineWithFMUL()

bool canCombineWithFMUL ( MachineBasicBlock & MBB,
MachineOperand & MO,
unsigned MulOpc )
static

Definition at line 7181 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getFMAPatterns().

◆ canCombineWithMUL()

bool canCombineWithMUL ( MachineBasicBlock & MBB,
MachineOperand & MO,
unsigned MulOpc,
unsigned ZeroReg )
static

Definition at line 7174 of file AArch64InstrInfo.cpp.

References canCombine(), and MBB.

Referenced by getMaddPatterns().

◆ canFoldIntoCSel()

unsigned canFoldIntoCSel ( const MachineRegisterInfo & MRI,
unsigned VReg,
unsigned * NewReg = nullptr )
static

Definition at line 784 of file AArch64InstrInfo.cpp.

References assert(), DefMI, llvm::Register::isVirtualRegister(), MRI, Opc, and removeCopies().

Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().

◆ canInstrSubstituteCmpInstr()

bool canInstrSubstituteCmpInstr ( MachineInstr & MI,
MachineInstr & CmpInstr,
const TargetRegisterInfo & TRI )
static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

  • CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
  • and, MI and CmpInstr are from the same MachineBB
  • and, condition flags are not alive in successors of the CmpInstr parent
  • and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
  • and, if C/V flags are not used after CmpInstr or if N flag is used but MI produces poison value if signed overflow occurs.

Definition at line 2205 of file AArch64InstrInfo.cpp.

References AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::examineCFlagsUse(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isADDSRegImm(), isANDOpcode(), llvm::MachineOperand::isImm(), isSUBSRegImm(), MI, llvm::MachineInstr::NoSWrap, sForm(), and TRI.

◆ canPairLdStOpc()

bool canPairLdStOpc ( unsigned FirstOpc,
unsigned SecondOpc )
static

Definition at line 5178 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ cloneInstr()

Register cloneInstr ( const MachineInstr * MI,
unsigned ReplaceOprNum,
Register ReplaceReg,
MachineBasicBlock & MBB,
MachineBasicBlock::iterator InsertTo )
static

Clone an instruction from MI.

The register of ReplaceOprNum-th operand is replaced by ReplaceReg. The output register is newly created. The other operands are unchanged from MI.

Definition at line 11377 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::Register::isVirtual(), MBB, MI, MRI, llvm::MachineOperand::setReg(), and TII.

◆ convertToNonFlagSettingOpc()

unsigned convertToNonFlagSettingOpc ( const MachineInstr & MI)
static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 1623 of file AArch64InstrInfo.cpp.

References MI.

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

◆ createDefCFAExpression()

MCCFIInstruction createDefCFAExpression ( const TargetRegisterInfo & TRI,
unsigned Reg,
const StackOffset & Offset )
static

Definition at line 6417 of file AArch64InstrInfo.cpp.

References llvm::SmallString< InternalLen >::append(), appendConstantExpr(), llvm::appendLEB128(), appendOffsetComment(), appendReadRegExpr(), assert(), llvm::MCCFIInstruction::createEscape(), llvm::Offset, llvm::printReg(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::SmallString< InternalLen >::str(), and TRI.

Referenced by llvm::createDefCFA(), and llvm::RISCVFrameLowering::emitPrologue().

◆ describeORRLoadedValue()

std::optional< ParamLoadedValue > describeORRLoadedValue ( const MachineInstr & MI,
Register DescribedReg,
const TargetInstrInfo * TII,
const TargetRegisterInfo * TRI )
static

If the given ORR instruction is a copy, and DescribedReg overlaps with the destination register then, if possible, describe the value in terms of the source register.

Definition at line 11038 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateReg(), llvm::MDNode::get(), llvm::Register::isValid(), MI, TII, and TRI.

◆ emitFrameOffsetAdj()

void emitFrameOffsetAdj ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc & DL,
unsigned DestReg,
unsigned SrcReg,
int64_t Offset,
unsigned Opc,
const TargetInstrInfo * TII,
MachineInstr::MIFlag Flag,
bool NeedsWinCFI,
bool * HasWinCFI,
bool EmitCFAOffset,
StackOffset CFAOffset,
unsigned FrameReg )
static

Definition at line 6525 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::createDefCFA(), DL, llvm::StackOffset::getFixed(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::StackOffset::getScalable(), llvm::AArch64_AM::getShifterImm(), llvm::MachineFunction::getSubtarget(), llvm_unreachable, llvm::AArch64_AM::LSL, MBB, MBBI, llvm::Offset, Opc, llvm::MachineInstrBuilder::setMIFlag(), llvm::MachineInstrBuilder::setMIFlags(), TII, and TRI.

Referenced by llvm::emitFrameOffset().

◆ extractPhiReg()

void extractPhiReg ( const MachineInstr & Phi,
const MachineBasicBlock * MBB,
Register & RegMBB,
Register & RegOther )
static

Definition at line 11502 of file AArch64InstrInfo.cpp.

References assert(), and MBB.

Referenced by getIndVarInfo().

◆ findCondCodeUsedByInstr()

AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr & Instr)
static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 2081 of file AArch64InstrInfo.cpp.

References findCondCodeUseOperandIdxForBranchOrSelect(), llvm::getImm(), and llvm::AArch64CC::Invalid.

Referenced by canCmpInstrBeRemoved(), and llvm::examineCFlagsUse().

◆ findCondCodeUseOperandIdxForBranchOrSelect()

int findCondCodeUseOperandIdxForBranchOrSelect ( const MachineInstr & Instr)
static
Returns
The condition code operand index for Instr if it is a branch or select and -1 otherwise.

Definition at line 2050 of file AArch64InstrInfo.cpp.

References assert().

Referenced by findCondCodeUsedByInstr().

◆ forwardCopyWillClobberTuple()

bool forwardCopyWillClobberTuple ( unsigned DestReg,
unsigned SrcReg,
unsigned NumRegs )
static

Definition at line 5333 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple(), and llvm::RISCVInstrInfo::copyPhysRegVector().

◆ generateGatherLanePattern()

void generateGatherLanePattern ( MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
SmallVectorImpl< MachineInstr * > & DelInstrs,
DenseMap< Register, unsigned > & InstrIdxForVirtReg,
unsigned Pattern,
unsigned NumLanes )
static

Generate optimized instruction sequence for gather load patterns to improve Memory-Level Parallelism (MLP).

This function transforms a chain of sequential NEON lane loads into parallel vector loads that can execute concurrently.

Definition at line 8083 of file AArch64InstrInfo.cpp.

References A(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), B(), llvm::BuildMI(), llvm::enumerate(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm_unreachable, llvm::make_range(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::sort(), and TII.

◆ genFNegatedMAD()

MachineInstr * genFNegatedMAD ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs )
static

Definition at line 8374 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), MRI, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ genFusedMultiply()

MachineInstr * genFusedMultiply ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
unsigned IdxMulOpd,
unsigned MaddOpc,
const TargetRegisterClass * RC,
FMAInstKind kind = FMAInstKind::Default,
const Register * ReplacedAddend = nullptr )
static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters
MFContaining MachineFunction
MRIRegister information
TIITarget information
Rootis the F|ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the f|madd instruction
RCRegister class of operands
kindof fma instruction (addressing mode) to be generated
ReplacedAddendis the result register from the instruction replacing the non-combined operand, if any.

Definition at line 8313 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Default, llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), Indexed, llvm::MachineOperand::isKill(), llvm::Register::isVirtual(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by genFusedMultiplyAcc(), genFusedMultiplyAccNeg(), genFusedMultiplyIdx(), and genFusedMultiplyIdxNeg().

◆ genFusedMultiplyAcc()

MachineInstr * genFusedMultiplyAcc ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
unsigned IdxMulOpd,
unsigned MaddOpc,
const TargetRegisterClass * RC )
static

genFusedMultiplyAcc - Helper to generate fused multiply accumulate instructions.

See also
genFusedMultiply

Definition at line 8457 of file AArch64InstrInfo.cpp.

References Accumulator, genFusedMultiply(), MRI, and TII.

◆ genFusedMultiplyAccNeg()

MachineInstr * genFusedMultiplyAccNeg ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
DenseMap< Register, unsigned > & InstrIdxForVirtReg,
unsigned IdxMulOpd,
unsigned MaddOpc,
unsigned MnegOpc,
const TargetRegisterClass * RC )
static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 8486 of file AArch64InstrInfo.cpp.

References Accumulator, assert(), genFusedMultiply(), genNeg(), MRI, and TII.

◆ genFusedMultiplyIdx()

MachineInstr * genFusedMultiplyIdx ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
unsigned IdxMulOpd,
unsigned MaddOpc,
const TargetRegisterClass * RC )
static

genFusedMultiplyIdx - Helper to generate fused multiply accumulate instructions.

See also
genFusedMultiply

Definition at line 8503 of file AArch64InstrInfo.cpp.

References genFusedMultiply(), Indexed, MRI, and TII.

◆ genFusedMultiplyIdxNeg()

MachineInstr * genFusedMultiplyIdxNeg ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
DenseMap< Register, unsigned > & InstrIdxForVirtReg,
unsigned IdxMulOpd,
unsigned MaddOpc,
unsigned MnegOpc,
const TargetRegisterClass * RC )
static

genFusedMultiplyAccNeg - Helper to generate fused multiply accumulate instructions with an additional negation of the accumulator

Definition at line 8513 of file AArch64InstrInfo.cpp.

References assert(), genFusedMultiply(), genNeg(), Indexed, MRI, and TII.

◆ genIndexedMultiply()

MachineInstr * genIndexedMultiply ( MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
unsigned IdxDupOp,
unsigned MulOpc,
const TargetRegisterClass * RC,
MachineRegisterInfo & MRI )
static

Fold (FMUL x (DUP y lane)) into (FMUL_indexed x y lane)

Definition at line 8416 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getUniqueVRegDef(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ genMaddR()

MachineInstr * genMaddR ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
unsigned IdxMulOpd,
unsigned MaddOpc,
unsigned VR,
const TargetRegisterClass * RC )
static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters
MFContaining MachineFunction
MRIRegister information
TIITarget information
Rootis the ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the madd instruction
VRis a virtual register that holds the value of an ADD operand (V in the example above).
RCRegister class of operands

Definition at line 8546 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::Register::isVirtual(), llvm::Register::isVirtualRegister(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

◆ genNeg()

Register genNeg ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
DenseMap< Register, unsigned > & InstrIdxForVirtReg,
unsigned MnegOpc,
const TargetRegisterClass * RC )
static

genNeg - Helper to generate an intermediate negation of the second operand of Root

Definition at line 8467 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty(), llvm::MachineInstr::getOperand(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TII.

Referenced by genFusedMultiplyAccNeg(), and genFusedMultiplyIdxNeg().

◆ genSubAdd2SubSub()

void genSubAdd2SubSub ( MachineFunction & MF,
MachineRegisterInfo & MRI,
const TargetInstrInfo * TII,
MachineInstr & Root,
SmallVectorImpl< MachineInstr * > & InsInstrs,
SmallVectorImpl< MachineInstr * > & DelInstrs,
unsigned IdxOpd1,
DenseMap< Register, unsigned > & InstrIdxForVirtReg )
static

Do the following transformation A - (B + C) ==> (A - B) - C A - (B + C) ==> (A - C) - B.

Definition at line 8582 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm::MachineInstr::mergeFlagsWith(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

◆ getBranchDisplacementBits()

unsigned getBranchDisplacementBits ( unsigned Opc)
static

Definition at line 270 of file AArch64InstrInfo.cpp.

References BCCDisplacementBits, BDisplacementBits, CBDisplacementBits, CBZDisplacementBits, llvm_unreachable, Opc, and TBZDisplacementBits.

Referenced by llvm::AArch64InstrInfo::isBranchOffsetInRange().

◆ getFMAPatterns()

bool getFMAPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Floating-Point Support.

Find instructions that can be turned into madd.

Definition at line 7563 of file AArch64InstrInfo.cpp.

References assert(), canCombineWithFMUL(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidateFP(), llvm::MachineOperand::isReg(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getFMULPatterns()

bool getFMULPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Definition at line 7705 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, MI, MRI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getFNEGPatterns()

bool getFNEGPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Definition at line 7757 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::FmContract, llvm::MachineInstr::FmNsz, llvm::FNMADD, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), MBB, MI, MRI, Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getGatherLanePattern()

bool getGatherLanePattern ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns,
unsigned LoadLaneOpCode,
unsigned NumLanes )
static

Check if the given instruction forms a gather load pattern that can be optimized for better Memory-Level Parallelism (MLP).

This function identifies chains of NEON lane load instructions that load data from different memory addresses into individual lanes of a 128-bit vector register, then attempts to split the pattern into parallel loads to break the serial dependency between instructions.

Pattern Matched: Initial scalar load -> SUBREG_TO_REG (lane 0) -> LD1i* (lane 1) -> LD1i* (lane 2) -> ... -> LD1i* (lane N-1, Root)

Transformed Into: Two parallel vector loads using fewer lanes each, followed by ZIP1v2i64 to combine the results, enabling better memory-level parallelism.

Supported Element Types:

  • 32-bit elements (LD1i32, 4 lanes total)
  • 16-bit elements (LD1i16, 8 lanes total)
  • 8-bit elements (LD1i8, 16 lanes total)

Definition at line 7961 of file AArch64InstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallPtrSetImplBase::empty(), llvm::SmallSet< T, N, C >::empty(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::SmallSet< T, N, C >::erase(), llvm::GATHER_LANE_i16, llvm::GATHER_LANE_i32, llvm::GATHER_LANE_i8, GatherOptSearchLimit, llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasMinSize(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MachineInstr::isLoadFoldBarrier(), llvm_unreachable, MBB, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Range, llvm::seq(), and TRI.

Referenced by getLoadPatterns().

◆ getIndVarInfo()

bool getIndVarInfo ( Register Reg,
const MachineBasicBlock * LoopBB,
MachineInstr *& UpdateInst,
unsigned & UpdateCounterOprNum,
Register & InitReg,
bool & IsUpdatePriorComp )
static

If Reg is an induction variable, return true and set some parameters.

Definition at line 11523 of file AArch64InstrInfo.cpp.

References extractPhiReg(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), isDefinedOutside(), llvm::Register::isVirtual(), MRI, llvm::MachineBasicBlock::pred_size(), and Reg.

Referenced by llvm::AArch64InstrInfo::analyzeLoopForPipelining().

◆ getLoadPatterns()

bool getLoadPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Search for patterns of LD instructions we can optimize.

Definition at line 8062 of file AArch64InstrInfo.cpp.

References getGatherLanePattern(), and llvm::MachineInstr::getOpcode().

◆ getMaddPatterns()

bool getMaddPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Find instructions that can be turned into madd.

Definition at line 7294 of file AArch64InstrInfo.cpp.

References assert(), canCombine(), canCombineWithMUL(), convertToNonFlagSettingOpc(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), MBB, Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMiscPatterns()

bool getMiscPatterns ( MachineInstr & Root,
SmallVectorImpl< unsigned > & Patterns )
static

Find other MI combine patterns.

Definition at line 7908 of file AArch64InstrInfo.cpp.

References canCombine(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrSettingFlag(), MBB, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SUBADD_OP1, and llvm::SUBADD_OP2.

◆ getRegClass()

const TargetRegisterClass * getRegClass ( const MachineInstr & MI,
Register Reg )
static

Definition at line 5070 of file AArch64InstrInfo.cpp.

References llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::MachineFunction::getRegInfo(), MI, and Reg.

Referenced by llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getLargestLegalSuperClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), llvm::M68kRegisterInfo::getSpillRegisterOrder(), llvm::AArch64InstrInfo::isFpOrNEON(), llvm::AArch64InstrInfo::isHForm(), llvm::AArch64InstrInfo::isQForm(), llvm::SIRegisterInfo::isSGPRClassID(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::reMaterialize(), selectCopy(), and llvm::AVRRegisterInfo::shouldCoalesce().

◆ getUsedNZCV()

UsedNZCV getUsedNZCV ( AArch64CC::CondCode CC)
static

Definition at line 2088 of file AArch64InstrInfo.cpp.

References assert(), llvm::UsedNZCV::C, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::UsedNZCV::N, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::UsedNZCV::V, llvm::AArch64CC::VC, llvm::AArch64CC::VS, and llvm::UsedNZCV::Z.

Referenced by canCmpInstrBeRemoved(), and llvm::examineCFlagsUse().

◆ isADDSRegImm()

bool isADDSRegImm ( unsigned Opcode)
static

Definition at line 2165 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

◆ isANDOpcode()

bool isANDOpcode ( MachineInstr & MI)
static

Definition at line 2173 of file AArch64InstrInfo.cpp.

References MI, Opc, and sForm().

Referenced by canInstrSubstituteCmpInstr().

◆ isCheapCopy()

bool isCheapCopy ( const MachineInstr & MI,
const AArch64RegisterInfo & RI )
static

Definition at line 1207 of file AArch64InstrInfo.cpp.

References assert(), MI, MRI, and Reg.

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

◆ isCheapImmediate()

bool isCheapImmediate ( const MachineInstr & MI,
unsigned BitSize )
static

Definition at line 1194 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_IMM::expandMOVImm(), llvm::getImm(), MI, and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

◆ isCombineInstrCandidate()

bool isCombineInstrCandidate ( unsigned Opc)
static

Definition at line 7134 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), isCombineInstrCandidate64(), and Opc.

Referenced by getMaddPatterns().

◆ isCombineInstrCandidate32()

bool isCombineInstrCandidate32 ( unsigned Opc)
static

Definition at line 7054 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidate64()

bool isCombineInstrCandidate64 ( unsigned Opc)
static

Definition at line 7073 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidateFP()

bool isCombineInstrCandidateFP ( const MachineInstr & Inst)
static

Definition at line 7104 of file AArch64InstrInfo.cpp.

References llvm::FPOpFusion::Fast, llvm::MachineInstr::FmContract, llvm::MachineInstr::getFlag(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and Options.

Referenced by getFMAPatterns().

◆ isCombineInstrSettingFlag()

bool isCombineInstrSettingFlag ( unsigned Opc)
static

Definition at line 7035 of file AArch64InstrInfo.cpp.

References Opc.

Referenced by canCombine(), getMaddPatterns(), and getMiscPatterns().

◆ isDefinedOutside()

bool isDefinedOutside ( Register Reg,
const MachineBasicBlock * BB )
static

Definition at line 11515 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, and Reg.

Referenced by llvm::AArch64InstrInfo::analyzeLoopForPipelining(), and getIndVarInfo().

◆ isFrameLoadOpcode()

bool isFrameLoadOpcode ( int Opcode)
static

Definition at line 2640 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlotPostFE(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().

◆ isFrameStoreOpcode()

bool isFrameStoreOpcode ( int Opcode)
static

Definition at line 2669 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlotPostFE(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().

◆ isInStreamingCallSiteRegion()

bool isInStreamingCallSiteRegion ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator I )
static

Returns true if the instruction at I is in a streaming call site region, within a single basic block.

A "call site streaming region" starts after smstart and ends at smstop around a call to a streaming function. This walks backward from I.

Definition at line 5396 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::hasStreamingModeChanges(), I, llvm::make_range(), MBB, MI, Opc, and llvm::reverse().

Referenced by mustAvoidNeonAtMBBI().

◆ isPostIndexLdStOpcode()

bool isPostIndexLdStOpcode ( unsigned Opcode)
static

Return true if the opcode is a post-index ld/st instruction, which really loads from base+0.

Definition at line 4132 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth().

◆ isSUBSRegImm()

bool isSUBSRegImm ( unsigned Opcode)
static

Definition at line 2169 of file AArch64InstrInfo.cpp.

Referenced by canCmpInstrBeRemoved(), and canInstrSubstituteCmpInstr().

◆ loadRegPairFromStackSlot()

void loadRegPairFromStackSlot ( const TargetRegisterInfo & TRI,
MachineBasicBlock & MBB,
MachineBasicBlock::iterator InsertBefore,
const MCInstrDesc & MCID,
Register DestReg,
unsigned SubIdx0,
unsigned SubIdx1,
int FI,
MachineMemOperand * MMO )
static

Definition at line 6131 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::RegState::Define, llvm::getUndefRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::loadRegFromStackSlot().

◆ mustAvoidNeonAtMBBI()

bool mustAvoidNeonAtMBBI ( const AArch64Subtarget & Subtarget,
MachineBasicBlock & MBB,
MachineBasicBlock::iterator I )
static

Returns true if in a streaming call site region without SME-FA64.

Definition at line 5418 of file AArch64InstrInfo.cpp.

References I, isInStreamingCallSiteRegion(), and MBB.

Referenced by llvm::AArch64InstrInfo::copyPhysReg().

◆ offsetExtendOpcode()

unsigned offsetExtendOpcode ( unsigned Opcode)
static

Definition at line 3961 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ outliningCandidatesSigningKeyConsensus()

bool outliningCandidatesSigningKeyConsensus ( const outliner::Candidate & a,
const outliner::Candidate & b )
static

Definition at line 9924 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::shouldSignWithBKey().

◆ outliningCandidatesSigningScopeConsensus()

bool outliningCandidatesSigningScopeConsensus ( const outliner::Candidate & a,
const outliner::Candidate & b )
static

Definition at line 9914 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getInfo(), llvm::outliner::Candidate::getMF(), and llvm::AArch64FunctionInfo::getSignReturnAddressCondition().

◆ outliningCandidatesV8_3OpsConsensus()

bool outliningCandidatesV8_3OpsConsensus ( const outliner::Candidate & a,
const outliner::Candidate & b )
static

Definition at line 9932 of file AArch64InstrInfo.cpp.

References llvm::outliner::Candidate::getMF(), and llvm::MachineFunction::getSubtarget().

◆ parseCondBranch()

void parseCondBranch ( MachineInstr * LastInst,
MachineBasicBlock *& Target,
SmallVectorImpl< MachineOperand > & Cond )
static

Definition at line 216 of file AArch64InstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::analyzeBranch(), llvm::CSKYInstrInfo::analyzeBranch(), llvm::LoongArchInstrInfo::analyzeBranch(), llvm::RISCVInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), and llvm::VEInstrInfo::analyzeBranch().

◆ regOffsetOpcode()

unsigned regOffsetOpcode ( unsigned Opcode)
static

Definition at line 3706 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ removeCopies()

unsigned removeCopies ( const MachineRegisterInfo & MRI,
unsigned VReg )
static

Definition at line 771 of file AArch64InstrInfo.cpp.

References DefMI, llvm::Register::isVirtualRegister(), and MRI.

Referenced by canFoldIntoCSel().

◆ scaledOffsetOpcode()

unsigned scaledOffsetOpcode ( unsigned Opcode,
unsigned & Scale )

Definition at line 3780 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ scaleOffset()

bool scaleOffset ( unsigned Opc,
int64_t & Offset )
static

Definition at line 5164 of file AArch64InstrInfo.cpp.

References llvm::AArch64InstrInfo::getMemScale(), llvm::Offset, and Opc.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ sForm()

unsigned sForm ( MachineInstr & Instr)
static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 1955 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr(), and isANDOpcode().

◆ shouldClusterFI()

bool shouldClusterFI ( const MachineFrameInfo & MFI,
int FI1,
int64_t Offset1,
unsigned Opcode1,
int FI2,
int64_t Offset2,
unsigned Opcode2 )
static

Definition at line 5223 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64InstrInfo::getMemScale(), llvm::MachineFrameInfo::getObjectOffset(), and llvm::MachineFrameInfo::isFixedObjectIndex().

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ signOutlinedFunction()

void signOutlinedFunction ( MachineFunction & MF,
MachineBasicBlock & MBB,
const AArch64InstrInfo * TII,
bool ShouldSignReturnAddr )
static

Definition at line 10719 of file AArch64InstrInfo.cpp.

References llvm::BuildMI(), llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, MBB, llvm::MachineInstrBuilder::setMIFlag(), and TII.

◆ STATISTIC() [1/4]

STATISTIC ( NumCopyInstrs ,
"Number of COPY instructions expanded"  )

◆ STATISTIC() [2/4]

STATISTIC ( NumZCRegMoveInstrsFPR ,
"Number of zero-cycle FPR register move " "instructions expanded from canonical COPY"  )

◆ STATISTIC() [3/4]

STATISTIC ( NumZCRegMoveInstrsGPR ,
"Number of zero-cycle GPR register move " "instructions expanded from canonical COPY"  )

◆ STATISTIC() [4/4]

STATISTIC ( NumZCZeroingInstrsGPR ,
"Number of zero-cycle GPR zeroing " "instructions expanded from canonical COPY"  )

◆ storeRegPairToStackSlot()

void storeRegPairToStackSlot ( const TargetRegisterInfo & TRI,
MachineBasicBlock & MBB,
MachineBasicBlock::iterator InsertBefore,
const MCInstrDesc & MCID,
Register SrcReg,
bool IsKill,
unsigned SubIdx0,
unsigned SubIdx1,
int FI,
MachineMemOperand * MMO )
static

Definition at line 5953 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::getKillRegState(), llvm::Register::isPhysical(), MBB, and TRI.

Referenced by llvm::AArch64InstrInfo::storeRegToStackSlot().

◆ unscaledOffsetOpcode()

unsigned unscaledOffsetOpcode ( unsigned Opcode)

Definition at line 3885 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr().

◆ UpdateOperandRegClass()

bool UpdateOperandRegClass ( MachineInstr & Instr)
static

Definition at line 1582 of file AArch64InstrInfo.cpp.

References assert(), llvm::TargetRegisterClass::contains(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::hasSubClassEq(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), MBB, MRI, OpIdx, Reg, TII, and TRI.

Referenced by llvm::AArch64InstrInfo::optimizeCompareInstr().

Variable Documentation

◆ BCCDisplacementBits

cl::opt< unsigned > BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)")) ( "aarch64-bcc-offset-bits" ,
cl::Hidden ,
cl::init(19) ,
cl::desc("Restrict range of Bcc instructions (DEBUG)")  )
static

Referenced by getBranchDisplacementBits().

◆ BDisplacementBits

cl::opt< unsigned > BDisplacementBits("aarch64-b-offset-bits", cl::Hidden, cl::init(26), cl::desc("Restrict range of B instructions (DEBUG)")) ( "aarch64-b-offset-bits" ,
cl::Hidden ,
cl::init(26) ,
cl::desc("Restrict range of B instructions (DEBUG)")  )
static

Referenced by getBranchDisplacementBits().

◆ CBDisplacementBits

cl::opt< unsigned > CBDisplacementBits("aarch64-cb-offset-bits", cl::Hidden, cl::init(9), cl::desc("Restrict range of CB instructions (DEBUG)")) ( "aarch64-cb-offset-bits" ,
cl::Hidden ,
cl::init(9) ,
cl::desc("Restrict range of CB instructions (DEBUG)")  )
static

Referenced by getBranchDisplacementBits().

◆ CBZDisplacementBits

cl::opt< unsigned > CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")) ( "aarch64-cbz-offset-bits" ,
cl::Hidden ,
cl::init(19) ,
cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")  )
static

Referenced by getBranchDisplacementBits().

◆ GatherOptSearchLimit

cl::opt< unsigned > GatherOptSearchLimit("aarch64-search-limit", cl::Hidden, cl::init(2048), cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization")) ( "aarch64-search-limit" ,
cl::Hidden ,
cl::init(2048) ,
cl::desc("Restrict range of instructions to search for the " "machine-combiner gather pattern optimization")  )
static

Referenced by getGatherLanePattern().

◆ TBZDisplacementBits

cl::opt< unsigned > TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")) ( "aarch64-tbz-offset-bits" ,
cl::Hidden ,
cl::init(14) ,
cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")  )
static

Referenced by getBranchDisplacementBits().

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