#include "HexagonVLIWPacketizer.h"
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
#include <iterator>

Macros
#define	DEBUG_TYPE "packets"

Enumerations
enum	PredicateKind { PK_False , PK_True , PK_Unknown }

Functions
	INITIALIZE_PASS_BEGIN (HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
static bool	hasWriteToReadDep (const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
static MachineBasicBlock::iterator	moveInstrOut (MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
static bool	isRegDependence (const SDep::Kind DepType)
static bool	isDirectJump (const MachineInstr &MI)
static bool	isSchedBarrier (const MachineInstr &MI)
static bool	isControlFlow (const MachineInstr &MI)
static bool	doesModifyCalleeSavedReg (const MachineInstr &MI, const TargetRegisterInfo *TRI)
	Returns true if the instruction modifies a callee-saved register.
static PredicateKind	getPredicateSense (const MachineInstr &MI, const HexagonInstrInfo *HII)
	Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.
static const MachineOperand &	getPostIncrementOperand (const MachineInstr &MI, const HexagonInstrInfo *HII)
static const MachineOperand &	getStoreValueOperand (const MachineInstr &MI)
static bool	isLoadAbsSet (const MachineInstr &MI)
static const MachineOperand &	getAbsSetOperand (const MachineInstr &MI)
static bool	isImplicitDependency (const MachineInstr &I, bool CheckDef, unsigned DepReg)
static unsigned	getPredicatedRegister (MachineInstr &MI, const HexagonInstrInfo *QII)
	Gets the predicate register of a predicated instruction.
static bool	cannotCoexistAsymm (const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
static bool	isSystemInstr (const MachineInstr &MI)

Variables
static cl::opt< bool >	DisablePacketizer ("disable-packetizer", cl::Hidden, cl::desc("Disable Hexagon packetizer pass"))
static cl::opt< bool >	Slot1Store ("slot1-store-slot0-load", cl::Hidden, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
static cl::opt< bool >	PacketizeVolatiles ("hexagon-packetize-volatiles", cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
static cl::opt< bool >	EnableGenAllInsnClass ("enable-gen-insn", cl::Hidden, cl::desc("Generate all instruction with TC"))
static cl::opt< bool >	DisableVecDblNVStores ("disable-vecdbl-nv-stores", cl::Hidden, cl::desc("Disable vector double new-value-stores"))
cl::opt< bool >	ScheduleInlineAsm
hexagon	packetizer
hexagon Hexagon	Packetizer
hexagon Hexagon	false

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "packets"

Definition at line 56 of file HexagonVLIWPacketizer.cpp.

Enumeration Type Documentation

◆ PredicateKind

enum PredicateKind

Enumerator
PK_False
PK_True
PK_Unknown

Definition at line 550 of file HexagonVLIWPacketizer.cpp.

Function Documentation

◆ cannotCoexistAsymm()

bool cannotCoexistAsymm	(	const MachineInstr &	MI,
		const MachineInstr &	MJ,
		const HexagonInstrInfo &	HII )

static

◆ doesModifyCalleeSavedReg()

bool doesModifyCalleeSavedReg	(	const MachineInstr &	MI,
		const TargetRegisterInfo *	TRI )

static

Returns true if the instruction modifies a callee-saved register.

Definition at line 340 of file HexagonVLIWPacketizer.cpp.

References MI, and TRI.

Referenced by llvm::HexagonPacketizerList::hasControlDependence().

◆ getAbsSetOperand()

const MachineOperand & getAbsSetOperand ( const MachineInstr & MI )

static

Definition at line 620 of file HexagonVLIWPacketizer.cpp.

References assert(), isLoadAbsSet(), and MI.

Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().

◆ getPostIncrementOperand()

const MachineOperand & getPostIncrementOperand	(	const MachineInstr &	MI,
		const HexagonInstrInfo *	HII )

static

Definition at line 567 of file HexagonVLIWPacketizer.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::HexagonInstrInfo::isPostIncrement(), llvm::MachineOperand::isReg(), llvm_unreachable, and MI.

Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().

◆ getPredicatedRegister()

unsigned getPredicatedRegister	(	MachineInstr &	MI,
		const HexagonInstrInfo *	QII )

static

Gets the predicate register of a predicated instruction.

We use the following rule: The first predicate register that is a use is the predicate register of a predicated instruction.

Definition at line 940 of file HexagonVLIWPacketizer.cpp.

References assert(), llvm::HexagonInstrInfo::isPredicated(), llvm_unreachable, and MI.

Referenced by llvm::HexagonPacketizerList::arePredicatesComplements().

◆ getPredicateSense()

PredicateKind getPredicateSense	(	const MachineInstr &	MI,
		const HexagonInstrInfo *	HII )

static

Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.

Definition at line 558 of file HexagonVLIWPacketizer.cpp.

References llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedTrue(), MI, PK_False, PK_True, and PK_Unknown.

Referenced by llvm::HexagonPacketizerList::arePredicatesComplements(), and llvm::HexagonPacketizerList::canPromoteToNewValueStore().

◆ getStoreValueOperand()

const MachineOperand & getStoreValueOperand ( const MachineInstr & MI )

static

Definition at line 601 of file HexagonVLIWPacketizer.cpp.

References MI.

Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().

◆ hasWriteToReadDep()

bool hasWriteToReadDep	(	const MachineInstr &	FirstI,
		const MachineInstr &	SecondI,
		const TargetRegisterInfo *	TRI )

static

Definition at line 140 of file HexagonVLIWPacketizer.cpp.

References llvm::MachineInstr::operands(), llvm::MachineInstr::readsRegister(), and TRI.

Referenced by llvm::HexagonPacketizerList::unpacketizeSoloInstrs().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	HexagonPacketizer	,
		"hexagon-packetizer"	,
		"Hexagon Packetizer"	,
		false	,
		false	)

References INITIALIZE_PASS_DEPENDENCY.

◆ isControlFlow()

bool isControlFlow ( const MachineInstr & MI )

static

Definition at line 335 of file HexagonVLIWPacketizer.cpp.

References MI.

Referenced by llvm::HexagonPacketizerList::hasControlDependence().

◆ isDirectJump()

bool isDirectJump ( const MachineInstr & MI )

static

Definition at line 323 of file HexagonVLIWPacketizer.cpp.

References MI.

Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().

◆ isImplicitDependency()

bool isImplicitDependency	(	const MachineInstr &	I,
		bool	CheckDef,
		unsigned	DepReg )

static

Definition at line 827 of file HexagonVLIWPacketizer.cpp.

References I.

Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew().

◆ isLoadAbsSet()

bool isLoadAbsSet ( const MachineInstr & MI )

static

Definition at line 606 of file HexagonVLIWPacketizer.cpp.

References MI, and Opc.

Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore(), and getAbsSetOperand().

◆ isRegDependence()

bool isRegDependence ( const SDep::Kind DepType )

static

Definition at line 318 of file HexagonVLIWPacketizer.cpp.

References llvm::SDep::Anti, llvm::SDep::Data, and llvm::SDep::Output.

Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().

◆ isSchedBarrier()

bool isSchedBarrier ( const MachineInstr & MI )

static

Definition at line 327 of file HexagonVLIWPacketizer.cpp.

References MI.

Referenced by llvm::HexagonPacketizerList::isSoloInstruction().

◆ isSystemInstr()

bool isSystemInstr ( const MachineInstr & MI )

static

Definition at line 1186 of file HexagonVLIWPacketizer.cpp.

References MI, and Opc.

Referenced by llvm::HexagonPacketizerList::hasDualStoreDependence().

◆ moveInstrOut()

MachineBasicBlock::iterator moveInstrOut	(	MachineInstr &	MI,
		MachineBasicBlock::iterator	BundleIt,
		bool	Before )

static

Definition at line 154 of file HexagonVLIWPacketizer.cpp.

References assert(), B(), llvm::MachineInstr::BundledPred, llvm::MachineInstr::BundledSucc, E(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), I, llvm::MachineInstr::isBundledWithSucc(), MI, Size, and llvm::MachineInstr::unbundleFromPred().

Referenced by llvm::HexagonPacketizerList::unpacketizeSoloInstrs().

Variable Documentation

◆ DisablePacketizer

cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::desc("Disable Hexagon packetizer pass"))	(	"disable-packetizer"	,
		cl::Hidden	,
		cl::desc("Disable Hexagon packetizer pass")	)

static

◆ DisableVecDblNVStores

cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::Hidden, cl::desc("Disable vector double new-value-stores"))	(	"disable-vecdbl-nv-stores"	,
		cl::Hidden	,
		cl::desc("Disable vector double new-value-stores")	)

static

Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew().

◆ EnableGenAllInsnClass

cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::Hidden, cl::desc("Generate all instruction with TC"))	(	"enable-gen-insn"	,
		cl::Hidden	,
		cl::desc("Generate all instruction with TC")	)

static

◆ false

hexagon Hexagon false

Definition at line 124 of file HexagonVLIWPacketizer.cpp.

◆ Packetizer

hexagon Hexagon Packetizer

Definition at line 124 of file HexagonVLIWPacketizer.cpp.

◆ packetizer

hexagon packetizer

Definition at line 123 of file HexagonVLIWPacketizer.cpp.

◆ PacketizeVolatiles

cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))	(	"hexagon-packetize-volatiles"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Allow non-solo packetization of volatile memory references")	)

static

Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().

◆ ScheduleInlineAsm

cl::opt<bool> ScheduleInlineAsm

extern

◆ Slot1Store

cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))	(	"slot1-store-slot0-load"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Allow slot1 store and slot0 load")	)

static

Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Enumeration Type Documentation

◆ PredicateKind

Function Documentation

◆ cannotCoexistAsymm()

◆ doesModifyCalleeSavedReg()

◆ getAbsSetOperand()

◆ getPostIncrementOperand()

◆ getPredicatedRegister()

◆ getPredicateSense()

◆ getStoreValueOperand()

◆ hasWriteToReadDep()

◆ INITIALIZE_PASS_BEGIN()

◆ isControlFlow()

◆ isDirectJump()

◆ isImplicitDependency()

◆ isLoadAbsSet()

◆ isRegDependence()

◆ isSchedBarrier()

◆ isSystemInstr()

◆ moveInstrOut()

Variable Documentation

◆ DisablePacketizer

◆ DisableVecDblNVStores

◆ EnableGenAllInsnClass

◆ false

◆ Packetizer

◆ packetizer

◆ PacketizeVolatiles

◆ ScheduleInlineAsm

◆ Slot1Store