38#define DEBUG_TYPE "vec-merger"
44 return MI &&
MI->isImplicitDef();
53 std::vector<Register> UndefReg;
56 assert(
MI->getOpcode() == R600::REG_SEQUENCE);
57 for (
unsigned i = 1, e =
Instr->getNumOperands(); i < e; i+=2) {
59 unsigned Chan =
Instr->getOperand(i + 1).getImm();
61 UndefReg.push_back(Chan);
63 RegToChan[MO.
getReg()] = Chan;
67 RegSeqInfo() =
default;
70 return RSI.Instr ==
Instr;
81 InstructionSetMap PreviousRegSeqByReg;
82 InstructionSetMap PreviousRegSeqByUndefCount;
85 bool areAllUsesSwizzeable(
Register Reg)
const;
87 const std::vector<std::pair<unsigned, unsigned>> &RemapChan)
const;
88 bool tryMergeVector(
const RegSeqInfo *Untouched, RegSeqInfo *ToMerge,
89 std::vector<std::pair<unsigned, unsigned>> &Remap)
const;
90 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
91 std::vector<std::pair<unsigned, unsigned>> &RemapChan);
92 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
93 std::vector<std::pair<unsigned, unsigned>> &RemapChan);
94 MachineInstr *RebuildVector(RegSeqInfo *
MI,
const RegSeqInfo *BaseVec,
95 const std::vector<std::pair<unsigned, unsigned>> &RemapChan)
const;
97 void trackRSI(
const RegSeqInfo &RSI);
115 .
set(MachineFunctionProperties::Property::IsSSA);
119 return "R600 Vector Registers Merge Pass";
128 "R600 Vector Reg Merger",
false,
false)
132char R600VectorRegMerger::
ID = 0;
140 switch (
MI.getOpcode()) {
141 case R600::R600_ExportSwz:
142 case R600::EG_ExportSwz:
149bool R600VectorRegMerger::tryMergeVector(
const RegSeqInfo *Untouched,
150 RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
152 unsigned CurrentUndexIdx = 0;
153 for (
auto &It : ToMerge->RegToChan) {
155 Untouched->RegToChan.
find(It.first);
156 if (PosInUntouched != Untouched->RegToChan.end()) {
158 std::pair<unsigned, unsigned>(It.second, (*PosInUntouched).second));
161 if (CurrentUndexIdx >= Untouched->UndefReg.size())
163 Remap.push_back(std::pair<unsigned, unsigned>(
164 It.second, Untouched->UndefReg[CurrentUndexIdx++]));
172 const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
174 for (
const auto &J : RemapChan) {
182 RegSeqInfo *RSI,
const RegSeqInfo *BaseRSI,
183 const std::vector<std::pair<unsigned, unsigned>> &RemapChan)
const {
189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
191 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg;
192 for (
const auto &It : RSI->RegToChan) {
193 Register DstReg =
MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
194 unsigned SubReg = It.first;
203 UpdatedRegToChan[
SubReg] = Chan;
204 std::vector<Register>::iterator ChanPos =
llvm::find(UpdatedUndef, Chan);
205 if (ChanPos != UpdatedUndef.end())
206 UpdatedUndef.erase(ChanPos);
208 "UpdatedUndef shouldn't contain Chan more than once!");
219 E =
MRI->use_instr_end(); It !=
E; ++It) {
221 SwizzleInput(*It, RemapChan);
224 RSI->Instr->eraseFromParent();
228 RSI->RegToChan = UpdatedRegToChan;
229 RSI->UndefReg = UpdatedUndef;
235 for (
auto &It : PreviousRegSeqByReg) {
236 std::vector<MachineInstr *> &MIs = It.second;
239 for (
auto &It : PreviousRegSeqByUndefCount) {
240 std::vector<MachineInstr *> &MIs = It.second;
246 const std::vector<std::pair<unsigned, unsigned>> &RemapChan)
const {
252 for (
unsigned i = 0; i < 4; i++) {
254 for (
const auto &J : RemapChan) {
256 MI.getOperand(i +
Offset).setImm(J.second - 1);
263bool R600VectorRegMerger::areAllUsesSwizzeable(
Register Reg)
const {
265 E =
MRI->use_instr_end(); It !=
E; ++It) {
266 if (!canSwizzle(*It))
272bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
273 RegSeqInfo &CompatibleRSI,
274 std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
276 MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
279 if (PreviousRegSeqByReg[MOp->getReg()].empty())
282 CompatibleRSI = PreviousRegSeq[
MI];
283 if (RSI == CompatibleRSI)
285 if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
292bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
293 RegSeqInfo &CompatibleRSI,
294 std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
295 unsigned NeededUndefs = 4 - RSI.UndefReg.
size();
296 if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
298 std::vector<MachineInstr *> &MIs =
299 PreviousRegSeqByUndefCount[NeededUndefs];
300 CompatibleRSI = PreviousRegSeq[MIs.back()];
301 tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
305void R600VectorRegMerger::trackRSI(
const RegSeqInfo &RSI) {
307 It = RSI.RegToChan.
begin(),
E = RSI.RegToChan.end(); It !=
E; ++It) {
308 PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
310 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
311 PreviousRegSeq[RSI.Instr] = RSI;
319 TII =
ST.getInstrInfo();
323 PreviousRegSeq.
clear();
324 PreviousRegSeqByReg.clear();
325 PreviousRegSeqByUndefCount.clear();
328 MII != MIIE; ++MII) {
330 if (
MI.getOpcode() != R600::REG_SEQUENCE) {
334 It =
MRI->def_instr_begin(Reg),
E =
MRI->def_instr_end();
342 RegSeqInfo RSI(*
MRI, &
MI);
346 if (!areAllUsesSwizzeable(Reg))
350 dbgs() <<
"Trying to optimize ";
354 RegSeqInfo CandidateRSI;
355 std::vector<std::pair<unsigned, unsigned>> RemapChan;
357 if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
359 RemoveMI(CandidateRSI.Instr);
360 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
366 if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
367 RemoveMI(CandidateRSI.Instr);
368 MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
380 return new R600VectorRegMerger();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
Provides R600 specific target descriptions.
static unsigned getReassignedChan(const std::vector< std::pair< unsigned, unsigned > > &RemapChan, unsigned Chan)
static bool isImplicitlyDef(MachineRegisterInfo &MRI, Register Reg)
AMDGPU R600 specific subclass of TargetSubtarget.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
iterator find(const_arg_type_t< KeyT > Val)
FunctionPass class - This class is used to implement most global optimizations.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< InstrNode * > Instr
This is an optimization pass for GlobalISel generic memory operations.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
FunctionPass * createR600VectorRegMerger()
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
char & R600VectorRegMergerID