LLVM  14.0.0git
SparcAsmPrinter.cpp
Go to the documentation of this file.
1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
17 #include "Sparc.h"
18 #include "SparcInstrInfo.h"
19 #include "SparcTargetMachine.h"
26 #include "llvm/IR/Mangler.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSymbol.h"
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "asm-printer"
37 
38 namespace {
39  class SparcAsmPrinter : public AsmPrinter {
40  SparcTargetStreamer &getTargetStreamer() {
41  return static_cast<SparcTargetStreamer &>(
42  *OutStreamer->getTargetStreamer());
43  }
44  public:
45  explicit SparcAsmPrinter(TargetMachine &TM,
46  std::unique_ptr<MCStreamer> Streamer)
47  : AsmPrinter(TM, std::move(Streamer)) {}
48 
49  StringRef getPassName() const override { return "Sparc Assembly Printer"; }
50 
51  void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
52  void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
53  const char *Modifier = nullptr);
54 
55  void emitFunctionBodyStart() override;
56  void emitInstruction(const MachineInstr *MI) override;
57 
58  static const char *getRegisterName(unsigned RegNo) {
60  }
61 
62  bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63  const char *ExtraCode, raw_ostream &O) override;
64  bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
65  const char *ExtraCode, raw_ostream &O) override;
66 
67  void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
68  const MCSubtargetInfo &STI);
69 
70  };
71 } // end of anonymous namespace
72 
74  MCSymbol *Sym, MCContext &OutContext) {
75  const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym,
76  OutContext);
77  const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
78  return MCOperand::createExpr(expr);
79 
80 }
82  MCContext &OutContext) {
83  return createSparcMCOperand(SparcMCExpr::VK_Sparc_WDISP30, Label, OutContext);
84 }
85 
87  MCSymbol *GOTLabel, MCSymbol *StartLabel,
88  MCSymbol *CurLabel,
89  MCContext &OutContext)
90 {
91  const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
92  const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
93  OutContext);
94  const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
95  OutContext);
96 
97  const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98  const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
99  const SparcMCExpr *expr = SparcMCExpr::create(Kind,
100  Add, OutContext);
101  return MCOperand::createExpr(expr);
102 }
103 
104 static void EmitCall(MCStreamer &OutStreamer,
105  MCOperand &Callee,
106  const MCSubtargetInfo &STI)
107 {
109  CallInst.setOpcode(SP::CALL);
110  CallInst.addOperand(Callee);
111  OutStreamer.emitInstruction(CallInst, STI);
112 }
113 
114 static void EmitSETHI(MCStreamer &OutStreamer,
115  MCOperand &Imm, MCOperand &RD,
116  const MCSubtargetInfo &STI)
117 {
118  MCInst SETHIInst;
119  SETHIInst.setOpcode(SP::SETHIi);
120  SETHIInst.addOperand(RD);
121  SETHIInst.addOperand(Imm);
122  OutStreamer.emitInstruction(SETHIInst, STI);
123 }
124 
125 static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
126  MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
127  const MCSubtargetInfo &STI)
128 {
129  MCInst Inst;
130  Inst.setOpcode(Opcode);
131  Inst.addOperand(RD);
132  Inst.addOperand(RS1);
133  Inst.addOperand(Src2);
134  OutStreamer.emitInstruction(Inst, STI);
135 }
136 
137 static void EmitOR(MCStreamer &OutStreamer,
138  MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
139  const MCSubtargetInfo &STI) {
140  EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
141 }
142 
143 static void EmitADD(MCStreamer &OutStreamer,
144  MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
145  const MCSubtargetInfo &STI) {
146  EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
147 }
148 
149 static void EmitSHL(MCStreamer &OutStreamer,
150  MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
151  const MCSubtargetInfo &STI) {
152  EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
153 }
154 
155 
156 static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym,
159  MCOperand &RD,
160  MCContext &OutContext,
161  const MCSubtargetInfo &STI) {
162 
163  MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
164  MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
165  EmitSETHI(OutStreamer, hi, RD, STI);
166  EmitOR(OutStreamer, RD, lo, RD, STI);
167 }
168 
169 void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
170  const MCSubtargetInfo &STI)
171 {
172  MCSymbol *GOTLabel =
173  OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
174 
175  const MachineOperand &MO = MI->getOperand(0);
176  assert(MO.getReg() != SP::O7 &&
177  "%o7 is assigned as destination for getpcx!");
178 
179  MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
180 
181 
182  if (!isPositionIndependent()) {
183  // Just load the address of GOT to MCRegOP.
184  switch(TM.getCodeModel()) {
185  default:
186  llvm_unreachable("Unsupported absolute code model");
187  case CodeModel::Small:
188  EmitHiLo(*OutStreamer, GOTLabel,
190  MCRegOP, OutContext, STI);
191  break;
192  case CodeModel::Medium: {
193  EmitHiLo(*OutStreamer, GOTLabel,
195  MCRegOP, OutContext, STI);
197  OutContext));
198  EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
200  GOTLabel, OutContext);
201  EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
202  break;
203  }
204  case CodeModel::Large: {
205  EmitHiLo(*OutStreamer, GOTLabel,
207  MCRegOP, OutContext, STI);
209  OutContext));
210  EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
211  // Use register %o7 to load the lower 32 bits.
212  MCOperand RegO7 = MCOperand::createReg(SP::O7);
213  EmitHiLo(*OutStreamer, GOTLabel,
215  RegO7, OutContext, STI);
216  EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
217  }
218  }
219  return;
220  }
221 
222  MCSymbol *StartLabel = OutContext.createTempSymbol();
223  MCSymbol *EndLabel = OutContext.createTempSymbol();
224  MCSymbol *SethiLabel = OutContext.createTempSymbol();
225 
226  MCOperand RegO7 = MCOperand::createReg(SP::O7);
227 
228  // <StartLabel>:
229  // call <EndLabel>
230  // <SethiLabel>:
231  // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
232  // <EndLabel>:
233  // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
234  // add <MO>, %o7, <MO>
235 
236  OutStreamer->emitLabel(StartLabel);
237  MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
238  EmitCall(*OutStreamer, Callee, STI);
239  OutStreamer->emitLabel(SethiLabel);
241  GOTLabel, StartLabel, SethiLabel,
242  OutContext);
243  EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
244  OutStreamer->emitLabel(EndLabel);
246  GOTLabel, StartLabel, EndLabel,
247  OutContext);
248  EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
249  EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
250 }
251 
252 void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) {
253 
254  switch (MI->getOpcode()) {
255  default: break;
256  case TargetOpcode::DBG_VALUE:
257  // FIXME: Debug Value.
258  return;
259  case SP::GETPCX:
260  LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
261  return;
262  }
264  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
265  do {
266  MCInst TmpInst;
267  LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
268  EmitToStreamer(*OutStreamer, TmpInst);
269  } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
270 }
271 
272 void SparcAsmPrinter::emitFunctionBodyStart() {
273  if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
274  return;
275 
276  const MachineRegisterInfo &MRI = MF->getRegInfo();
277  const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
278  for (unsigned i = 0; globalRegs[i] != 0; ++i) {
279  unsigned reg = globalRegs[i];
280  if (MRI.use_empty(reg))
281  continue;
282 
283  if (reg == SP::G6 || reg == SP::G7)
284  getTargetStreamer().emitSparcRegisterIgnore(reg);
285  else
286  getTargetStreamer().emitSparcRegisterScratch(reg);
287  }
288 }
289 
290 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
291  raw_ostream &O) {
292  const DataLayout &DL = getDataLayout();
293  const MachineOperand &MO = MI->getOperand (opNum);
295 
296 #ifndef NDEBUG
297  // Verify the target flags.
298  if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
299  if (MI->getOpcode() == SP::CALL)
301  "Cannot handle target flags on call address");
302  else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
305  || TF == SparcMCExpr::VK_Sparc_HH
306  || TF == SparcMCExpr::VK_Sparc_LM
312  "Invalid target flags for address operand on sethi");
313  else if (MI->getOpcode() == SP::TLS_CALL)
317  "Cannot handle target flags on tls call address");
318  else if (MI->getOpcode() == SP::TLS_ADDrr)
323  "Cannot handle target flags on add for TLS");
324  else if (MI->getOpcode() == SP::TLS_LDrr)
326  "Cannot handle target flags on ld for TLS");
327  else if (MI->getOpcode() == SP::TLS_LDXrr)
329  "Cannot handle target flags on ldx for TLS");
330  else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
333  "Cannot handle target flags on xor for TLS");
334  else
338  || TF == SparcMCExpr::VK_Sparc_HM
342  "Invalid target flags for small address operand");
343  }
344 #endif
345 
346 
347  bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
348 
349  switch (MO.getType()) {
351  O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
352  break;
353 
355  O << MO.getImm();
356  break;
358  MO.getMBB()->getSymbol()->print(O, MAI);
359  return;
361  PrintSymbolOperand(MO, O);
362  break;
364  O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
365  break;
367  O << MO.getSymbolName();
368  break;
370  O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
371  << MO.getIndex();
372  break;
374  MO.getMetadata()->printAsOperand(O, MMI->getModule());
375  break;
376  default:
377  llvm_unreachable("<unknown operand type>");
378  }
379  if (CloseParen) O << ")";
380 }
381 
382 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
383  raw_ostream &O, const char *Modifier) {
384  printOperand(MI, opNum, O);
385 
386  // If this is an ADD operand, emit it like normal operands.
387  if (Modifier && !strcmp(Modifier, "arith")) {
388  O << ", ";
389  printOperand(MI, opNum+1, O);
390  return;
391  }
392 
393  if (MI->getOperand(opNum+1).isReg() &&
394  MI->getOperand(opNum+1).getReg() == SP::G0)
395  return; // don't print "+%g0"
396  if (MI->getOperand(opNum+1).isImm() &&
397  MI->getOperand(opNum+1).getImm() == 0)
398  return; // don't print "+0"
399 
400  O << "+";
401  printOperand(MI, opNum+1, O);
402 }
403 
404 /// PrintAsmOperand - Print out an operand for an inline asm expression.
405 ///
406 bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
407  const char *ExtraCode,
408  raw_ostream &O) {
409  if (ExtraCode && ExtraCode[0]) {
410  if (ExtraCode[1] != 0) return true; // Unknown modifier.
411 
412  switch (ExtraCode[0]) {
413  default:
414  // See if this is a generic print operand
415  return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
416  case 'f':
417  case 'r':
418  break;
419  }
420  }
421 
422  printOperand(MI, OpNo, O);
423 
424  return false;
425 }
426 
427 bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
428  unsigned OpNo,
429  const char *ExtraCode,
430  raw_ostream &O) {
431  if (ExtraCode && ExtraCode[0])
432  return true; // Unknown modifier
433 
434  O << '[';
435  printMemOperand(MI, OpNo, O);
436  O << ']';
437 
438  return false;
439 }
440 
441 // Force static initialization.
446 }
SparcInstrInfo.h
llvm::SparcMCExpr::VK_Sparc_TLS_IE_LO10
@ VK_Sparc_TLS_IE_LO10
Definition: SparcMCExpr.h:56
i
i
Definition: README.txt:29
AsmPrinter.h
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MachineModuleInfoImpls.h
SparcTargetInfo.h
llvm::SparcMCExpr::VK_Sparc_TLS_IE_ADD
@ VK_Sparc_TLS_IE_ADD
Definition: SparcMCExpr.h:59
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SparcMCExpr::VK_Sparc_L44
@ VK_Sparc_L44
Definition: SparcMCExpr.h:31
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::SparcMCExpr::VK_Sparc_HM
@ VK_Sparc_HM
Definition: SparcMCExpr.h:33
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::SparcMCExpr::VK_Sparc_None
@ VK_Sparc_None
Definition: SparcMCExpr.h:26
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
llvm::SparcMCExpr::VK_Sparc_TLS_LE_LOX10
@ VK_Sparc_TLS_LE_LOX10
Definition: SparcMCExpr.h:61
EmitSHL
static void EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:149
llvm::SparcMCExpr::VK_Sparc_TLS_LDO_ADD
@ VK_Sparc_TLS_LDO_ADD
Definition: SparcMCExpr.h:54
llvm::getTheSparcTarget
Target & getTheSparcTarget()
Definition: SparcTargetInfo.cpp:13
EmitHiLo
static void EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:156
createPCXRelExprOp
static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, MCSymbol *GOTLabel, MCSymbol *StartLabel, MCSymbol *CurLabel, MCContext &OutContext)
Definition: SparcAsmPrinter.cpp:86
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:341
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4717
printOperand
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
Definition: SelectionDAGDumper.cpp:946
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::SparcMCExpr::VK_Sparc_TLS_LDM_ADD
@ VK_Sparc_TLS_LDM_ADD
Definition: SparcMCExpr.h:50
llvm::SparcMCExpr
Definition: SparcMCExpr.h:23
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:480
llvm::SparcMCExpr::VK_Sparc_TLS_LDM_HI22
@ VK_Sparc_TLS_LDM_HI22
Definition: SparcMCExpr.h:48
SparcInstPrinter.h
llvm::SparcMCExpr::VK_Sparc_M44
@ VK_Sparc_M44
Definition: SparcMCExpr.h:30
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
MachineRegisterInfo.h
llvm::SparcMCExpr::VK_Sparc_TLS_GD_CALL
@ VK_Sparc_TLS_GD_CALL
Definition: SparcMCExpr.h:47
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:60
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::SparcMCExpr::VK_Sparc_TLS_LE_HIX22
@ VK_Sparc_TLS_LE_HIX22
Definition: SparcMCExpr.h:60
llvm::SparcTargetStreamer
Definition: SparcTargetStreamer.h:19
llvm::SparcMCExpr::VK_Sparc_TLS_LDM_CALL
@ VK_Sparc_TLS_LDM_CALL
Definition: SparcMCExpr.h:51
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::SparcMCExpr::VK_Sparc_H44
@ VK_Sparc_H44
Definition: SparcMCExpr.h:29
llvm::SparcMCExpr::create
static const SparcMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: SparcMCExpr.cpp:26
EmitBinary
static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:125
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
MCSymbol.h
SparcMCExpr.h
EmitCall
static void EmitCall(MCStreamer &OutStreamer, MCOperand &Callee, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:104
MCInst.h
llvm::getTheSparcelTarget
Target & getTheSparcelTarget()
Definition: SparcTargetInfo.cpp:21
llvm::SparcMCExpr::VK_Sparc_LM
@ VK_Sparc_LM
Definition: SparcMCExpr.h:34
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::SparcInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::SparcMCExpr::VK_Sparc_TLS_LDM_LO10
@ VK_Sparc_TLS_LDM_LO10
Definition: SparcMCExpr.h:49
llvm::MCSymbol::print
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
llvm::SparcSubtarget
Definition: SparcSubtarget.h:31
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
@ VK_Sparc_TLS_LDO_HIX22
Definition: SparcMCExpr.h:52
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:646
llvm::SparcSubtarget::is64Bit
bool is64Bit() const
Definition: SparcSubtarget.h:107
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:197
llvm::SparcMCExpr::VK_Sparc_TLS_IE_LDX
@ VK_Sparc_TLS_IE_LDX
Definition: SparcMCExpr.h:58
llvm::SparcMCExpr::VK_Sparc_PC22
@ VK_Sparc_PC22
Definition: SparcMCExpr.h:35
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SparcMCExpr::VK_Sparc_TLS_IE_LD
@ VK_Sparc_TLS_IE_LD
Definition: SparcMCExpr.h:57
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::SparcMCExpr::VK_Sparc_TLS_GD_LO10
@ VK_Sparc_TLS_GD_LO10
Definition: SparcMCExpr.h:45
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1087
llvm::SparcMCExpr::VK_Sparc_TLS_IE_HI22
@ VK_Sparc_TLS_IE_HI22
Definition: SparcMCExpr.h:55
llvm::LowerSparcMachineInstrToMCInst
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP)
Definition: SparcMCInstLower.cpp:93
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
llvm::MachineOperand::isCPI
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:333
llvm::SparcMCExpr::VariantKind
VariantKind
Definition: SparcMCExpr.h:25
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
printMemOperand
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
Definition: SelectionDAGDumper.cpp:513
createPCXCallOP
static MCOperand createPCXCallOP(MCSymbol *Label, MCContext &OutContext)
Definition: SparcAsmPrinter.cpp:81
llvm::SparcMCExpr::VK_Sparc_PC10
@ VK_Sparc_PC10
Definition: SparcMCExpr.h:36
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:609
SparcTargetStreamer.h
SparcTargetMachine.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::SparcMCExpr::VK_Sparc_WDISP30
@ VK_Sparc_WDISP30
Definition: SparcMCExpr.h:42
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
Mangler.h
llvm::SparcMCExpr::VK_Sparc_HH
@ VK_Sparc_HH
Definition: SparcMCExpr.h:32
EmitOR
static void EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:137
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:524
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SparcMCExpr::printVariantKind
static bool printVariantKind(raw_ostream &OS, VariantKind Kind)
Definition: SparcMCExpr.cpp:42
LLVMInitializeSparcAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcAsmPrinter()
Definition: SparcAsmPrinter.cpp:442
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
createSparcMCOperand
static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, MCSymbol *Sym, MCContext &OutContext)
Definition: SparcAsmPrinter.cpp:73
EmitADD
static void EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:143
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SparcMCExpr::VK_Sparc_HI
@ VK_Sparc_HI
Definition: SparcMCExpr.h:28
llvm::SparcMCExpr::VK_Sparc_TLS_GD_HI22
@ VK_Sparc_TLS_GD_HI22
Definition: SparcMCExpr.h:44
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::SparcMCExpr::VK_Sparc_TLS_GD_ADD
@ VK_Sparc_TLS_GD_ADD
Definition: SparcMCExpr.h:46
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
@ VK_Sparc_TLS_LDO_LOX10
Definition: SparcMCExpr.h:53
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
Sparc.h
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
EmitSETHI
static void EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI)
Definition: SparcAsmPrinter.cpp:114
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:385
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
MCStreamer.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::SparcMCExpr::VK_Sparc_LO
@ VK_Sparc_LO
Definition: SparcMCExpr.h:27
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1338
raw_ostream.h
llvm::SPISD::TLS_CALL
@ TLS_CALL
Definition: SparcISelLowering.h:49
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:599
llvm::getTheSparcV9Target
Target & getTheSparcV9Target()
Definition: SparcTargetInfo.cpp:17
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
getRegisterName
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
Definition: MIParser.cpp:1326
TargetLoweringObjectFileImpl.h