LLVM  13.0.0git
SelectionDAGDumper.cpp
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1 //===- SelectionDAGDumper.cpp - Implement SelectionDAG::dump() ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the SelectionDAG::dump method and friends.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/None.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/StringExtras.h"
29 #include "llvm/Config/llvm-config.h"
30 #include "llvm/IR/BasicBlock.h"
31 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DebugLoc.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/IR/Value.h"
38 #include "llvm/Support/Casting.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/Printable.h"
48 #include "SDNodeDbgValue.h"
49 #include <cstdint>
50 #include <iterator>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool>
55 VerboseDAGDumping("dag-dump-verbose", cl::Hidden,
56  cl::desc("Display more information when dumping selection "
57  "DAG nodes."));
58 
59 std::string SDNode::getOperationName(const SelectionDAG *G) const {
60  switch (getOpcode()) {
61  default:
63  return "<<Unknown DAG Node>>";
64  if (isMachineOpcode()) {
65  if (G)
66  if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
67  if (getMachineOpcode() < TII->getNumOpcodes())
68  return std::string(TII->getName(getMachineOpcode()));
69  return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
70  }
71  if (G) {
72  const TargetLowering &TLI = G->getTargetLoweringInfo();
73  const char *Name = TLI.getTargetNodeName(getOpcode());
74  if (Name) return Name;
75  return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
76  }
77  return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
78 
79 #ifndef NDEBUG
80  case ISD::DELETED_NODE: return "<<Deleted Node!>>";
81 #endif
82  case ISD::PREFETCH: return "Prefetch";
83  case ISD::ATOMIC_FENCE: return "AtomicFence";
84  case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
85  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
86  case ISD::ATOMIC_SWAP: return "AtomicSwap";
87  case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
88  case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
89  case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
90  case ISD::ATOMIC_LOAD_CLR: return "AtomicLoadClr";
91  case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
92  case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
93  case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
94  case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
95  case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
96  case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
97  case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
98  case ISD::ATOMIC_LOAD_FADD: return "AtomicLoadFAdd";
99  case ISD::ATOMIC_LOAD: return "AtomicLoad";
100  case ISD::ATOMIC_STORE: return "AtomicStore";
101  case ISD::PCMARKER: return "PCMarker";
102  case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
103  case ISD::SRCVALUE: return "SrcValue";
104  case ISD::MDNODE_SDNODE: return "MDNode";
105  case ISD::EntryToken: return "EntryToken";
106  case ISD::TokenFactor: return "TokenFactor";
107  case ISD::AssertSext: return "AssertSext";
108  case ISD::AssertZext: return "AssertZext";
109  case ISD::AssertAlign: return "AssertAlign";
110 
111  case ISD::BasicBlock: return "BasicBlock";
112  case ISD::VALUETYPE: return "ValueType";
113  case ISD::Register: return "Register";
114  case ISD::RegisterMask: return "RegisterMask";
115  case ISD::Constant:
116  if (cast<ConstantSDNode>(this)->isOpaque())
117  return "OpaqueConstant";
118  return "Constant";
119  case ISD::ConstantFP: return "ConstantFP";
120  case ISD::GlobalAddress: return "GlobalAddress";
121  case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
122  case ISD::FrameIndex: return "FrameIndex";
123  case ISD::JumpTable: return "JumpTable";
124  case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
125  case ISD::RETURNADDR: return "RETURNADDR";
126  case ISD::ADDROFRETURNADDR: return "ADDROFRETURNADDR";
127  case ISD::FRAMEADDR: return "FRAMEADDR";
128  case ISD::SPONENTRY: return "SPONENTRY";
129  case ISD::LOCAL_RECOVER: return "LOCAL_RECOVER";
130  case ISD::READ_REGISTER: return "READ_REGISTER";
131  case ISD::WRITE_REGISTER: return "WRITE_REGISTER";
132  case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
133  case ISD::EH_DWARF_CFA: return "EH_DWARF_CFA";
134  case ISD::EH_RETURN: return "EH_RETURN";
135  case ISD::EH_SJLJ_SETJMP: return "EH_SJLJ_SETJMP";
136  case ISD::EH_SJLJ_LONGJMP: return "EH_SJLJ_LONGJMP";
137  case ISD::EH_SJLJ_SETUP_DISPATCH: return "EH_SJLJ_SETUP_DISPATCH";
138  case ISD::ConstantPool: return "ConstantPool";
139  case ISD::TargetIndex: return "TargetIndex";
140  case ISD::ExternalSymbol: return "ExternalSymbol";
141  case ISD::BlockAddress: return "BlockAddress";
143  case ISD::INTRINSIC_VOID:
144  case ISD::INTRINSIC_W_CHAIN: {
145  unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
146  unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
147  if (IID < Intrinsic::num_intrinsics)
148  return Intrinsic::getName((Intrinsic::ID)IID, None);
149  else if (!G)
150  return "Unknown intrinsic";
151  else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
152  return TII->getName(IID);
153  llvm_unreachable("Invalid intrinsic ID");
154  }
155 
156  case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
157  case ISD::TargetConstant:
158  if (cast<ConstantSDNode>(this)->isOpaque())
159  return "OpaqueTargetConstant";
160  return "TargetConstant";
161  case ISD::TargetConstantFP: return "TargetConstantFP";
162  case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
163  case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
164  case ISD::TargetFrameIndex: return "TargetFrameIndex";
165  case ISD::TargetJumpTable: return "TargetJumpTable";
166  case ISD::TargetConstantPool: return "TargetConstantPool";
167  case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
168  case ISD::MCSymbol: return "MCSymbol";
169  case ISD::TargetBlockAddress: return "TargetBlockAddress";
170 
171  case ISD::CopyToReg: return "CopyToReg";
172  case ISD::CopyFromReg: return "CopyFromReg";
173  case ISD::UNDEF: return "undef";
174  case ISD::VSCALE: return "vscale";
175  case ISD::MERGE_VALUES: return "merge_values";
176  case ISD::INLINEASM: return "inlineasm";
177  case ISD::INLINEASM_BR: return "inlineasm_br";
178  case ISD::EH_LABEL: return "eh_label";
179  case ISD::ANNOTATION_LABEL: return "annotation_label";
180  case ISD::HANDLENODE: return "handlenode";
181 
182  // Unary operators
183  case ISD::FABS: return "fabs";
184  case ISD::FMINNUM: return "fminnum";
185  case ISD::STRICT_FMINNUM: return "strict_fminnum";
186  case ISD::FMAXNUM: return "fmaxnum";
187  case ISD::STRICT_FMAXNUM: return "strict_fmaxnum";
188  case ISD::FMINNUM_IEEE: return "fminnum_ieee";
189  case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
190  case ISD::FMINIMUM: return "fminimum";
191  case ISD::STRICT_FMINIMUM: return "strict_fminimum";
192  case ISD::FMAXIMUM: return "fmaximum";
193  case ISD::STRICT_FMAXIMUM: return "strict_fmaximum";
194  case ISD::FNEG: return "fneg";
195  case ISD::FSQRT: return "fsqrt";
196  case ISD::STRICT_FSQRT: return "strict_fsqrt";
197  case ISD::FCBRT: return "fcbrt";
198  case ISD::FSIN: return "fsin";
199  case ISD::STRICT_FSIN: return "strict_fsin";
200  case ISD::FCOS: return "fcos";
201  case ISD::STRICT_FCOS: return "strict_fcos";
202  case ISD::FSINCOS: return "fsincos";
203  case ISD::FTRUNC: return "ftrunc";
204  case ISD::STRICT_FTRUNC: return "strict_ftrunc";
205  case ISD::FFLOOR: return "ffloor";
206  case ISD::STRICT_FFLOOR: return "strict_ffloor";
207  case ISD::FCEIL: return "fceil";
208  case ISD::STRICT_FCEIL: return "strict_fceil";
209  case ISD::FRINT: return "frint";
210  case ISD::STRICT_FRINT: return "strict_frint";
211  case ISD::FNEARBYINT: return "fnearbyint";
212  case ISD::STRICT_FNEARBYINT: return "strict_fnearbyint";
213  case ISD::FROUND: return "fround";
214  case ISD::STRICT_FROUND: return "strict_fround";
215  case ISD::FROUNDEVEN: return "froundeven";
216  case ISD::STRICT_FROUNDEVEN: return "strict_froundeven";
217  case ISD::FEXP: return "fexp";
218  case ISD::STRICT_FEXP: return "strict_fexp";
219  case ISD::FEXP2: return "fexp2";
220  case ISD::STRICT_FEXP2: return "strict_fexp2";
221  case ISD::FLOG: return "flog";
222  case ISD::STRICT_FLOG: return "strict_flog";
223  case ISD::FLOG2: return "flog2";
224  case ISD::STRICT_FLOG2: return "strict_flog2";
225  case ISD::FLOG10: return "flog10";
226  case ISD::STRICT_FLOG10: return "strict_flog10";
227 
228  // Binary operators
229  case ISD::ADD: return "add";
230  case ISD::SUB: return "sub";
231  case ISD::MUL: return "mul";
232  case ISD::MULHU: return "mulhu";
233  case ISD::MULHS: return "mulhs";
234  case ISD::SDIV: return "sdiv";
235  case ISD::UDIV: return "udiv";
236  case ISD::SREM: return "srem";
237  case ISD::UREM: return "urem";
238  case ISD::SMUL_LOHI: return "smul_lohi";
239  case ISD::UMUL_LOHI: return "umul_lohi";
240  case ISD::SDIVREM: return "sdivrem";
241  case ISD::UDIVREM: return "udivrem";
242  case ISD::AND: return "and";
243  case ISD::OR: return "or";
244  case ISD::XOR: return "xor";
245  case ISD::SHL: return "shl";
246  case ISD::SRA: return "sra";
247  case ISD::SRL: return "srl";
248  case ISD::ROTL: return "rotl";
249  case ISD::ROTR: return "rotr";
250  case ISD::FSHL: return "fshl";
251  case ISD::FSHR: return "fshr";
252  case ISD::FADD: return "fadd";
253  case ISD::STRICT_FADD: return "strict_fadd";
254  case ISD::FSUB: return "fsub";
255  case ISD::STRICT_FSUB: return "strict_fsub";
256  case ISD::FMUL: return "fmul";
257  case ISD::STRICT_FMUL: return "strict_fmul";
258  case ISD::FDIV: return "fdiv";
259  case ISD::STRICT_FDIV: return "strict_fdiv";
260  case ISD::FMA: return "fma";
261  case ISD::STRICT_FMA: return "strict_fma";
262  case ISD::FMAD: return "fmad";
263  case ISD::FREM: return "frem";
264  case ISD::STRICT_FREM: return "strict_frem";
265  case ISD::FCOPYSIGN: return "fcopysign";
266  case ISD::FGETSIGN: return "fgetsign";
267  case ISD::FCANONICALIZE: return "fcanonicalize";
268  case ISD::FPOW: return "fpow";
269  case ISD::STRICT_FPOW: return "strict_fpow";
270  case ISD::SMIN: return "smin";
271  case ISD::SMAX: return "smax";
272  case ISD::UMIN: return "umin";
273  case ISD::UMAX: return "umax";
274 
275  case ISD::FPOWI: return "fpowi";
276  case ISD::STRICT_FPOWI: return "strict_fpowi";
277  case ISD::SETCC: return "setcc";
278  case ISD::SETCCCARRY: return "setcccarry";
279  case ISD::STRICT_FSETCC: return "strict_fsetcc";
280  case ISD::STRICT_FSETCCS: return "strict_fsetccs";
281  case ISD::SELECT: return "select";
282  case ISD::VSELECT: return "vselect";
283  case ISD::SELECT_CC: return "select_cc";
284  case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
285  case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
286  case ISD::CONCAT_VECTORS: return "concat_vectors";
287  case ISD::INSERT_SUBVECTOR: return "insert_subvector";
288  case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
289  case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
290  case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
291  case ISD::VECTOR_SPLICE: return "vector_splice";
292  case ISD::SPLAT_VECTOR: return "splat_vector";
293  case ISD::SPLAT_VECTOR_PARTS: return "splat_vector_parts";
294  case ISD::VECTOR_REVERSE: return "vector_reverse";
295  case ISD::STEP_VECTOR: return "step_vector";
296  case ISD::CARRY_FALSE: return "carry_false";
297  case ISD::ADDC: return "addc";
298  case ISD::ADDE: return "adde";
299  case ISD::ADDCARRY: return "addcarry";
300  case ISD::SADDO_CARRY: return "saddo_carry";
301  case ISD::SADDO: return "saddo";
302  case ISD::UADDO: return "uaddo";
303  case ISD::SSUBO: return "ssubo";
304  case ISD::USUBO: return "usubo";
305  case ISD::SMULO: return "smulo";
306  case ISD::UMULO: return "umulo";
307  case ISD::SUBC: return "subc";
308  case ISD::SUBE: return "sube";
309  case ISD::SUBCARRY: return "subcarry";
310  case ISD::SSUBO_CARRY: return "ssubo_carry";
311  case ISD::SHL_PARTS: return "shl_parts";
312  case ISD::SRA_PARTS: return "sra_parts";
313  case ISD::SRL_PARTS: return "srl_parts";
314 
315  case ISD::SADDSAT: return "saddsat";
316  case ISD::UADDSAT: return "uaddsat";
317  case ISD::SSUBSAT: return "ssubsat";
318  case ISD::USUBSAT: return "usubsat";
319  case ISD::SSHLSAT: return "sshlsat";
320  case ISD::USHLSAT: return "ushlsat";
321 
322  case ISD::SMULFIX: return "smulfix";
323  case ISD::SMULFIXSAT: return "smulfixsat";
324  case ISD::UMULFIX: return "umulfix";
325  case ISD::UMULFIXSAT: return "umulfixsat";
326 
327  case ISD::SDIVFIX: return "sdivfix";
328  case ISD::SDIVFIXSAT: return "sdivfixsat";
329  case ISD::UDIVFIX: return "udivfix";
330  case ISD::UDIVFIXSAT: return "udivfixsat";
331 
332  // Conversion operators.
333  case ISD::SIGN_EXTEND: return "sign_extend";
334  case ISD::ZERO_EXTEND: return "zero_extend";
335  case ISD::ANY_EXTEND: return "any_extend";
336  case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
337  case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
338  case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
339  case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
340  case ISD::TRUNCATE: return "truncate";
341  case ISD::FP_ROUND: return "fp_round";
342  case ISD::STRICT_FP_ROUND: return "strict_fp_round";
343  case ISD::FP_EXTEND: return "fp_extend";
344  case ISD::STRICT_FP_EXTEND: return "strict_fp_extend";
345 
346  case ISD::SINT_TO_FP: return "sint_to_fp";
347  case ISD::STRICT_SINT_TO_FP: return "strict_sint_to_fp";
348  case ISD::UINT_TO_FP: return "uint_to_fp";
349  case ISD::STRICT_UINT_TO_FP: return "strict_uint_to_fp";
350  case ISD::FP_TO_SINT: return "fp_to_sint";
351  case ISD::STRICT_FP_TO_SINT: return "strict_fp_to_sint";
352  case ISD::FP_TO_UINT: return "fp_to_uint";
353  case ISD::STRICT_FP_TO_UINT: return "strict_fp_to_uint";
354  case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat";
355  case ISD::FP_TO_UINT_SAT: return "fp_to_uint_sat";
356  case ISD::BITCAST: return "bitcast";
357  case ISD::ADDRSPACECAST: return "addrspacecast";
358  case ISD::FP16_TO_FP: return "fp16_to_fp";
359  case ISD::STRICT_FP16_TO_FP: return "strict_fp16_to_fp";
360  case ISD::FP_TO_FP16: return "fp_to_fp16";
361  case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16";
362  case ISD::LROUND: return "lround";
363  case ISD::STRICT_LROUND: return "strict_lround";
364  case ISD::LLROUND: return "llround";
365  case ISD::STRICT_LLROUND: return "strict_llround";
366  case ISD::LRINT: return "lrint";
367  case ISD::STRICT_LRINT: return "strict_lrint";
368  case ISD::LLRINT: return "llrint";
369  case ISD::STRICT_LLRINT: return "strict_llrint";
370 
371  // Control flow instructions
372  case ISD::BR: return "br";
373  case ISD::BRIND: return "brind";
374  case ISD::BR_JT: return "br_jt";
375  case ISD::BRCOND: return "brcond";
376  case ISD::BR_CC: return "br_cc";
377  case ISD::CALLSEQ_START: return "callseq_start";
378  case ISD::CALLSEQ_END: return "callseq_end";
379 
380  // EH instructions
381  case ISD::CATCHRET: return "catchret";
382  case ISD::CLEANUPRET: return "cleanupret";
383 
384  // Other operators
385  case ISD::LOAD: return "load";
386  case ISD::STORE: return "store";
387  case ISD::MLOAD: return "masked_load";
388  case ISD::MSTORE: return "masked_store";
389  case ISD::MGATHER: return "masked_gather";
390  case ISD::MSCATTER: return "masked_scatter";
391  case ISD::VAARG: return "vaarg";
392  case ISD::VACOPY: return "vacopy";
393  case ISD::VAEND: return "vaend";
394  case ISD::VASTART: return "vastart";
395  case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
396  case ISD::EXTRACT_ELEMENT: return "extract_element";
397  case ISD::BUILD_PAIR: return "build_pair";
398  case ISD::STACKSAVE: return "stacksave";
399  case ISD::STACKRESTORE: return "stackrestore";
400  case ISD::TRAP: return "trap";
401  case ISD::DEBUGTRAP: return "debugtrap";
402  case ISD::UBSANTRAP: return "ubsantrap";
403  case ISD::LIFETIME_START: return "lifetime.start";
404  case ISD::LIFETIME_END: return "lifetime.end";
405  case ISD::PSEUDO_PROBE:
406  return "pseudoprobe";
407  case ISD::GC_TRANSITION_START: return "gc_transition.start";
408  case ISD::GC_TRANSITION_END: return "gc_transition.end";
409  case ISD::GET_DYNAMIC_AREA_OFFSET: return "get.dynamic.area.offset";
410  case ISD::FREEZE: return "freeze";
412  return "call_setup";
414  return "call_alloc";
415 
416  // Floating point environment manipulation
417  case ISD::FLT_ROUNDS_: return "flt_rounds";
418  case ISD::SET_ROUNDING: return "set_rounding";
419 
420  // Bit manipulation
421  case ISD::ABS: return "abs";
422  case ISD::BITREVERSE: return "bitreverse";
423  case ISD::BSWAP: return "bswap";
424  case ISD::CTPOP: return "ctpop";
425  case ISD::CTTZ: return "cttz";
426  case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef";
427  case ISD::CTLZ: return "ctlz";
428  case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef";
429  case ISD::PARITY: return "parity";
430 
431  // Trampolines
432  case ISD::INIT_TRAMPOLINE: return "init_trampoline";
433  case ISD::ADJUST_TRAMPOLINE: return "adjust_trampoline";
434 
435  case ISD::CONDCODE:
436  switch (cast<CondCodeSDNode>(this)->get()) {
437  default: llvm_unreachable("Unknown setcc condition!");
438  case ISD::SETOEQ: return "setoeq";
439  case ISD::SETOGT: return "setogt";
440  case ISD::SETOGE: return "setoge";
441  case ISD::SETOLT: return "setolt";
442  case ISD::SETOLE: return "setole";
443  case ISD::SETONE: return "setone";
444 
445  case ISD::SETO: return "seto";
446  case ISD::SETUO: return "setuo";
447  case ISD::SETUEQ: return "setueq";
448  case ISD::SETUGT: return "setugt";
449  case ISD::SETUGE: return "setuge";
450  case ISD::SETULT: return "setult";
451  case ISD::SETULE: return "setule";
452  case ISD::SETUNE: return "setune";
453 
454  case ISD::SETEQ: return "seteq";
455  case ISD::SETGT: return "setgt";
456  case ISD::SETGE: return "setge";
457  case ISD::SETLT: return "setlt";
458  case ISD::SETLE: return "setle";
459  case ISD::SETNE: return "setne";
460 
461  case ISD::SETTRUE: return "settrue";
462  case ISD::SETTRUE2: return "settrue2";
463  case ISD::SETFALSE: return "setfalse";
464  case ISD::SETFALSE2: return "setfalse2";
465  }
466  case ISD::VECREDUCE_FADD: return "vecreduce_fadd";
467  case ISD::VECREDUCE_SEQ_FADD: return "vecreduce_seq_fadd";
468  case ISD::VECREDUCE_FMUL: return "vecreduce_fmul";
469  case ISD::VECREDUCE_SEQ_FMUL: return "vecreduce_seq_fmul";
470  case ISD::VECREDUCE_ADD: return "vecreduce_add";
471  case ISD::VECREDUCE_MUL: return "vecreduce_mul";
472  case ISD::VECREDUCE_AND: return "vecreduce_and";
473  case ISD::VECREDUCE_OR: return "vecreduce_or";
474  case ISD::VECREDUCE_XOR: return "vecreduce_xor";
475  case ISD::VECREDUCE_SMAX: return "vecreduce_smax";
476  case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
477  case ISD::VECREDUCE_UMAX: return "vecreduce_umax";
478  case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
479  case ISD::VECREDUCE_FMAX: return "vecreduce_fmax";
480  case ISD::VECREDUCE_FMIN: return "vecreduce_fmin";
481 
482  // Vector Predication
483 #define BEGIN_REGISTER_VP_SDNODE(SDID, LEGALARG, NAME, ...) \
484  case ISD::SDID: \
485  return #NAME;
486 #include "llvm/IR/VPIntrinsics.def"
487  }
488 }
489 
491  switch (AM) {
492  default: return "";
493  case ISD::PRE_INC: return "<pre-inc>";
494  case ISD::PRE_DEC: return "<pre-dec>";
495  case ISD::POST_INC: return "<post-inc>";
496  case ISD::POST_DEC: return "<post-dec>";
497  }
498 }
499 
500 static Printable PrintNodeId(const SDNode &Node) {
501  return Printable([&Node](raw_ostream &OS) {
502 #ifndef NDEBUG
503  OS << 't' << Node.PersistentId;
504 #else
505  OS << (const void*)&Node;
506 #endif
507  });
508 }
509 
510 // Print the MMO with more information from the SelectionDAG.
511 static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
512  const MachineFunction *MF, const Module *M,
513  const MachineFrameInfo *MFI,
514  const TargetInstrInfo *TII, LLVMContext &Ctx) {
515  ModuleSlotTracker MST(M);
516  if (MF)
517  MST.incorporateFunction(MF->getFunction());
519  MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
520 }
521 
522 static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO,
523  const SelectionDAG *G) {
524  if (G) {
525  const MachineFunction *MF = &G->getMachineFunction();
526  return printMemOperand(OS, MMO, MF, MF->getFunction().getParent(),
527  &MF->getFrameInfo(), G->getSubtarget().getInstrInfo(),
528  *G->getContext());
529  } else {
530  LLVMContext Ctx;
531  return printMemOperand(OS, MMO, /*MF=*/nullptr, /*M=*/nullptr,
532  /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
533  }
534 }
535 
536 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
537 LLVM_DUMP_METHOD void SDNode::dump() const { dump(nullptr); }
538 
540  print(dbgs(), G);
541  dbgs() << '\n';
542 }
543 #endif
544 
546  for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
547  if (i) OS << ",";
548  if (getValueType(i) == MVT::Other)
549  OS << "ch";
550  else
551  OS << getValueType(i).getEVTString();
552  }
553 }
554 
556  if (getFlags().hasNoUnsignedWrap())
557  OS << " nuw";
558 
559  if (getFlags().hasNoSignedWrap())
560  OS << " nsw";
561 
562  if (getFlags().hasExact())
563  OS << " exact";
564 
565  if (getFlags().hasNoNaNs())
566  OS << " nnan";
567 
568  if (getFlags().hasNoInfs())
569  OS << " ninf";
570 
571  if (getFlags().hasNoSignedZeros())
572  OS << " nsz";
573 
574  if (getFlags().hasAllowReciprocal())
575  OS << " arcp";
576 
577  if (getFlags().hasAllowContract())
578  OS << " contract";
579 
580  if (getFlags().hasApproximateFuncs())
581  OS << " afn";
582 
583  if (getFlags().hasAllowReassociation())
584  OS << " reassoc";
585 
586  if (getFlags().hasNoFPExcept())
587  OS << " nofpexcept";
588 
589  if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) {
590  if (!MN->memoperands_empty()) {
591  OS << "<";
592  OS << "Mem:";
593  for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
594  e = MN->memoperands_end(); i != e; ++i) {
595  printMemOperand(OS, **i, G);
596  if (std::next(i) != e)
597  OS << " ";
598  }
599  OS << ">";
600  }
601  } else if (const ShuffleVectorSDNode *SVN =
602  dyn_cast<ShuffleVectorSDNode>(this)) {
603  OS << "<";
604  for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
605  int Idx = SVN->getMaskElt(i);
606  if (i) OS << ",";
607  if (Idx < 0)
608  OS << "u";
609  else
610  OS << Idx;
611  }
612  OS << ">";
613  } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
614  OS << '<' << CSDN->getAPIntValue() << '>';
615  } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
616  if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEsingle())
617  OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
618  else if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEdouble())
619  OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
620  else {
621  OS << "<APFloat(";
622  CSDN->getValueAPF().bitcastToAPInt().print(OS, false);
623  OS << ")>";
624  }
625  } else if (const GlobalAddressSDNode *GADN =
626  dyn_cast<GlobalAddressSDNode>(this)) {
627  int64_t offset = GADN->getOffset();
628  OS << '<';
629  GADN->getGlobal()->printAsOperand(OS);
630  OS << '>';
631  if (offset > 0)
632  OS << " + " << offset;
633  else
634  OS << " " << offset;
635  if (unsigned int TF = GADN->getTargetFlags())
636  OS << " [TF=" << TF << ']';
637  } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
638  OS << "<" << FIDN->getIndex() << ">";
639  } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
640  OS << "<" << JTDN->getIndex() << ">";
641  if (unsigned int TF = JTDN->getTargetFlags())
642  OS << " [TF=" << TF << ']';
643  } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
644  int offset = CP->getOffset();
645  if (CP->isMachineConstantPoolEntry())
646  OS << "<" << *CP->getMachineCPVal() << ">";
647  else
648  OS << "<" << *CP->getConstVal() << ">";
649  if (offset > 0)
650  OS << " + " << offset;
651  else
652  OS << " " << offset;
653  if (unsigned int TF = CP->getTargetFlags())
654  OS << " [TF=" << TF << ']';
655  } else if (const TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(this)) {
656  OS << "<" << TI->getIndex() << '+' << TI->getOffset() << ">";
657  if (unsigned TF = TI->getTargetFlags())
658  OS << " [TF=" << TF << ']';
659  } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
660  OS << "<";
661  const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
662  if (LBB)
663  OS << LBB->getName() << " ";
664  OS << (const void*)BBDN->getBasicBlock() << ">";
665  } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
666  OS << ' ' << printReg(R->getReg(),
667  G ? G->getSubtarget().getRegisterInfo() : nullptr);
668  } else if (const ExternalSymbolSDNode *ES =
669  dyn_cast<ExternalSymbolSDNode>(this)) {
670  OS << "'" << ES->getSymbol() << "'";
671  if (unsigned int TF = ES->getTargetFlags())
672  OS << " [TF=" << TF << ']';
673  } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
674  if (M->getValue())
675  OS << "<" << M->getValue() << ">";
676  else
677  OS << "<null>";
678  } else if (const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(this)) {
679  if (MD->getMD())
680  OS << "<" << MD->getMD() << ">";
681  else
682  OS << "<null>";
683  } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
684  OS << ":" << N->getVT().getEVTString();
685  }
686  else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
687  OS << "<";
688 
689  printMemOperand(OS, *LD->getMemOperand(), G);
690 
691  bool doExt = true;
692  switch (LD->getExtensionType()) {
693  default: doExt = false; break;
694  case ISD::EXTLOAD: OS << ", anyext"; break;
695  case ISD::SEXTLOAD: OS << ", sext"; break;
696  case ISD::ZEXTLOAD: OS << ", zext"; break;
697  }
698  if (doExt)
699  OS << " from " << LD->getMemoryVT().getEVTString();
700 
701  const char *AM = getIndexedModeName(LD->getAddressingMode());
702  if (*AM)
703  OS << ", " << AM;
704 
705  OS << ">";
706  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
707  OS << "<";
708  printMemOperand(OS, *ST->getMemOperand(), G);
709 
710  if (ST->isTruncatingStore())
711  OS << ", trunc to " << ST->getMemoryVT().getEVTString();
712 
713  const char *AM = getIndexedModeName(ST->getAddressingMode());
714  if (*AM)
715  OS << ", " << AM;
716 
717  OS << ">";
718  } else if (const MaskedLoadSDNode *MLd = dyn_cast<MaskedLoadSDNode>(this)) {
719  OS << "<";
720 
721  printMemOperand(OS, *MLd->getMemOperand(), G);
722 
723  bool doExt = true;
724  switch (MLd->getExtensionType()) {
725  default: doExt = false; break;
726  case ISD::EXTLOAD: OS << ", anyext"; break;
727  case ISD::SEXTLOAD: OS << ", sext"; break;
728  case ISD::ZEXTLOAD: OS << ", zext"; break;
729  }
730  if (doExt)
731  OS << " from " << MLd->getMemoryVT().getEVTString();
732 
733  const char *AM = getIndexedModeName(MLd->getAddressingMode());
734  if (*AM)
735  OS << ", " << AM;
736 
737  if (MLd->isExpandingLoad())
738  OS << ", expanding";
739 
740  OS << ">";
741  } else if (const MaskedStoreSDNode *MSt = dyn_cast<MaskedStoreSDNode>(this)) {
742  OS << "<";
743  printMemOperand(OS, *MSt->getMemOperand(), G);
744 
745  if (MSt->isTruncatingStore())
746  OS << ", trunc to " << MSt->getMemoryVT().getEVTString();
747 
748  const char *AM = getIndexedModeName(MSt->getAddressingMode());
749  if (*AM)
750  OS << ", " << AM;
751 
752  if (MSt->isCompressingStore())
753  OS << ", compressing";
754 
755  OS << ">";
756  } else if (const auto *MGather = dyn_cast<MaskedGatherSDNode>(this)) {
757  OS << "<";
758  printMemOperand(OS, *MGather->getMemOperand(), G);
759 
760  bool doExt = true;
761  switch (MGather->getExtensionType()) {
762  default: doExt = false; break;
763  case ISD::EXTLOAD: OS << ", anyext"; break;
764  case ISD::SEXTLOAD: OS << ", sext"; break;
765  case ISD::ZEXTLOAD: OS << ", zext"; break;
766  }
767  if (doExt)
768  OS << " from " << MGather->getMemoryVT().getEVTString();
769 
770  auto Signed = MGather->isIndexSigned() ? "signed" : "unsigned";
771  auto Scaled = MGather->isIndexScaled() ? "scaled" : "unscaled";
772  OS << ", " << Signed << " " << Scaled << " offset";
773 
774  OS << ">";
775  } else if (const auto *MScatter = dyn_cast<MaskedScatterSDNode>(this)) {
776  OS << "<";
777  printMemOperand(OS, *MScatter->getMemOperand(), G);
778 
779  if (MScatter->isTruncatingStore())
780  OS << ", trunc to " << MScatter->getMemoryVT().getEVTString();
781 
782  auto Signed = MScatter->isIndexSigned() ? "signed" : "unsigned";
783  auto Scaled = MScatter->isIndexScaled() ? "scaled" : "unscaled";
784  OS << ", " << Signed << " " << Scaled << " offset";
785 
786  OS << ">";
787  } else if (const MemSDNode *M = dyn_cast<MemSDNode>(this)) {
788  OS << "<";
789  printMemOperand(OS, *M->getMemOperand(), G);
790  OS << ">";
791  } else if (const BlockAddressSDNode *BA =
792  dyn_cast<BlockAddressSDNode>(this)) {
793  int64_t offset = BA->getOffset();
794  OS << "<";
795  BA->getBlockAddress()->getFunction()->printAsOperand(OS, false);
796  OS << ", ";
797  BA->getBlockAddress()->getBasicBlock()->printAsOperand(OS, false);
798  OS << ">";
799  if (offset > 0)
800  OS << " + " << offset;
801  else
802  OS << " " << offset;
803  if (unsigned int TF = BA->getTargetFlags())
804  OS << " [TF=" << TF << ']';
805  } else if (const AddrSpaceCastSDNode *ASC =
806  dyn_cast<AddrSpaceCastSDNode>(this)) {
807  OS << '['
808  << ASC->getSrcAddressSpace()
809  << " -> "
810  << ASC->getDestAddressSpace()
811  << ']';
812  } else if (const LifetimeSDNode *LN = dyn_cast<LifetimeSDNode>(this)) {
813  if (LN->hasOffset())
814  OS << "<" << LN->getOffset() << " to " << LN->getOffset() + LN->getSize() << ">";
815  }
816 
817  if (VerboseDAGDumping) {
818  if (unsigned Order = getIROrder())
819  OS << " [ORD=" << Order << ']';
820 
821  if (getNodeId() != -1)
822  OS << " [ID=" << getNodeId() << ']';
823  if (!(isa<ConstantSDNode>(this) || (isa<ConstantFPSDNode>(this))))
824  OS << " # D:" << isDivergent();
825 
826  if (G && !G->GetDbgValues(this).empty()) {
827  OS << " [NoOfDbgValues=" << G->GetDbgValues(this).size() << ']';
828  for (SDDbgValue *Dbg : G->GetDbgValues(this))
829  if (!Dbg->isInvalidated())
830  Dbg->print(OS);
831  } else if (getHasDebugValue())
832  OS << " [NoOfDbgValues>0]";
833  }
834 }
835 
836 LLVM_DUMP_METHOD void SDDbgValue::print(raw_ostream &OS) const {
837  OS << " DbgVal(Order=" << getOrder() << ')';
838  if (isInvalidated())
839  OS << "(Invalidated)";
840  if (isEmitted())
841  OS << "(Emitted)";
842  OS << "(";
843  bool Comma = false;
844  for (const SDDbgOperand &Op : getLocationOps()) {
845  if (Comma)
846  OS << ", ";
847  switch (Op.getKind()) {
848  case SDDbgOperand::SDNODE:
849  if (Op.getSDNode())
850  OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':' << Op.getResNo();
851  else
852  OS << "SDNODE";
853  break;
854  case SDDbgOperand::CONST:
855  OS << "CONST";
856  break;
857  case SDDbgOperand::FRAMEIX:
858  OS << "FRAMEIX=" << Op.getFrameIx();
859  break;
860  case SDDbgOperand::VREG:
861  OS << "VREG=" << Op.getVReg();
862  break;
863  }
864  Comma = true;
865  }
866  OS << ")";
867  if (isIndirect()) OS << "(Indirect)";
868  if (isVariadic())
869  OS << "(Variadic)";
870  OS << ":\"" << Var->getName() << '"';
871 #ifndef NDEBUG
872  if (Expr->getNumElements())
873  Expr->dump();
874 #endif
875 }
876 
877 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
878 LLVM_DUMP_METHOD void SDDbgValue::dump() const {
879  if (isInvalidated())
880  return;
881  print(dbgs());
882  dbgs() << "\n";
883 }
884 #endif
885 
886 /// Return true if this node is so simple that we should just print it inline
887 /// if it appears as an operand.
888 static bool shouldPrintInline(const SDNode &Node, const SelectionDAG *G) {
889  // Avoid lots of cluttering when inline printing nodes with associated
890  // DbgValues in verbose mode.
891  if (VerboseDAGDumping && G && !G->GetDbgValues(&Node).empty())
892  return false;
893  if (Node.getOpcode() == ISD::EntryToken)
894  return false;
895  return Node.getNumOperands() == 0;
896 }
897 
898 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
899 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
900  for (const SDValue &Op : N->op_values()) {
901  if (shouldPrintInline(*Op.getNode(), G))
902  continue;
903  if (Op.getNode()->hasOneUse())
904  DumpNodes(Op.getNode(), indent+2, G);
905  }
906 
907  dbgs().indent(indent);
908  N->dump(G);
909 }
910 
911 LLVM_DUMP_METHOD void SelectionDAG::dump() const {
912  dbgs() << "SelectionDAG has " << AllNodes.size() << " nodes:\n";
913 
914  for (const SDNode &N : allnodes()) {
915  if (!N.hasOneUse() && &N != getRoot().getNode() &&
916  (!shouldPrintInline(N, this) || N.use_empty()))
917  DumpNodes(&N, 2, this);
918  }
919 
920  if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
921  dbgs() << "\n";
922 
923  if (VerboseDAGDumping) {
924  if (DbgBegin() != DbgEnd())
925  dbgs() << "SDDbgValues:\n";
926  for (auto *Dbg : make_range(DbgBegin(), DbgEnd()))
927  Dbg->dump();
928  if (ByvalParmDbgBegin() != ByvalParmDbgEnd())
929  dbgs() << "Byval SDDbgValues:\n";
930  for (auto *Dbg : make_range(ByvalParmDbgBegin(), ByvalParmDbgEnd()))
931  Dbg->dump();
932  }
933  dbgs() << "\n";
934 }
935 #endif
936 
937 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
938  OS << PrintNodeId(*this) << ": ";
939  print_types(OS, G);
940  OS << " = " << getOperationName(G);
941  print_details(OS, G);
942 }
943 
944 static bool printOperand(raw_ostream &OS, const SelectionDAG *G,
945  const SDValue Value) {
946  if (!Value.getNode()) {
947  OS << "<null>";
948  return false;
949  } else if (shouldPrintInline(*Value.getNode(), G)) {
950  OS << Value->getOperationName(G) << ':';
951  Value->print_types(OS, G);
952  Value->print_details(OS, G);
953  return true;
954  } else {
955  OS << PrintNodeId(*Value.getNode());
956  if (unsigned RN = Value.getResNo())
957  OS << ':' << RN;
958  return false;
959  }
960 }
961 
962 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
963 using VisitedSDNodeSet = SmallPtrSet<const SDNode *, 32>;
964 
965 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
966  const SelectionDAG *G, VisitedSDNodeSet &once) {
967  if (!once.insert(N).second) // If we've been here before, return now.
968  return;
969 
970  // Dump the current SDNode, but don't end the line yet.
971  OS.indent(indent);
972  N->printr(OS, G);
973 
974  // Having printed this SDNode, walk the children:
975  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
976  if (i) OS << ",";
977  OS << " ";
978 
979  const SDValue Op = N->getOperand(i);
980  bool printedInline = printOperand(OS, G, Op);
981  if (printedInline)
982  once.insert(Op.getNode());
983  }
984 
985  OS << "\n";
986 
987  // Dump children that have grandchildren on their own line(s).
988  for (const SDValue &Op : N->op_values())
989  DumpNodesr(OS, Op.getNode(), indent+2, G, once);
990 }
991 
992 LLVM_DUMP_METHOD void SDNode::dumpr() const {
993  VisitedSDNodeSet once;
994  DumpNodesr(dbgs(), this, 0, nullptr, once);
995 }
996 
997 LLVM_DUMP_METHOD void SDNode::dumpr(const SelectionDAG *G) const {
998  VisitedSDNodeSet once;
999  DumpNodesr(dbgs(), this, 0, G, once);
1000 }
1001 #endif
1002 
1003 static void printrWithDepthHelper(raw_ostream &OS, const SDNode *N,
1004  const SelectionDAG *G, unsigned depth,
1005  unsigned indent) {
1006  if (depth == 0)
1007  return;
1008 
1009  OS.indent(indent);
1010 
1011  N->print(OS, G);
1012 
1013  if (depth < 1)
1014  return;
1015 
1016  for (const SDValue &Op : N->op_values()) {
1017  // Don't follow chain operands.
1018  if (Op.getValueType() == MVT::Other)
1019  continue;
1020  OS << '\n';
1021  printrWithDepthHelper(OS, Op.getNode(), G, depth-1, indent+2);
1022  }
1023 }
1024 
1025 void SDNode::printrWithDepth(raw_ostream &OS, const SelectionDAG *G,
1026  unsigned depth) const {
1027  printrWithDepthHelper(OS, this, G, depth, 0);
1028 }
1029 
1030 void SDNode::printrFull(raw_ostream &OS, const SelectionDAG *G) const {
1031  // Don't print impossibly deep things.
1032  printrWithDepth(OS, G, 10);
1033 }
1034 
1035 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1036 LLVM_DUMP_METHOD
1037 void SDNode::dumprWithDepth(const SelectionDAG *G, unsigned depth) const {
1038  printrWithDepth(dbgs(), G, depth);
1039 }
1040 
1041 LLVM_DUMP_METHOD void SDNode::dumprFull(const SelectionDAG *G) const {
1042  // Don't print impossibly deep things.
1043  dumprWithDepth(G, 10);
1044 }
1045 #endif
1046 
1047 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
1048  printr(OS, G);
1049  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1050  if (i) OS << ", "; else OS << " ";
1051  printOperand(OS, G, getOperand(i));
1052  }
1053  if (DebugLoc DL = getDebugLoc()) {
1054  OS << ", ";
1055  DL.print(OS);
1056  }
1057 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::ISD::FPOWI
@ FPOWI
Definition: ISDOpcodes.h:862
llvm::ISD::FROUNDEVEN
@ FROUNDEVEN
Definition: ISDOpcodes.h:874
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:76
llvm::ISD::STRICT_FP_ROUND
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:445
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1354
ValueTypes.h
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1532
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:700
llvm::ISD::SETTRUE
@ SETTRUE
Definition: ISDOpcodes.h:1358
llvm::ISD::STRICT_FSETCC
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:456
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:557
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1365
llvm::ISD::INTRINSIC_VOID
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:192
llvm::ISD::SETO
@ SETO
Definition: ISDOpcodes.h:1350
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1290
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:499
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:312
llvm::ISD::STRICT_FSQRT
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:392
llvm
Definition: AllocatorList.h:23
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:74
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Definition: SelectionDAGNodes.h:958
llvm::ISD::VECTOR_REVERSE
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
Definition: ISDOpcodes.h:548
llvm::ISD::STRICT_FSIN
@ STRICT_FSIN
Definition: ISDOpcodes.h:395
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:623
llvm::ISD::FLT_ROUNDS_
@ FLT_ROUNDS_
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
Definition: ISDOpcodes.h:815
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1362
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:838
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1164
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1366
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:936
llvm::APFloatBase::IEEEsingle
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:163
DebugInfoMetadata.h
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:888
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:59
llvm::ISD::UDIVFIXSAT
@ UDIVFIXSAT
Definition: ISDOpcodes.h:368
llvm::ISD::STRICT_FMAXNUM
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:404
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1136
Printable.h
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:513
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1163
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1290
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1069
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:656
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::ISD::STRICT_UINT_TO_FP
@ STRICT_UINT_TO_FP
Definition: ISDOpcodes.h:430
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:304
llvm::ISD::STRICT_FMINNUM
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:405
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:921
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1129
llvm::ISD::CTTZ_ZERO_UNDEF
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:664
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:262
llvm::ISD::INIT_TRAMPOLINE
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:1069
llvm::ISD::MLOAD
@ MLOAD
Definition: ISDOpcodes.h:1146
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:652
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ISD::FP_TO_UINT_SAT
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:791
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1361
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1002
llvm::ISD::CONDCODE
@ CONDCODE
Definition: ISDOpcodes.h:66
llvm::ISD::TargetIndex
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition: ISDOpcodes.h:170
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2518
ErrorHandling.h
llvm::ISD::SDIVFIX
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:361
llvm::ISD::MGATHER
@ MGATHER
Definition: ISDOpcodes.h:1158
llvm::Intrinsic::getName
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:829
llvm::ISD::STEP_VECTOR
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
Definition: ISDOpcodes.h:606
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:978
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:865
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:722
llvm::ISD::USUBSAT
@ USUBSAT
Definition: ISDOpcodes.h:330
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
MachineBasicBlock.h
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:460
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:775
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
APInt.h
llvm::ISD::STRICT_FMAXIMUM
@ STRICT_FMAXIMUM
Definition: ISDOpcodes.h:415
llvm::ISD::USHLSAT
@ USHLSAT
Definition: ISDOpcodes.h:340
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1356
llvm::ISD::PREALLOCATED_SETUP
@ PREALLOCATED_SETUP
Definition: ISDOpcodes.h:1036
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:705
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:692
llvm::ISD::STRICT_FPOW
@ STRICT_FPOW
Definition: ISDOpcodes.h:393
llvm::ISD::CALLSEQ_START
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
Definition: ISDOpcodes.h:1016
llvm::ISD::SPLAT_VECTOR_PARTS
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
Definition: ISDOpcodes.h:593
llvm::ISD::VECREDUCE_FMAX
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1214
llvm::ISD::FMAXNUM_IEEE
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:896
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:229
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:892
llvm::ISD::SIGN_EXTEND_VECTOR_INREG
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:759
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1031
llvm::ISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1198
SDNodeDbgValue.h
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1344
SelectionDAG.h
llvm::ISD::FREEZE
@ FREEZE
Definition: ISDOpcodes.h:209
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:29
llvm::ISD::GC_TRANSITION_END
@ GC_TRANSITION_END
Definition: ISDOpcodes.h:1173
llvm::ISD::STRICT_FLOG
@ STRICT_FLOG
Definition: ISDOpcodes.h:399
llvm::ISD::CALLSEQ_END
@ CALLSEQ_END
Definition: ISDOpcodes.h:1017
llvm::ISD::STRICT_FP_TO_UINT
@ STRICT_FP_TO_UINT
Definition: ISDOpcodes.h:423
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1352
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:617
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1130
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:857
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:283
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:946
llvm::ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:134
llvm::ShuffleVectorSDNode
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
Definition: SelectionDAGNodes.h:1474
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:970
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1183
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::ISD::STRICT_FLOG2
@ STRICT_FLOG2
Definition: ISDOpcodes.h:401
llvm::ISD::STRICT_FROUND
@ STRICT_FROUND
Definition: ISDOpcodes.h:408
MachineValueType.h
llvm::ISD::BRIND
@ BRIND
BRIND - Indirect branch.
Definition: ISDOpcodes.h:932
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:650
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:140
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1226
llvm::ISD::GC_TRANSITION_START
@ GC_TRANSITION_START
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
Definition: ISDOpcodes.h:1172
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:875
CommandLine.h
llvm::ISD::STRICT_FDIV
@ STRICT_FDIV
Definition: ISDOpcodes.h:384
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:953
TargetLowering.h
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:653
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:621
llvm::ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:144
llvm::ISD::STRICT_FP_TO_SINT
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:422
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:71
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:684
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
hasNoUnsignedWrap
static bool hasNoUnsignedWrap(BinaryOperator &I)
Definition: InstructionCombining.cpp:281
TargetMachine.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:658
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
SelectionDAGNodes.h
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:669
llvm::ISD::SMULFIXSAT
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:354
Constants.h
llvm::ISD::STRICT_FRINT
@ STRICT_FRINT
Definition: ISDOpcodes.h:402
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:69
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:719
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:630
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1363
llvm::ISD::SMULFIX
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:348
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:989
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:737
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:196
llvm::ISD::STRICT_FNEARBYINT
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:403
llvm::ISD::ANY_EXTEND_VECTOR_INREG
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:748
Intrinsics.h
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::ISD::STRICT_FP16_TO_FP
@ STRICT_FP16_TO_FP
Definition: ISDOpcodes.h:850
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:873
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:725
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:648
llvm::ISD::STRICT_FLOG10
@ STRICT_FLOG10
Definition: ISDOpcodes.h:400
llvm::ISD::LLROUND
@ LLROUND
Definition: ISDOpcodes.h:877
llvm::ISD::FMINNUM_IEEE
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:895
llvm::ISD::GLOBAL_OFFSET_TABLE
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:80
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:249
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::ISD::DELETED_NODE
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
llvm::ISD::ADDRSPACECAST
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:842
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1128
llvm::ISD::MDNODE_SDNODE
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
Definition: ISDOpcodes.h:1047
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1135
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:729
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:872
llvm::ISD::FP16_TO_FP
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:848
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:871
llvm::ISD::ATOMIC_STORE
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:1104
llvm::ISD::AssertAlign
@ AssertAlign
Definition: ISDOpcodes.h:61
DebugLoc.h
SmallPtrSet.h
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:622
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:311
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1347
llvm::ISD::TargetGlobalAddress
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:157
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:584
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:905
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:201
llvm::None
const NoneType None
Definition: None.h:23
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:308
llvm::ISD::FCBRT
@ FCBRT
Definition: ISDOpcodes.h:859
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1348
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1353
llvm::ISD::VALUETYPE
@ VALUETYPE
Definition: ISDOpcodes.h:65
llvm::ISD::VECREDUCE_FMUL
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1212
llvm::ISD::ATOMIC_LOAD_FADD
@ ATOMIC_LOAD_FADD
Definition: ISDOpcodes.h:1137
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1290
llvm::ISD::TargetConstantFP
@ TargetConstantFP
Definition: ISDOpcodes.h:152
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:863
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:371
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:77
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1357
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::ISD::STRICT_FSETCCS
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:457
llvm::ISD::STRICT_FMINIMUM
@ STRICT_FMINIMUM
Definition: ISDOpcodes.h:416
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:616
llvm::ISD::WRITE_REGISTER
@ WRITE_REGISTER
Definition: ISDOpcodes.h:112
llvm::ISD::FMINIMUM
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:901
BasicBlock.h
llvm::cl::opt< bool >
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:67
llvm::ISD::GET_DYNAMIC_AREA_OFFSET
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1179
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:303
llvm::ISD::FLOG10
@ FLOG10
Definition: ISDOpcodes.h:866
llvm::ISD::VECREDUCE_FMIN
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1215
llvm::ISD::FMAD
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:464
llvm::ISD::LOCAL_RECOVER
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition: ISDOpcodes.h:107
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1096
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1117
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1133
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:776
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1575
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1219
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:911
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1224
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:60
llvm::SDNode::print_details
void print_details(raw_ostream &OS, const SelectionDAG *G) const
Definition: SelectionDAGDumper.cpp:555
llvm::ISD::SRCVALUE
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
Definition: ISDOpcodes.h:1043
llvm::ISD::STRICT_LRINT
@ STRICT_LRINT
Definition: ISDOpcodes.h:413
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1078
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::ISD::SPONENTRY
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
Definition: ISDOpcodes.h:99
llvm::ISD::SSUBO_CARRY
@ SSUBO_CARRY
Definition: ISDOpcodes.h:294
llvm::nodes
iterator_range< typename GraphTraits< GraphType >::nodes_iterator > nodes(const GraphType &G)
Definition: GraphTraits.h:108
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:505
llvm::ISD::VECREDUCE_FADD
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1211
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:993
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:665
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1132
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:896
PrintNodeId
static Printable PrintNodeId(const SDNode &Node)
Definition: SelectionDAGDumper.cpp:500
llvm::ISD::VECREDUCE_SEQ_FMUL
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1199
llvm::ISD::LRINT
@ LRINT
Definition: ISDOpcodes.h:878
StringExtras.h
llvm::ISD::FP_TO_FP16
@ FP_TO_FP16
Definition: ISDOpcodes.h:849
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1111
llvm::ISD::UADDSAT
@ UADDSAT
Definition: ISDOpcodes.h:321
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1126
MachineConstantPool.h
llvm::ISD::SSUBSAT
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:329
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:470
llvm::SDNode::dump
void dump() const
Dump this node, for debugging.
Definition: SelectionDAGDumper.cpp:537
llvm::MachineSDNode::mmo_iterator
ArrayRef< MachineMemOperand * >::const_iterator mmo_iterator
Definition: SelectionDAGNodes.h:2548
printMemOperand
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
Definition: SelectionDAGDumper.cpp:511
llvm::ISD::MSTORE
@ MSTORE
Definition: ISDOpcodes.h:1147
llvm::ISD::STRICT_LROUND
@ STRICT_LROUND
Definition: ISDOpcodes.h:411
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1345
llvm::ISD::ADJUST_TRAMPOLINE
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:1075
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:612
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:574
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1355
llvm::ISD::DEBUGTRAP
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1081
llvm::SDNode::print
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
Definition: SelectionDAGDumper.cpp:1047
llvm::ISD::EH_DWARF_CFA
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:122
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:64
llvm::ISD::SDIVFIXSAT
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:367
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1221
llvm::ISD::TargetGlobalTLSAddress
@ TargetGlobalTLSAddress
Definition: ISDOpcodes.h:158
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:88
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:284
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::TargetLowering::getTargetNodeName
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
Definition: TargetLowering.cpp:41
llvm::ISD::POST_DEC
@ POST_DEC
Definition: ISDOpcodes.h:1290
llvm::ISD::STRICT_LLRINT
@ STRICT_LLRINT
Definition: ISDOpcodes.h:414
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:706
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1032
llvm::SDNode::isMachineOpcode
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
Definition: SelectionDAGNodes.h:673
llvm::ISD::TargetBlockAddress
@ TargetBlockAddress
Definition: ISDOpcodes.h:163
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:984
llvm::ISD::VSCALE
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
Definition: ISDOpcodes.h:1188
llvm::ISD::STRICT_FROUNDEVEN
@ STRICT_FROUNDEVEN
Definition: ISDOpcodes.h:409
llvm::ISD::HANDLENODE
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
Definition: ISDOpcodes.h:1061
llvm::ISD::STRICT_FEXP
@ STRICT_FEXP
Definition: ISDOpcodes.h:397
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:75
llvm::ISD::FMAXIMUM
@ FMAXIMUM
Definition: ISDOpcodes.h:902
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:72
llvm::ISD::UBSANTRAP
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1085
llvm::ISD::TargetConstantPool
@ TargetConstantPool
Definition: ISDOpcodes.h:161
llvm::SDNode::print_types
void print_types(raw_ostream &OS, const SelectionDAG *G) const
Definition: SelectionDAGDumper.cpp:545
llvm::ISD::STRICT_FCOS
@ STRICT_FCOS
Definition: ISDOpcodes.h:396
llvm::ISD::UMAX
@ UMAX
Definition: ISDOpcodes.h:619
llvm::ISD::PRE_INC
@ PRE_INC
Definition: ISDOpcodes.h:1290
None.h
llvm::ISD::SETTRUE2
@ SETTRUE2
Definition: ISDOpcodes.h:1367
llvm::ISD::STRICT_FTRUNC
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:410
llvm::APFloatBase::IEEEdouble
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:166
llvm::ISD::STRICT_SINT_TO_FP
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition: ISDOpcodes.h:429
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:237
llvm::ISD::LLRINT
@ LLRINT
Definition: ISDOpcodes.h:879
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:244
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1127
llvm::ISD::STRICT_FSUB
@ STRICT_FSUB
Definition: ISDOpcodes.h:382
Compiler.h
TargetSubtargetInfo.h
llvm::SDNode::getIndexedModeName
static const char * getIndexedModeName(ISD::MemIndexedMode AM)
Definition: SelectionDAGDumper.cpp:490
llvm::ISD::FEXP
@ FEXP
Definition: ISDOpcodes.h:867
llvm::ISD::UNDEF
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:204
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:243
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1235
llvm::ISD::UMULFIX
@ UMULFIX
Definition: ISDOpcodes.h:349
llvm::ISD::SETFALSE
@ SETFALSE
Definition: ISDOpcodes.h:1343
llvm::ISD::FEXP2
@ FEXP2
Definition: ISDOpcodes.h:868
llvm::ISD::STRICT_FP_EXTEND
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:450
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1223
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:373
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1125
llvm::ISD::VECTOR_SPLICE
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:569
llvm::ISD::CARRY_FALSE
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition: ISDOpcodes.h:253
llvm::ISD::SSHLSAT
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:339
llvm::ISD::PCMARKER
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
Definition: ISDOpcodes.h:1050
llvm::ISD::INTRINSIC_WO_CHAIN
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:177
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:624
llvm::SDNode::getOperationName
std::string getOperationName(const SelectionDAG *G=nullptr) const
Return the opcode of this operation for printing.
Definition: SelectionDAGDumper.cpp:59
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:87
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:858
llvm::EVT::getEVTString
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:152
llvm::ISD::INSERT_SUBVECTOR
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition: ISDOpcodes.h:529
llvm::ISD::READ_REGISTER
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:111
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1364
llvm::ISD::STRICT_FMUL
@ STRICT_FMUL
Definition: ISDOpcodes.h:383
llvm::ISD::STRICT_FMA
@ STRICT_FMA
Definition: ISDOpcodes.h:386
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:889
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1688
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::ISD::EXTRACT_SUBVECTOR
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition: ISDOpcodes.h:543
llvm::ISD::FP_TO_SINT_SAT
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:790
llvm::ISD::SADDO_CARRY
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:293
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1220
llvm::ISD::UMULFIXSAT
@ UMULFIXSAT
Definition: ISDOpcodes.h:355
llvm::ISD::STRICT_FP_TO_FP16
@ STRICT_FP_TO_FP16
Definition: ISDOpcodes.h:851
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:927
llvm::ISD::TargetExternalSymbol
@ TargetExternalSymbol
Definition: ISDOpcodes.h:162
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:861
llvm::ISD::FCEIL
@ FCEIL
Definition: ISDOpcodes.h:869
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:860
ISDOpcodes.h
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:973
llvm::ISD::BUILD_VECTOR
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:485
Casting.h
llvm::ISD::STRICT_FCEIL
@ STRICT_FCEIL
Definition: ISDOpcodes.h:406
llvm::ISD::FRAME_TO_ARGS_OFFSET
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:117
Function.h
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:263
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1222
llvm::ISD::SETUO
@ SETUO
Definition: ISDOpcodes.h:1351
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:235
llvm::ISD::TargetConstant
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:151
llvm::ISD::PREALLOCATED_ARG
@ PREALLOCATED_ARG
Definition: ISDOpcodes.h:1039
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:955
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:128
hasNoSignedWrap
static bool hasNoSignedWrap(BinaryOperator &I)
Definition: InstructionCombining.cpp:286
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:912
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1027
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:707
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:730
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:307
llvm::SDNode::getMachineOpcode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
Definition: SelectionDAGNodes.h:678
llvm::ISD::STRICT_FFLOOR
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:407
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1346
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:823
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::ISD::FGETSIGN
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:474
llvm::ISD::RegisterMask
@ RegisterMask
Definition: ISDOpcodes.h:68
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:372
llvm::ISD::PREFETCH
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1091
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:647
llvm::ISD::READCYCLECOUNTER
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1058
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:375
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:37
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:238
TargetIntrinsicInfo.h
llvm::ISD::ZERO_EXTEND_VECTOR_INREG
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:770
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:660
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:273
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:649
llvm::ISD::ADDROFRETURNADDR
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
Definition: ISDOpcodes.h:94
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:657
llvm::ISD::TargetJumpTable
@ TargetJumpTable
Definition: ISDOpcodes.h:160
llvm::ISD::STRICT_FADD
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:381
llvm::ISD::PARITY
@ PARITY
Definition: ISDOpcodes.h:661
llvm::ISD::STRICT_LLROUND
@ STRICT_LLROUND
Definition: ISDOpcodes.h:412
llvm::ISD::UMIN
@ UMIN
Definition: ISDOpcodes.h:618
ModuleSlotTracker.h
MachineMemOperand.h
llvm::ISD::SETFALSE2
@ SETFALSE2
Definition: ISDOpcodes.h:1360
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:611
llvm::ISD::LROUND
@ LROUND
Definition: ISDOpcodes.h:876
llvm::ISD::STRICT_FREM
@ STRICT_FREM
Definition: ISDOpcodes.h:385
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1349
llvm::ISD::INTRINSIC_W_CHAIN
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:185
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:856
llvm::ISD::STRICT_FEXP2
@ STRICT_FEXP2
Definition: ISDOpcodes.h:398
llvm::ISD::BUILD_PAIR
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:222
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1022
llvm::ISD::UDIVFIX
@ UDIVFIX
Definition: ISDOpcodes.h:362
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:248
llvm::ISD::STRICT_FPOWI
@ STRICT_FPOWI
Definition: ISDOpcodes.h:394
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ISD::ATOMIC_LOAD_XOR
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1131
llvm::ISD::TargetFrameIndex
@ TargetFrameIndex
Definition: ISDOpcodes.h:159
llvm::ISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1225
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:716
raw_ostream.h
llvm::ISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1227
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::ISD::FTRUNC
@ FTRUNC
Definition: ISDOpcodes.h:870
llvm::SDNode::getFlags
SDNodeFlags getFlags() const
Definition: SelectionDAGNodes.h:947
Value.h
llvm::ISD::INSERT_VECTOR_ELT
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:494
llvm::ISD::FCANONICALIZE
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:477
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:998
llvm::ISD::FLOG
@ FLOG
Definition: ISDOpcodes.h:864
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:272
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:804
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:651
TargetRegisterInfo.h
Debug.h
llvm::ISD::SET_ROUNDING
@ SET_ROUNDING
Set rounding mode.
Definition: ISDOpcodes.h:820
llvm::ISD::ATOMIC_LOAD
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:1100
llvm::ISD::SCALAR_TO_VECTOR
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:577
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:659
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:165
llvm::ISD::SADDSAT
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:320
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1134
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:215
llvm::ISD::MSCATTER
@ MSCATTER
Definition: ISDOpcodes.h:1159
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::ISD::VSELECT
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:678
VerboseDAGDumping
static cl::opt< bool > VerboseDAGDumping("dag-dump-verbose", cl::Hidden, cl::desc("Display more information when dumping selection " "DAG nodes."))
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:374