LLVM 18.0.0git
SelectionDAGDumper.cpp
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1//===- SelectionDAGDumper.cpp - Implement SelectionDAG::dump() ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the SelectionDAG::dump method and friends.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SDNodeDbgValue.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/APInt.h"
30#include "llvm/Config/llvm-config.h"
31#include "llvm/IR/BasicBlock.h"
32#include "llvm/IR/Constants.h"
34#include "llvm/IR/DebugLoc.h"
35#include "llvm/IR/Function.h"
36#include "llvm/IR/Intrinsics.h"
38#include "llvm/IR/Value.h"
42#include "llvm/Support/Debug.h"
48#include <cstdint>
49#include <iterator>
50
51using namespace llvm;
52
53static cl::opt<bool>
54VerboseDAGDumping("dag-dump-verbose", cl::Hidden,
55 cl::desc("Display more information when dumping selection "
56 "DAG nodes."));
57
58std::string SDNode::getOperationName(const SelectionDAG *G) const {
59 switch (getOpcode()) {
60 default:
62 return "<<Unknown DAG Node>>";
63 if (isMachineOpcode()) {
64 if (G)
65 if (const TargetInstrInfo *TII = G->getSubtarget().getInstrInfo())
66 if (getMachineOpcode() < TII->getNumOpcodes())
67 return std::string(TII->getName(getMachineOpcode()));
68 return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
69 }
70 if (G) {
71 const TargetLowering &TLI = G->getTargetLoweringInfo();
72 const char *Name = TLI.getTargetNodeName(getOpcode());
73 if (Name) return Name;
74 return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
75 }
76 return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
77
78#ifndef NDEBUG
79 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
80#endif
81 case ISD::PREFETCH: return "Prefetch";
82 case ISD::MEMBARRIER: return "MemBarrier";
83 case ISD::ATOMIC_FENCE: return "AtomicFence";
84 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
85 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess";
86 case ISD::ATOMIC_SWAP: return "AtomicSwap";
87 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
88 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
89 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
90 case ISD::ATOMIC_LOAD_CLR: return "AtomicLoadClr";
91 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr";
92 case ISD::ATOMIC_LOAD_XOR: return "AtomicLoadXor";
93 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand";
94 case ISD::ATOMIC_LOAD_MIN: return "AtomicLoadMin";
95 case ISD::ATOMIC_LOAD_MAX: return "AtomicLoadMax";
96 case ISD::ATOMIC_LOAD_UMIN: return "AtomicLoadUMin";
97 case ISD::ATOMIC_LOAD_UMAX: return "AtomicLoadUMax";
98 case ISD::ATOMIC_LOAD_FADD: return "AtomicLoadFAdd";
100 return "AtomicLoadUIncWrap";
102 return "AtomicLoadUDecWrap";
103 case ISD::ATOMIC_LOAD: return "AtomicLoad";
104 case ISD::ATOMIC_STORE: return "AtomicStore";
105 case ISD::PCMARKER: return "PCMarker";
106 case ISD::READCYCLECOUNTER: return "ReadCycleCounter";
107 case ISD::SRCVALUE: return "SrcValue";
108 case ISD::MDNODE_SDNODE: return "MDNode";
109 case ISD::EntryToken: return "EntryToken";
110 case ISD::TokenFactor: return "TokenFactor";
111 case ISD::AssertSext: return "AssertSext";
112 case ISD::AssertZext: return "AssertZext";
113 case ISD::AssertAlign: return "AssertAlign";
114
115 case ISD::BasicBlock: return "BasicBlock";
116 case ISD::VALUETYPE: return "ValueType";
117 case ISD::Register: return "Register";
118 case ISD::RegisterMask: return "RegisterMask";
119 case ISD::Constant:
120 if (cast<ConstantSDNode>(this)->isOpaque())
121 return "OpaqueConstant";
122 return "Constant";
123 case ISD::ConstantFP: return "ConstantFP";
124 case ISD::GlobalAddress: return "GlobalAddress";
125 case ISD::GlobalTLSAddress: return "GlobalTLSAddress";
126 case ISD::FrameIndex: return "FrameIndex";
127 case ISD::JumpTable: return "JumpTable";
129 return "JUMP_TABLE_DEBUG_INFO";
130 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
131 case ISD::RETURNADDR: return "RETURNADDR";
132 case ISD::ADDROFRETURNADDR: return "ADDROFRETURNADDR";
133 case ISD::FRAMEADDR: return "FRAMEADDR";
134 case ISD::SPONENTRY: return "SPONENTRY";
135 case ISD::LOCAL_RECOVER: return "LOCAL_RECOVER";
136 case ISD::READ_REGISTER: return "READ_REGISTER";
137 case ISD::WRITE_REGISTER: return "WRITE_REGISTER";
138 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
139 case ISD::EH_DWARF_CFA: return "EH_DWARF_CFA";
140 case ISD::EH_RETURN: return "EH_RETURN";
141 case ISD::EH_SJLJ_SETJMP: return "EH_SJLJ_SETJMP";
142 case ISD::EH_SJLJ_LONGJMP: return "EH_SJLJ_LONGJMP";
143 case ISD::EH_SJLJ_SETUP_DISPATCH: return "EH_SJLJ_SETUP_DISPATCH";
144 case ISD::ConstantPool: return "ConstantPool";
145 case ISD::TargetIndex: return "TargetIndex";
146 case ISD::ExternalSymbol: return "ExternalSymbol";
147 case ISD::BlockAddress: return "BlockAddress";
151 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
152 unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
153 if (IID < Intrinsic::num_intrinsics)
155 if (!G)
156 return "Unknown intrinsic";
157 if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
158 return TII->getName(IID);
159 llvm_unreachable("Invalid intrinsic ID");
160 }
161
162 case ISD::BUILD_VECTOR: return "BUILD_VECTOR";
164 if (cast<ConstantSDNode>(this)->isOpaque())
165 return "OpaqueTargetConstant";
166 return "TargetConstant";
167 case ISD::TargetConstantFP: return "TargetConstantFP";
168 case ISD::TargetGlobalAddress: return "TargetGlobalAddress";
169 case ISD::TargetGlobalTLSAddress: return "TargetGlobalTLSAddress";
170 case ISD::TargetFrameIndex: return "TargetFrameIndex";
171 case ISD::TargetJumpTable: return "TargetJumpTable";
172 case ISD::TargetConstantPool: return "TargetConstantPool";
173 case ISD::TargetExternalSymbol: return "TargetExternalSymbol";
174 case ISD::MCSymbol: return "MCSymbol";
175 case ISD::TargetBlockAddress: return "TargetBlockAddress";
176
177 case ISD::CopyToReg: return "CopyToReg";
178 case ISD::CopyFromReg: return "CopyFromReg";
179 case ISD::UNDEF: return "undef";
180 case ISD::VSCALE: return "vscale";
181 case ISD::MERGE_VALUES: return "merge_values";
182 case ISD::INLINEASM: return "inlineasm";
183 case ISD::INLINEASM_BR: return "inlineasm_br";
184 case ISD::EH_LABEL: return "eh_label";
185 case ISD::ANNOTATION_LABEL: return "annotation_label";
186 case ISD::HANDLENODE: return "handlenode";
187
188 // Unary operators
189 case ISD::FABS: return "fabs";
190 case ISD::FMINNUM: return "fminnum";
191 case ISD::STRICT_FMINNUM: return "strict_fminnum";
192 case ISD::FMAXNUM: return "fmaxnum";
193 case ISD::STRICT_FMAXNUM: return "strict_fmaxnum";
194 case ISD::FMINNUM_IEEE: return "fminnum_ieee";
195 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
196 case ISD::FMINIMUM: return "fminimum";
197 case ISD::STRICT_FMINIMUM: return "strict_fminimum";
198 case ISD::FMAXIMUM: return "fmaximum";
199 case ISD::STRICT_FMAXIMUM: return "strict_fmaximum";
200 case ISD::FNEG: return "fneg";
201 case ISD::FSQRT: return "fsqrt";
202 case ISD::STRICT_FSQRT: return "strict_fsqrt";
203 case ISD::FCBRT: return "fcbrt";
204 case ISD::FSIN: return "fsin";
205 case ISD::STRICT_FSIN: return "strict_fsin";
206 case ISD::FCOS: return "fcos";
207 case ISD::STRICT_FCOS: return "strict_fcos";
208 case ISD::FSINCOS: return "fsincos";
209 case ISD::FTRUNC: return "ftrunc";
210 case ISD::STRICT_FTRUNC: return "strict_ftrunc";
211 case ISD::FFLOOR: return "ffloor";
212 case ISD::STRICT_FFLOOR: return "strict_ffloor";
213 case ISD::FCEIL: return "fceil";
214 case ISD::STRICT_FCEIL: return "strict_fceil";
215 case ISD::FRINT: return "frint";
216 case ISD::STRICT_FRINT: return "strict_frint";
217 case ISD::FNEARBYINT: return "fnearbyint";
218 case ISD::STRICT_FNEARBYINT: return "strict_fnearbyint";
219 case ISD::FROUND: return "fround";
220 case ISD::STRICT_FROUND: return "strict_fround";
221 case ISD::FROUNDEVEN: return "froundeven";
222 case ISD::STRICT_FROUNDEVEN: return "strict_froundeven";
223 case ISD::FEXP: return "fexp";
224 case ISD::STRICT_FEXP: return "strict_fexp";
225 case ISD::FEXP2: return "fexp2";
226 case ISD::STRICT_FEXP2: return "strict_fexp2";
227 case ISD::FEXP10: return "fexp10";
228 case ISD::FLOG: return "flog";
229 case ISD::STRICT_FLOG: return "strict_flog";
230 case ISD::FLOG2: return "flog2";
231 case ISD::STRICT_FLOG2: return "strict_flog2";
232 case ISD::FLOG10: return "flog10";
233 case ISD::STRICT_FLOG10: return "strict_flog10";
234
235 // Binary operators
236 case ISD::ADD: return "add";
237 case ISD::SUB: return "sub";
238 case ISD::MUL: return "mul";
239 case ISD::MULHU: return "mulhu";
240 case ISD::MULHS: return "mulhs";
241 case ISD::AVGFLOORU: return "avgflooru";
242 case ISD::AVGFLOORS: return "avgfloors";
243 case ISD::AVGCEILU: return "avgceilu";
244 case ISD::AVGCEILS: return "avgceils";
245 case ISD::ABDS: return "abds";
246 case ISD::ABDU: return "abdu";
247 case ISD::SDIV: return "sdiv";
248 case ISD::UDIV: return "udiv";
249 case ISD::SREM: return "srem";
250 case ISD::UREM: return "urem";
251 case ISD::SMUL_LOHI: return "smul_lohi";
252 case ISD::UMUL_LOHI: return "umul_lohi";
253 case ISD::SDIVREM: return "sdivrem";
254 case ISD::UDIVREM: return "udivrem";
255 case ISD::AND: return "and";
256 case ISD::OR: return "or";
257 case ISD::XOR: return "xor";
258 case ISD::SHL: return "shl";
259 case ISD::SRA: return "sra";
260 case ISD::SRL: return "srl";
261 case ISD::ROTL: return "rotl";
262 case ISD::ROTR: return "rotr";
263 case ISD::FSHL: return "fshl";
264 case ISD::FSHR: return "fshr";
265 case ISD::FADD: return "fadd";
266 case ISD::STRICT_FADD: return "strict_fadd";
267 case ISD::FSUB: return "fsub";
268 case ISD::STRICT_FSUB: return "strict_fsub";
269 case ISD::FMUL: return "fmul";
270 case ISD::STRICT_FMUL: return "strict_fmul";
271 case ISD::FDIV: return "fdiv";
272 case ISD::STRICT_FDIV: return "strict_fdiv";
273 case ISD::FMA: return "fma";
274 case ISD::STRICT_FMA: return "strict_fma";
275 case ISD::FMAD: return "fmad";
276 case ISD::FREM: return "frem";
277 case ISD::STRICT_FREM: return "strict_frem";
278 case ISD::FCOPYSIGN: return "fcopysign";
279 case ISD::FGETSIGN: return "fgetsign";
280 case ISD::FCANONICALIZE: return "fcanonicalize";
281 case ISD::IS_FPCLASS: return "is_fpclass";
282 case ISD::FPOW: return "fpow";
283 case ISD::STRICT_FPOW: return "strict_fpow";
284 case ISD::SMIN: return "smin";
285 case ISD::SMAX: return "smax";
286 case ISD::UMIN: return "umin";
287 case ISD::UMAX: return "umax";
288
289 case ISD::FLDEXP: return "fldexp";
290 case ISD::STRICT_FLDEXP: return "strict_fldexp";
291 case ISD::FFREXP: return "ffrexp";
292 case ISD::FPOWI: return "fpowi";
293 case ISD::STRICT_FPOWI: return "strict_fpowi";
294 case ISD::SETCC: return "setcc";
295 case ISD::SETCCCARRY: return "setcccarry";
296 case ISD::STRICT_FSETCC: return "strict_fsetcc";
297 case ISD::STRICT_FSETCCS: return "strict_fsetccs";
298 case ISD::SELECT: return "select";
299 case ISD::VSELECT: return "vselect";
300 case ISD::SELECT_CC: return "select_cc";
301 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
302 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
303 case ISD::CONCAT_VECTORS: return "concat_vectors";
304 case ISD::INSERT_SUBVECTOR: return "insert_subvector";
305 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
306 case ISD::VECTOR_DEINTERLEAVE: return "vector_deinterleave";
307 case ISD::VECTOR_INTERLEAVE: return "vector_interleave";
308 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
309 case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
310 case ISD::VECTOR_SPLICE: return "vector_splice";
311 case ISD::SPLAT_VECTOR: return "splat_vector";
312 case ISD::SPLAT_VECTOR_PARTS: return "splat_vector_parts";
313 case ISD::VECTOR_REVERSE: return "vector_reverse";
314 case ISD::STEP_VECTOR: return "step_vector";
315 case ISD::CARRY_FALSE: return "carry_false";
316 case ISD::ADDC: return "addc";
317 case ISD::ADDE: return "adde";
318 case ISD::UADDO_CARRY: return "uaddo_carry";
319 case ISD::SADDO_CARRY: return "saddo_carry";
320 case ISD::SADDO: return "saddo";
321 case ISD::UADDO: return "uaddo";
322 case ISD::SSUBO: return "ssubo";
323 case ISD::USUBO: return "usubo";
324 case ISD::SMULO: return "smulo";
325 case ISD::UMULO: return "umulo";
326 case ISD::SUBC: return "subc";
327 case ISD::SUBE: return "sube";
328 case ISD::USUBO_CARRY: return "usubo_carry";
329 case ISD::SSUBO_CARRY: return "ssubo_carry";
330 case ISD::SHL_PARTS: return "shl_parts";
331 case ISD::SRA_PARTS: return "sra_parts";
332 case ISD::SRL_PARTS: return "srl_parts";
333
334 case ISD::SADDSAT: return "saddsat";
335 case ISD::UADDSAT: return "uaddsat";
336 case ISD::SSUBSAT: return "ssubsat";
337 case ISD::USUBSAT: return "usubsat";
338 case ISD::SSHLSAT: return "sshlsat";
339 case ISD::USHLSAT: return "ushlsat";
340
341 case ISD::SMULFIX: return "smulfix";
342 case ISD::SMULFIXSAT: return "smulfixsat";
343 case ISD::UMULFIX: return "umulfix";
344 case ISD::UMULFIXSAT: return "umulfixsat";
345
346 case ISD::SDIVFIX: return "sdivfix";
347 case ISD::SDIVFIXSAT: return "sdivfixsat";
348 case ISD::UDIVFIX: return "udivfix";
349 case ISD::UDIVFIXSAT: return "udivfixsat";
350
351 // Conversion operators.
352 case ISD::SIGN_EXTEND: return "sign_extend";
353 case ISD::ZERO_EXTEND: return "zero_extend";
354 case ISD::ANY_EXTEND: return "any_extend";
355 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
356 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg";
357 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg";
358 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg";
359 case ISD::TRUNCATE: return "truncate";
360 case ISD::FP_ROUND: return "fp_round";
361 case ISD::STRICT_FP_ROUND: return "strict_fp_round";
362 case ISD::FP_EXTEND: return "fp_extend";
363 case ISD::STRICT_FP_EXTEND: return "strict_fp_extend";
364
365 case ISD::SINT_TO_FP: return "sint_to_fp";
366 case ISD::STRICT_SINT_TO_FP: return "strict_sint_to_fp";
367 case ISD::UINT_TO_FP: return "uint_to_fp";
368 case ISD::STRICT_UINT_TO_FP: return "strict_uint_to_fp";
369 case ISD::FP_TO_SINT: return "fp_to_sint";
370 case ISD::STRICT_FP_TO_SINT: return "strict_fp_to_sint";
371 case ISD::FP_TO_UINT: return "fp_to_uint";
372 case ISD::STRICT_FP_TO_UINT: return "strict_fp_to_uint";
373 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat";
374 case ISD::FP_TO_UINT_SAT: return "fp_to_uint_sat";
375 case ISD::BITCAST: return "bitcast";
376 case ISD::ADDRSPACECAST: return "addrspacecast";
377 case ISD::FP16_TO_FP: return "fp16_to_fp";
378 case ISD::STRICT_FP16_TO_FP: return "strict_fp16_to_fp";
379 case ISD::FP_TO_FP16: return "fp_to_fp16";
380 case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16";
381 case ISD::BF16_TO_FP: return "bf16_to_fp";
382 case ISD::FP_TO_BF16: return "fp_to_bf16";
383 case ISD::LROUND: return "lround";
384 case ISD::STRICT_LROUND: return "strict_lround";
385 case ISD::LLROUND: return "llround";
386 case ISD::STRICT_LLROUND: return "strict_llround";
387 case ISD::LRINT: return "lrint";
388 case ISD::STRICT_LRINT: return "strict_lrint";
389 case ISD::LLRINT: return "llrint";
390 case ISD::STRICT_LLRINT: return "strict_llrint";
391
392 // Control flow instructions
393 case ISD::BR: return "br";
394 case ISD::BRIND: return "brind";
395 case ISD::BR_JT: return "br_jt";
396 case ISD::BRCOND: return "brcond";
397 case ISD::BR_CC: return "br_cc";
398 case ISD::CALLSEQ_START: return "callseq_start";
399 case ISD::CALLSEQ_END: return "callseq_end";
400
401 // EH instructions
402 case ISD::CATCHRET: return "catchret";
403 case ISD::CLEANUPRET: return "cleanupret";
404
405 // Other operators
406 case ISD::LOAD: return "load";
407 case ISD::STORE: return "store";
408 case ISD::MLOAD: return "masked_load";
409 case ISD::MSTORE: return "masked_store";
410 case ISD::MGATHER: return "masked_gather";
411 case ISD::MSCATTER: return "masked_scatter";
412 case ISD::VAARG: return "vaarg";
413 case ISD::VACOPY: return "vacopy";
414 case ISD::VAEND: return "vaend";
415 case ISD::VASTART: return "vastart";
416 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc";
417 case ISD::EXTRACT_ELEMENT: return "extract_element";
418 case ISD::BUILD_PAIR: return "build_pair";
419 case ISD::STACKSAVE: return "stacksave";
420 case ISD::STACKRESTORE: return "stackrestore";
421 case ISD::TRAP: return "trap";
422 case ISD::DEBUGTRAP: return "debugtrap";
423 case ISD::UBSANTRAP: return "ubsantrap";
424 case ISD::LIFETIME_START: return "lifetime.start";
425 case ISD::LIFETIME_END: return "lifetime.end";
427 return "pseudoprobe";
428 case ISD::GC_TRANSITION_START: return "gc_transition.start";
429 case ISD::GC_TRANSITION_END: return "gc_transition.end";
430 case ISD::GET_DYNAMIC_AREA_OFFSET: return "get.dynamic.area.offset";
431 case ISD::FREEZE: return "freeze";
433 return "call_setup";
435 return "call_alloc";
436
437 // Floating point environment manipulation
438 case ISD::GET_ROUNDING: return "get_rounding";
439 case ISD::SET_ROUNDING: return "set_rounding";
440 case ISD::GET_FPENV: return "get_fpenv";
441 case ISD::SET_FPENV: return "set_fpenv";
442 case ISD::RESET_FPENV: return "reset_fpenv";
443 case ISD::GET_FPENV_MEM: return "get_fpenv_mem";
444 case ISD::SET_FPENV_MEM: return "set_fpenv_mem";
445 case ISD::GET_FPMODE: return "get_fpmode";
446 case ISD::SET_FPMODE: return "set_fpmode";
447 case ISD::RESET_FPMODE: return "reset_fpmode";
448
449 // Bit manipulation
450 case ISD::ABS: return "abs";
451 case ISD::BITREVERSE: return "bitreverse";
452 case ISD::BSWAP: return "bswap";
453 case ISD::CTPOP: return "ctpop";
454 case ISD::CTTZ: return "cttz";
455 case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef";
456 case ISD::CTLZ: return "ctlz";
457 case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef";
458 case ISD::PARITY: return "parity";
459
460 // Trampolines
461 case ISD::INIT_TRAMPOLINE: return "init_trampoline";
462 case ISD::ADJUST_TRAMPOLINE: return "adjust_trampoline";
463
464 case ISD::CONDCODE:
465 switch (cast<CondCodeSDNode>(this)->get()) {
466 default: llvm_unreachable("Unknown setcc condition!");
467 case ISD::SETOEQ: return "setoeq";
468 case ISD::SETOGT: return "setogt";
469 case ISD::SETOGE: return "setoge";
470 case ISD::SETOLT: return "setolt";
471 case ISD::SETOLE: return "setole";
472 case ISD::SETONE: return "setone";
473
474 case ISD::SETO: return "seto";
475 case ISD::SETUO: return "setuo";
476 case ISD::SETUEQ: return "setueq";
477 case ISD::SETUGT: return "setugt";
478 case ISD::SETUGE: return "setuge";
479 case ISD::SETULT: return "setult";
480 case ISD::SETULE: return "setule";
481 case ISD::SETUNE: return "setune";
482
483 case ISD::SETEQ: return "seteq";
484 case ISD::SETGT: return "setgt";
485 case ISD::SETGE: return "setge";
486 case ISD::SETLT: return "setlt";
487 case ISD::SETLE: return "setle";
488 case ISD::SETNE: return "setne";
489
490 case ISD::SETTRUE: return "settrue";
491 case ISD::SETTRUE2: return "settrue2";
492 case ISD::SETFALSE: return "setfalse";
493 case ISD::SETFALSE2: return "setfalse2";
494 }
495 case ISD::VECREDUCE_FADD: return "vecreduce_fadd";
496 case ISD::VECREDUCE_SEQ_FADD: return "vecreduce_seq_fadd";
497 case ISD::VECREDUCE_FMUL: return "vecreduce_fmul";
498 case ISD::VECREDUCE_SEQ_FMUL: return "vecreduce_seq_fmul";
499 case ISD::VECREDUCE_ADD: return "vecreduce_add";
500 case ISD::VECREDUCE_MUL: return "vecreduce_mul";
501 case ISD::VECREDUCE_AND: return "vecreduce_and";
502 case ISD::VECREDUCE_OR: return "vecreduce_or";
503 case ISD::VECREDUCE_XOR: return "vecreduce_xor";
504 case ISD::VECREDUCE_SMAX: return "vecreduce_smax";
505 case ISD::VECREDUCE_SMIN: return "vecreduce_smin";
506 case ISD::VECREDUCE_UMAX: return "vecreduce_umax";
507 case ISD::VECREDUCE_UMIN: return "vecreduce_umin";
508 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax";
509 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin";
510 case ISD::VECREDUCE_FMAXIMUM: return "vecreduce_fmaximum";
511 case ISD::VECREDUCE_FMINIMUM: return "vecreduce_fminimum";
512 case ISD::STACKMAP:
513 return "stackmap";
514 case ISD::PATCHPOINT:
515 return "patchpoint";
516
517 // Vector Predication
518#define BEGIN_REGISTER_VP_SDNODE(SDID, LEGALARG, NAME, ...) \
519 case ISD::SDID: \
520 return #NAME;
521#include "llvm/IR/VPIntrinsics.def"
522 }
523}
524
526 switch (AM) {
527 default: return "";
528 case ISD::PRE_INC: return "<pre-inc>";
529 case ISD::PRE_DEC: return "<pre-dec>";
530 case ISD::POST_INC: return "<post-inc>";
531 case ISD::POST_DEC: return "<post-dec>";
532 }
533}
534
536 return Printable([&Node](raw_ostream &OS) {
537#ifndef NDEBUG
538 OS << 't' << Node.PersistentId;
539#else
540 OS << (const void*)&Node;
541#endif
542 });
543}
544
545// Print the MMO with more information from the SelectionDAG.
547 const MachineFunction *MF, const Module *M,
548 const MachineFrameInfo *MFI,
549 const TargetInstrInfo *TII, LLVMContext &Ctx) {
550 ModuleSlotTracker MST(M);
551 if (MF)
554 MMO.print(OS, MST, SSNs, Ctx, MFI, TII);
555}
556
558 const SelectionDAG *G) {
559 if (G) {
560 const MachineFunction *MF = &G->getMachineFunction();
561 return printMemOperand(OS, MMO, MF, MF->getFunction().getParent(),
562 &MF->getFrameInfo(),
563 G->getSubtarget().getInstrInfo(), *G->getContext());
564 }
565
566 LLVMContext Ctx;
567 return printMemOperand(OS, MMO, /*MF=*/nullptr, /*M=*/nullptr,
568 /*MFI=*/nullptr, /*TII=*/nullptr, Ctx);
569}
570
571#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
572LLVM_DUMP_METHOD void SDNode::dump() const { dump(nullptr); }
573
575 print(dbgs(), G);
576 dbgs() << '\n';
577}
578#endif
579
581 for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
582 if (i) OS << ",";
583 if (getValueType(i) == MVT::Other)
584 OS << "ch";
585 else
587 }
588}
589
592 OS << " nuw";
593
595 OS << " nsw";
596
597 if (getFlags().hasExact())
598 OS << " exact";
599
600 if (getFlags().hasNoNaNs())
601 OS << " nnan";
602
603 if (getFlags().hasNoInfs())
604 OS << " ninf";
605
606 if (getFlags().hasNoSignedZeros())
607 OS << " nsz";
608
609 if (getFlags().hasAllowReciprocal())
610 OS << " arcp";
611
612 if (getFlags().hasAllowContract())
613 OS << " contract";
614
615 if (getFlags().hasApproximateFuncs())
616 OS << " afn";
617
618 if (getFlags().hasAllowReassociation())
619 OS << " reassoc";
620
621 if (getFlags().hasNoFPExcept())
622 OS << " nofpexcept";
623
624 if (const MachineSDNode *MN = dyn_cast<MachineSDNode>(this)) {
625 if (!MN->memoperands_empty()) {
626 OS << "<";
627 OS << "Mem:";
628 for (MachineSDNode::mmo_iterator i = MN->memoperands_begin(),
629 e = MN->memoperands_end(); i != e; ++i) {
630 printMemOperand(OS, **i, G);
631 if (std::next(i) != e)
632 OS << " ";
633 }
634 OS << ">";
635 }
636 } else if (const ShuffleVectorSDNode *SVN =
637 dyn_cast<ShuffleVectorSDNode>(this)) {
638 OS << "<";
639 for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
640 int Idx = SVN->getMaskElt(i);
641 if (i) OS << ",";
642 if (Idx < 0)
643 OS << "u";
644 else
645 OS << Idx;
646 }
647 OS << ">";
648 } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
649 OS << '<' << CSDN->getAPIntValue() << '>';
650 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
651 if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEsingle())
652 OS << '<' << CSDN->getValueAPF().convertToFloat() << '>';
653 else if (&CSDN->getValueAPF().getSemantics() == &APFloat::IEEEdouble())
654 OS << '<' << CSDN->getValueAPF().convertToDouble() << '>';
655 else {
656 OS << "<APFloat(";
657 CSDN->getValueAPF().bitcastToAPInt().print(OS, false);
658 OS << ")>";
659 }
660 } else if (const GlobalAddressSDNode *GADN =
661 dyn_cast<GlobalAddressSDNode>(this)) {
662 int64_t offset = GADN->getOffset();
663 OS << '<';
664 GADN->getGlobal()->printAsOperand(OS);
665 OS << '>';
666 if (offset > 0)
667 OS << " + " << offset;
668 else
669 OS << " " << offset;
670 if (unsigned int TF = GADN->getTargetFlags())
671 OS << " [TF=" << TF << ']';
672 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
673 OS << "<" << FIDN->getIndex() << ">";
674 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
675 OS << "<" << JTDN->getIndex() << ">";
676 if (unsigned int TF = JTDN->getTargetFlags())
677 OS << " [TF=" << TF << ']';
678 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
679 int offset = CP->getOffset();
680 if (CP->isMachineConstantPoolEntry())
681 OS << "<" << *CP->getMachineCPVal() << ">";
682 else
683 OS << "<" << *CP->getConstVal() << ">";
684 if (offset > 0)
685 OS << " + " << offset;
686 else
687 OS << " " << offset;
688 if (unsigned int TF = CP->getTargetFlags())
689 OS << " [TF=" << TF << ']';
690 } else if (const TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(this)) {
691 OS << "<" << TI->getIndex() << '+' << TI->getOffset() << ">";
692 if (unsigned TF = TI->getTargetFlags())
693 OS << " [TF=" << TF << ']';
694 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
695 OS << "<";
696 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
697 if (LBB)
698 OS << LBB->getName() << " ";
699 OS << (const void*)BBDN->getBasicBlock() << ">";
700 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
701 OS << ' ' << printReg(R->getReg(),
702 G ? G->getSubtarget().getRegisterInfo() : nullptr);
703 } else if (const ExternalSymbolSDNode *ES =
704 dyn_cast<ExternalSymbolSDNode>(this)) {
705 OS << "'" << ES->getSymbol() << "'";
706 if (unsigned int TF = ES->getTargetFlags())
707 OS << " [TF=" << TF << ']';
708 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
709 if (M->getValue())
710 OS << "<" << M->getValue() << ">";
711 else
712 OS << "<null>";
713 } else if (const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(this)) {
714 if (MD->getMD())
715 OS << "<" << MD->getMD() << ">";
716 else
717 OS << "<null>";
718 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
719 OS << ":" << N->getVT();
720 }
721 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
722 OS << "<";
723
724 printMemOperand(OS, *LD->getMemOperand(), G);
725
726 bool doExt = true;
727 switch (LD->getExtensionType()) {
728 default: doExt = false; break;
729 case ISD::EXTLOAD: OS << ", anyext"; break;
730 case ISD::SEXTLOAD: OS << ", sext"; break;
731 case ISD::ZEXTLOAD: OS << ", zext"; break;
732 }
733 if (doExt)
734 OS << " from " << LD->getMemoryVT();
735
736 const char *AM = getIndexedModeName(LD->getAddressingMode());
737 if (*AM)
738 OS << ", " << AM;
739
740 OS << ">";
741 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
742 OS << "<";
743 printMemOperand(OS, *ST->getMemOperand(), G);
744
745 if (ST->isTruncatingStore())
746 OS << ", trunc to " << ST->getMemoryVT();
747
748 const char *AM = getIndexedModeName(ST->getAddressingMode());
749 if (*AM)
750 OS << ", " << AM;
751
752 OS << ">";
753 } else if (const MaskedLoadSDNode *MLd = dyn_cast<MaskedLoadSDNode>(this)) {
754 OS << "<";
755
756 printMemOperand(OS, *MLd->getMemOperand(), G);
757
758 bool doExt = true;
759 switch (MLd->getExtensionType()) {
760 default: doExt = false; break;
761 case ISD::EXTLOAD: OS << ", anyext"; break;
762 case ISD::SEXTLOAD: OS << ", sext"; break;
763 case ISD::ZEXTLOAD: OS << ", zext"; break;
764 }
765 if (doExt)
766 OS << " from " << MLd->getMemoryVT();
767
768 const char *AM = getIndexedModeName(MLd->getAddressingMode());
769 if (*AM)
770 OS << ", " << AM;
771
772 if (MLd->isExpandingLoad())
773 OS << ", expanding";
774
775 OS << ">";
776 } else if (const MaskedStoreSDNode *MSt = dyn_cast<MaskedStoreSDNode>(this)) {
777 OS << "<";
778 printMemOperand(OS, *MSt->getMemOperand(), G);
779
780 if (MSt->isTruncatingStore())
781 OS << ", trunc to " << MSt->getMemoryVT();
782
783 const char *AM = getIndexedModeName(MSt->getAddressingMode());
784 if (*AM)
785 OS << ", " << AM;
786
787 if (MSt->isCompressingStore())
788 OS << ", compressing";
789
790 OS << ">";
791 } else if (const auto *MGather = dyn_cast<MaskedGatherSDNode>(this)) {
792 OS << "<";
793 printMemOperand(OS, *MGather->getMemOperand(), G);
794
795 bool doExt = true;
796 switch (MGather->getExtensionType()) {
797 default: doExt = false; break;
798 case ISD::EXTLOAD: OS << ", anyext"; break;
799 case ISD::SEXTLOAD: OS << ", sext"; break;
800 case ISD::ZEXTLOAD: OS << ", zext"; break;
801 }
802 if (doExt)
803 OS << " from " << MGather->getMemoryVT();
804
805 auto Signed = MGather->isIndexSigned() ? "signed" : "unsigned";
806 auto Scaled = MGather->isIndexScaled() ? "scaled" : "unscaled";
807 OS << ", " << Signed << " " << Scaled << " offset";
808
809 OS << ">";
810 } else if (const auto *MScatter = dyn_cast<MaskedScatterSDNode>(this)) {
811 OS << "<";
812 printMemOperand(OS, *MScatter->getMemOperand(), G);
813
814 if (MScatter->isTruncatingStore())
815 OS << ", trunc to " << MScatter->getMemoryVT();
816
817 auto Signed = MScatter->isIndexSigned() ? "signed" : "unsigned";
818 auto Scaled = MScatter->isIndexScaled() ? "scaled" : "unscaled";
819 OS << ", " << Signed << " " << Scaled << " offset";
820
821 OS << ">";
822 } else if (const MemSDNode *M = dyn_cast<MemSDNode>(this)) {
823 OS << "<";
824 printMemOperand(OS, *M->getMemOperand(), G);
825 OS << ">";
826 } else if (const BlockAddressSDNode *BA =
827 dyn_cast<BlockAddressSDNode>(this)) {
828 int64_t offset = BA->getOffset();
829 OS << "<";
830 BA->getBlockAddress()->getFunction()->printAsOperand(OS, false);
831 OS << ", ";
832 BA->getBlockAddress()->getBasicBlock()->printAsOperand(OS, false);
833 OS << ">";
834 if (offset > 0)
835 OS << " + " << offset;
836 else
837 OS << " " << offset;
838 if (unsigned int TF = BA->getTargetFlags())
839 OS << " [TF=" << TF << ']';
840 } else if (const AddrSpaceCastSDNode *ASC =
841 dyn_cast<AddrSpaceCastSDNode>(this)) {
842 OS << '['
843 << ASC->getSrcAddressSpace()
844 << " -> "
845 << ASC->getDestAddressSpace()
846 << ']';
847 } else if (const LifetimeSDNode *LN = dyn_cast<LifetimeSDNode>(this)) {
848 if (LN->hasOffset())
849 OS << "<" << LN->getOffset() << " to " << LN->getOffset() + LN->getSize() << ">";
850 } else if (const auto *AA = dyn_cast<AssertAlignSDNode>(this)) {
851 OS << '<' << AA->getAlign().value() << '>';
852 }
853
854 if (VerboseDAGDumping) {
855 if (unsigned Order = getIROrder())
856 OS << " [ORD=" << Order << ']';
857
858 if (getNodeId() != -1)
859 OS << " [ID=" << getNodeId() << ']';
860 if (!(isa<ConstantSDNode>(this) || (isa<ConstantFPSDNode>(this))))
861 OS << " # D:" << isDivergent();
862
863 if (G && !G->GetDbgValues(this).empty()) {
864 OS << " [NoOfDbgValues=" << G->GetDbgValues(this).size() << ']';
865 for (SDDbgValue *Dbg : G->GetDbgValues(this))
866 if (!Dbg->isInvalidated())
867 Dbg->print(OS);
868 } else if (getHasDebugValue())
869 OS << " [NoOfDbgValues>0]";
870
871 if (const auto *MD = G ? G->getPCSections(this) : nullptr) {
872 OS << " [pcsections ";
873 MD->printAsOperand(OS, G->getMachineFunction().getFunction().getParent());
874 OS << ']';
875 }
876 }
877}
878
880 OS << " DbgVal(Order=" << getOrder() << ')';
881 if (isInvalidated())
882 OS << "(Invalidated)";
883 if (isEmitted())
884 OS << "(Emitted)";
885 OS << "(";
886 bool Comma = false;
887 for (const SDDbgOperand &Op : getLocationOps()) {
888 if (Comma)
889 OS << ", ";
890 switch (Op.getKind()) {
892 if (Op.getSDNode())
893 OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':' << Op.getResNo();
894 else
895 OS << "SDNODE";
896 break;
898 OS << "CONST";
899 break;
901 OS << "FRAMEIX=" << Op.getFrameIx();
902 break;
904 OS << "VREG=" << Op.getVReg();
905 break;
906 }
907 Comma = true;
908 }
909 OS << ")";
910 if (isIndirect()) OS << "(Indirect)";
911 if (isVariadic())
912 OS << "(Variadic)";
913 OS << ":\"" << Var->getName() << '"';
914#ifndef NDEBUG
915 if (Expr->getNumElements())
916 Expr->dump();
917#endif
918}
919
920#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
922 if (isInvalidated())
923 return;
924 print(dbgs());
925 dbgs() << "\n";
926}
927#endif
928
929/// Return true if this node is so simple that we should just print it inline
930/// if it appears as an operand.
931static bool shouldPrintInline(const SDNode &Node, const SelectionDAG *G) {
932 // Avoid lots of cluttering when inline printing nodes with associated
933 // DbgValues in verbose mode.
934 if (VerboseDAGDumping && G && !G->GetDbgValues(&Node).empty())
935 return false;
936 if (Node.getOpcode() == ISD::EntryToken)
937 return false;
938 return Node.getNumOperands() == 0;
939}
940
941#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
942static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
943 for (const SDValue &Op : N->op_values()) {
944 if (shouldPrintInline(*Op.getNode(), G))
945 continue;
946 if (Op.getNode()->hasOneUse())
947 DumpNodes(Op.getNode(), indent+2, G);
948 }
949
950 dbgs().indent(indent);
951 N->dump(G);
952}
953
955 dbgs() << "SelectionDAG has " << AllNodes.size() << " nodes:\n";
956
957 for (const SDNode &N : allnodes()) {
958 if (!N.hasOneUse() && &N != getRoot().getNode() &&
959 (!shouldPrintInline(N, this) || N.use_empty()))
960 DumpNodes(&N, 2, this);
961 }
962
963 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
964 dbgs() << "\n";
965
966 if (VerboseDAGDumping) {
967 if (DbgBegin() != DbgEnd())
968 dbgs() << "SDDbgValues:\n";
969 for (auto *Dbg : make_range(DbgBegin(), DbgEnd()))
970 Dbg->dump();
972 dbgs() << "Byval SDDbgValues:\n";
973 for (auto *Dbg : make_range(ByvalParmDbgBegin(), ByvalParmDbgEnd()))
974 Dbg->dump();
975 }
976 dbgs() << "\n";
977}
978#endif
979
981 OS << PrintNodeId(*this) << ": ";
982 print_types(OS, G);
983 OS << " = " << getOperationName(G);
985}
986
988 const SDValue Value) {
989 if (!Value.getNode()) {
990 OS << "<null>";
991 return false;
992 }
993
994 if (shouldPrintInline(*Value.getNode(), G)) {
995 OS << Value->getOperationName(G) << ':';
996 Value->print_types(OS, G);
997 Value->print_details(OS, G);
998 return true;
999 }
1000
1001 OS << PrintNodeId(*Value.getNode());
1002 if (unsigned RN = Value.getResNo())
1003 OS << ':' << RN;
1004 return false;
1005}
1006
1007#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1009
1010static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
1011 const SelectionDAG *G, VisitedSDNodeSet &once) {
1012 if (!once.insert(N).second) // If we've been here before, return now.
1013 return;
1014
1015 // Dump the current SDNode, but don't end the line yet.
1016 OS.indent(indent);
1017 N->printr(OS, G);
1018
1019 // Having printed this SDNode, walk the children:
1020 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1021 if (i) OS << ",";
1022 OS << " ";
1023
1024 const SDValue Op = N->getOperand(i);
1025 bool printedInline = printOperand(OS, G, Op);
1026 if (printedInline)
1027 once.insert(Op.getNode());
1028 }
1029
1030 OS << "\n";
1031
1032 // Dump children that have grandchildren on their own line(s).
1033 for (const SDValue &Op : N->op_values())
1034 DumpNodesr(OS, Op.getNode(), indent+2, G, once);
1035}
1036
1038 VisitedSDNodeSet once;
1039 DumpNodesr(dbgs(), this, 0, nullptr, once);
1040}
1041
1043 VisitedSDNodeSet once;
1044 DumpNodesr(dbgs(), this, 0, G, once);
1045}
1046#endif
1047
1049 const SelectionDAG *G, unsigned depth,
1050 unsigned indent) {
1051 if (depth == 0)
1052 return;
1053
1054 OS.indent(indent);
1055
1056 N->print(OS, G);
1057
1058 for (const SDValue &Op : N->op_values()) {
1059 // Don't follow chain operands.
1060 if (Op.getValueType() == MVT::Other)
1061 continue;
1062 OS << '\n';
1063 printrWithDepthHelper(OS, Op.getNode(), G, depth - 1, indent + 2);
1064 }
1065}
1066
1068 unsigned depth) const {
1069 printrWithDepthHelper(OS, this, G, depth, 0);
1070}
1071
1073 // Don't print impossibly deep things.
1074 printrWithDepth(OS, G, 10);
1075}
1076
1077#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1079void SDNode::dumprWithDepth(const SelectionDAG *G, unsigned depth) const {
1080 printrWithDepth(dbgs(), G, depth);
1081}
1082
1084 // Don't print impossibly deep things.
1085 dumprWithDepth(G, 10);
1086}
1087#endif
1088
1090 printr(OS, G);
1091 // Under VerboseDAGDumping divergence will be printed always.
1093 OS << " # D:1";
1094 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1095 if (i) OS << ", "; else OS << " ";
1097 }
1098 if (DebugLoc DL = getDebugLoc()) {
1099 OS << ", ";
1100 DL.print(OS);
1101 }
1102}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
@ Scaled
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static bool hasNoInfs(const TargetOptions &Options, SDValue N)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
const HexagonInstrInfo * TII
static bool hasNoSignedWrap(BinaryOperator &I)
static bool hasNoUnsignedWrap(BinaryOperator &I)
#define G(x, y, z)
Definition: MD5.cpp:56
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
raw_pwrite_stream & OS
static Printable PrintNodeId(const SDNode &Node)
static cl::opt< bool > VerboseDAGDumping("dag-dump-verbose", cl::Hidden, cl::desc("Display more information when dumping selection " "DAG nodes."))
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
static bool shouldPrintInline(const SDNode &Node, const SelectionDAG *G)
Return true if this node is so simple that we should just print it inline if it appears as an operand...
static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent, const SelectionDAG *G, VisitedSDNodeSet &once)
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G)
static void printrWithDepthHelper(raw_ostream &OS, const SDNode *N, const SelectionDAG *G, unsigned depth, unsigned indent)
This file defines the SmallPtrSet class.
This file contains some functions that are useful when dealing with strings.
This file describes how to lower LLVM code to machine code.
unsigned getNumElements() const
StringRef getName() const
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
A description of a memory reference used in the backend.
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MLOAD node.
This class is used to represent an MSTORE node.
This is an abstract virtual class for memory operations.
void dump() const
User-friendly dump.
Definition: AsmWriter.cpp:4959
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:873
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Holds the information for a single machine location through SDISel; either an SDNode,...
@ VREG
Value is a virtual register.
@ FRAMEIX
Value is contents of a stack location.
@ SDNODE
Value is the result of an expression.
@ CONST
Value is a constant.
Holds the information from a dbg_value node through SDISel.
bool isEmitted() const
LLVM_DUMP_METHOD void print(raw_ostream &OS) const
unsigned getOrder() const
Returns the SDNodeOrder.
LLVM_DUMP_METHOD void dump() const
bool isInvalidated() const
ArrayRef< SDDbgOperand > getLocationOps() const
bool isIndirect() const
Returns whether this is an indirect value.
bool isVariadic() const
Represents one node in the SelectionDAG.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
int getNodeId() const
Return the unique node id.
void dump() const
Dump this node, for debugging.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isDivergent() const
static const char * getIndexedModeName(ISD::MemIndexedMode AM)
unsigned getIROrder() const
Return the node ordering.
bool getHasDebugValue() const
void dumpr() const
Dump (recursively) this node and its use-def subgraph.
SDNodeFlags getFlags() const
std::string getOperationName(const SelectionDAG *G=nullptr) const
Return the opcode of this operation for printing.
void printrFull(raw_ostream &O, const SelectionDAG *G=nullptr) const
Print a SelectionDAG node and all children down to the leaves.
void printr(raw_ostream &OS, const SelectionDAG *G=nullptr) const
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const SDValue & getOperand(unsigned Num) const
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
const DebugLoc & getDebugLoc() const
Return the source location info.
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
void dumprWithDepth(const SelectionDAG *G=nullptr, unsigned depth=100) const
printrWithDepth to dbgs().
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void print_details(raw_ostream &OS, const SelectionDAG *G) const
void print_types(raw_ostream &OS, const SelectionDAG *G) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Definition: SelectionDAG.h:551
SDDbgInfo::DbgIterator ByvalParmDbgEnd() const
SDDbgInfo::DbgIterator ByvalParmDbgBegin() const
SDDbgInfo::DbgIterator DbgEnd() const
SDDbgInfo::DbgIterator DbgBegin() const
iterator_range< allnodes_iterator > allnodes()
Definition: SelectionDAG.h:543
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:366
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:451
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
An SDNode that holds an arbitrary LLVM IR Value.
This class is used to represent ISD::STORE nodes.
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
Completely target-dependent object reference.
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
This class is used to represent EVT's, which are used to parameterize some operations.
LLVM Value Representation.
Definition: Value.h:74
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & indent(unsigned NumSpaces)
indent - Insert 'NumSpaces' spaces.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1121
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1117
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:723
@ TargetConstantPool
Definition: ISDOpcodes.h:168
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
Definition: ISDOpcodes.h:1166
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition: ISDOpcodes.h:476
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
@ SET_FPENV
Sets the current floating-point environment.
Definition: ISDOpcodes.h:993
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1328
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1359
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:147
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:497
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1258
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition: ISDOpcodes.h:559
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
Definition: ISDOpcodes.h:1055
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:714
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1150
@ TargetBlockAddress
Definition: ISDOpcodes.h:170
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1260
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
Definition: ISDOpcodes.h:1230
@ STRICT_FCEIL
Definition: ISDOpcodes.h:426
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1261
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:124
@ RESET_FPENV
Set floating-point environment to default state.
Definition: ISDOpcodes.h:997
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:487
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:974
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1026
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1016
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:780
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:483
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:199
@ RETURNADDR
Definition: ISDOpcodes.h:95
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:151
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1243
@ STRICT_FMINIMUM
Definition: ISDOpcodes.h:436
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:787
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:543
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1344
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
Definition: ISDOpcodes.h:1348
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:688
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
Definition: ISDOpcodes.h:1217
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1222
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
Definition: ISDOpcodes.h:1020
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:817
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1358
@ STRICT_FSETCCS
Definition: ISDOpcodes.h:477
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:910
@ STRICT_FLOG2
Definition: ISDOpcodes.h:421
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1256
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:900
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:229
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1257
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
Definition: ISDOpcodes.h:1188
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
Definition: ISDOpcodes.h:934
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:411
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1380
@ ATOMIC_LOAD_FADD
Definition: ISDOpcodes.h:1263
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
Definition: ISDOpcodes.h:1162
@ FrameIndex
Definition: ISDOpcodes.h:80
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1097
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1103
@ SET_ROUNDING
Set rounding mode.
Definition: ISDOpcodes.h:882
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:662
@ STRICT_UINT_TO_FP
Definition: ISDOpcodes.h:450
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:620
@ PREALLOCATED_SETUP
Definition: ISDOpcodes.h:1155
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
Definition: ISDOpcodes.h:101
@ TargetExternalSymbol
Definition: ISDOpcodes.h:169
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:1042
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1341
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:722
@ TargetJumpTable
Definition: ISDOpcodes.h:167
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition: ISDOpcodes.h:177
@ WRITE_REGISTER
Definition: ISDOpcodes.h:119
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1210
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1345
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:983
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:758
@ STRICT_LROUND
Definition: ISDOpcodes.h:431
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:925
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1072
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1259
@ PREALLOCATED_ARG
Definition: ISDOpcodes.h:1158
@ BRIND
BRIND - Indirect branch.
Definition: ISDOpcodes.h:1047
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1051
@ GC_TRANSITION_START
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
Definition: ISDOpcodes.h:1302
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the same...
Definition: ISDOpcodes.h:586
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
Definition: ISDOpcodes.h:646
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:500
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:507
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ STRICT_FPOWI
Definition: ISDOpcodes.h:413
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
Definition: ISDOpcodes.h:1226
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:211
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1360
@ RegisterMask
Definition: ISDOpcodes.h:75
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:627
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
Definition: ISDOpcodes.h:68
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1146
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:164
@ STRICT_FTRUNC
Definition: ISDOpcodes.h:430
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1353
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
Definition: ISDOpcodes.h:877
@ STRICT_FP_TO_FP16
Definition: ISDOpcodes.h:913
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:651
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1112
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1011
@ STRICT_FP16_TO_FP
Definition: ISDOpcodes.h:912
@ GET_FPENV
Gets the current floating-point environment.
Definition: ISDOpcodes.h:988
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1255
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:600
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1254
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition: ISDOpcodes.h:573
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:973
@ STRICT_FMAXIMUM
Definition: ISDOpcodes.h:435
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
@ STRICT_FMAXNUM
Definition: ISDOpcodes.h:424
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition: ISDOpcodes.h:118
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:535
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:777
@ TargetConstantFP
Definition: ISDOpcodes.h:159
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1200
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:853
@ STRICT_FMINNUM
Definition: ISDOpcodes.h:425
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:742
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
Definition: ISDOpcodes.h:1318
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1237
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1262
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition: ISDOpcodes.h:114
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:966
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1204
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1036
@ STRICT_LRINT
Definition: ISDOpcodes.h:433
@ TargetFrameIndex
Definition: ISDOpcodes.h:166
@ ConstantPool
Definition: ISDOpcodes.h:82
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:806
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:795
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:674
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
Definition: ISDOpcodes.h:591
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1293
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:885
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:87
@ STRICT_FROUND
Definition: ISDOpcodes.h:428
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:736
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition: ISDOpcodes.h:449
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
Definition: ISDOpcodes.h:1180
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1361
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
Definition: ISDOpcodes.h:1169
@ STRICT_FFLOOR
Definition: ISDOpcodes.h:427
@ STRICT_FROUNDEVEN
Definition: ISDOpcodes.h:429
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1092
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition: ISDOpcodes.h:129
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
Definition: ISDOpcodes.h:919
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
@ ATOMIC_LOAD_UDEC_WRAP
Definition: ISDOpcodes.h:1268
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1252
@ STRICT_FP_TO_UINT
Definition: ISDOpcodes.h:443
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:465
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:442
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:979
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1253
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:833
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1177
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:158
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:470
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1197
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:184
@ GET_FPENV_MEM
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1002
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1313
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition: ISDOpcodes.h:260
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:657
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1342
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:400
@ STRICT_FLOG10
Definition: ISDOpcodes.h:420
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
Definition: ISDOpcodes.h:636
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:524
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ STRICT_LLRINT
Definition: ISDOpcodes.h:434
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:612
@ STRICT_FEXP2
Definition: ISDOpcodes.h:418
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1251
@ ExternalSymbol
Definition: ISDOpcodes.h:83
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
Definition: ISDOpcodes.h:939
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:866
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
Definition: ISDOpcodes.h:106
@ STRICT_FLDEXP
Definition: ISDOpcodes.h:414
@ STRICT_LLROUND
Definition: ISDOpcodes.h:432
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:828
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:904
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1089
@ STRICT_FNEARBYINT
Definition: ISDOpcodes.h:423
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:852
@ VECREDUCE_FMINIMUM
Definition: ISDOpcodes.h:1349
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:141
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:783
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1141
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1065
@ BlockAddress
Definition: ISDOpcodes.h:84
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1329
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:763
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1108
@ GC_TRANSITION_END
Definition: ISDOpcodes.h:1303
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ ATOMIC_LOAD_UINC_WRAP
Definition: ISDOpcodes.h:1267
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:493
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
@ AssertZext
Definition: ISDOpcodes.h:62
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
Definition: ISDOpcodes.h:1135
@ STRICT_FRINT
Definition: ISDOpcodes.h:422
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the sa...
Definition: ISDOpcodes.h:580
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1309
@ SET_FPENV_MEM
Sets the current floating point environment.
Definition: ISDOpcodes.h:1007
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:1194
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:192
@ TargetGlobalTLSAddress
Definition: ISDOpcodes.h:165
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:515
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1452
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:983
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
#define N
static const fltSemantics & IEEEsingle() LLVM_READNONE
Definition: APFloat.cpp:249
static const fltSemantics & IEEEdouble() LLVM_READNONE
Definition: APFloat.cpp:250
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:153