LLVM  16.0.0git
VERegisterInfo.cpp
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1 //===-- VERegisterInfo.cpp - VE Register Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "VERegisterInfo.h"
14 #include "VE.h"
15 #include "VESubtarget.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/IR/Type.h"
25 #include "llvm/Support/Debug.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "ve-register-info"
31 
32 #define GET_REGINFO_TARGET_DESC
33 #include "VEGenRegisterInfo.inc"
34 
35 // VE uses %s10 == %lp to keep return address
37 
38 const MCPhysReg *
40  switch (MF->getFunction().getCallingConv()) {
41  case CallingConv::Fast:
42  // Being explicit (same as standard CC).
43  default:
44  return CSR_SaveList;
46  return CSR_preserve_all_SaveList;
47  }
48 }
49 
51  CallingConv::ID CC) const {
52  switch (CC) {
53  case CallingConv::Fast:
54  // Being explicit (same as standard CC).
55  default:
56  return CSR_RegMask;
58  return CSR_preserve_all_RegMask;
59  }
60 }
61 
63  return CSR_NoRegs_RegMask;
64 }
65 
67  BitVector Reserved(getNumRegs());
68 
69  const Register ReservedRegs[] = {
70  VE::SX8, // Stack limit
71  VE::SX9, // Frame pointer
72  VE::SX10, // Link register (return address)
73  VE::SX11, // Stack pointer
74 
75  // FIXME: maybe not need to be reserved
76  VE::SX12, // Outer register
77  VE::SX13, // Id register for dynamic linker
78 
79  VE::SX14, // Thread pointer
80  VE::SX15, // Global offset table register
81  VE::SX16, // Procedure linkage table register
82  VE::SX17, // Linkage-area register
83  // sx18-sx33 are callee-saved registers
84  // sx34-sx63 are temporary registers
85  };
86 
87  for (auto R : ReservedRegs)
88  for (MCRegAliasIterator ItAlias(R, this, true); ItAlias.isValid();
89  ++ItAlias)
90  Reserved.set(*ItAlias);
91 
92  // Reserve constant registers.
93  Reserved.set(VE::VM0);
94  Reserved.set(VE::VMP0);
95 
96  return Reserved;
97 }
98 
99 const TargetRegisterClass *
101  unsigned Kind) const {
102  return &VE::I64RegClass;
103 }
104 
105 static unsigned offsetToDisp(MachineInstr &MI) {
106  // Default offset in instruction's operands (reg+reg+imm).
107  unsigned OffDisp = 2;
108 
109 #define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii
110 
111  {
112  using namespace llvm::VE;
113  switch (MI.getOpcode()) {
114  case INLINEASM:
115  case RRCAS_multi_cases(TS1AML):
116  case RRCAS_multi_cases(TS1AMW):
117  case RRCAS_multi_cases(CASL):
118  case RRCAS_multi_cases(CASW):
119  // These instructions use AS format (reg+imm).
120  OffDisp = 1;
121  break;
122  }
123  }
124 #undef RRCAS_multi_cases
125 
126  return OffDisp;
127 }
128 
130  const TargetInstrInfo &TII;
131  const TargetRegisterInfo &TRI;
132  const DebugLoc &DL;
135  Register clobber;
136 
137  // Some helper functions for the ease of instruction building.
138  MachineFunction &getFunc() const { return *MBB.getParent(); }
139  inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
140  return TRI.getSubReg(Reg, Idx);
141  }
142  inline const MCInstrDesc &get(unsigned Opcode) const {
143  return TII.get(Opcode);
144  }
145  inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) {
146  return BuildMI(MBB, II, DL, MCID, DestReg);
147  }
148  inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) {
149  return build(get(InstOpc), DestReg);
150  }
151  inline MachineInstrBuilder build(const MCInstrDesc &MCID) {
152  return BuildMI(MBB, II, DL, MCID);
153  }
154  inline MachineInstrBuilder build(unsigned InstOpc) {
155  return build(get(InstOpc));
156  }
157 
158  // Calculate an address of frame index from a frame register and a given
159  // offset if the offset doesn't fit in the immediate field. Use a clobber
160  // register to hold calculated address.
161  void prepareReplaceFI(MachineInstr &MI, Register &FrameReg, int64_t &Offset,
162  int64_t Bytes = 0);
163  // Replace the frame index in \p MI with a frame register and a given offset
164  // if it fits in the immediate field. Otherwise, use pre-calculated address
165  // in a clobber regsiter.
166  void replaceFI(MachineInstr &MI, Register FrameReg, int64_t Offset,
167  int FIOperandNum);
168 
169  // Expand and eliminate Frame Index of pseudo STQrii and LDQrii.
170  void processSTQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
171  int FIOperandNum);
172  void processLDQ(MachineInstr &MI, Register FrameReg, int64_t Offset,
173  int FIOperandNum);
174  // Expand and eliminate Frame Index of pseudo STVMrii and LDVMrii.
175  void processSTVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
176  int FIOperandNum);
177  void processLDVM(MachineInstr &MI, Register FrameReg, int64_t Offset,
178  int FIOperandNum);
179  // Expand and eliminate Frame Index of pseudo STVM512rii and LDVM512rii.
180  void processSTVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,
181  int FIOperandNum);
182  void processLDVM512(MachineInstr &MI, Register FrameReg, int64_t Offset,
183  int FIOperandNum);
184 
185 public:
187  const DebugLoc &DL, MachineBasicBlock &MBB,
189  : TII(TII), TRI(TRI), DL(DL), MBB(MBB), II(II), clobber(VE::SX13) {}
190 
191  // Expand and eliminate Frame Index from MI
192  void processMI(MachineInstr &MI, Register FrameReg, int64_t Offset,
193  int FIOperandNum);
194 };
195 
196 // Prepare the frame index if it doesn't fit in the immediate field. Use
197 // clobber register to hold calculated address.
198 void EliminateFrameIndex::prepareReplaceFI(MachineInstr &MI, Register &FrameReg,
199  int64_t &Offset, int64_t Bytes) {
200  if (isInt<32>(Offset) && isInt<32>(Offset + Bytes)) {
201  // If the offset is small enough to fit in the immediate field, directly
202  // encode it. So, nothing to prepare here.
203  return;
204  }
205 
206  // If the offset doesn't fit, emit following codes. This clobbers SX13
207  // which we always know is available here.
208  // lea %clobber, Offset@lo
209  // and %clobber, %clobber, (32)0
210  // lea.sl %clobber, Offset@hi(FrameReg, %clobber)
211  build(VE::LEAzii, clobber).addImm(0).addImm(0).addImm(Lo_32(Offset));
212  build(VE::ANDrm, clobber).addReg(clobber).addImm(M0(32));
213  build(VE::LEASLrri, clobber)
214  .addReg(clobber)
215  .addReg(FrameReg)
216  .addImm(Hi_32(Offset));
217 
218  // Use clobber register as a frame register and 0 offset
219  FrameReg = clobber;
220  Offset = 0;
221 }
222 
223 // Replace the frame index in \p MI with a proper byte and framereg offset.
224 void EliminateFrameIndex::replaceFI(MachineInstr &MI, Register FrameReg,
225  int64_t Offset, int FIOperandNum) {
226  assert(isInt<32>(Offset));
227 
228  // The offset must be small enough to fit in the immediate field after
229  // call of prepareReplaceFI. Therefore, we directly encode it.
230  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
231  MI.getOperand(FIOperandNum + offsetToDisp(MI)).ChangeToImmediate(Offset);
232 }
233 
234 void EliminateFrameIndex::processSTQ(MachineInstr &MI, Register FrameReg,
235  int64_t Offset, int FIOperandNum) {
236  assert(MI.getOpcode() == VE::STQrii);
237  LLVM_DEBUG(dbgs() << "processSTQ: "; MI.dump());
238 
239  prepareReplaceFI(MI, FrameReg, Offset, 8);
240 
241  Register SrcReg = MI.getOperand(3).getReg();
242  Register SrcHiReg = getSubReg(SrcReg, VE::sub_even);
243  Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd);
244  // VE stores HiReg to 8(addr) and LoReg to 0(addr)
245  MachineInstr *StMI =
246  build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(SrcLoReg);
247  replaceFI(*StMI, FrameReg, Offset, 0);
248  // Mutate to 'hi' store.
249  MI.setDesc(get(VE::STrii));
250  MI.getOperand(3).setReg(SrcHiReg);
251  Offset += 8;
252  replaceFI(MI, FrameReg, Offset, FIOperandNum);
253 }
254 
255 void EliminateFrameIndex::processLDQ(MachineInstr &MI, Register FrameReg,
256  int64_t Offset, int FIOperandNum) {
257  assert(MI.getOpcode() == VE::LDQrii);
258  LLVM_DEBUG(dbgs() << "processLDQ: "; MI.dump());
259 
260  prepareReplaceFI(MI, FrameReg, Offset, 8);
261 
262  Register DestReg = MI.getOperand(0).getReg();
263  Register DestHiReg = getSubReg(DestReg, VE::sub_even);
264  Register DestLoReg = getSubReg(DestReg, VE::sub_odd);
265  // VE loads HiReg from 8(addr) and LoReg from 0(addr)
266  MachineInstr *StMI =
267  build(VE::LDrii, DestLoReg).addReg(FrameReg).addImm(0).addImm(0);
268  replaceFI(*StMI, FrameReg, Offset, 1);
269  MI.setDesc(get(VE::LDrii));
270  MI.getOperand(0).setReg(DestHiReg);
271  Offset += 8;
272  replaceFI(MI, FrameReg, Offset, FIOperandNum);
273 }
274 
275 void EliminateFrameIndex::processSTVM(MachineInstr &MI, Register FrameReg,
276  int64_t Offset, int FIOperandNum) {
277  assert(MI.getOpcode() == VE::STVMrii);
278  LLVM_DEBUG(dbgs() << "processSTVM: "; MI.dump());
279 
280  // Original MI is:
281  // STVMrii frame-index, 0, offset, reg (, memory operand)
282  // Convert it to:
283  // SVMi tmp-reg, reg, 0
284  // STrii frame-reg, 0, offset, tmp-reg
285  // SVMi tmp-reg, reg, 1
286  // STrii frame-reg, 0, offset+8, tmp-reg
287  // SVMi tmp-reg, reg, 2
288  // STrii frame-reg, 0, offset+16, tmp-reg
289  // SVMi tmp-reg, reg, 3
290  // STrii frame-reg, 0, offset+24, tmp-reg
291 
292  prepareReplaceFI(MI, FrameReg, Offset, 24);
293 
294  Register SrcReg = MI.getOperand(3).getReg();
295  bool isKill = MI.getOperand(3).isKill();
296  // FIXME: it would be better to scavenge a register here instead of
297  // reserving SX16 all of the time.
298  Register TmpReg = VE::SX16;
299  for (int i = 0; i < 3; ++i) {
300  build(VE::SVMmr, TmpReg).addReg(SrcReg).addImm(i);
301  MachineInstr *StMI =
302  build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
303  TmpReg, getKillRegState(true));
304  replaceFI(*StMI, FrameReg, Offset, 0);
305  Offset += 8;
306  }
307  build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3);
308  MI.setDesc(get(VE::STrii));
309  MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);
310  replaceFI(MI, FrameReg, Offset, FIOperandNum);
311 }
312 
313 void EliminateFrameIndex::processLDVM(MachineInstr &MI, Register FrameReg,
314  int64_t Offset, int FIOperandNum) {
315  assert(MI.getOpcode() == VE::LDVMrii);
316  LLVM_DEBUG(dbgs() << "processLDVM: "; MI.dump());
317 
318  // Original MI is:
319  // LDVMri reg, frame-index, 0, offset (, memory operand)
320  // Convert it to:
321  // LDrii tmp-reg, frame-reg, 0, offset
322  // LVMir vm, 0, tmp-reg
323  // LDrii tmp-reg, frame-reg, 0, offset+8
324  // LVMir_m vm, 1, tmp-reg, vm
325  // LDrii tmp-reg, frame-reg, 0, offset+16
326  // LVMir_m vm, 2, tmp-reg, vm
327  // LDrii tmp-reg, frame-reg, 0, offset+24
328  // LVMir_m vm, 3, tmp-reg, vm
329 
330  prepareReplaceFI(MI, FrameReg, Offset, 24);
331 
332  Register DestReg = MI.getOperand(0).getReg();
333  // FIXME: it would be better to scavenge a register here instead of
334  // reserving SX16 all of the time.
335  unsigned TmpReg = VE::SX16;
336  for (int i = 0; i < 4; ++i) {
337  if (i != 3) {
338  MachineInstr *StMI =
339  build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
340  replaceFI(*StMI, FrameReg, Offset, 1);
341  Offset += 8;
342  } else {
343  // Last LDrii replace the target instruction.
344  MI.setDesc(get(VE::LDrii));
345  MI.getOperand(0).ChangeToRegister(TmpReg, true);
346  }
347  // First LVM is LVMir. Others are LVMir_m. Last LVM places at the
348  // next of the target instruction.
349  if (i == 0)
350  build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true));
351  else if (i != 3)
352  build(VE::LVMir_m, DestReg)
353  .addImm(i)
354  .addReg(TmpReg, getKillRegState(true))
355  .addReg(DestReg);
356  else
357  BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestReg)
358  .addImm(3)
359  .addReg(TmpReg, getKillRegState(true))
360  .addReg(DestReg);
361  }
362  replaceFI(MI, FrameReg, Offset, FIOperandNum);
363 }
364 
365 void EliminateFrameIndex::processSTVM512(MachineInstr &MI, Register FrameReg,
366  int64_t Offset, int FIOperandNum) {
367  assert(MI.getOpcode() == VE::STVM512rii);
368  LLVM_DEBUG(dbgs() << "processSTVM512: "; MI.dump());
369 
370  prepareReplaceFI(MI, FrameReg, Offset, 56);
371 
372  Register SrcReg = MI.getOperand(3).getReg();
373  Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd);
374  Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even);
375  bool isKill = MI.getOperand(3).isKill();
376  // FIXME: it would be better to scavenge a register here instead of
377  // reserving SX16 all of the time.
378  Register TmpReg = VE::SX16;
379  // store low part of VMP
380  MachineInstr *LastMI = nullptr;
381  for (int i = 0; i < 4; ++i) {
382  LastMI = build(VE::SVMmr, TmpReg).addReg(SrcLoReg).addImm(i);
383  MachineInstr *StMI =
384  build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
385  TmpReg, getKillRegState(true));
386  replaceFI(*StMI, FrameReg, Offset, 0);
387  Offset += 8;
388  }
389  if (isKill)
390  LastMI->addRegisterKilled(SrcLoReg, &TRI, true);
391  // store high part of VMP
392  for (int i = 0; i < 3; ++i) {
393  build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(i);
394  MachineInstr *StMI =
395  build(VE::STrii).addReg(FrameReg).addImm(0).addImm(0).addReg(
396  TmpReg, getKillRegState(true));
397  replaceFI(*StMI, FrameReg, Offset, 0);
398  Offset += 8;
399  }
400  LastMI = build(VE::SVMmr, TmpReg).addReg(SrcHiReg).addImm(3);
401  if (isKill) {
402  LastMI->addRegisterKilled(SrcHiReg, &TRI, true);
403  // Add implicit super-register kills to the particular MI.
404  LastMI->addRegisterKilled(SrcReg, &TRI, true);
405  }
406  MI.setDesc(get(VE::STrii));
407  MI.getOperand(3).ChangeToRegister(TmpReg, false, false, true);
408  replaceFI(MI, FrameReg, Offset, FIOperandNum);
409 }
410 
411 void EliminateFrameIndex::processLDVM512(MachineInstr &MI, Register FrameReg,
412  int64_t Offset, int FIOperandNum) {
413  assert(MI.getOpcode() == VE::LDVM512rii);
414  LLVM_DEBUG(dbgs() << "processLDVM512: "; MI.dump());
415 
416  prepareReplaceFI(MI, FrameReg, Offset, 56);
417 
418  Register DestReg = MI.getOperand(0).getReg();
419  Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd);
420  Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even);
421  // FIXME: it would be better to scavenge a register here instead of
422  // reserving SX16 all of the time.
423  Register TmpReg = VE::SX16;
424  build(VE::IMPLICIT_DEF, DestReg);
425  for (int i = 0; i < 4; ++i) {
426  MachineInstr *LdMI =
427  build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
428  replaceFI(*LdMI, FrameReg, Offset, 1);
429  build(VE::LVMir_m, DestLoReg)
430  .addImm(i)
431  .addReg(TmpReg, getKillRegState(true))
432  .addReg(DestLoReg);
433  Offset += 8;
434  }
435  for (int i = 0; i < 3; ++i) {
436  MachineInstr *LdMI =
437  build(VE::LDrii, TmpReg).addReg(FrameReg).addImm(0).addImm(0);
438  replaceFI(*LdMI, FrameReg, Offset, 1);
439  build(VE::LVMir_m, DestHiReg)
440  .addImm(i)
441  .addReg(TmpReg, getKillRegState(true))
442  .addReg(DestHiReg);
443  Offset += 8;
444  }
445  MI.setDesc(get(VE::LDrii));
446  MI.getOperand(0).ChangeToRegister(TmpReg, true);
447  BuildMI(*MI.getParent(), std::next(II), DL, get(VE::LVMir_m), DestHiReg)
448  .addImm(3)
449  .addReg(TmpReg, getKillRegState(true))
450  .addReg(DestHiReg);
451  replaceFI(MI, FrameReg, Offset, FIOperandNum);
452 }
453 
455  int64_t Offset, int FIOperandNum) {
456  switch (MI.getOpcode()) {
457  case VE::STQrii:
458  processSTQ(MI, FrameReg, Offset, FIOperandNum);
459  return;
460  case VE::LDQrii:
461  processLDQ(MI, FrameReg, Offset, FIOperandNum);
462  return;
463  case VE::STVMrii:
464  processSTVM(MI, FrameReg, Offset, FIOperandNum);
465  return;
466  case VE::LDVMrii:
467  processLDVM(MI, FrameReg, Offset, FIOperandNum);
468  return;
469  case VE::STVM512rii:
470  processSTVM512(MI, FrameReg, Offset, FIOperandNum);
471  return;
472  case VE::LDVM512rii:
473  processLDVM512(MI, FrameReg, Offset, FIOperandNum);
474  return;
475  }
476  prepareReplaceFI(MI, FrameReg, Offset);
477  replaceFI(MI, FrameReg, Offset, FIOperandNum);
478 }
479 
481  int SPAdj, unsigned FIOperandNum,
482  RegScavenger *RS) const {
483  assert(SPAdj == 0 && "Unexpected");
484 
485  MachineInstr &MI = *II;
486  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
487 
488  MachineFunction &MF = *MI.getParent()->getParent();
489  const VESubtarget &Subtarget = MF.getSubtarget<VESubtarget>();
490  const VEFrameLowering &TFI = *getFrameLowering(MF);
491  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
492  const VERegisterInfo &TRI = *Subtarget.getRegisterInfo();
493  DebugLoc DL = MI.getDebugLoc();
494  EliminateFrameIndex EFI(TII, TRI, DL, *MI.getParent(), II);
495 
496  // Retrieve FrameReg and byte offset for stack slot.
497  Register FrameReg;
498  int64_t Offset =
499  TFI.getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed();
500  Offset += MI.getOperand(FIOperandNum + offsetToDisp(MI)).getImm();
501 
502  EFI.processMI(MI, FrameReg, Offset, FIOperandNum);
503  return false;
504 }
505 
507  return VE::SX9;
508 }
i
i
Definition: README.txt:29
llvm::VERegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: VERegisterInfo.cpp:39
EliminateFrameIndex
Definition: VERegisterInfo.cpp:129
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::VERegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: VERegisterInfo.cpp:62
llvm::VERegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:506
replaceFI
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr)
Definition: SparcRegisterInfo.cpp:111
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
offsetToDisp
static unsigned offsetToDisp(MachineInstr &MI)
Definition: VERegisterInfo.cpp:105
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::VESubtarget::getRegisterInfo
const VERegisterInfo * getRegisterInfo() const override
Definition: VESubtarget.h:55
TargetInstrInfo.h
STLExtras.h
llvm::Lo_32
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition: MathExtras.h:335
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::CallingConv::PreserveAll
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
CommandLine.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1877
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:465
BitVector.h
llvm::BitVector
Definition: BitVector.h:75
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VERegisterInfo::eliminateFrameIndex
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: VERegisterInfo.cpp:480
llvm::Hi_32
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition: MathExtras.h:330
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
EliminateFrameIndex::processMI
void processMI(MachineInstr &MI, Register FrameReg, int64_t Offset, int FIOperandNum)
Definition: VERegisterInfo.cpp:454
llvm::RegScavenger
Definition: RegisterScavenging.h:34
VERegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::VEFrameLowering
Definition: VEFrameLowering.h:23
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
VEGenRegisterInfo
llvm::MachineFunction
Definition: MachineFunction.h:257
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:136
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VESubtarget::getInstrInfo
const VEInstrInfo * getInstrInfo() const override
Definition: VESubtarget.h:51
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
MachineFrameInfo.h
llvm::VERegisterInfo
Definition: VERegisterInfo.h:22
EliminateFrameIndex::EliminateFrameIndex
EliminateFrameIndex(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const DebugLoc &DL, MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Definition: VERegisterInfo.cpp:186
VE.h
llvm::VERegisterInfo::VERegisterInfo
VERegisterInfo()
Definition: VERegisterInfo.cpp:36
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
MachineInstrBuilder.h
llvm::VESubtarget
Definition: VESubtarget.h:31
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
llvm::PseudoProbeAttributes::Reserved
@ Reserved
VESubtarget.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1142
llvm::VE
Definition: VEFixupKinds.h:15
llvm::VERegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
Definition: VERegisterInfo.cpp:50
llvm::VERegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:66
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::VERegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Definition: VERegisterInfo.cpp:100
RRCAS_multi_cases
#define RRCAS_multi_cases(NAME)
Debug.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::irsymtab::build
Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
Definition: IRSymtab.cpp:365