63 return TE.OldOpc < Opc;
66#include "X86GenCompressEVEXTables.inc"
68#define COMP_EVEX_DESC "Compressing EVEX instrs when possible"
69#define COMP_EVEX_NAME "x86-compress-evex"
71#define DEBUG_TYPE COMP_EVEX_NAME
86 MachineFunctionProperties::Property::NoVRegs);
92char CompressEVEXPass::ID = 0;
95 auto isHiRegIdx = [](
unsigned Reg) {
97 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
100 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
116 "ZMM instructions should not be in the EVEX->VEX tables");
127 unsigned Opc =
MI.getOpcode();
129 case X86::VALIGNDZ128rri:
130 case X86::VALIGNDZ128rmi:
131 case X86::VALIGNQZ128rri:
132 case X86::VALIGNQZ128rmi: {
133 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
134 "Unexpected new opcode!");
136 (Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
138 Imm.setImm(Imm.getImm() * Scale);
141 case X86::VSHUFF32X4Z256rmi:
142 case X86::VSHUFF32X4Z256rri:
143 case X86::VSHUFF64X2Z256rmi:
144 case X86::VSHUFF64X2Z256rri:
145 case X86::VSHUFI32X4Z256rmi:
146 case X86::VSHUFI32X4Z256rri:
147 case X86::VSHUFI64X2Z256rmi:
148 case X86::VSHUFI64X2Z256rri: {
149 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
150 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
151 "Unexpected new opcode!");
153 int64_t ImmVal = Imm.getImm();
155 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
158 case X86::VRNDSCALEPDZ128rri:
159 case X86::VRNDSCALEPDZ128rmi:
160 case X86::VRNDSCALEPSZ128rri:
161 case X86::VRNDSCALEPSZ128rmi:
162 case X86::VRNDSCALEPDZ256rri:
163 case X86::VRNDSCALEPDZ256rmi:
164 case X86::VRNDSCALEPSZ256rri:
165 case X86::VRNDSCALEPSZ256rmi:
166 case X86::VRNDSCALESDZr:
167 case X86::VRNDSCALESDZm:
168 case X86::VRNDSCALESSZr:
169 case X86::VRNDSCALESSZm:
170 case X86::VRNDSCALESDZr_Int:
171 case X86::VRNDSCALESDZm_Int:
172 case X86::VRNDSCALESSZr_Int:
173 case X86::VRNDSCALESSZm_Int:
175 int64_t ImmVal = Imm.getImm();
177 if ((ImmVal & 0xf) != ImmVal)
199 if (!
Desc.isCommutable() ||
Desc.getNumOperands() < 3 ||
200 !
MI.getOperand(2).isReg() ||
MI.getOperand(2).getReg() != Reg0)
203 ST.getInstrInfo()->commuteInstruction(
MI,
false, 1, 2);
228 unsigned Opc =
MI.getOpcode();
233 bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
239 Opc =
MI.getOpcode();
241 if (
I == Table.
end() ||
I->OldOpc != Opc) {
242 assert(!IsNDLike &&
"Missing entry for ND-like instruction");
252 const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(
I->NewOpc);
265 "Unknown EVEX2EVEX compression");
270 MI.setAsmPrinterFlag(AsmComment);
272 MI.tieOperands(0, 1);
280 static std::atomic<bool> TableChecked(
false);
281 if (!TableChecked.load(std::memory_order_relaxed)) {
283 "X86CompressEVEXTable is not sorted!");
284 TableChecked.store(
true, std::memory_order_relaxed);
288 if (!
ST.hasAVX512() && !
ST.hasEGPR() && !
ST.hasNDD())
291 bool Changed =
false;
305 return new CompressEVEXPass();
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc)
static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST)
static bool isRedundantNewDataDest(MachineInstr &MI, const X86Subtarget &ST)
static bool usesExtendedRegister(const MachineInstr &MI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
FunctionPass class - This class is used to implement most global optimizations.
Describe properties that are true of each instruction in the target description file.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool hasNewDataDest(uint64_t TSFlags)
bool isZMMReg(unsigned RegNo)
bool isApxExtendedReg(unsigned RegNo)
@ EVEX
EVEX - Specifies that this instruction use EVEX form which provides syntax support up to 32 512-bit r...
@ VEX
VEX - encoding using 0xC4/0xC5.
@ LEGACY
LEGACY - encoding using REX/REX2 or w/o opcode prefix.
int getFirstAddrOperandIdx(const MachineInstr &MI)
Return the index of the instruction's first address operand, if it has a memory reference,...
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createX86CompressEVEXPass()
This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
bool operator<(const X86CompressEVEXTableEntry &RHS) const
friend bool operator<(const X86CompressEVEXTableEntry &TE, unsigned Opc)
Description of the encoding of one expression Op.