LLVM  15.0.0git
X86TileConfig.cpp
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1 //===-- X86TileConfig.cpp - Tile Register Configure----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Pass to config the shape of AMX physical registers
10 /// AMX register need to be configured before use. In X86PreTileConfig pass
11 /// the pldtilecfg instruction is inserted, however at that time we don't
12 /// know the shape of each physical tile registers, because the register
13 /// allocation is not done yet. This pass runs after egister allocation
14 /// pass. It collects the shape information of each physical tile register
15 /// and store the shape in the stack slot that is allocated for load config
16 /// to tile config register.
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "X86.h"
21 #include "X86InstrBuilder.h"
22 #include "X86MachineFunctionInfo.h"
23 #include "X86RegisterInfo.h"
24 #include "X86Subtarget.h"
30 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/InitializePasses.h"
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "tileconfig"
40 
41 namespace {
42 
43 struct X86TileConfig : public MachineFunctionPass {
44 
45  X86TileConfig() : MachineFunctionPass(ID) {}
46 
47  /// Return the pass name.
48  StringRef getPassName() const override { return "Tile Register Configure"; }
49 
50  /// X86TileConfig analysis usage.
51  void getAnalysisUsage(AnalysisUsage &AU) const override {
52  AU.setPreservesAll();
53  AU.addRequired<VirtRegMap>();
56  }
57 
58  /// Perform register allocation.
59  bool runOnMachineFunction(MachineFunction &mf) override;
60 
61  MachineFunctionProperties getRequiredProperties() const override {
64  }
65 
66  static char ID;
67 };
68 
69 } // end anonymous namespace
70 
71 char X86TileConfig::ID = 0;
72 
73 INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure",
74  false, false)
77  false)
78 
79 bool X86TileConfig::runOnMachineFunction(MachineFunction &MF) {
80  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
81  const TargetRegisterInfo *TRI = ST.getRegisterInfo();
82  const TargetInstrInfo *TII = ST.getInstrInfo();
83  MachineRegisterInfo &MRI = MF.getRegInfo();
84  LiveIntervals &LIS = getAnalysis<LiveIntervals>();
85  VirtRegMap &VRM = getAnalysis<VirtRegMap>();
86 
87  if (VRM.isShapeMapEmpty())
88  return false;
89 
90  int SS = INT_MAX;
91  for (MachineBasicBlock &MBB : MF) {
92  for (MachineInstr &MI : MBB) {
93  if (MI.getOpcode() == X86::PLDTILECFGV) {
94  SS = MI.getOperand(0).getIndex();
95  break;
96  }
97  }
98  if (SS != INT_MAX)
99  break;
100  }
101  // Didn't find PLDTILECFGV, just return false;
102  if (SS == INT_MAX)
103  return false;
104 
105  // Try to find a point to insert MIs for constant shapes.
106  // Here we are leveraging the palette id inserted in PreRA pass.
107  unsigned ConstPos = 0;
108  MachineInstr *ConstMI = nullptr;
109  for (MachineInstr &MI : MF.front()) {
110  if (MI.getOpcode() == X86::MOV8mi && SS == MI.getOperand(0).getIndex()) {
111  ConstMI = &MI;
112  break;
113  }
114  ++ConstPos;
115  }
116  assert(ConstMI && "Cannot find an insertion point");
117 
118  unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();
119  SmallVector<Register, 8> Phys2Virt(AMXRegNum, 0);
120  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
122  if (MRI.reg_nodbg_empty(VirtReg))
123  continue;
124  if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID)
125  continue;
126  if (VRM.getPhys(VirtReg) == VirtRegMap::NO_PHYS_REG)
127  continue;
128  unsigned Index = VRM.getPhys(VirtReg) - X86::TMM0;
129  if (!Phys2Virt[Index])
130  Phys2Virt[Index] = VirtReg;
131  }
132 
133  // Fill in the shape of each tile physical register.
134  for (unsigned I = 0; I < AMXRegNum; ++I) {
135  if (!Phys2Virt[I])
136  continue;
137  DebugLoc DL;
138  bool IsRow = true;
139  MachineInstr *NewMI = nullptr;
140  ShapeT Shape = VRM.getShape(Phys2Virt[I]);
141  for (auto &R : {Shape.getRow()->getReg(), Shape.getCol()->getReg()}) {
142  // Here is the data format for the tile config.
143  // 0 palette
144  // 1 start_row
145  // 2-15 reserved, must be zero
146  // 16-17 tile0.colsb Tile 0 bytes per row.
147  // 18-19 tile1.colsb Tile 1 bytes per row.
148  // 20-21 tile2.colsb Tile 2 bytes per row.
149  // ... (sequence continues)
150  // 30-31 tile7.colsb Tile 7 bytes per row.
151  // 32-47 reserved, must be zero
152  // 48 tile0.rows Tile 0 rows.
153  // 49 tile1.rows Tile 1 rows.
154  // 50 tile2.rows Tile 2 rows.
155  // ... (sequence continues)
156  // 55 tile7.rows Tile 7 rows.
157  // 56-63 reserved, must be zero
158  int64_t Imm = INT64_MAX;
159  int Offset = IsRow ? 48 + I : 16 + I * 2;
160  for (auto &DefMI : MRI.def_instructions(R)) {
161  MachineBasicBlock &MBB = *DefMI.getParent();
162  if (DefMI.isMoveImmediate()) {
163  if (Imm != INT64_MAX) {
164  // FIXME: We should handle this case in future.
165  assert(Imm == DefMI.getOperand(1).getImm() &&
166  "Cannot initialize with different shapes");
167  continue;
168  }
169  Imm = DefMI.getOperand(1).getImm();
170  NewMI = addFrameReference(
171  BuildMI(MF.front(), ++ConstMI->getIterator(), DL,
172  TII->get(IsRow ? X86::MOV8mi : X86::MOV16mi)),
173  SS, Offset)
174  .addImm(Imm);
175  ConstMI = NewMI;
176  LIS.InsertMachineInstrInMaps(*NewMI);
177  } else {
178  unsigned SubIdx = IsRow ? X86::sub_8bit : X86::sub_16bit;
179  unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
180  if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16))
181  SubIdx = 0;
182  auto Iter = DefMI.getIterator();
183  if (&MBB == &MF.front() &&
184  (unsigned)std::distance(MBB.instr_begin(), Iter) < ConstPos)
185  Iter = ConstMI->getIterator();
186  NewMI = addFrameReference(
187  BuildMI(MBB, ++Iter, DL,
188  TII->get(IsRow ? X86::MOV8mr : X86::MOV16mr)),
189  SS, Offset)
190  .addReg(R, 0, SubIdx);
191  SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
192  LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});
193  }
194  }
195  IsRow = false;
196  }
197  }
198  return true;
199 }
200 
201 FunctionPass *llvm::createX86TileConfigPass() { return new X86TileConfig(); }
TileShapeInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ShapeT::getRow
MachineOperand * getRow() const
Definition: TileShapeInfo.h:57
X86Subtarget.h
llvm::VirtRegMap::isShapeMapEmpty
bool isShapeMapEmpty() const
Definition: VirtRegMap.h:114
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:121
X86InstrBuilder.h
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
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Definition: X86Subtarget.h:52
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
TargetInstrInfo.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:765
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::ShapeT
Definition: TileShapeInfo.h:30
llvm::createX86TileConfigPass
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
Definition: X86TileConfig.cpp:201
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
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void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
MachineRegisterInfo.h
X86MachineFunctionInfo.h
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:266
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::ShapeT::getCol
MachineOperand * getCol() const
Definition: TileShapeInfo.h:59
llvm::VirtRegMap::NO_PHYS_REG
@ NO_PHYS_REG
Definition: VirtRegMap.h:36
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false, false) INITIALIZE_PASS_END(X86TileConfig
Passes.h
llvm::X86AS::SS
@ SS
Definition: X86.h:193
Configure
Tile Register Configure
Definition: X86TileConfig.cpp:76
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
VirtRegMap.h
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::MachineRegisterInfo::def_instructions
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:413
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:262
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::VirtRegMap::getShape
ShapeT getShape(Register virtReg) const
Definition: VirtRegMap.h:120
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
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self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
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unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:80
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@ NoPHIs
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
llvm::LiveIntervals::extendToIndices
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
Definition: LiveIntervals.cpp:631
MachineFrameInfo.h
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Definition: MachineBasicBlock.h:257
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Definition: LiveIntervals.h:54
X86RegisterInfo.h
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@ Imm
Definition: RISCVMatInt.h:23
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MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
DefMI
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Definition: AArch64ExpandPseudoInsts.cpp:104
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FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
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AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
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bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
InitializePasses.h
TargetRegisterInfo.h
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86TileConfig.cpp:39
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unsigned ID
Definition: TargetTransformInfo.h:38