LLVM  9.0.0svn
RISCVISelLowering.cpp
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1 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVISelLowering.h"
15 #include "RISCV.h"
17 #include "RISCVRegisterInfo.h"
18 #include "RISCVSubtarget.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
30 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/Support/Debug.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "riscv-lower"
39 
40 STATISTIC(NumTailCalls, "Number of tail calls");
41 
43  const RISCVSubtarget &STI)
44  : TargetLowering(TM), Subtarget(STI) {
45 
46  if (Subtarget.isRV32E())
47  report_fatal_error("Codegen not yet implemented for RV32E");
48 
49  RISCVABI::ABI ABI = Subtarget.getTargetABI();
50  assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
51 
52  switch (ABI) {
53  default:
54  report_fatal_error("Don't know how to lower this ABI");
58  case RISCVABI::ABI_LP64:
61  break;
62  }
63 
64  MVT XLenVT = Subtarget.getXLenVT();
65 
66  // Set up the register classes.
67  addRegisterClass(XLenVT, &RISCV::GPRRegClass);
68 
69  if (Subtarget.hasStdExtF())
70  addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
71  if (Subtarget.hasStdExtD())
72  addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
73 
74  // Compute derived properties from the register classes.
76 
78 
79  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
80  setLoadExtAction(N, XLenVT, MVT::i1, Promote);
81 
82  // TODO: add all necessary setOperationAction calls.
84 
89 
92 
97 
98  for (auto VT : {MVT::i1, MVT::i8, MVT::i16})
100 
101  if (Subtarget.is64Bit()) {
105  }
106 
107  if (!Subtarget.hasStdExtM()) {
115  }
116 
117  if (Subtarget.is64Bit() && Subtarget.hasStdExtM()) {
121  }
122 
127 
131 
138 
139  ISD::CondCode FPCCToExtend[] = {
143 
144  ISD::NodeType FPOpToExtend[] = {
146 
147  if (Subtarget.hasStdExtF()) {
150  for (auto CC : FPCCToExtend)
155  for (auto Op : FPOpToExtend)
157  }
158 
159  if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
161 
162  if (Subtarget.hasStdExtD()) {
165  for (auto CC : FPCCToExtend)
172  for (auto Op : FPOpToExtend)
174  }
175 
179 
180  if (Subtarget.hasStdExtA()) {
183  } else {
185  }
186 
188 
189  // Function alignments (log2).
190  unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
191  setMinFunctionAlignment(FunctionAlignment);
192  setPrefFunctionAlignment(FunctionAlignment);
193 
194  // Effectively disable jump table generation.
196 }
197 
199  EVT VT) const {
200  if (!VT.isVector())
201  return getPointerTy(DL);
203 }
204 
206  const CallInst &I,
207  MachineFunction &MF,
208  unsigned Intrinsic) const {
209  switch (Intrinsic) {
210  default:
211  return false;
212  case Intrinsic::riscv_masked_atomicrmw_xchg_i32:
213  case Intrinsic::riscv_masked_atomicrmw_add_i32:
214  case Intrinsic::riscv_masked_atomicrmw_sub_i32:
215  case Intrinsic::riscv_masked_atomicrmw_nand_i32:
216  case Intrinsic::riscv_masked_atomicrmw_max_i32:
217  case Intrinsic::riscv_masked_atomicrmw_min_i32:
218  case Intrinsic::riscv_masked_atomicrmw_umax_i32:
219  case Intrinsic::riscv_masked_atomicrmw_umin_i32:
220  case Intrinsic::riscv_masked_cmpxchg_i32:
221  PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
223  Info.memVT = MVT::getVT(PtrTy->getElementType());
224  Info.ptrVal = I.getArgOperand(0);
225  Info.offset = 0;
226  Info.align = 4;
229  return true;
230  }
231 }
232 
234  const AddrMode &AM, Type *Ty,
235  unsigned AS,
236  Instruction *I) const {
237  // No global is ever allowed as a base.
238  if (AM.BaseGV)
239  return false;
240 
241  // Require a 12-bit signed offset.
242  if (!isInt<12>(AM.BaseOffs))
243  return false;
244 
245  switch (AM.Scale) {
246  case 0: // "r+i" or just "i", depending on HasBaseReg.
247  break;
248  case 1:
249  if (!AM.HasBaseReg) // allow "r+i".
250  break;
251  return false; // disallow "r+r" or "r+r+i".
252  default:
253  return false;
254  }
255 
256  return true;
257 }
258 
260  return isInt<12>(Imm);
261 }
262 
264  return isInt<12>(Imm);
265 }
266 
267 // On RV32, 64-bit integers are split into their high and low parts and held
268 // in two different registers, so the trunc is free since the low register can
269 // just be used.
270 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
271  if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
272  return false;
273  unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();
274  unsigned DestBits = DstTy->getPrimitiveSizeInBits();
275  return (SrcBits == 64 && DestBits == 32);
276 }
277 
278 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
279  if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() ||
280  !SrcVT.isInteger() || !DstVT.isInteger())
281  return false;
282  unsigned SrcBits = SrcVT.getSizeInBits();
283  unsigned DestBits = DstVT.getSizeInBits();
284  return (SrcBits == 64 && DestBits == 32);
285 }
286 
288  // Zexts are free if they can be combined with a load.
289  if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
290  EVT MemVT = LD->getMemoryVT();
291  if ((MemVT == MVT::i8 || MemVT == MVT::i16 ||
292  (Subtarget.is64Bit() && MemVT == MVT::i32)) &&
293  (LD->getExtensionType() == ISD::NON_EXTLOAD ||
294  LD->getExtensionType() == ISD::ZEXTLOAD))
295  return true;
296  }
297 
298  return TargetLowering::isZExtFree(Val, VT2);
299 }
300 
302  return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
303 }
304 
306  return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
307  (VT == MVT::f64 && Subtarget.hasStdExtD());
308 }
309 
310 // Changes the condition code and swaps operands if necessary, so the SetCC
311 // operation matches one of the comparisons supported directly in the RISC-V
312 // ISA.
313 static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
314  switch (CC) {
315  default:
316  break;
317  case ISD::SETGT:
318  case ISD::SETLE:
319  case ISD::SETUGT:
320  case ISD::SETULE:
322  std::swap(LHS, RHS);
323  break;
324  }
325 }
326 
327 // Return the RISC-V branch opcode that matches the given DAG integer
328 // condition code. The CondCode must be one of those supported by the RISC-V
329 // ISA (see normaliseSetCC).
331  switch (CC) {
332  default:
333  llvm_unreachable("Unsupported CondCode");
334  case ISD::SETEQ:
335  return RISCV::BEQ;
336  case ISD::SETNE:
337  return RISCV::BNE;
338  case ISD::SETLT:
339  return RISCV::BLT;
340  case ISD::SETGE:
341  return RISCV::BGE;
342  case ISD::SETULT:
343  return RISCV::BLTU;
344  case ISD::SETUGE:
345  return RISCV::BGEU;
346  }
347 }
348 
350  SelectionDAG &DAG) const {
351  switch (Op.getOpcode()) {
352  default:
353  report_fatal_error("unimplemented operand");
354  case ISD::GlobalAddress:
355  return lowerGlobalAddress(Op, DAG);
356  case ISD::BlockAddress:
357  return lowerBlockAddress(Op, DAG);
358  case ISD::ConstantPool:
359  return lowerConstantPool(Op, DAG);
360  case ISD::SELECT:
361  return lowerSELECT(Op, DAG);
362  case ISD::VASTART:
363  return lowerVASTART(Op, DAG);
364  case ISD::FRAMEADDR:
365  return lowerFRAMEADDR(Op, DAG);
366  case ISD::RETURNADDR:
367  return lowerRETURNADDR(Op, DAG);
368  case ISD::SHL_PARTS:
369  return lowerShiftLeftParts(Op, DAG);
370  case ISD::SRA_PARTS:
371  return lowerShiftRightParts(Op, DAG, true);
372  case ISD::SRL_PARTS:
373  return lowerShiftRightParts(Op, DAG, false);
374  case ISD::BITCAST: {
375  assert(Subtarget.is64Bit() && Subtarget.hasStdExtF() &&
376  "Unexpected custom legalisation");
377  SDLoc DL(Op);
378  SDValue Op0 = Op.getOperand(0);
379  if (Op.getValueType() != MVT::f32 || Op0.getValueType() != MVT::i32)
380  return SDValue();
381  SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
382  SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
383  return FPConv;
384  }
385  }
386 }
387 
389  SelectionDAG &DAG, unsigned Flags) {
390  return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
391 }
392 
394  SelectionDAG &DAG, unsigned Flags) {
395  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
396  Flags);
397 }
398 
400  SelectionDAG &DAG, unsigned Flags) {
401  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
402  N->getOffset(), Flags);
403 }
404 
405 template <class NodeTy>
406 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
407  bool IsLocal) const {
408  SDLoc DL(N);
409  EVT Ty = getPointerTy(DAG.getDataLayout());
410 
411  if (isPositionIndependent()) {
412  SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
413  if (IsLocal)
414  // Use PC-relative addressing to access the symbol. This generates the
415  // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
416  // %pcrel_lo(auipc)).
417  return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
418 
419  // Use PC-relative addressing to access the GOT for this symbol, then load
420  // the address from the GOT. This generates the pattern (PseudoLA sym),
421  // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
422  return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
423  }
424 
425  switch (getTargetMachine().getCodeModel()) {
426  default:
427  report_fatal_error("Unsupported code model for lowering");
428  case CodeModel::Small: {
429  // Generate a sequence for accessing addresses within the first 2 GiB of
430  // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
431  SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI);
432  SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO);
433  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
434  return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0);
435  }
436  case CodeModel::Medium: {
437  // Generate a sequence for accessing addresses within any 2GiB range within
438  // the address space. This generates the pattern (PseudoLLA sym), which
439  // expands to (addi (auipc %pcrel_hi(sym)) %pcrel_lo(auipc)).
440  SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
441  return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
442  }
443  }
444 }
445 
446 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
447  SelectionDAG &DAG) const {
448  SDLoc DL(Op);
449  EVT Ty = Op.getValueType();
450  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
451  int64_t Offset = N->getOffset();
452  MVT XLenVT = Subtarget.getXLenVT();
453 
454  const GlobalValue *GV = N->getGlobal();
455  bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
456  SDValue Addr = getAddr(N, DAG, IsLocal);
457 
458  // In order to maximise the opportunity for common subexpression elimination,
459  // emit a separate ADD node for the global address offset instead of folding
460  // it in the global address node. Later peephole optimisations may choose to
461  // fold it back in when profitable.
462  if (Offset != 0)
463  return DAG.getNode(ISD::ADD, DL, Ty, Addr,
464  DAG.getConstant(Offset, DL, XLenVT));
465  return Addr;
466 }
467 
468 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
469  SelectionDAG &DAG) const {
470  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
471 
472  return getAddr(N, DAG);
473 }
474 
475 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
476  SelectionDAG &DAG) const {
477  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
478 
479  return getAddr(N, DAG);
480 }
481 
482 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
483  SDValue CondV = Op.getOperand(0);
484  SDValue TrueV = Op.getOperand(1);
485  SDValue FalseV = Op.getOperand(2);
486  SDLoc DL(Op);
487  MVT XLenVT = Subtarget.getXLenVT();
488 
489  // If the result type is XLenVT and CondV is the output of a SETCC node
490  // which also operated on XLenVT inputs, then merge the SETCC node into the
491  // lowered RISCVISD::SELECT_CC to take advantage of the integer
492  // compare+branch instructions. i.e.:
493  // (select (setcc lhs, rhs, cc), truev, falsev)
494  // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
495  if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
496  CondV.getOperand(0).getSimpleValueType() == XLenVT) {
497  SDValue LHS = CondV.getOperand(0);
498  SDValue RHS = CondV.getOperand(1);
499  auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
500  ISD::CondCode CCVal = CC->get();
501 
502  normaliseSetCC(LHS, RHS, CCVal);
503 
504  SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
505  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
506  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
507  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
508  }
509 
510  // Otherwise:
511  // (select condv, truev, falsev)
512  // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
513  SDValue Zero = DAG.getConstant(0, DL, XLenVT);
514  SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT);
515 
516  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
517  SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
518 
519  return DAG.getNode(RISCVISD::SELECT_CC, DL, VTs, Ops);
520 }
521 
522 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
525 
526  SDLoc DL(Op);
527  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
529 
530  // vastart just stores the address of the VarArgsFrameIndex slot into the
531  // memory location argument.
532  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
533  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
534  MachinePointerInfo(SV));
535 }
536 
537 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
538  SelectionDAG &DAG) const {
539  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
541  MachineFrameInfo &MFI = MF.getFrameInfo();
542  MFI.setFrameAddressIsTaken(true);
543  unsigned FrameReg = RI.getFrameRegister(MF);
544  int XLenInBytes = Subtarget.getXLen() / 8;
545 
546  EVT VT = Op.getValueType();
547  SDLoc DL(Op);
548  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);
549  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
550  while (Depth--) {
551  int Offset = -(XLenInBytes * 2);
552  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
553  DAG.getIntPtrConstant(Offset, DL));
554  FrameAddr =
555  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
556  }
557  return FrameAddr;
558 }
559 
560 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
561  SelectionDAG &DAG) const {
562  const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo();
564  MachineFrameInfo &MFI = MF.getFrameInfo();
565  MFI.setReturnAddressIsTaken(true);
566  MVT XLenVT = Subtarget.getXLenVT();
567  int XLenInBytes = Subtarget.getXLen() / 8;
568 
570  return SDValue();
571 
572  EVT VT = Op.getValueType();
573  SDLoc DL(Op);
574  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
575  if (Depth) {
576  int Off = -XLenInBytes;
577  SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
578  SDValue Offset = DAG.getConstant(Off, DL, VT);
579  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
580  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
582  }
583 
584  // Return the value of the return address register, marking it an implicit
585  // live-in.
586  unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
587  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
588 }
589 
590 SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
591  SelectionDAG &DAG) const {
592  SDLoc DL(Op);
593  SDValue Lo = Op.getOperand(0);
594  SDValue Hi = Op.getOperand(1);
595  SDValue Shamt = Op.getOperand(2);
596  EVT VT = Lo.getValueType();
597 
598  // if Shamt-XLEN < 0: // Shamt < XLEN
599  // Lo = Lo << Shamt
600  // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt))
601  // else:
602  // Lo = 0
603  // Hi = Lo << (Shamt-XLEN)
604 
605  SDValue Zero = DAG.getConstant(0, DL, VT);
606  SDValue One = DAG.getConstant(1, DL, VT);
607  SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
608  SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
609  SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
610  SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
611 
612  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
613  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
614  SDValue ShiftRightLo =
615  DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt);
616  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
617  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
618  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen);
619 
620  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
621 
622  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
623  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
624 
625  SDValue Parts[2] = {Lo, Hi};
626  return DAG.getMergeValues(Parts, DL);
627 }
628 
629 SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
630  bool IsSRA) const {
631  SDLoc DL(Op);
632  SDValue Lo = Op.getOperand(0);
633  SDValue Hi = Op.getOperand(1);
634  SDValue Shamt = Op.getOperand(2);
635  EVT VT = Lo.getValueType();
636 
637  // SRA expansion:
638  // if Shamt-XLEN < 0: // Shamt < XLEN
639  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
640  // Hi = Hi >>s Shamt
641  // else:
642  // Lo = Hi >>s (Shamt-XLEN);
643  // Hi = Hi >>s (XLEN-1)
644  //
645  // SRL expansion:
646  // if Shamt-XLEN < 0: // Shamt < XLEN
647  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
648  // Hi = Hi >>u Shamt
649  // else:
650  // Lo = Hi >>u (Shamt-XLEN);
651  // Hi = 0;
652 
653  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
654 
655  SDValue Zero = DAG.getConstant(0, DL, VT);
656  SDValue One = DAG.getConstant(1, DL, VT);
657  SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
658  SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
659  SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
660  SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
661 
662  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
663  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
664  SDValue ShiftLeftHi =
665  DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt);
666  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
667  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
668  SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);
669  SDValue HiFalse =
670  IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero;
671 
672  SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
673 
674  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
675  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
676 
677  SDValue Parts[2] = {Lo, Hi};
678  return DAG.getMergeValues(Parts, DL);
679 }
680 
681 // Returns the opcode of the target-specific SDNode that implements the 32-bit
682 // form of the given Opcode.
683 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
684  switch (Opcode) {
685  default:
686  llvm_unreachable("Unexpected opcode");
687  case ISD::SHL:
688  return RISCVISD::SLLW;
689  case ISD::SRA:
690  return RISCVISD::SRAW;
691  case ISD::SRL:
692  return RISCVISD::SRLW;
693  case ISD::SDIV:
694  return RISCVISD::DIVW;
695  case ISD::UDIV:
696  return RISCVISD::DIVUW;
697  case ISD::UREM:
698  return RISCVISD::REMUW;
699  }
700 }
701 
702 // Converts the given 32-bit operation to a target-specific SelectionDAG node.
703 // Because i32 isn't a legal type for RV64, these operations would otherwise
704 // be promoted to i64, making it difficult to select the SLLW/DIVUW/.../*W
705 // later one because the fact the operation was originally of type i32 is
706 // lost.
708  SDLoc DL(N);
710  SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0));
711  SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
712  SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1);
713  // ReplaceNodeResults requires we maintain the same type for the return value.
714  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
715 }
716 
719  SelectionDAG &DAG) const {
720  SDLoc DL(N);
721  switch (N->getOpcode()) {
722  default:
723  llvm_unreachable("Don't know how to custom type legalize this operation!");
724  case ISD::SHL:
725  case ISD::SRA:
726  case ISD::SRL:
727  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
728  "Unexpected custom legalisation");
729  if (N->getOperand(1).getOpcode() == ISD::Constant)
730  return;
731  Results.push_back(customLegalizeToWOp(N, DAG));
732  break;
733  case ISD::SDIV:
734  case ISD::UDIV:
735  case ISD::UREM:
736  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
737  Subtarget.hasStdExtM() && "Unexpected custom legalisation");
738  if (N->getOperand(0).getOpcode() == ISD::Constant ||
740  return;
741  Results.push_back(customLegalizeToWOp(N, DAG));
742  break;
743  case ISD::BITCAST: {
744  assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
745  Subtarget.hasStdExtF() && "Unexpected custom legalisation");
746  SDLoc DL(N);
747  SDValue Op0 = N->getOperand(0);
748  if (Op0.getValueType() != MVT::f32)
749  return;
750  SDValue FPConv =
752  Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
753  break;
754  }
755  }
756 }
757 
759  DAGCombinerInfo &DCI) const {
760  SelectionDAG &DAG = DCI.DAG;
761 
762  switch (N->getOpcode()) {
763  default:
764  break;
765  case RISCVISD::SplitF64: {
766  SDValue Op0 = N->getOperand(0);
767  // If the input to SplitF64 is just BuildPairF64 then the operation is
768  // redundant. Instead, use BuildPairF64's operands directly.
769  if (Op0->getOpcode() == RISCVISD::BuildPairF64)
770  return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
771 
772  SDLoc DL(N);
773 
774  // It's cheaper to materialise two 32-bit integers than to load a double
775  // from the constant pool and transfer it to integer registers through the
776  // stack.
777  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op0)) {
778  APInt V = C->getValueAPF().bitcastToAPInt();
779  SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32);
780  SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32);
781  return DCI.CombineTo(N, Lo, Hi);
782  }
783 
784  // This is a target-specific version of a DAGCombine performed in
785  // DAGCombiner::visitBITCAST. It performs the equivalent of:
786  // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
787  // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
788  if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
789  !Op0.getNode()->hasOneUse())
790  break;
791  SDValue NewSplitF64 =
793  Op0.getOperand(0));
794  SDValue Lo = NewSplitF64.getValue(0);
795  SDValue Hi = NewSplitF64.getValue(1);
796  APInt SignBit = APInt::getSignMask(32);
797  if (Op0.getOpcode() == ISD::FNEG) {
798  SDValue NewHi = DAG.getNode(ISD::XOR, DL, MVT::i32, Hi,
799  DAG.getConstant(SignBit, DL, MVT::i32));
800  return DCI.CombineTo(N, Lo, NewHi);
801  }
802  assert(Op0.getOpcode() == ISD::FABS);
803  SDValue NewHi = DAG.getNode(ISD::AND, DL, MVT::i32, Hi,
804  DAG.getConstant(~SignBit, DL, MVT::i32));
805  return DCI.CombineTo(N, Lo, NewHi);
806  }
807  case RISCVISD::SLLW:
808  case RISCVISD::SRAW:
809  case RISCVISD::SRLW: {
810  // Only the lower 32 bits of LHS and lower 5 bits of RHS are read.
811  SDValue LHS = N->getOperand(0);
812  SDValue RHS = N->getOperand(1);
813  APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32);
814  APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5);
815  if ((SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI)) ||
816  (SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)))
817  return SDValue();
818  break;
819  }
821  SDLoc DL(N);
822  SDValue Op0 = N->getOperand(0);
823  // If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the
824  // conversion is unnecessary and can be replaced with an ANY_EXTEND
825  // of the FMV_W_X_RV64 operand.
826  if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
827  SDValue AExtOp =
828  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0));
829  return DCI.CombineTo(N, AExtOp);
830  }
831 
832  // This is a target-specific version of a DAGCombine performed in
833  // DAGCombiner::visitBITCAST. It performs the equivalent of:
834  // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
835  // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
836  if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
837  !Op0.getNode()->hasOneUse())
838  break;
840  Op0.getOperand(0));
841  APInt SignBit = APInt::getSignMask(32).sext(64);
842  if (Op0.getOpcode() == ISD::FNEG) {
843  return DCI.CombineTo(N,
844  DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV,
845  DAG.getConstant(SignBit, DL, MVT::i64)));
846  }
847  assert(Op0.getOpcode() == ISD::FABS);
848  return DCI.CombineTo(N,
849  DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
850  DAG.getConstant(~SignBit, DL, MVT::i64)));
851  }
852  }
853 
854  return SDValue();
855 }
856 
858  SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
859  unsigned Depth) const {
860  switch (Op.getOpcode()) {
861  default:
862  break;
863  case RISCVISD::SLLW:
864  case RISCVISD::SRAW:
865  case RISCVISD::SRLW:
866  case RISCVISD::DIVW:
867  case RISCVISD::DIVUW:
868  case RISCVISD::REMUW:
869  // TODO: As the result is sign-extended, this is conservatively correct. A
870  // more precise answer could be calculated for SRAW depending on known
871  // bits in the shift amount.
872  return 33;
873  }
874 
875  return 1;
876 }
877 
879  MachineBasicBlock *BB) {
880  assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
881 
882  MachineFunction &MF = *BB->getParent();
883  DebugLoc DL = MI.getDebugLoc();
884  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
885  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
886  unsigned LoReg = MI.getOperand(0).getReg();
887  unsigned HiReg = MI.getOperand(1).getReg();
888  unsigned SrcReg = MI.getOperand(2).getReg();
889  const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
890  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
891 
892  TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
893  RI);
894  MachineMemOperand *MMO =
895  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
897  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
898  .addFrameIndex(FI)
899  .addImm(0)
900  .addMemOperand(MMO);
901  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
902  .addFrameIndex(FI)
903  .addImm(4)
904  .addMemOperand(MMO);
905  MI.eraseFromParent(); // The pseudo instruction is gone now.
906  return BB;
907 }
908 
910  MachineBasicBlock *BB) {
911  assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
912  "Unexpected instruction");
913 
914  MachineFunction &MF = *BB->getParent();
915  DebugLoc DL = MI.getDebugLoc();
916  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
917  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
918  unsigned DstReg = MI.getOperand(0).getReg();
919  unsigned LoReg = MI.getOperand(1).getReg();
920  unsigned HiReg = MI.getOperand(2).getReg();
921  const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
922  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex();
923 
924  MachineMemOperand *MMO =
925  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
927  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
928  .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
929  .addFrameIndex(FI)
930  .addImm(0)
931  .addMemOperand(MMO);
932  BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
933  .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
934  .addFrameIndex(FI)
935  .addImm(4)
936  .addMemOperand(MMO);
937  TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI);
938  MI.eraseFromParent(); // The pseudo instruction is gone now.
939  return BB;
940 }
941 
943  switch (MI.getOpcode()) {
944  default:
945  return false;
946  case RISCV::Select_GPR_Using_CC_GPR:
947  case RISCV::Select_FPR32_Using_CC_GPR:
948  case RISCV::Select_FPR64_Using_CC_GPR:
949  return true;
950  }
951 }
952 
954  MachineBasicBlock *BB) {
955  // To "insert" Select_* instructions, we actually have to insert the triangle
956  // control-flow pattern. The incoming instructions know the destination vreg
957  // to set, the condition code register to branch on, the true/false values to
958  // select between, and the condcode to use to select the appropriate branch.
959  //
960  // We produce the following control flow:
961  // HeadMBB
962  // | \
963  // | IfFalseMBB
964  // | /
965  // TailMBB
966  //
967  // When we find a sequence of selects we attempt to optimize their emission
968  // by sharing the control flow. Currently we only handle cases where we have
969  // multiple selects with the exact same condition (same LHS, RHS and CC).
970  // The selects may be interleaved with other instructions if the other
971  // instructions meet some requirements we deem safe:
972  // - They are debug instructions. Otherwise,
973  // - They do not have side-effects, do not access memory and their inputs do
974  // not depend on the results of the select pseudo-instructions.
975  // The TrueV/FalseV operands of the selects cannot depend on the result of
976  // previous selects in the sequence.
977  // These conditions could be further relaxed. See the X86 target for a
978  // related approach and more information.
979  unsigned LHS = MI.getOperand(1).getReg();
980  unsigned RHS = MI.getOperand(2).getReg();
981  auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
982 
983  SmallVector<MachineInstr *, 4> SelectDebugValues;
984  SmallSet<unsigned, 4> SelectDests;
985  SelectDests.insert(MI.getOperand(0).getReg());
986 
987  MachineInstr *LastSelectPseudo = &MI;
988 
989  for (auto E = BB->end(), SequenceMBBI = MachineBasicBlock::iterator(MI);
990  SequenceMBBI != E; ++SequenceMBBI) {
991  if (SequenceMBBI->isDebugInstr())
992  continue;
993  else if (isSelectPseudo(*SequenceMBBI)) {
994  if (SequenceMBBI->getOperand(1).getReg() != LHS ||
995  SequenceMBBI->getOperand(2).getReg() != RHS ||
996  SequenceMBBI->getOperand(3).getImm() != CC ||
997  SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
998  SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
999  break;
1000  LastSelectPseudo = &*SequenceMBBI;
1001  SequenceMBBI->collectDebugValues(SelectDebugValues);
1002  SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
1003  } else {
1004  if (SequenceMBBI->hasUnmodeledSideEffects() ||
1005  SequenceMBBI->mayLoadOrStore())
1006  break;
1007  if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
1008  return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
1009  }))
1010  break;
1011  }
1012  }
1013 
1014  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1015  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1016  DebugLoc DL = MI.getDebugLoc();
1018 
1019  MachineBasicBlock *HeadMBB = BB;
1020  MachineFunction *F = BB->getParent();
1021  MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB);
1022  MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
1023 
1024  F->insert(I, IfFalseMBB);
1025  F->insert(I, TailMBB);
1026 
1027  // Transfer debug instructions associated with the selects to TailMBB.
1028  for (MachineInstr *DebugInstr : SelectDebugValues) {
1029  TailMBB->push_back(DebugInstr->removeFromParent());
1030  }
1031 
1032  // Move all instructions after the sequence to TailMBB.
1033  TailMBB->splice(TailMBB->end(), HeadMBB,
1034  std::next(LastSelectPseudo->getIterator()), HeadMBB->end());
1035  // Update machine-CFG edges by transferring all successors of the current
1036  // block to the new block which will contain the Phi nodes for the selects.
1037  TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB);
1038  // Set the successors for HeadMBB.
1039  HeadMBB->addSuccessor(IfFalseMBB);
1040  HeadMBB->addSuccessor(TailMBB);
1041 
1042  // Insert appropriate branch.
1043  unsigned Opcode = getBranchOpcodeForIntCondCode(CC);
1044 
1045  BuildMI(HeadMBB, DL, TII.get(Opcode))
1046  .addReg(LHS)
1047  .addReg(RHS)
1048  .addMBB(TailMBB);
1049 
1050  // IfFalseMBB just falls through to TailMBB.
1051  IfFalseMBB->addSuccessor(TailMBB);
1052 
1053  // Create PHIs for all of the select pseudo-instructions.
1054  auto SelectMBBI = MI.getIterator();
1055  auto SelectEnd = std::next(LastSelectPseudo->getIterator());
1056  auto InsertionPoint = TailMBB->begin();
1057  while (SelectMBBI != SelectEnd) {
1058  auto Next = std::next(SelectMBBI);
1059  if (isSelectPseudo(*SelectMBBI)) {
1060  // %Result = phi [ %TrueValue, HeadMBB ], [ %FalseValue, IfFalseMBB ]
1061  BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
1062  TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
1063  .addReg(SelectMBBI->getOperand(4).getReg())
1064  .addMBB(HeadMBB)
1065  .addReg(SelectMBBI->getOperand(5).getReg())
1066  .addMBB(IfFalseMBB);
1067  SelectMBBI->eraseFromParent();
1068  }
1069  SelectMBBI = Next;
1070  }
1071 
1072  return TailMBB;
1073 }
1074 
1077  MachineBasicBlock *BB) const {
1078  switch (MI.getOpcode()) {
1079  default:
1080  llvm_unreachable("Unexpected instr type to insert");
1081  case RISCV::Select_GPR_Using_CC_GPR:
1082  case RISCV::Select_FPR32_Using_CC_GPR:
1083  case RISCV::Select_FPR64_Using_CC_GPR:
1084  return emitSelectPseudo(MI, BB);
1085  case RISCV::BuildPairF64Pseudo:
1086  return emitBuildPairF64Pseudo(MI, BB);
1087  case RISCV::SplitF64Pseudo:
1088  return emitSplitF64Pseudo(MI, BB);
1089  }
1090 }
1091 
1092 // Calling Convention Implementation.
1093 // The expectations for frontend ABI lowering vary from target to target.
1094 // Ideally, an LLVM frontend would be able to avoid worrying about many ABI
1095 // details, but this is a longer term goal. For now, we simply try to keep the
1096 // role of the frontend as simple and well-defined as possible. The rules can
1097 // be summarised as:
1098 // * Never split up large scalar arguments. We handle them here.
1099 // * If a hardfloat calling convention is being used, and the struct may be
1100 // passed in a pair of registers (fp+fp, int+fp), and both registers are
1101 // available, then pass as two separate arguments. If either the GPRs or FPRs
1102 // are exhausted, then pass according to the rule below.
1103 // * If a struct could never be passed in registers or directly in a stack
1104 // slot (as it is larger than 2*XLEN and the floating point rules don't
1105 // apply), then pass it using a pointer with the byval attribute.
1106 // * If a struct is less than 2*XLEN, then coerce to either a two-element
1107 // word-sized array or a 2*XLEN scalar (depending on alignment).
1108 // * The frontend can determine whether a struct is returned by reference or
1109 // not based on its size and fields. If it will be returned by reference, the
1110 // frontend must modify the prototype so a pointer with the sret annotation is
1111 // passed as the first argument. This is not necessary for large scalar
1112 // returns.
1113 // * Struct return values and varargs should be coerced to structs containing
1114 // register-size fields in the same situations they would be for fixed
1115 // arguments.
1116 
1117 static const MCPhysReg ArgGPRs[] = {
1118  RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
1119  RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
1120 };
1121 static const MCPhysReg ArgFPR32s[] = {
1122  RISCV::F10_32, RISCV::F11_32, RISCV::F12_32, RISCV::F13_32,
1123  RISCV::F14_32, RISCV::F15_32, RISCV::F16_32, RISCV::F17_32
1124 };
1125 static const MCPhysReg ArgFPR64s[] = {
1126  RISCV::F10_64, RISCV::F11_64, RISCV::F12_64, RISCV::F13_64,
1127  RISCV::F14_64, RISCV::F15_64, RISCV::F16_64, RISCV::F17_64
1128 };
1129 
1130 // Pass a 2*XLEN argument that has been split into two XLEN values through
1131 // registers or the stack as necessary.
1132 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
1133  ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
1134  MVT ValVT2, MVT LocVT2,
1135  ISD::ArgFlagsTy ArgFlags2) {
1136  unsigned XLenInBytes = XLen / 8;
1137  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
1138  // At least one half can be passed via register.
1139  State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
1140  VA1.getLocVT(), CCValAssign::Full));
1141  } else {
1142  // Both halves must be passed on the stack, with proper alignment.
1143  unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
1144  State.addLoc(
1145  CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
1146  State.AllocateStack(XLenInBytes, StackAlign),
1147  VA1.getLocVT(), CCValAssign::Full));
1149  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1151  return false;
1152  }
1153 
1154  if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
1155  // The second half can also be passed via register.
1156  State.addLoc(
1157  CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
1158  } else {
1159  // The second half is passed via the stack, without additional alignment.
1161  ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
1163  }
1164 
1165  return false;
1166 }
1167 
1168 // Implements the RISC-V calling convention. Returns true upon failure.
1169 static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
1170  MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
1171  ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
1172  bool IsRet, Type *OrigTy) {
1173  unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
1174  assert(XLen == 32 || XLen == 64);
1175  MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
1176 
1177  // Any return value split in to more than two values can't be returned
1178  // directly.
1179  if (IsRet && ValNo > 1)
1180  return true;
1181 
1182  // UseGPRForF32 if targeting one of the soft-float ABIs, if passing a
1183  // variadic argument, or if no F32 argument registers are available.
1184  bool UseGPRForF32 = true;
1185  // UseGPRForF64 if targeting soft-float ABIs or an FLEN=32 ABI, if passing a
1186  // variadic argument, or if no F64 argument registers are available.
1187  bool UseGPRForF64 = true;
1188 
1189  switch (ABI) {
1190  default:
1191  llvm_unreachable("Unexpected ABI");
1192  case RISCVABI::ABI_ILP32:
1193  case RISCVABI::ABI_LP64:
1194  break;
1195  case RISCVABI::ABI_ILP32F:
1196  case RISCVABI::ABI_LP64F:
1197  UseGPRForF32 = !IsFixed;
1198  break;
1199  case RISCVABI::ABI_ILP32D:
1200  case RISCVABI::ABI_LP64D:
1201  UseGPRForF32 = !IsFixed;
1202  UseGPRForF64 = !IsFixed;
1203  break;
1204  }
1205 
1207  UseGPRForF32 = true;
1209  UseGPRForF64 = true;
1210 
1211  // From this point on, rely on UseGPRForF32, UseGPRForF64 and similar local
1212  // variables rather than directly checking against the target ABI.
1213 
1214  if (UseGPRForF32 && ValVT == MVT::f32) {
1215  LocVT = XLenVT;
1216  LocInfo = CCValAssign::BCvt;
1217  } else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) {
1218  LocVT = MVT::i64;
1219  LocInfo = CCValAssign::BCvt;
1220  }
1221 
1222  // If this is a variadic argument, the RISC-V calling convention requires
1223  // that it is assigned an 'even' or 'aligned' register if it has 8-byte
1224  // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
1225  // be used regardless of whether the original argument was split during
1226  // legalisation or not. The argument will not be passed by registers if the
1227  // original type is larger than 2*XLEN, so the register alignment rule does
1228  // not apply.
1229  unsigned TwoXLenInBytes = (2 * XLen) / 8;
1230  if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
1231  DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
1232  unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
1233  // Skip 'odd' register if necessary.
1234  if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
1235  State.AllocateReg(ArgGPRs);
1236  }
1237 
1238  SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
1239  SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
1240  State.getPendingArgFlags();
1241 
1242  assert(PendingLocs.size() == PendingArgFlags.size() &&
1243  "PendingLocs and PendingArgFlags out of sync");
1244 
1245  // Handle passing f64 on RV32D with a soft float ABI or when floating point
1246  // registers are exhausted.
1247  if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
1248  assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
1249  "Can't lower f64 if it is split");
1250  // Depending on available argument GPRS, f64 may be passed in a pair of
1251  // GPRs, split between a GPR and the stack, or passed completely on the
1252  // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
1253  // cases.
1254  unsigned Reg = State.AllocateReg(ArgGPRs);
1255  LocVT = MVT::i32;
1256  if (!Reg) {
1257  unsigned StackOffset = State.AllocateStack(8, 8);
1258  State.addLoc(
1259  CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
1260  return false;
1261  }
1262  if (!State.AllocateReg(ArgGPRs))
1263  State.AllocateStack(4, 4);
1264  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1265  return false;
1266  }
1267 
1268  // Split arguments might be passed indirectly, so keep track of the pending
1269  // values.
1270  if (ArgFlags.isSplit() || !PendingLocs.empty()) {
1271  LocVT = XLenVT;
1272  LocInfo = CCValAssign::Indirect;
1273  PendingLocs.push_back(
1274  CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
1275  PendingArgFlags.push_back(ArgFlags);
1276  if (!ArgFlags.isSplitEnd()) {
1277  return false;
1278  }
1279  }
1280 
1281  // If the split argument only had two elements, it should be passed directly
1282  // in registers or on the stack.
1283  if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
1284  assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
1285  // Apply the normal calling convention rules to the first half of the
1286  // split argument.
1287  CCValAssign VA = PendingLocs[0];
1288  ISD::ArgFlagsTy AF = PendingArgFlags[0];
1289  PendingLocs.clear();
1290  PendingArgFlags.clear();
1291  return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
1292  ArgFlags);
1293  }
1294 
1295  // Allocate to a register if possible, or else a stack slot.
1296  unsigned Reg;
1297  if (ValVT == MVT::f32 && !UseGPRForF32)
1298  Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);
1299  else if (ValVT == MVT::f64 && !UseGPRForF64)
1300  Reg = State.AllocateReg(ArgFPR64s, ArgFPR32s);
1301  else
1302  Reg = State.AllocateReg(ArgGPRs);
1303  unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
1304 
1305  // If we reach this point and PendingLocs is non-empty, we must be at the
1306  // end of a split argument that must be passed indirectly.
1307  if (!PendingLocs.empty()) {
1308  assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
1309  assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
1310 
1311  for (auto &It : PendingLocs) {
1312  if (Reg)
1313  It.convertToReg(Reg);
1314  else
1315  It.convertToMem(StackOffset);
1316  State.addLoc(It);
1317  }
1318  PendingLocs.clear();
1319  PendingArgFlags.clear();
1320  return false;
1321  }
1322 
1323  assert((!UseGPRForF32 || !UseGPRForF64 || LocVT == XLenVT) &&
1324  "Expected an XLenVT at this stage");
1325 
1326  if (Reg) {
1327  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1328  return false;
1329  }
1330 
1331  // When an f32 or f64 is passed on the stack, no bit-conversion is needed.
1332  if (ValVT == MVT::f32 || ValVT == MVT::f64) {
1333  LocVT = ValVT;
1334  LocInfo = CCValAssign::Full;
1335  }
1336  State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
1337  return false;
1338 }
1339 
1340 void RISCVTargetLowering::analyzeInputArgs(
1341  MachineFunction &MF, CCState &CCInfo,
1342  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
1343  unsigned NumArgs = Ins.size();
1344  FunctionType *FType = MF.getFunction().getFunctionType();
1345 
1346  for (unsigned i = 0; i != NumArgs; ++i) {
1347  MVT ArgVT = Ins[i].VT;
1348  ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
1349 
1350  Type *ArgTy = nullptr;
1351  if (IsRet)
1352  ArgTy = FType->getReturnType();
1353  else if (Ins[i].isOrigArg())
1354  ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
1355 
1356  RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
1357  if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
1358  ArgFlags, CCInfo, /*IsRet=*/true, IsRet, ArgTy)) {
1359  LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
1360  << EVT(ArgVT).getEVTString() << '\n');
1361  llvm_unreachable(nullptr);
1362  }
1363  }
1364 }
1365 
1366 void RISCVTargetLowering::analyzeOutputArgs(
1367  MachineFunction &MF, CCState &CCInfo,
1368  const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsRet,
1369  CallLoweringInfo *CLI) const {
1370  unsigned NumArgs = Outs.size();
1371 
1372  for (unsigned i = 0; i != NumArgs; i++) {
1373  MVT ArgVT = Outs[i].VT;
1374  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
1375  Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr;
1376 
1377  RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
1378  if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full,
1379  ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
1380  LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
1381  << EVT(ArgVT).getEVTString() << "\n");
1382  llvm_unreachable(nullptr);
1383  }
1384  }
1385 }
1386 
1387 // Convert Val to a ValVT. Should not be called for CCValAssign::Indirect
1388 // values.
1390  const CCValAssign &VA, const SDLoc &DL) {
1391  switch (VA.getLocInfo()) {
1392  default:
1393  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1394  case CCValAssign::Full:
1395  break;
1396  case CCValAssign::BCvt:
1397  if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1398  Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val);
1399  break;
1400  }
1401  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1402  break;
1403  }
1404  return Val;
1405 }
1406 
1407 // The caller is responsible for loading the full value if the argument is
1408 // passed with CCValAssign::Indirect.
1410  const CCValAssign &VA, const SDLoc &DL) {
1411  MachineFunction &MF = DAG.getMachineFunction();
1412  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1413  EVT LocVT = VA.getLocVT();
1414  SDValue Val;
1415  const TargetRegisterClass *RC;
1416 
1417  switch (LocVT.getSimpleVT().SimpleTy) {
1418  default:
1419  llvm_unreachable("Unexpected register type");
1420  case MVT::i32:
1421  case MVT::i64:
1422  RC = &RISCV::GPRRegClass;
1423  break;
1424  case MVT::f32:
1425  RC = &RISCV::FPR32RegClass;
1426  break;
1427  case MVT::f64:
1428  RC = &RISCV::FPR64RegClass;
1429  break;
1430  }
1431 
1432  unsigned VReg = RegInfo.createVirtualRegister(RC);
1433  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1434  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
1435 
1436  if (VA.getLocInfo() == CCValAssign::Indirect)
1437  return Val;
1438 
1439  return convertLocVTToValVT(DAG, Val, VA, DL);
1440 }
1441 
1443  const CCValAssign &VA, const SDLoc &DL) {
1444  EVT LocVT = VA.getLocVT();
1445 
1446  switch (VA.getLocInfo()) {
1447  default:
1448  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1449  case CCValAssign::Full:
1450  break;
1451  case CCValAssign::BCvt:
1452  if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) {
1453  Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val);
1454  break;
1455  }
1456  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
1457  break;
1458  }
1459  return Val;
1460 }
1461 
1462 // The caller is responsible for loading the full value if the argument is
1463 // passed with CCValAssign::Indirect.
1465  const CCValAssign &VA, const SDLoc &DL) {
1466  MachineFunction &MF = DAG.getMachineFunction();
1467  MachineFrameInfo &MFI = MF.getFrameInfo();
1468  EVT LocVT = VA.getLocVT();
1469  EVT ValVT = VA.getValVT();
1471  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
1472  VA.getLocMemOffset(), /*Immutable=*/true);
1473  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1474  SDValue Val;
1475 
1477  switch (VA.getLocInfo()) {
1478  default:
1479  llvm_unreachable("Unexpected CCValAssign::LocInfo");
1480  case CCValAssign::Full:
1481  case CCValAssign::Indirect:
1482  case CCValAssign::BCvt:
1483  ExtType = ISD::NON_EXTLOAD;
1484  break;
1485  }
1486  Val = DAG.getExtLoad(
1487  ExtType, DL, LocVT, Chain, FIN,
1489  return Val;
1490 }
1491 
1493  const CCValAssign &VA, const SDLoc &DL) {
1494  assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 &&
1495  "Unexpected VA");
1496  MachineFunction &MF = DAG.getMachineFunction();
1497  MachineFrameInfo &MFI = MF.getFrameInfo();
1498  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1499 
1500  if (VA.isMemLoc()) {
1501  // f64 is passed on the stack.
1502  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
1503  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1504  return DAG.getLoad(MVT::f64, DL, Chain, FIN,
1506  }
1507 
1508  assert(VA.isRegLoc() && "Expected register VA assignment");
1509 
1510  unsigned LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1511  RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
1512  SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
1513  SDValue Hi;
1514  if (VA.getLocReg() == RISCV::X17) {
1515  // Second half of f64 is passed on the stack.
1516  int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
1517  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1518  Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
1520  } else {
1521  // Second half of f64 is passed in another GPR.
1522  unsigned HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1523  RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
1524  Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
1525  }
1526  return DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1527 }
1528 
1529 // Transform physical registers into virtual registers.
1530 SDValue RISCVTargetLowering::LowerFormalArguments(
1531  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1532  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1533  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1534 
1535  switch (CallConv) {
1536  default:
1537  report_fatal_error("Unsupported calling convention");
1538  case CallingConv::C:
1539  case CallingConv::Fast:
1540  break;
1541  }
1542 
1543  MachineFunction &MF = DAG.getMachineFunction();
1544 
1545  const Function &Func = MF.getFunction();
1546  if (Func.hasFnAttribute("interrupt")) {
1547  if (!Func.arg_empty())
1549  "Functions with the interrupt attribute cannot have arguments!");
1550 
1551  StringRef Kind =
1552  MF.getFunction().getFnAttribute("interrupt").getValueAsString();
1553 
1554  if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
1556  "Function interrupt attribute argument not supported!");
1557  }
1558 
1559  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1560  MVT XLenVT = Subtarget.getXLenVT();
1561  unsigned XLenInBytes = Subtarget.getXLen() / 8;
1562  // Used with vargs to acumulate store chains.
1563  std::vector<SDValue> OutChains;
1564 
1565  // Assign locations to all of the incoming arguments.
1567  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1568  analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
1569 
1570  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1571  CCValAssign &VA = ArgLocs[i];
1572  SDValue ArgValue;
1573  // Passing f64 on RV32D with a soft float ABI must be handled as a special
1574  // case.
1575  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
1576  ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
1577  else if (VA.isRegLoc())
1578  ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);
1579  else
1580  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
1581 
1582  if (VA.getLocInfo() == CCValAssign::Indirect) {
1583  // If the original argument was split and passed by reference (e.g. i128
1584  // on RV32), we need to load all parts of it here (using the same
1585  // address).
1586  InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
1587  MachinePointerInfo()));
1588  unsigned ArgIndex = Ins[i].OrigArgIndex;
1589  assert(Ins[i].PartOffset == 0);
1590  while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) {
1591  CCValAssign &PartVA = ArgLocs[i + 1];
1592  unsigned PartOffset = Ins[i + 1].PartOffset;
1593  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1594  DAG.getIntPtrConstant(PartOffset, DL));
1595  InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address,
1596  MachinePointerInfo()));
1597  ++i;
1598  }
1599  continue;
1600  }
1601  InVals.push_back(ArgValue);
1602  }
1603 
1604  if (IsVarArg) {
1606  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
1607  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1608  MachineFrameInfo &MFI = MF.getFrameInfo();
1609  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1611 
1612  // Offset of the first variable argument from stack pointer, and size of
1613  // the vararg save area. For now, the varargs save area is either zero or
1614  // large enough to hold a0-a7.
1615  int VaArgOffset, VarArgsSaveSize;
1616 
1617  // If all registers are allocated, then all varargs must be passed on the
1618  // stack and we don't need to save any argregs.
1619  if (ArgRegs.size() == Idx) {
1620  VaArgOffset = CCInfo.getNextStackOffset();
1621  VarArgsSaveSize = 0;
1622  } else {
1623  VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
1624  VaArgOffset = -VarArgsSaveSize;
1625  }
1626 
1627  // Record the frame index of the first variable argument
1628  // which is a value necessary to VASTART.
1629  int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1630  RVFI->setVarArgsFrameIndex(FI);
1631 
1632  // If saving an odd number of registers then create an extra stack slot to
1633  // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
1634  // offsets to even-numbered registered remain 2*XLEN-aligned.
1635  if (Idx % 2) {
1636  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes,
1637  true);
1638  VarArgsSaveSize += XLenInBytes;
1639  }
1640 
1641  // Copy the integer registers that may have been used for passing varargs
1642  // to the vararg save area.
1643  for (unsigned I = Idx; I < ArgRegs.size();
1644  ++I, VaArgOffset += XLenInBytes) {
1645  const unsigned Reg = RegInfo.createVirtualRegister(RC);
1646  RegInfo.addLiveIn(ArgRegs[I], Reg);
1647  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
1648  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
1649  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1650  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
1652  cast<StoreSDNode>(Store.getNode())
1653  ->getMemOperand()
1654  ->setValue((Value *)nullptr);
1655  OutChains.push_back(Store);
1656  }
1657  RVFI->setVarArgsSaveSize(VarArgsSaveSize);
1658  }
1659 
1660  // All stores are grouped in one node to allow the matching between
1661  // the size of Ins and InVals. This only happens for vararg functions.
1662  if (!OutChains.empty()) {
1663  OutChains.push_back(Chain);
1664  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1665  }
1666 
1667  return Chain;
1668 }
1669 
1670 /// isEligibleForTailCallOptimization - Check whether the call is eligible
1671 /// for tail call optimization.
1672 /// Note: This is modelled after ARM's IsEligibleForTailCallOptimization.
1673 bool RISCVTargetLowering::isEligibleForTailCallOptimization(
1674  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
1675  const SmallVector<CCValAssign, 16> &ArgLocs) const {
1676 
1677  auto &Callee = CLI.Callee;
1678  auto CalleeCC = CLI.CallConv;
1679  auto IsVarArg = CLI.IsVarArg;
1680  auto &Outs = CLI.Outs;
1681  auto &Caller = MF.getFunction();
1682  auto CallerCC = Caller.getCallingConv();
1683 
1684  // Do not tail call opt functions with "disable-tail-calls" attribute.
1685  if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
1686  return false;
1687 
1688  // Exception-handling functions need a special set of instructions to
1689  // indicate a return to the hardware. Tail-calling another function would
1690  // probably break this.
1691  // TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
1692  // should be expanded as new function attributes are introduced.
1693  if (Caller.hasFnAttribute("interrupt"))
1694  return false;
1695 
1696  // Do not tail call opt functions with varargs.
1697  if (IsVarArg)
1698  return false;
1699 
1700  // Do not tail call opt if the stack is used to pass parameters.
1701  if (CCInfo.getNextStackOffset() != 0)
1702  return false;
1703 
1704  // Do not tail call opt if any parameters need to be passed indirectly.
1705  // Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
1706  // passed indirectly. So the address of the value will be passed in a
1707  // register, or if not available, then the address is put on the stack. In
1708  // order to pass indirectly, space on the stack often needs to be allocated
1709  // in order to store the value. In this case the CCInfo.getNextStackOffset()
1710  // != 0 check is not enough and we need to check if any CCValAssign ArgsLocs
1711  // are passed CCValAssign::Indirect.
1712  for (auto &VA : ArgLocs)
1713  if (VA.getLocInfo() == CCValAssign::Indirect)
1714  return false;
1715 
1716  // Do not tail call opt if either caller or callee uses struct return
1717  // semantics.
1718  auto IsCallerStructRet = Caller.hasStructRetAttr();
1719  auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
1720  if (IsCallerStructRet || IsCalleeStructRet)
1721  return false;
1722 
1723  // Externally-defined functions with weak linkage should not be
1724  // tail-called. The behaviour of branch instructions in this situation (as
1725  // used for tail calls) is implementation-defined, so we cannot rely on the
1726  // linker replacing the tail call with a return.
1727  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1728  const GlobalValue *GV = G->getGlobal();
1729  if (GV->hasExternalWeakLinkage())
1730  return false;
1731  }
1732 
1733  // The callee has to preserve all registers the caller needs to preserve.
1734  const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
1735  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1736  if (CalleeCC != CallerCC) {
1737  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1738  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1739  return false;
1740  }
1741 
1742  // Byval parameters hand the function a pointer directly into the stack area
1743  // we want to reuse during a tail call. Working around this *is* possible
1744  // but less efficient and uglier in LowerCall.
1745  for (auto &Arg : Outs)
1746  if (Arg.Flags.isByVal())
1747  return false;
1748 
1749  return true;
1750 }
1751 
1752 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
1753 // and output parameter nodes.
1754 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
1755  SmallVectorImpl<SDValue> &InVals) const {
1756  SelectionDAG &DAG = CLI.DAG;
1757  SDLoc &DL = CLI.DL;
1758  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1759  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1760  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1761  SDValue Chain = CLI.Chain;
1762  SDValue Callee = CLI.Callee;
1763  bool &IsTailCall = CLI.IsTailCall;
1764  CallingConv::ID CallConv = CLI.CallConv;
1765  bool IsVarArg = CLI.IsVarArg;
1766  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1767  MVT XLenVT = Subtarget.getXLenVT();
1768 
1769  MachineFunction &MF = DAG.getMachineFunction();
1770 
1771  // Analyze the operands of the call, assigning locations to each operand.
1773  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1774  analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
1775 
1776  // Check if it's really possible to do a tail call.
1777  if (IsTailCall)
1778  IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
1779 
1780  if (IsTailCall)
1781  ++NumTailCalls;
1782  else if (CLI.CS && CLI.CS.isMustTailCall())
1783  report_fatal_error("failed to perform tail call elimination on a call "
1784  "site marked musttail");
1785 
1786  // Get a count of how many bytes are to be pushed on the stack.
1787  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1788 
1789  // Create local copies for byval args
1790  SmallVector<SDValue, 8> ByValArgs;
1791  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1792  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1793  if (!Flags.isByVal())
1794  continue;
1795 
1796  SDValue Arg = OutVals[i];
1797  unsigned Size = Flags.getByValSize();
1798  unsigned Align = Flags.getByValAlign();
1799 
1800  int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false);
1801  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
1802  SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
1803 
1804  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
1805  /*IsVolatile=*/false,
1806  /*AlwaysInline=*/false,
1807  IsTailCall, MachinePointerInfo(),
1808  MachinePointerInfo());
1809  ByValArgs.push_back(FIPtr);
1810  }
1811 
1812  if (!IsTailCall)
1813  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
1814 
1815  // Copy argument values to their designated locations.
1817  SmallVector<SDValue, 8> MemOpChains;
1818  SDValue StackPtr;
1819  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
1820  CCValAssign &VA = ArgLocs[i];
1821  SDValue ArgValue = OutVals[i];
1822  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1823 
1824  // Handle passing f64 on RV32D with a soft float ABI as a special case.
1825  bool IsF64OnRV32DSoftABI =
1826  VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
1827  if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
1828  SDValue SplitF64 = DAG.getNode(
1829  RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
1830  SDValue Lo = SplitF64.getValue(0);
1831  SDValue Hi = SplitF64.getValue(1);
1832 
1833  unsigned RegLo = VA.getLocReg();
1834  RegsToPass.push_back(std::make_pair(RegLo, Lo));
1835 
1836  if (RegLo == RISCV::X17) {
1837  // Second half of f64 is passed on the stack.
1838  // Work out the address of the stack slot.
1839  if (!StackPtr.getNode())
1840  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1841  // Emit the store.
1842  MemOpChains.push_back(
1843  DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
1844  } else {
1845  // Second half of f64 is passed in another GPR.
1846  unsigned RegHigh = RegLo + 1;
1847  RegsToPass.push_back(std::make_pair(RegHigh, Hi));
1848  }
1849  continue;
1850  }
1851 
1852  // IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way
1853  // as any other MemLoc.
1854 
1855  // Promote the value if needed.
1856  // For now, only handle fully promoted and indirect arguments.
1857  if (VA.getLocInfo() == CCValAssign::Indirect) {
1858  // Store the argument in a stack slot and pass its address.
1859  SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT);
1860  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1861  MemOpChains.push_back(
1862  DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1864  // If the original argument was split (e.g. i128), we need
1865  // to store all parts of it here (and pass just one address).
1866  unsigned ArgIndex = Outs[i].OrigArgIndex;
1867  assert(Outs[i].PartOffset == 0);
1868  while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) {
1869  SDValue PartValue = OutVals[i + 1];
1870  unsigned PartOffset = Outs[i + 1].PartOffset;
1871  SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1872  DAG.getIntPtrConstant(PartOffset, DL));
1873  MemOpChains.push_back(
1874  DAG.getStore(Chain, DL, PartValue, Address,
1876  ++i;
1877  }
1878  ArgValue = SpillSlot;
1879  } else {
1880  ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
1881  }
1882 
1883  // Use local copy if it is a byval arg.
1884  if (Flags.isByVal())
1885  ArgValue = ByValArgs[j++];
1886 
1887  if (VA.isRegLoc()) {
1888  // Queue up the argument copies and emit them at the end.
1889  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1890  } else {
1891  assert(VA.isMemLoc() && "Argument not register or memory");
1892  assert(!IsTailCall && "Tail call not allowed if stack is used "
1893  "for passing parameters");
1894 
1895  // Work out the address of the stack slot.
1896  if (!StackPtr.getNode())
1897  StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT);
1898  SDValue Address =
1899  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1900  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
1901 
1902  // Emit the store.
1903  MemOpChains.push_back(
1904  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
1905  }
1906  }
1907 
1908  // Join the stores, which are independent of one another.
1909  if (!MemOpChains.empty())
1910  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1911 
1912  SDValue Glue;
1913 
1914  // Build a sequence of copy-to-reg nodes, chained and glued together.
1915  for (auto &Reg : RegsToPass) {
1916  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
1917  Glue = Chain.getValue(1);
1918  }
1919 
1920  // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
1921  // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
1922  // split it and then direct call can be matched by PseudoCALL.
1923  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
1924  Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0,
1926  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1927  Callee =
1928  DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, RISCVII::MO_CALL);
1929  }
1930 
1931  // The first call operand is the chain and the second is the target address.
1933  Ops.push_back(Chain);
1934  Ops.push_back(Callee);
1935 
1936  // Add argument registers to the end of the list so that they are
1937  // known live into the call.
1938  for (auto &Reg : RegsToPass)
1939  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1940 
1941  if (!IsTailCall) {
1942  // Add a register mask operand representing the call-preserved registers.
1943  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1944  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1945  assert(Mask && "Missing call preserved mask for calling convention");
1946  Ops.push_back(DAG.getRegisterMask(Mask));
1947  }
1948 
1949  // Glue the call to the argument copies, if any.
1950  if (Glue.getNode())
1951  Ops.push_back(Glue);
1952 
1953  // Emit the call.
1954  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1955 
1956  if (IsTailCall) {
1958  return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
1959  }
1960 
1961  Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
1962  Glue = Chain.getValue(1);
1963 
1964  // Mark the end of the call, which is glued to the call itself.
1965  Chain = DAG.getCALLSEQ_END(Chain,
1966  DAG.getConstant(NumBytes, DL, PtrVT, true),
1967  DAG.getConstant(0, DL, PtrVT, true),
1968  Glue, DL);
1969  Glue = Chain.getValue(1);
1970 
1971  // Assign locations to each value returned by this call.
1973  CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
1974  analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true);
1975 
1976  // Copy all of the result registers out of their specified physreg.
1977  for (auto &VA : RVLocs) {
1978  // Copy the value out
1979  SDValue RetValue =
1980  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
1981  // Glue the RetValue to the end of the call sequence
1982  Chain = RetValue.getValue(1);
1983  Glue = RetValue.getValue(2);
1984 
1985  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
1986  assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment");
1987  SDValue RetValue2 =
1988  DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue);
1989  Chain = RetValue2.getValue(1);
1990  Glue = RetValue2.getValue(2);
1991  RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue,
1992  RetValue2);
1993  }
1994 
1995  RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
1996 
1997  InVals.push_back(RetValue);
1998  }
1999 
2000  return Chain;
2001 }
2002 
2003 bool RISCVTargetLowering::CanLowerReturn(
2004  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
2005  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2007  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2008  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2009  MVT VT = Outs[i].VT;
2010  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2011  RISCVABI::ABI ABI = MF.getSubtarget<RISCVSubtarget>().getTargetABI();
2012  if (CC_RISCV(MF.getDataLayout(), ABI, i, VT, VT, CCValAssign::Full,
2013  ArgFlags, CCInfo, /*IsFixed=*/true, /*IsRet=*/true, nullptr))
2014  return false;
2015  }
2016  return true;
2017 }
2018 
2019 SDValue
2020 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2021  bool IsVarArg,
2022  const SmallVectorImpl<ISD::OutputArg> &Outs,
2023  const SmallVectorImpl<SDValue> &OutVals,
2024  const SDLoc &DL, SelectionDAG &DAG) const {
2025  // Stores the assignment of the return value to a location.
2027 
2028  // Info about the registers and stack slot.
2029  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2030  *DAG.getContext());
2031 
2032  analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
2033  nullptr);
2034 
2035  SDValue Glue;
2036  SmallVector<SDValue, 4> RetOps(1, Chain);
2037 
2038  // Copy the result values into the output registers.
2039  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
2040  SDValue Val = OutVals[i];
2041  CCValAssign &VA = RVLocs[i];
2042  assert(VA.isRegLoc() && "Can only return in registers!");
2043 
2044  if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
2045  // Handle returning f64 on RV32D with a soft float ABI.
2046  assert(VA.isRegLoc() && "Expected return via registers");
2048  DAG.getVTList(MVT::i32, MVT::i32), Val);
2049  SDValue Lo = SplitF64.getValue(0);
2050  SDValue Hi = SplitF64.getValue(1);
2051  unsigned RegLo = VA.getLocReg();
2052  unsigned RegHi = RegLo + 1;
2053  Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
2054  Glue = Chain.getValue(1);
2055  RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
2056  Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
2057  Glue = Chain.getValue(1);
2058  RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
2059  } else {
2060  // Handle a 'normal' return.
2061  Val = convertValVTToLocVT(DAG, Val, VA, DL);
2062  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
2063 
2064  // Guarantee that all emitted copies are stuck together.
2065  Glue = Chain.getValue(1);
2066  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2067  }
2068  }
2069 
2070  RetOps[0] = Chain; // Update chain.
2071 
2072  // Add the glue node if we have it.
2073  if (Glue.getNode()) {
2074  RetOps.push_back(Glue);
2075  }
2076 
2077  // Interrupt service routines use different return instructions.
2078  const Function &Func = DAG.getMachineFunction().getFunction();
2079  if (Func.hasFnAttribute("interrupt")) {
2080  if (!Func.getReturnType()->isVoidTy())
2082  "Functions with the interrupt attribute must have void return type!");
2083 
2084  MachineFunction &MF = DAG.getMachineFunction();
2085  StringRef Kind =
2086  MF.getFunction().getFnAttribute("interrupt").getValueAsString();
2087 
2088  unsigned RetOpc;
2089  if (Kind == "user")
2090  RetOpc = RISCVISD::URET_FLAG;
2091  else if (Kind == "supervisor")
2092  RetOpc = RISCVISD::SRET_FLAG;
2093  else
2094  RetOpc = RISCVISD::MRET_FLAG;
2095 
2096  return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
2097  }
2098 
2099  return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
2100 }
2101 
2102 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
2103  switch ((RISCVISD::NodeType)Opcode) {
2105  break;
2106  case RISCVISD::RET_FLAG:
2107  return "RISCVISD::RET_FLAG";
2108  case RISCVISD::URET_FLAG:
2109  return "RISCVISD::URET_FLAG";
2110  case RISCVISD::SRET_FLAG:
2111  return "RISCVISD::SRET_FLAG";
2112  case RISCVISD::MRET_FLAG:
2113  return "RISCVISD::MRET_FLAG";
2114  case RISCVISD::CALL:
2115  return "RISCVISD::CALL";
2116  case RISCVISD::SELECT_CC:
2117  return "RISCVISD::SELECT_CC";
2119  return "RISCVISD::BuildPairF64";
2120  case RISCVISD::SplitF64:
2121  return "RISCVISD::SplitF64";
2122  case RISCVISD::TAIL:
2123  return "RISCVISD::TAIL";
2124  case RISCVISD::SLLW:
2125  return "RISCVISD::SLLW";
2126  case RISCVISD::SRAW:
2127  return "RISCVISD::SRAW";
2128  case RISCVISD::SRLW:
2129  return "RISCVISD::SRLW";
2130  case RISCVISD::DIVW:
2131  return "RISCVISD::DIVW";
2132  case RISCVISD::DIVUW:
2133  return "RISCVISD::DIVUW";
2134  case RISCVISD::REMUW:
2135  return "RISCVISD::REMUW";
2137  return "RISCVISD::FMV_W_X_RV64";
2139  return "RISCVISD::FMV_X_ANYEXTW_RV64";
2140  }
2141  return nullptr;
2142 }
2143 
2144 std::pair<unsigned, const TargetRegisterClass *>
2146  StringRef Constraint,
2147  MVT VT) const {
2148  // First, see if this is a constraint that directly corresponds to a
2149  // RISCV register class.
2150  if (Constraint.size() == 1) {
2151  switch (Constraint[0]) {
2152  case 'r':
2153  return std::make_pair(0U, &RISCV::GPRRegClass);
2154  default:
2155  break;
2156  }
2157  }
2158 
2159  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2160 }
2161 
2163  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2164  SelectionDAG &DAG) const {
2165  // Currently only support length 1 constraints.
2166  if (Constraint.length() == 1) {
2167  switch (Constraint[0]) {
2168  case 'I':
2169  // Validate & create a 12-bit signed immediate operand.
2170  if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2171  uint64_t CVal = C->getSExtValue();
2172  if (isInt<12>(CVal))
2173  Ops.push_back(
2174  DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
2175  }
2176  return;
2177  case 'J':
2178  // Validate & create an integer zero operand.
2179  if (auto *C = dyn_cast<ConstantSDNode>(Op))
2180  if (C->getZExtValue() == 0)
2181  Ops.push_back(
2182  DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getXLenVT()));
2183  return;
2184  case 'K':
2185  // Validate & create a 5-bit unsigned immediate operand.
2186  if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
2187  uint64_t CVal = C->getZExtValue();
2188  if (isUInt<5>(CVal))
2189  Ops.push_back(
2190  DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
2191  }
2192  return;
2193  default:
2194  break;
2195  }
2196  }
2197  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2198 }
2199 
2201  Instruction *Inst,
2202  AtomicOrdering Ord) const {
2203  if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
2204  return Builder.CreateFence(Ord);
2205  if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
2206  return Builder.CreateFence(AtomicOrdering::Release);
2207  return nullptr;
2208 }
2209 
2211  Instruction *Inst,
2212  AtomicOrdering Ord) const {
2213  if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
2214  return Builder.CreateFence(AtomicOrdering::Acquire);
2215  return nullptr;
2216 }
2217 
2219 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
2220  // atomicrmw {fadd,fsub} must be expanded to use compare-exchange, as floating
2221  // point operations can't be used in an lr/sc sequence without breaking the
2222  // forward-progress guarantee.
2223  if (AI->isFloatingPointOperation())
2225 
2226  unsigned Size = AI->getType()->getPrimitiveSizeInBits();
2227  if (Size == 8 || Size == 16)
2230 }
2231 
2232 static Intrinsic::ID
2234  if (XLen == 32) {
2235  switch (BinOp) {
2236  default:
2237  llvm_unreachable("Unexpected AtomicRMW BinOp");
2238  case AtomicRMWInst::Xchg:
2239  return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
2240  case AtomicRMWInst::Add:
2241  return Intrinsic::riscv_masked_atomicrmw_add_i32;
2242  case AtomicRMWInst::Sub:
2243  return Intrinsic::riscv_masked_atomicrmw_sub_i32;
2244  case AtomicRMWInst::Nand:
2245  return Intrinsic::riscv_masked_atomicrmw_nand_i32;
2246  case AtomicRMWInst::Max:
2247  return Intrinsic::riscv_masked_atomicrmw_max_i32;
2248  case AtomicRMWInst::Min:
2249  return Intrinsic::riscv_masked_atomicrmw_min_i32;
2250  case AtomicRMWInst::UMax:
2251  return Intrinsic::riscv_masked_atomicrmw_umax_i32;
2252  case AtomicRMWInst::UMin:
2253  return Intrinsic::riscv_masked_atomicrmw_umin_i32;
2254  }
2255  }
2256 
2257  if (XLen == 64) {
2258  switch (BinOp) {
2259  default:
2260  llvm_unreachable("Unexpected AtomicRMW BinOp");
2261  case AtomicRMWInst::Xchg:
2262  return Intrinsic::riscv_masked_atomicrmw_xchg_i64;
2263  case AtomicRMWInst::Add:
2264  return Intrinsic::riscv_masked_atomicrmw_add_i64;
2265  case AtomicRMWInst::Sub:
2266  return Intrinsic::riscv_masked_atomicrmw_sub_i64;
2267  case AtomicRMWInst::Nand:
2268  return Intrinsic::riscv_masked_atomicrmw_nand_i64;
2269  case AtomicRMWInst::Max:
2270  return Intrinsic::riscv_masked_atomicrmw_max_i64;
2271  case AtomicRMWInst::Min:
2272  return Intrinsic::riscv_masked_atomicrmw_min_i64;
2273  case AtomicRMWInst::UMax:
2274  return Intrinsic::riscv_masked_atomicrmw_umax_i64;
2275  case AtomicRMWInst::UMin:
2276  return Intrinsic::riscv_masked_atomicrmw_umin_i64;
2277  }
2278  }
2279 
2280  llvm_unreachable("Unexpected XLen\n");
2281 }
2282 
2283 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
2284  IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
2285  Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
2286  unsigned XLen = Subtarget.getXLen();
2287  Value *Ordering =
2288  Builder.getIntN(XLen, static_cast<uint64_t>(AI->getOrdering()));
2289  Type *Tys[] = {AlignedAddr->getType()};
2290  Function *LrwOpScwLoop = Intrinsic::getDeclaration(
2291  AI->getModule(),
2293 
2294  if (XLen == 64) {
2295  Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty());
2296  Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
2297  ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty());
2298  }
2299 
2300  Value *Result;
2301 
2302  // Must pass the shift amount needed to sign extend the loaded value prior
2303  // to performing a signed comparison for min/max. ShiftAmt is the number of
2304  // bits to shift the value into position. Pass XLen-ShiftAmt-ValWidth, which
2305  // is the number of bits to left+right shift the value in order to
2306  // sign-extend.
2307  if (AI->getOperation() == AtomicRMWInst::Min ||
2308  AI->getOperation() == AtomicRMWInst::Max) {
2309  const DataLayout &DL = AI->getModule()->getDataLayout();
2310  unsigned ValWidth =
2312  Value *SextShamt =
2313  Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt);
2314  Result = Builder.CreateCall(LrwOpScwLoop,
2315  {AlignedAddr, Incr, Mask, SextShamt, Ordering});
2316  } else {
2317  Result =
2318  Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
2319  }
2320 
2321  if (XLen == 64)
2322  Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
2323  return Result;
2324 }
2325 
2327 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
2328  AtomicCmpXchgInst *CI) const {
2329  unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
2330  if (Size == 8 || Size == 16)
2333 }
2334 
2335 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
2336  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
2337  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
2338  unsigned XLen = Subtarget.getXLen();
2339  Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
2340  Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32;
2341  if (XLen == 64) {
2342  CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty());
2343  NewVal = Builder.CreateSExt(NewVal, Builder.getInt64Ty());
2344  Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
2345  CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64;
2346  }
2347  Type *Tys[] = {AlignedAddr->getType()};
2348  Function *MaskedCmpXchg =
2349  Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys);
2350  Value *Result = Builder.CreateCall(
2351  MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
2352  if (XLen == 64)
2353  Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
2354  return Result;
2355 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
static MVT getIntegerVT(unsigned BitWidth)
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
uint64_t getTypeStoreSizeInBits(Type *Ty) const
Returns the maximum number of bits that may be overwritten by storing the specified type; always a mu...
Definition: DataLayout.h:452
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
RISCVABI::ABI getTargetABI() const
void collectDebugValues(SmallVectorImpl< MachineInstr *> &DbgValues)
Scan instructions following MI and collect any matching DBG_VALUEs.
const GlobalValue * getGlobal() const
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:833
*p = old <signed v ? old : v
Definition: Instructions.h:721
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:953
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it&#39;s not CSE&#39;d)...
Definition: SelectionDAG.h:852
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Type * getParamType(unsigned i) const
Parameter type accessors.
Definition: DerivedTypes.h:134
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
unsigned getReg() const
getReg - Returns the register number.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:647
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const RISCVRegisterInfo * getRegisterInfo() const override
*p = old <unsigned v ? old : v
Definition: Instructions.h:725
Function Alias Analysis Results
*p = old >unsigned v ? old : v
Definition: Instructions.h:723
unsigned getValNo() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC)
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Value * CreateSExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1740
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
static const MCPhysReg ArgFPR32s[]
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
*p = old >signed v ? old : v
Definition: Instructions.h:719
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isMemLoc() const
IntegerType * getInt32Ty()
Fetch the type representing a 32-bit integer.
Definition: IRBuilder.h:346
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1241
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:480
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
bool hasOneUse() const
Return true if there is exactly one use of this node.
A description of a memory reference used in the backend.
static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
const HexagonInstrInfo * TII
IntegerType * getInt64Ty()
Fetch the type representing a 64-bit integer.
Definition: IRBuilder.h:351
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getXLen() const
Shift and rotation operations.
Definition: ISDOpcodes.h:434
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
BinOp getOperation() const
Definition: Instructions.h:750
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
static MachineBasicBlock * emitSplitF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:463
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
const BlockAddress * getBlockAddress() const
LocInfo getLocInfo() const
static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Class to represent function types.
Definition: DerivedTypes.h:102
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
bool isRV32E() const
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue getRegisterMask(const uint32_t *RegMask)
BinOp
This enumeration lists the possible modifications atomicrmw can make.
Definition: Instructions.h:703
bool arg_empty() const
Definition: Function.h:715
SmallVectorImpl< CCValAssign > & getPendingLocs()
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool hasStdExtA() const
static MachineBasicBlock * emitBuildPairF64Pseudo(MachineInstr &MI, MachineBasicBlock *BB)
SmallVectorImpl< ISD::ArgFlagsTy > & getPendingArgFlags()
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
static const MCPhysReg ArgFPR64s[]
Value * CreateSub(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:1066
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
virtual const TargetInstrInfo * getInstrInfo() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:582
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Function * getDeclaration(Module *M, ID id, ArrayRef< Type *> Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1044
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
ConstantInt * getIntN(unsigned N, uint64_t C)
Get a constant N-bit value, zero extended or truncated from a 64-bit value.
Definition: IRBuilder.h:317
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Class to represent pointers.
Definition: DerivedTypes.h:498
unsigned getByValSize() const
unsigned getKillRegState(bool B)
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
TargetInstrInfo - Interface to description of machine instruction set.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
MachineInstrBundleIterator< MachineInstr > iterator
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
unsigned getOrigAlign() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasStdExtF() const
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:759
bool isFloatingPointOperation() const
Definition: Instructions.h:823
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
const SDValue & getOperand(unsigned Num) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:970
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:840
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1199
bool hasStdExtM() const
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
Definition: DataLayout.cpp:791
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:81
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:288
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it&#39;s implicit...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Extended Value Type.
Definition: ValueTypes.h:33
static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
size_t size() const
Definition: SmallVector.h:52
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
Definition: Instructions.h:789
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1732
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
The memory access writes data.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReleaseOrStronger(AtomicOrdering ao)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:645
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:554
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
Value * getValOperand()
Definition: Instructions.h:815
static const MCPhysReg ArgGPRs[]
bool hasStdExtD() const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG)
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:95
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:437
Type * getReturnType() const
Definition: DerivedTypes.h:123
static bool isSelectPseudo(MachineInstr &MI)
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Constant * getConstVal() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:685
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.h:163
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
Class for arbitrary precision integers.
Definition: APInt.h:69
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
void setMinFunctionAlignment(unsigned Align)
Set the target&#39;s minimum function alignment (in log2(bytes))
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
bool is64Bit() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:469
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:666
Representation of each machine instruction.
Definition: MachineInstr.h:63
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:755
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:679
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1514
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:711
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:510
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
PointerUnion< const Value *, const PseudoSourceValue * > ptrVal
static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
void push_back(MachineInstr *MI)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2051
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:636
SDValue getValue(unsigned R) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isRegLoc() const
bool hasStdExtC() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:114
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
SDValue getRegister(unsigned Reg, EVT VT)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getLocReg() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
#define LLVM_DEBUG(X)
Definition: Debug.h:122
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:610
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Function Alias Analysis false
static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
LLVMContext * getContext() const
Definition: SelectionDAG.h:410
Type * getElementType() const
Definition: DerivedTypes.h:517
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:628
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:404
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:651