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43 #define DEBUG_TYPE "aarch64-cond-br-tuning"
44 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
76 void AArch64CondBrTuning::getAnalysisUsage(
AnalysisUsage &AU)
const {
98 unsigned NewOpc =
TII->convertToFlagSettingOpc(
MI.getOpcode());
99 Register NewDestReg =
MI.getOperand(0).getReg();
101 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
104 TII->get(NewOpc), NewDestReg);
114 switch (
MI.getOpcode()) {
135 return BuildMI(*
MI.getParent(),
MI,
MI.getDebugLoc(),
TII->get(AArch64::Bcc))
143 if (
MI.getParent() !=
DefMI.getParent())
146 bool IsFlagSetting =
true;
147 unsigned MIOpc =
MI.getOpcode();
149 switch (
DefMI.getOpcode()) {
152 case AArch64::ADDWri:
153 case AArch64::ADDWrr:
154 case AArch64::ADDWrs:
155 case AArch64::ADDWrx:
156 case AArch64::ANDWri:
157 case AArch64::ANDWrr:
158 case AArch64::ANDWrs:
159 case AArch64::BICWrr:
160 case AArch64::BICWrs:
161 case AArch64::SUBWri:
162 case AArch64::SUBWrr:
163 case AArch64::SUBWrs:
164 case AArch64::SUBWrx:
165 IsFlagSetting =
false;
167 case AArch64::ADDSWri:
168 case AArch64::ADDSWrr:
169 case AArch64::ADDSWrs:
170 case AArch64::ADDSWrx:
171 case AArch64::ANDSWri:
172 case AArch64::ANDSWrr:
173 case AArch64::ANDSWrs:
174 case AArch64::BICSWrr:
175 case AArch64::BICSWrs:
176 case AArch64::SUBSWri:
177 case AArch64::SUBSWrr:
178 case AArch64::SUBSWrs:
179 case AArch64::SUBSWrx:
189 if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&
190 MI.getOperand(1).getImm() != 31)
202 NewCmp = convertToFlagSetting(
DefMI, IsFlagSetting,
false);
203 NewBr = convertToCondBr(
MI);
208 case AArch64::ADDXri:
209 case AArch64::ADDXrr:
210 case AArch64::ADDXrs:
211 case AArch64::ADDXrx:
212 case AArch64::ANDXri:
213 case AArch64::ANDXrr:
214 case AArch64::ANDXrs:
215 case AArch64::BICXrr:
216 case AArch64::BICXrs:
217 case AArch64::SUBXri:
218 case AArch64::SUBXrr:
219 case AArch64::SUBXrs:
220 case AArch64::SUBXrx:
221 IsFlagSetting =
false;
223 case AArch64::ADDSXri:
224 case AArch64::ADDSXrr:
225 case AArch64::ADDSXrs:
226 case AArch64::ADDSXrx:
227 case AArch64::ANDSXri:
228 case AArch64::ANDSXrr:
229 case AArch64::ANDSXrs:
230 case AArch64::BICSXrr:
231 case AArch64::BICSXrs:
232 case AArch64::SUBSXri:
233 case AArch64::SUBSXrr:
234 case AArch64::SUBSXrs:
235 case AArch64::SUBSXrx:
243 case AArch64::TBNZX: {
245 if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&
246 MI.getOperand(1).getImm() != 63)
257 NewCmp = convertToFlagSetting(
DefMI, IsFlagSetting,
true);
258 NewBr = convertToCondBr(
MI);
264 (void)NewCmp; (void)NewBr;
265 assert(NewCmp && NewBr &&
"Expected new instructions.");
276 DefMI.eraseFromParent();
277 MI.eraseFromParent();
286 dbgs() <<
"********** AArch64 Conditional Branch Tuning **********\n"
287 <<
"********** Function: " << MF.
getName() <<
'\n');
293 bool Changed =
false;
295 bool LocalChange =
false;
297 switch (
MI.getOpcode()) {
324 return new AArch64CondBrTuning();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
virtual const TargetInstrInfo * getInstrInfo() const
FunctionPass * createAArch64CondBrTuning()
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
iterator_range< iterator > terminators()
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void setIsDead(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI, const MachineInstr &UseMI, const TargetRegisterInfo *TRI)
Return true if there is an instruction /after/ DefMI and before UseMI which either reads or clobbers ...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void initializeAArch64CondBrTuningPass(PassRegistry &)
Register getReg() const
getReg - Returns the register number.
StringRef - Represent a constant reference to a string, i.e.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
Function & getFunction()
Return the LLVM function that this machine code represents.
#define AARCH64_CONDBR_TUNING_NAME
INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning", AARCH64_CONDBR_TUNING_NAME, false, false) void AArch64CondBrTuning
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBuilder MachineInstrBuilder & DefMI
FunctionPass class - This class is used to implement most global optimizations.