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HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonFrameLowering.h"
11 #include "HexagonBlockRanges.h"
12 #include "HexagonInstrInfo.h"
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/MC/MCDwarf.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Pass.h"
47 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/Debug.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstdint>
59 #include <iterator>
60 #include <limits>
61 #include <map>
62 #include <optional>
63 #include <utility>
64 #include <vector>
65 
66 #define DEBUG_TYPE "hexagon-pei"
67 
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134 
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141 
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149 
150 using namespace llvm;
151 
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154 
155 static cl::opt<unsigned>
156  NumberScavengerSlots("number-scavenger-slots", cl::Hidden,
157  cl::desc("Set the number of scavenger slots"),
158  cl::init(2));
159 
160 static cl::opt<int>
161  SpillFuncThreshold("spill-func-threshold", cl::Hidden,
162  cl::desc("Specify O2(not Os) spill func threshold"),
163  cl::init(6));
164 
165 static cl::opt<int>
166  SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden,
167  cl::desc("Specify Os spill func threshold"),
168  cl::init(1));
169 
171  "enable-stackovf-sanitizer", cl::Hidden,
172  cl::desc("Enable runtime checks for stack overflow."), cl::init(false));
173 
174 static cl::opt<bool>
175  EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden,
176  cl::desc("Enable stack frame shrink wrapping"));
177 
178 static cl::opt<unsigned>
179  ShrinkLimit("shrink-frame-limit",
181  cl::desc("Max count of stack frame shrink-wraps"));
182 
183 static cl::opt<bool>
184  EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden,
185  cl::desc("Enable long calls for save-restore stubs."),
186  cl::init(false));
187 
188 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
189  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
190 
191 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
192  cl::init(true), cl::desc("Optimize spill slots"));
193 
194 #ifndef NDEBUG
195 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
197 static unsigned SpillOptCount = 0;
198 #endif
199 
200 namespace llvm {
201 
204 
205 } // end namespace llvm
206 
207 namespace {
208 
209  class HexagonCallFrameInformation : public MachineFunctionPass {
210  public:
211  static char ID;
212 
213  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
216  }
217 
218  bool runOnMachineFunction(MachineFunction &MF) override;
219 
220  MachineFunctionProperties getRequiredProperties() const override {
223  }
224  };
225 
227 
228 } // end anonymous namespace
229 
230 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
231  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
232  bool NeedCFI = MF.needsFrameMoves();
233 
234  if (!NeedCFI)
235  return false;
236  HFI.insertCFIInstructions(MF);
237  return true;
238 }
239 
240 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
241  "Hexagon call frame information", false, false)
242 
244  return new HexagonCallFrameInformation();
245 }
246 
247 /// Map a register pair Reg to the subregister that has the greater "number",
248 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
250  const TargetRegisterInfo &TRI,
251  bool hireg = true) {
252  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
253  return Reg;
254 
255  Register RegNo = 0;
256  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
257  if (hireg) {
258  if (*SubRegs > RegNo)
259  RegNo = *SubRegs;
260  } else {
261  if (!RegNo || *SubRegs < RegNo)
262  RegNo = *SubRegs;
263  }
264  }
265  return RegNo;
266 }
267 
268 /// Returns the callee saved register with the largest id in the vector.
270  const TargetRegisterInfo &TRI) {
271  static_assert(Hexagon::R1 > 0,
272  "Assume physical registers are encoded as positive integers");
273  if (CSI.empty())
274  return 0;
275 
276  Register Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
277  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
279  if (Reg > Max)
280  Max = Reg;
281  }
282  return Max;
283 }
284 
285 /// Checks if the basic block contains any instruction that needs a stack
286 /// frame to be already in place.
287 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
288  const HexagonRegisterInfo &HRI) {
289  for (const MachineInstr &MI : MBB) {
290  if (MI.isCall())
291  return true;
292  unsigned Opc = MI.getOpcode();
293  switch (Opc) {
294  case Hexagon::PS_alloca:
295  case Hexagon::PS_aligna:
296  return true;
297  default:
298  break;
299  }
300  // Check individual operands.
301  for (const MachineOperand &MO : MI.operands()) {
302  // While the presence of a frame index does not prove that a stack
303  // frame will be required, all frame indexes should be within alloc-
304  // frame/deallocframe. Otherwise, the code that translates a frame
305  // index into an offset would have to be aware of the placement of
306  // the frame creation/destruction instructions.
307  if (MO.isFI())
308  return true;
309  if (MO.isReg()) {
310  Register R = MO.getReg();
311  // Virtual registers will need scavenging, which then may require
312  // a stack slot.
313  if (R.isVirtual())
314  return true;
315  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
316  if (CSR[*S])
317  return true;
318  continue;
319  }
320  if (MO.isRegMask()) {
321  // A regmask would normally have all callee-saved registers marked
322  // as preserved, so this check would not be needed, but in case of
323  // ever having other regmasks (for other calling conventions),
324  // make sure they would be processed correctly.
325  const uint32_t *BM = MO.getRegMask();
326  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
327  unsigned R = x;
328  // If this regmask does not preserve a CSR, a frame will be needed.
329  if (!(BM[R/32] & (1u << (R%32))))
330  return true;
331  }
332  }
333  }
334  }
335  return false;
336 }
337 
338  /// Returns true if MBB has a machine instructions that indicates a tail call
339  /// in the block.
340 static bool hasTailCall(const MachineBasicBlock &MBB) {
342  if (I == MBB.end())
343  return false;
344  unsigned RetOpc = I->getOpcode();
345  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
346 }
347 
348 /// Returns true if MBB contains an instruction that returns.
349 static bool hasReturn(const MachineBasicBlock &MBB) {
350  for (const MachineInstr &MI : MBB.terminators())
351  if (MI.isReturn())
352  return true;
353  return false;
354 }
355 
356 /// Returns the "return" instruction from this block, or nullptr if there
357 /// isn't any.
359  for (auto &I : MBB)
360  if (I.isReturn())
361  return &I;
362  return nullptr;
363 }
364 
365 static bool isRestoreCall(unsigned Opc) {
366  switch (Opc) {
367  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
368  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
369  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
370  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
371  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
372  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
373  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
374  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
375  return true;
376  }
377  return false;
378 }
379 
380 static inline bool isOptNone(const MachineFunction &MF) {
381  return MF.getFunction().hasOptNone() ||
383 }
384 
385 static inline bool isOptSize(const MachineFunction &MF) {
386  const Function &F = MF.getFunction();
387  return F.hasOptSize() && !F.hasMinSize();
388 }
389 
390 static inline bool isMinSize(const MachineFunction &MF) {
391  return MF.getFunction().hasMinSize();
392 }
393 
394 /// Implements shrink-wrapping of the stack frame. By default, stack frame
395 /// is created in the function entry block, and is cleaned up in every block
396 /// that returns. This function finds alternate blocks: one for the frame
397 /// setup (prolog) and one for the cleanup (epilog).
398 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
399  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
400  static unsigned ShrinkCounter = 0;
401 
403  MF.getFunction().isVarArg())
404  return;
405  if (ShrinkLimit.getPosition()) {
406  if (ShrinkCounter >= ShrinkLimit)
407  return;
408  ShrinkCounter++;
409  }
410 
411  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
412 
414  MDT.runOnMachineFunction(MF);
416  MPT.runOnMachineFunction(MF);
417 
418  using UnsignedMap = DenseMap<unsigned, unsigned>;
420 
421  UnsignedMap RPO;
422  RPOTType RPOT(&MF);
423  unsigned RPON = 0;
424  for (auto &I : RPOT)
425  RPO[I->getNumber()] = RPON++;
426 
427  // Don't process functions that have loops, at least for now. Placement
428  // of prolog and epilog must take loop structure into account. For simpli-
429  // city don't do it right now.
430  for (auto &I : MF) {
431  unsigned BN = RPO[I.getNumber()];
432  for (MachineBasicBlock *Succ : I.successors())
433  // If found a back-edge, return.
434  if (RPO[Succ->getNumber()] <= BN)
435  return;
436  }
437 
438  // Collect the set of blocks that need a stack frame to execute. Scan
439  // each block for uses/defs of callee-saved registers, calls, etc.
441  BitVector CSR(Hexagon::NUM_TARGET_REGS);
442  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
443  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
444  CSR[*S] = true;
445 
446  for (auto &I : MF)
447  if (needsStackFrame(I, CSR, HRI))
448  SFBlocks.push_back(&I);
449 
450  LLVM_DEBUG({
451  dbgs() << "Blocks needing SF: {";
452  for (auto &B : SFBlocks)
453  dbgs() << " " << printMBBReference(*B);
454  dbgs() << " }\n";
455  });
456  // No frame needed?
457  if (SFBlocks.empty())
458  return;
459 
460  // Pick a common dominator and a common post-dominator.
461  MachineBasicBlock *DomB = SFBlocks[0];
462  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
463  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
464  if (!DomB)
465  break;
466  }
467  MachineBasicBlock *PDomB = SFBlocks[0];
468  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
469  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
470  if (!PDomB)
471  break;
472  }
473  LLVM_DEBUG({
474  dbgs() << "Computed dom block: ";
475  if (DomB)
476  dbgs() << printMBBReference(*DomB);
477  else
478  dbgs() << "<null>";
479  dbgs() << ", computed pdom block: ";
480  if (PDomB)
481  dbgs() << printMBBReference(*PDomB);
482  else
483  dbgs() << "<null>";
484  dbgs() << "\n";
485  });
486  if (!DomB || !PDomB)
487  return;
488 
489  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
490  if (!MDT.dominates(DomB, PDomB)) {
491  LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
492  return;
493  }
494  if (!MPT.dominates(PDomB, DomB)) {
495  LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
496  return;
497  }
498 
499  // Finally, everything seems right.
500  PrologB = DomB;
501  EpilogB = PDomB;
502 }
503 
504 /// Perform most of the PEI work here:
505 /// - saving/restoring of the callee-saved registers,
506 /// - stack frame creation and destruction.
507 /// Normally, this work is distributed among various functions, but doing it
508 /// in one place allows shrink-wrapping of the stack frame.
510  MachineBasicBlock &MBB) const {
511  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
512 
513  MachineFrameInfo &MFI = MF.getFrameInfo();
514  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
515 
516  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
518  findShrunkPrologEpilog(MF, PrologB, EpilogB);
519 
520  bool PrologueStubs = false;
521  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
522  insertPrologueInBlock(*PrologB, PrologueStubs);
523  updateEntryPaths(MF, *PrologB);
524 
525  if (EpilogB) {
526  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
527  insertEpilogueInBlock(*EpilogB);
528  } else {
529  for (auto &B : MF)
530  if (B.isReturnBlock())
531  insertCSRRestoresInBlock(B, CSI, HRI);
532 
533  for (auto &B : MF)
534  if (B.isReturnBlock())
535  insertEpilogueInBlock(B);
536 
537  for (auto &B : MF) {
538  if (B.empty())
539  continue;
540  MachineInstr *RetI = getReturn(B);
541  if (!RetI || isRestoreCall(RetI->getOpcode()))
542  continue;
543  for (auto &R : CSI)
544  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
545  }
546  }
547 
548  if (EpilogB) {
549  // If there is an epilog block, it may not have a return instruction.
550  // In such case, we need to add the callee-saved registers as live-ins
551  // in all blocks on all paths from the epilog to any return block.
552  unsigned MaxBN = MF.getNumBlockIDs();
553  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
554  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
555  }
556 }
557 
558 /// Returns true if the target can safely skip saving callee-saved registers
559 /// for noreturn nounwind functions.
561  const MachineFunction &MF) const {
562  const auto &F = MF.getFunction();
563  assert(F.hasFnAttribute(Attribute::NoReturn) &&
564  F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
565  !F.getFunction().hasFnAttribute(Attribute::UWTable));
566  (void)F;
567 
568  // No need to save callee saved registers if the function does not return.
569  return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
570 }
571 
572 // Helper function used to determine when to eliminate the stack frame for
573 // functions marked as noreturn and when the noreturn-stack-elim options are
574 // specified. When both these conditions are true, then a FP may not be needed
575 // if the function makes a call. It is very similar to enableCalleeSaveSkip,
576 // but it used to check if the allocframe can be eliminated as well.
577 static bool enableAllocFrameElim(const MachineFunction &MF) {
578  const auto &F = MF.getFunction();
579  const auto &MFI = MF.getFrameInfo();
580  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
581  assert(!MFI.hasVarSizedObjects() &&
582  !HST.getRegisterInfo()->hasStackRealignment(MF));
583  return F.hasFnAttribute(Attribute::NoReturn) &&
584  F.hasFnAttribute(Attribute::NoUnwind) &&
585  !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&
586  MFI.getStackSize() == 0;
587 }
588 
589 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
590  bool PrologueStubs) const {
591  MachineFunction &MF = *MBB.getParent();
592  MachineFrameInfo &MFI = MF.getFrameInfo();
593  auto &HST = MF.getSubtarget<HexagonSubtarget>();
594  auto &HII = *HST.getInstrInfo();
595  auto &HRI = *HST.getRegisterInfo();
596 
597  Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
598 
599  // Calculate the total stack frame size.
600  // Get the number of bytes to allocate from the FrameInfo.
601  unsigned FrameSize = MFI.getStackSize();
602  // Round up the max call frame size to the max alignment on the stack.
603  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
604  MFI.setMaxCallFrameSize(MaxCFA);
605 
606  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
607  MFI.setStackSize(FrameSize);
608 
609  bool AlignStack = (MaxAlign > getStackAlign());
610 
611  // Get the number of bytes to allocate from the FrameInfo.
612  unsigned NumBytes = MFI.getStackSize();
613  Register SP = HRI.getStackRegister();
614  unsigned MaxCF = MFI.getMaxCallFrameSize();
616 
618  for (auto &MBB : MF)
619  for (auto &MI : MBB)
620  if (MI.getOpcode() == Hexagon::PS_alloca)
621  AdjustRegs.push_back(&MI);
622 
623  for (auto *MI : AdjustRegs) {
624  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
625  expandAlloca(MI, HII, SP, MaxCF);
626  MI->eraseFromParent();
627  }
628 
629  DebugLoc dl = MBB.findDebugLoc(InsertPt);
630 
631  if (MF.getFunction().isVarArg() &&
632  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
633  // Calculate the size of register saved area.
634  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
635  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)
636  ? NumVarArgRegs * 4
637  : NumVarArgRegs * 4 + 4;
638  if (RegisterSavedAreaSizePlusPadding > 0) {
639  // Decrement the stack pointer by size of register saved area plus
640  // padding if any.
641  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
642  .addReg(SP)
643  .addImm(-RegisterSavedAreaSizePlusPadding)
645 
646  int NumBytes = 0;
647  // Copy all the named arguments below register saved area.
648  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
649  for (int i = HMFI.getFirstNamedArgFrameIndex(),
650  e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {
651  uint64_t ObjSize = MFI.getObjectSize(i);
652  Align ObjAlign = MFI.getObjectAlign(i);
653 
654  // Determine the kind of load/store that should be used.
655  unsigned LDOpc, STOpc;
656  uint64_t OpcodeChecker = ObjAlign.value();
657 
658  // Handle cases where alignment of an object is > its size.
659  if (ObjAlign > ObjSize) {
660  if (ObjSize <= 1)
661  OpcodeChecker = 1;
662  else if (ObjSize <= 2)
663  OpcodeChecker = 2;
664  else if (ObjSize <= 4)
665  OpcodeChecker = 4;
666  else if (ObjSize > 4)
667  OpcodeChecker = 8;
668  }
669 
670  switch (OpcodeChecker) {
671  case 1:
672  LDOpc = Hexagon::L2_loadrb_io;
673  STOpc = Hexagon::S2_storerb_io;
674  break;
675  case 2:
676  LDOpc = Hexagon::L2_loadrh_io;
677  STOpc = Hexagon::S2_storerh_io;
678  break;
679  case 4:
680  LDOpc = Hexagon::L2_loadri_io;
681  STOpc = Hexagon::S2_storeri_io;
682  break;
683  case 8:
684  default:
685  LDOpc = Hexagon::L2_loadrd_io;
686  STOpc = Hexagon::S2_storerd_io;
687  break;
688  }
689 
690  Register RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
691  : Hexagon::R6;
692  int LoadStoreCount = ObjSize / OpcodeChecker;
693 
694  if (ObjSize % OpcodeChecker)
695  ++LoadStoreCount;
696 
697  // Get the start location of the load. NumBytes is basically the
698  // offset from the stack pointer of previous function, which would be
699  // the caller in this case, as this function has variable argument
700  // list.
701  if (NumBytes != 0)
702  NumBytes = alignTo(NumBytes, ObjAlign);
703 
704  int Count = 0;
705  while (Count < LoadStoreCount) {
706  // Load the value of the named argument on stack.
707  BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
708  .addReg(SP)
709  .addImm(RegisterSavedAreaSizePlusPadding +
710  ObjAlign.value() * Count + NumBytes)
712 
713  // Store it below the register saved area plus padding.
714  BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
715  .addReg(SP)
716  .addImm(ObjAlign.value() * Count + NumBytes)
717  .addReg(RegUsed)
719 
720  Count++;
721  }
722  NumBytes += MFI.getObjectSize(i);
723  }
724 
725  // Make NumBytes 8 byte aligned
726  NumBytes = alignTo(NumBytes, 8);
727 
728  // If the number of registers having variable arguments is odd,
729  // leave 4 bytes of padding to get to the location where first
730  // variable argument which was passed through register was copied.
731  NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;
732 
733  for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {
734  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
735  .addReg(SP)
736  .addImm(NumBytes + 4 * i)
737  .addReg(Hexagon::R0 + j)
739  }
740  }
741  }
742 
743  if (hasFP(MF)) {
744  insertAllocframe(MBB, InsertPt, NumBytes);
745  if (AlignStack) {
746  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
747  .addReg(SP)
748  .addImm(-int64_t(MaxAlign.value()));
749  }
750  // If the stack-checking is enabled, and we spilled the callee-saved
751  // registers inline (i.e. did not use a spill function), then call
752  // the stack checker directly.
753  if (EnableStackOVFSanitizer && !PrologueStubs)
754  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
755  .addExternalSymbol("__runtime_stack_check");
756  } else if (NumBytes > 0) {
757  assert(alignTo(NumBytes, 8) == NumBytes);
758  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
759  .addReg(SP)
760  .addImm(-int(NumBytes));
761  }
762 }
763 
764 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
765  MachineFunction &MF = *MBB.getParent();
766  auto &HST = MF.getSubtarget<HexagonSubtarget>();
767  auto &HII = *HST.getInstrInfo();
768  auto &HRI = *HST.getRegisterInfo();
769  Register SP = HRI.getStackRegister();
770 
772  DebugLoc dl = MBB.findDebugLoc(InsertPt);
773 
774  if (!hasFP(MF)) {
775  MachineFrameInfo &MFI = MF.getFrameInfo();
776  unsigned NumBytes = MFI.getStackSize();
777  if (MF.getFunction().isVarArg() &&
778  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
779  // On Hexagon Linux, deallocate the stack for the register saved area.
780  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
781  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
782  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
783  NumBytes += RegisterSavedAreaSizePlusPadding;
784  }
785  if (NumBytes) {
786  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
787  .addReg(SP)
788  .addImm(NumBytes);
789  }
790  return;
791  }
792 
793  MachineInstr *RetI = getReturn(MBB);
794  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
795 
796  // Handle EH_RETURN.
797  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
798  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
799  .addDef(Hexagon::D15)
800  .addReg(Hexagon::R30);
801  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
802  .addReg(SP)
803  .addReg(Hexagon::R28);
804  return;
805  }
806 
807  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
808  // frame instruction if we encounter it.
809  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
810  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
811  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
812  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
813  MachineBasicBlock::iterator It = RetI;
814  ++It;
815  // Delete all instructions after the RESTORE (except labels).
816  while (It != MBB.end()) {
817  if (!It->isLabel())
818  It = MBB.erase(It);
819  else
820  ++It;
821  }
822  return;
823  }
824 
825  // It is possible that the restoring code is a call to a library function.
826  // All of the restore* functions include "deallocframe", so we need to make
827  // sure that we don't add an extra one.
828  bool NeedsDeallocframe = true;
829  if (!MBB.empty() && InsertPt != MBB.begin()) {
830  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
831  unsigned COpc = PrevIt->getOpcode();
832  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
833  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
834  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
835  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
836  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
837  NeedsDeallocframe = false;
838  }
839 
841  !MF.getFunction().isVarArg()) {
842  if (!NeedsDeallocframe)
843  return;
844  // If the returning instruction is PS_jmpret, replace it with
845  // dealloc_return, otherwise just add deallocframe. The function
846  // could be returning via a tail call.
847  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
848  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
849  .addDef(Hexagon::D15)
850  .addReg(Hexagon::R30);
851  return;
852  }
853  unsigned NewOpc = Hexagon::L4_return;
854  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
855  .addDef(Hexagon::D15)
856  .addReg(Hexagon::R30);
857  // Transfer the function live-out registers.
858  NewI->copyImplicitOps(MF, *RetI);
859  MBB.erase(RetI);
860  } else {
861  // L2_deallocframe instruction after it.
862  // Calculate the size of register saved area.
863  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
864  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
865  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
866 
869  : std::prev(Term);
870  if (I == MBB.end() ||
871  (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
872  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
873  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
874  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
875  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
876  .addDef(Hexagon::D15)
877  .addReg(Hexagon::R30);
878  if (RegisterSavedAreaSizePlusPadding != 0)
879  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
880  .addReg(SP)
881  .addImm(RegisterSavedAreaSizePlusPadding);
882  }
883 }
884 
885 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
886  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
887  MachineFunction &MF = *MBB.getParent();
888  auto &HST = MF.getSubtarget<HexagonSubtarget>();
889  auto &HII = *HST.getInstrInfo();
890  auto &HRI = *HST.getRegisterInfo();
891 
892  // Check for overflow.
893  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
894  const unsigned int ALLOCFRAME_MAX = 16384;
895 
896  // Create a dummy memory operand to avoid allocframe from being treated as
897  // a volatile memory reference.
900 
901  DebugLoc dl = MBB.findDebugLoc(InsertPt);
902  Register SP = HRI.getStackRegister();
903 
904  if (NumBytes >= ALLOCFRAME_MAX) {
905  // Emit allocframe(#0).
906  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
907  .addDef(SP)
908  .addReg(SP)
909  .addImm(0)
910  .addMemOperand(MMO);
911 
912  // Subtract the size from the stack pointer.
913  Register SP = HRI.getStackRegister();
914  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
915  .addReg(SP)
916  .addImm(-int(NumBytes));
917  } else {
918  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
919  .addDef(SP)
920  .addReg(SP)
921  .addImm(NumBytes)
922  .addMemOperand(MMO);
923  }
924 }
925 
926 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
927  MachineBasicBlock &SaveB) const {
928  SetVector<unsigned> Worklist;
929 
930  MachineBasicBlock &EntryB = MF.front();
931  Worklist.insert(EntryB.getNumber());
932 
933  unsigned SaveN = SaveB.getNumber();
934  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
935 
936  for (unsigned i = 0; i < Worklist.size(); ++i) {
937  unsigned BN = Worklist[i];
939  for (auto &R : CSI)
940  if (!MBB.isLiveIn(R.getReg()))
941  MBB.addLiveIn(R.getReg());
942  if (BN != SaveN)
943  for (auto &SB : MBB.successors())
944  Worklist.insert(SB->getNumber());
945  }
946 }
947 
948 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
949  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
950  BitVector &Path) const {
951  assert(MBB.getNumber() >= 0);
952  unsigned BN = MBB.getNumber();
953  if (Path[BN] || DoneF[BN])
954  return false;
955  if (DoneT[BN])
956  return true;
957 
958  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
959 
960  Path[BN] = true;
961  bool ReachedExit = false;
962  for (auto &SB : MBB.successors())
963  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
964 
965  if (!MBB.empty() && MBB.back().isReturn()) {
966  // Add implicit uses of all callee-saved registers to the reached
967  // return instructions. This is to prevent the anti-dependency breaker
968  // from renaming these registers.
969  MachineInstr &RetI = MBB.back();
970  if (!isRestoreCall(RetI.getOpcode()))
971  for (auto &R : CSI)
972  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
973  ReachedExit = true;
974  }
975 
976  // We don't want to add unnecessary live-ins to the restore block: since
977  // the callee-saved registers are being defined in it, the entry of the
978  // restore block cannot be on the path from the definitions to any exit.
979  if (ReachedExit && &MBB != &RestoreB) {
980  for (auto &R : CSI)
981  if (!MBB.isLiveIn(R.getReg()))
982  MBB.addLiveIn(R.getReg());
983  DoneT[BN] = true;
984  }
985  if (!ReachedExit)
986  DoneF[BN] = true;
987 
988  Path[BN] = false;
989  return ReachedExit;
990 }
991 
992 static std::optional<MachineBasicBlock::iterator>
994  // The CFI instructions need to be inserted right after allocframe.
995  // An exception to this is a situation where allocframe is bundled
996  // with a call: then the CFI instructions need to be inserted before
997  // the packet with the allocframe+call (in case the call throws an
998  // exception).
999  auto End = B.instr_end();
1000 
1001  for (MachineInstr &I : B) {
1002  MachineBasicBlock::iterator It = I.getIterator();
1003  if (!I.isBundle()) {
1004  if (I.getOpcode() == Hexagon::S2_allocframe)
1005  return std::next(It);
1006  continue;
1007  }
1008  // I is a bundle.
1009  bool HasCall = false, HasAllocFrame = false;
1010  auto T = It.getInstrIterator();
1011  while (++T != End && T->isBundled()) {
1012  if (T->getOpcode() == Hexagon::S2_allocframe)
1013  HasAllocFrame = true;
1014  else if (T->isCall())
1015  HasCall = true;
1016  }
1017  if (HasAllocFrame)
1018  return HasCall ? It : std::next(It);
1019  }
1020  return std::nullopt;
1021 }
1022 
1024  for (auto &B : MF) {
1025  auto At = findCFILocation(B);
1026  if (At)
1027  insertCFIInstructionsAt(B, At.value());
1028  }
1029 }
1030 
1031 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
1032  MachineBasicBlock::iterator At) const {
1033  MachineFunction &MF = *MBB.getParent();
1034  MachineFrameInfo &MFI = MF.getFrameInfo();
1035  MachineModuleInfo &MMI = MF.getMMI();
1036  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1037  auto &HII = *HST.getInstrInfo();
1038  auto &HRI = *HST.getRegisterInfo();
1039 
1040  // If CFI instructions have debug information attached, something goes
1041  // wrong with the final assembly generation: the prolog_end is placed
1042  // in a wrong location.
1043  DebugLoc DL;
1044  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1045 
1046  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
1047  bool HasFP = hasFP(MF);
1048 
1049  if (HasFP) {
1050  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
1051  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
1052 
1053  // Define CFA via an offset from the value of FP.
1054  //
1055  // -8 -4 0 (SP)
1056  // --+----+----+---------------------
1057  // | FP | LR | increasing addresses -->
1058  // --+----+----+---------------------
1059  // | +-- Old SP (before allocframe)
1060  // +-- New FP (after allocframe)
1061  //
1062  // MCCFIInstruction::cfiDefCfa adds the offset from the register.
1063  // MCCFIInstruction::createOffset takes the offset without sign change.
1064  auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);
1065  BuildMI(MBB, At, DL, CFID)
1066  .addCFIIndex(MF.addFrameInst(DefCfa));
1067  // R31 (return addr) = CFA - 4
1068  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
1069  BuildMI(MBB, At, DL, CFID)
1070  .addCFIIndex(MF.addFrameInst(OffR31));
1071  // R30 (frame ptr) = CFA - 8
1072  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
1073  BuildMI(MBB, At, DL, CFID)
1074  .addCFIIndex(MF.addFrameInst(OffR30));
1075  }
1076 
1077  static Register RegsToMove[] = {
1078  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1079  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1080  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1081  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1082  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1083  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1084  Hexagon::NoRegister
1085  };
1086 
1087  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1088 
1089  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1090  Register Reg = RegsToMove[i];
1091  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
1092  return C.getReg() == Reg;
1093  };
1094  auto F = find_if(CSI, IfR);
1095  if (F == CSI.end())
1096  continue;
1097 
1098  int64_t Offset;
1099  if (HasFP) {
1100  // If the function has a frame pointer (i.e. has an allocframe),
1101  // then the CFA has been defined in terms of FP. Any offsets in
1102  // the following CFI instructions have to be defined relative
1103  // to FP, which points to the bottom of the stack frame.
1104  // The function getFrameIndexReference can still choose to use SP
1105  // for the offset calculation, so we cannot simply call it here.
1106  // Instead, get the offset (relative to the FP) directly.
1107  Offset = MFI.getObjectOffset(F->getFrameIdx());
1108  } else {
1109  Register FrameReg;
1110  Offset =
1111  getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();
1112  }
1113  // Subtract 8 to make room for R30 and R31, which are added above.
1114  Offset -= 8;
1115 
1116  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1117  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
1118  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
1119  Offset);
1120  BuildMI(MBB, At, DL, CFID)
1121  .addCFIIndex(MF.addFrameInst(OffReg));
1122  } else {
1123  // Split the double regs into subregs, and generate appropriate
1124  // cfi_offsets.
1125  // The only reason, we are split double regs is, llvm-mc does not
1126  // understand paired registers for cfi_offset.
1127  // Eg .cfi_offset r1:0, -64
1128 
1129  Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1130  Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1131  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
1132  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
1133  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
1134  Offset+4);
1135  BuildMI(MBB, At, DL, CFID)
1136  .addCFIIndex(MF.addFrameInst(OffHi));
1137  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
1138  Offset);
1139  BuildMI(MBB, At, DL, CFID)
1140  .addCFIIndex(MF.addFrameInst(OffLo));
1141  }
1142  }
1143 }
1144 
1146  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1147  return false;
1148 
1149  auto &MFI = MF.getFrameInfo();
1150  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1151  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1152  bool HasAlloca = MFI.hasVarSizedObjects();
1153 
1154  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
1155  // that this shouldn't be required, but doing so now because gcc does and
1156  // gdb can't break at the start of the function without it. Will remove if
1157  // this turns out to be a gdb bug.
1158  //
1159  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
1160  return true;
1161 
1162  // By default we want to use SP (since it's always there). FP requires
1163  // some setup (i.e. ALLOCFRAME).
1164  // Both, alloca and stack alignment modify the stack pointer by an
1165  // undetermined value, so we need to save it at the entry to the function
1166  // (i.e. use allocframe).
1167  if (HasAlloca || HasExtraAlign)
1168  return true;
1169 
1170  if (MFI.getStackSize() > 0) {
1171  // If FP-elimination is disabled, we have to use FP at this point.
1172  const TargetMachine &TM = MF.getTarget();
1173  if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
1174  return true;
1176  return true;
1177  }
1178 
1179  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1180  if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())
1181  return true;
1182 
1183  return false;
1184 }
1185 
1190 };
1191 
1192 static const char *getSpillFunctionFor(Register MaxReg, SpillKind SpillType,
1193  bool Stkchk = false) {
1194  const char * V4SpillToMemoryFunctions[] = {
1195  "__save_r16_through_r17",
1196  "__save_r16_through_r19",
1197  "__save_r16_through_r21",
1198  "__save_r16_through_r23",
1199  "__save_r16_through_r25",
1200  "__save_r16_through_r27" };
1201 
1202  const char * V4SpillToMemoryStkchkFunctions[] = {
1203  "__save_r16_through_r17_stkchk",
1204  "__save_r16_through_r19_stkchk",
1205  "__save_r16_through_r21_stkchk",
1206  "__save_r16_through_r23_stkchk",
1207  "__save_r16_through_r25_stkchk",
1208  "__save_r16_through_r27_stkchk" };
1209 
1210  const char * V4SpillFromMemoryFunctions[] = {
1211  "__restore_r16_through_r17_and_deallocframe",
1212  "__restore_r16_through_r19_and_deallocframe",
1213  "__restore_r16_through_r21_and_deallocframe",
1214  "__restore_r16_through_r23_and_deallocframe",
1215  "__restore_r16_through_r25_and_deallocframe",
1216  "__restore_r16_through_r27_and_deallocframe" };
1217 
1218  const char * V4SpillFromMemoryTailcallFunctions[] = {
1219  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1220  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1221  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1222  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1223  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1224  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1225  };
1226 
1227  const char **SpillFunc = nullptr;
1228 
1229  switch(SpillType) {
1230  case SK_ToMem:
1231  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1232  : V4SpillToMemoryFunctions;
1233  break;
1234  case SK_FromMem:
1235  SpillFunc = V4SpillFromMemoryFunctions;
1236  break;
1237  case SK_FromMemTailcall:
1238  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1239  break;
1240  }
1241  assert(SpillFunc && "Unknown spill kind");
1242 
1243  // Spill all callee-saved registers up to the highest register used.
1244  switch (MaxReg) {
1245  case Hexagon::R17:
1246  return SpillFunc[0];
1247  case Hexagon::R19:
1248  return SpillFunc[1];
1249  case Hexagon::R21:
1250  return SpillFunc[2];
1251  case Hexagon::R23:
1252  return SpillFunc[3];
1253  case Hexagon::R25:
1254  return SpillFunc[4];
1255  case Hexagon::R27:
1256  return SpillFunc[5];
1257  default:
1258  llvm_unreachable("Unhandled maximum callee save register");
1259  }
1260  return nullptr;
1261 }
1262 
1265  Register &FrameReg) const {
1266  auto &MFI = MF.getFrameInfo();
1267  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1268 
1269  int Offset = MFI.getObjectOffset(FI);
1270  bool HasAlloca = MFI.hasVarSizedObjects();
1271  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1272  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1273 
1274  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1275  unsigned FrameSize = MFI.getStackSize();
1276  Register SP = HRI.getStackRegister();
1277  Register FP = HRI.getFrameRegister();
1278  Register AP = HMFI.getStackAlignBaseReg();
1279  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1280  // is true. HasExtraAlign may be set because of vector spills, without
1281  // aligned locals or aligned outgoing function arguments. Since vector
1282  // spills will ultimately be "unaligned", it is safe to use FP as the
1283  // base register.
1284  // In fact, in such a scenario the stack is actually not required to be
1285  // aligned, although it may end up being aligned anyway, since this
1286  // particular case is not easily detectable. The alignment will be
1287  // unnecessary, but not incorrect.
1288  // Unfortunately there is no quick way to verify that the above is
1289  // indeed the case (and that it's not a result of an error), so just
1290  // assume that missing AP will be replaced by FP.
1291  // (A better fix would be to rematerialize AP from FP and always align
1292  // vector spills.)
1293  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1294  // Use FP at -O0, except when there are objects with extra alignment.
1295  // That additional alignment requirement may cause a pad to be inserted,
1296  // which will make it impossible to use FP to access objects located
1297  // past the pad.
1298  if (NoOpt && !HasExtraAlign)
1299  UseFP = true;
1300  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1301  // Fixed and preallocated objects will be located before any padding
1302  // so FP must be used to access them.
1303  UseFP |= (HasAlloca || HasExtraAlign);
1304  } else {
1305  if (HasAlloca) {
1306  if (HasExtraAlign)
1307  UseAP = true;
1308  else
1309  UseFP = true;
1310  }
1311  }
1312 
1313  // If FP was picked, then there had better be FP.
1314  bool HasFP = hasFP(MF);
1315  assert((HasFP || !UseFP) && "This function must have frame pointer");
1316 
1317  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1318  // FP/LR. If the base register is used to access an object across these
1319  // 8 bytes, then the offset will need to be adjusted by 8.
1320  //
1321  // After allocframe:
1322  // HexagonISelLowering adds 8 to ---+
1323  // the offsets of all stack-based |
1324  // arguments (*) |
1325  // |
1326  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1327  // ------------------------+-----+------------------------> increasing
1328  // <local objects> |FP/LR| <input arguments> addresses
1329  // -----------------+------+-----+------------------------>
1330  // | |
1331  // SP/AP point --+ +-- FP points here (**)
1332  // somewhere on
1333  // this side of FP/LR
1334  //
1335  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1336  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1337 
1338  // The lowering assumes that FP/LR is present, and so the offsets of
1339  // the formal arguments start at 8. If FP/LR is not there we need to
1340  // reduce the offset by 8.
1341  if (Offset > 0 && !HasFP)
1342  Offset -= 8;
1343 
1344  if (UseFP)
1345  FrameReg = FP;
1346  else if (UseAP)
1347  FrameReg = AP;
1348  else
1349  FrameReg = SP;
1350 
1351  // Calculate the actual offset in the instruction. If there is no FP
1352  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1353  // there will be no SP -= FrameSize), so the frame size should not be
1354  // added to the calculated offset.
1355  int RealOffset = Offset;
1356  if (!UseFP && !UseAP)
1357  RealOffset = FrameSize+Offset;
1358  return StackOffset::getFixed(RealOffset);
1359 }
1360 
1361 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1362  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1363  bool &PrologueStubs) const {
1364  if (CSI.empty())
1365  return true;
1366 
1368  PrologueStubs = false;
1369  MachineFunction &MF = *MBB.getParent();
1370  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1371  auto &HII = *HST.getInstrInfo();
1372 
1373  if (useSpillFunction(MF, CSI)) {
1374  PrologueStubs = true;
1375  Register MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1376  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1377  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1378  StkOvrFlowEnabled);
1379  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1380  bool IsPIC = HTM.isPositionIndependent();
1381  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1382 
1383  // Call spill function.
1384  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1385  unsigned SpillOpc;
1386  if (StkOvrFlowEnabled) {
1387  if (LongCalls)
1388  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1389  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1390  else
1391  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1392  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1393  } else {
1394  if (LongCalls)
1395  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1396  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1397  else
1398  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1399  : Hexagon::SAVE_REGISTERS_CALL_V4;
1400  }
1401 
1402  MachineInstr *SaveRegsCall =
1403  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1404  .addExternalSymbol(SpillFun);
1405 
1406  // Add callee-saved registers as use.
1407  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1408  // Add live in registers.
1409  for (const CalleeSavedInfo &I : CSI)
1410  MBB.addLiveIn(I.getReg());
1411  return true;
1412  }
1413 
1414  for (const CalleeSavedInfo &I : CSI) {
1415  Register Reg = I.getReg();
1416  // Add live in registers. We treat eh_return callee saved register r0 - r3
1417  // specially. They are not really callee saved registers as they are not
1418  // supposed to be killed.
1419  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1420  int FI = I.getFrameIdx();
1421  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1422  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1423  if (IsKill)
1424  MBB.addLiveIn(Reg);
1425  }
1426  return true;
1427 }
1428 
1429 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1430  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1431  if (CSI.empty())
1432  return false;
1433 
1435  MachineFunction &MF = *MBB.getParent();
1436  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1437  auto &HII = *HST.getInstrInfo();
1438 
1439  if (useRestoreFunction(MF, CSI)) {
1440  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1441  Register MaxR = getMaxCalleeSavedReg(CSI, HRI);
1443  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1444  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1445  bool IsPIC = HTM.isPositionIndependent();
1446  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1447 
1448  // Call spill function.
1449  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1450  : MBB.findDebugLoc(MBB.end());
1451  MachineInstr *DeallocCall = nullptr;
1452 
1453  if (HasTC) {
1454  unsigned RetOpc;
1455  if (LongCalls)
1456  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1457  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1458  else
1459  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1460  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1461  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1462  .addExternalSymbol(RestoreFn);
1463  } else {
1464  // The block has a return.
1466  assert(It->isReturn() && std::next(It) == MBB.end());
1467  unsigned RetOpc;
1468  if (LongCalls)
1469  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1470  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1471  else
1472  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1473  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1474  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1475  .addExternalSymbol(RestoreFn);
1476  // Transfer the function live-out registers.
1477  DeallocCall->copyImplicitOps(MF, *It);
1478  }
1479  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1480  return true;
1481  }
1482 
1483  for (const CalleeSavedInfo &I : CSI) {
1484  Register Reg = I.getReg();
1485  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1486  int FI = I.getFrameIdx();
1487  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1488  }
1489 
1490  return true;
1491 }
1492 
1496  MachineInstr &MI = *I;
1497  unsigned Opc = MI.getOpcode();
1498  (void)Opc; // Silence compiler warning.
1499  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1500  "Cannot handle this call frame pseudo instruction");
1501  return MBB.erase(I);
1502 }
1503 
1505  MachineFunction &MF, RegScavenger *RS) const {
1506  // If this function has uses aligned stack and also has variable sized stack
1507  // objects, then we need to map all spill slots to fixed positions, so that
1508  // they can be accessed through FP. Otherwise they would have to be accessed
1509  // via AP, which may not be available at the particular place in the program.
1510  MachineFrameInfo &MFI = MF.getFrameInfo();
1511  bool HasAlloca = MFI.hasVarSizedObjects();
1512  bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
1513 
1514  if (!HasAlloca || !NeedsAlign)
1515  return;
1516 
1517  // Set the physical aligned-stack base address register.
1518  Register AP = 0;
1519  if (const MachineInstr *AI = getAlignaInstr(MF))
1520  AP = AI->getOperand(0).getReg();
1521  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1522  assert(!AP.isValid() || AP.isPhysical());
1523  HMFI.setStackAlignBaseReg(AP);
1524 }
1525 
1526 /// Returns true if there are no caller-saved registers available in class RC.
1528  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1530 
1531  auto IsUsed = [&HRI,&MRI] (Register Reg) -> bool {
1532  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1533  if (MRI.isPhysRegUsed(*AI))
1534  return true;
1535  return false;
1536  };
1537 
1538  // Check for an unused caller-saved register. Callee-saved registers
1539  // have become pristine by now.
1540  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1541  if (!IsUsed(*P))
1542  return false;
1543 
1544  // All caller-saved registers are used.
1545  return true;
1546 }
1547 
1548 #ifndef NDEBUG
1549 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1550  dbgs() << '{';
1551  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1552  Register R = x;
1553  dbgs() << ' ' << printReg(R, &TRI);
1554  }
1555  dbgs() << " }";
1556 }
1557 #endif
1558 
1560  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1561  LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1562  MachineFrameInfo &MFI = MF.getFrameInfo();
1563  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1564 
1565  // Generate a set of unique, callee-saved registers (SRegs), where each
1566  // register in the set is maximal in terms of sub-/super-register relation,
1567  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1568 
1569  // (1) For each callee-saved register, add that register and all of its
1570  // sub-registers to SRegs.
1571  LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1572  for (const CalleeSavedInfo &I : CSI) {
1573  Register R = I.getReg();
1574  LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1575  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1576  SRegs[*SR] = true;
1577  }
1578  LLVM_DEBUG(dbgs() << " }\n");
1579  LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1580  dbgs() << "\n");
1581 
1582  // (2) For each reserved register, remove that register and all of its
1583  // sub- and super-registers from SRegs.
1585  // Unreserve the stack align register: it is reserved for this function
1586  // only, it still needs to be saved/restored.
1587  Register AP =
1588  MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseReg();
1589  if (AP.isValid()) {
1590  Reserved[AP] = false;
1591  // Unreserve super-regs if no other subregisters are reserved.
1592  for (MCSuperRegIterator SP(AP, TRI, false); SP.isValid(); ++SP) {
1593  bool HasResSub = false;
1594  for (MCSubRegIterator SB(*SP, TRI, false); SB.isValid(); ++SB) {
1595  if (!Reserved[*SB])
1596  continue;
1597  HasResSub = true;
1598  break;
1599  }
1600  if (!HasResSub)
1601  Reserved[*SP] = false;
1602  }
1603  }
1604 
1605  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1606  Register R = x;
1607  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1608  SRegs[*SR] = false;
1609  }
1610  LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1611  dbgs() << "\n");
1612  LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1613  dbgs() << "\n");
1614 
1615  // (3) Collect all registers that have at least one sub-register in SRegs,
1616  // and also have no sub-registers that are reserved. These will be the can-
1617  // didates for saving as a whole instead of their individual sub-registers.
1618  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1619  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1620  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1621  Register R = x;
1622  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1623  TmpSup[*SR] = true;
1624  }
1625  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1626  Register R = x;
1627  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1628  if (!Reserved[*SR])
1629  continue;
1630  TmpSup[R] = false;
1631  break;
1632  }
1633  }
1634  LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1635  dbgs() << "\n");
1636 
1637  // (4) Include all super-registers found in (3) into SRegs.
1638  SRegs |= TmpSup;
1639  LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1640  dbgs() << "\n");
1641 
1642  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1643  // remove R from SRegs.
1644  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1645  Register R = x;
1646  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1647  if (!SRegs[*SR])
1648  continue;
1649  SRegs[R] = false;
1650  break;
1651  }
1652  }
1653  LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1654  dbgs() << "\n");
1655 
1656  // Now, for each register that has a fixed stack slot, create the stack
1657  // object for it.
1658  CSI.clear();
1659 
1661 
1662  unsigned NumFixed;
1663  int MinOffset = 0; // CS offsets are negative.
1664  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1665  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1666  if (!SRegs[S->Reg])
1667  continue;
1668  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1669  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1670  MinOffset = std::min(MinOffset, S->Offset);
1671  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1672  SRegs[S->Reg] = false;
1673  }
1674 
1675  // There can be some registers that don't have fixed slots. For example,
1676  // we need to store R0-R3 in functions with exception handling. For each
1677  // such register, create a non-fixed stack object.
1678  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1679  Register R = x;
1681  unsigned Size = TRI->getSpillSize(*RC);
1682  int Off = MinOffset - Size;
1683  Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
1684  Off &= -Alignment.value();
1685  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1686  MinOffset = std::min(MinOffset, Off);
1687  CSI.push_back(CalleeSavedInfo(R, FI));
1688  SRegs[R] = false;
1689  }
1690 
1691  LLVM_DEBUG({
1692  dbgs() << "CS information: {";
1693  for (const CalleeSavedInfo &I : CSI) {
1694  int FI = I.getFrameIdx();
1695  int Off = MFI.getObjectOffset(FI);
1696  dbgs() << ' ' << printReg(I.getReg(), TRI) << ":fi#" << FI << ":sp";
1697  if (Off >= 0)
1698  dbgs() << '+';
1699  dbgs() << Off;
1700  }
1701  dbgs() << " }\n";
1702  });
1703 
1704 #ifndef NDEBUG
1705  // Verify that all registers were handled.
1706  bool MissedReg = false;
1707  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1708  Register R = x;
1709  dbgs() << printReg(R, TRI) << ' ';
1710  MissedReg = true;
1711  }
1712  if (MissedReg)
1713  llvm_unreachable("...there are unhandled callee-saved registers!");
1714 #endif
1715 
1716  return true;
1717 }
1718 
1719 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1721  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1722  MachineInstr *MI = &*It;
1723  DebugLoc DL = MI->getDebugLoc();
1724  Register DstR = MI->getOperand(0).getReg();
1725  Register SrcR = MI->getOperand(1).getReg();
1726  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1727  !Hexagon::ModRegsRegClass.contains(SrcR))
1728  return false;
1729 
1730  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1731  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1732  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1733  .addReg(TmpR, RegState::Kill);
1734 
1735  NewRegs.push_back(TmpR);
1736  B.erase(It);
1737  return true;
1738 }
1739 
1740 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1742  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1743  MachineInstr *MI = &*It;
1744  if (!MI->getOperand(0).isFI())
1745  return false;
1746 
1747  DebugLoc DL = MI->getDebugLoc();
1748  unsigned Opc = MI->getOpcode();
1749  Register SrcR = MI->getOperand(2).getReg();
1750  bool IsKill = MI->getOperand(2).isKill();
1751  int FI = MI->getOperand(0).getIndex();
1752 
1753  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1754  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1755  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1756  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1757  : Hexagon::A2_tfrcrr;
1758  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1759  .addReg(SrcR, getKillRegState(IsKill));
1760 
1761  // S2_storeri_io FI, 0, TmpR
1762  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1763  .addFrameIndex(FI)
1764  .addImm(0)
1765  .addReg(TmpR, RegState::Kill)
1766  .cloneMemRefs(*MI);
1767 
1768  NewRegs.push_back(TmpR);
1769  B.erase(It);
1770  return true;
1771 }
1772 
1773 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1775  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1776  MachineInstr *MI = &*It;
1777  if (!MI->getOperand(1).isFI())
1778  return false;
1779 
1780  DebugLoc DL = MI->getDebugLoc();
1781  unsigned Opc = MI->getOpcode();
1782  Register DstR = MI->getOperand(0).getReg();
1783  int FI = MI->getOperand(1).getIndex();
1784 
1785  // TmpR = L2_loadri_io FI, 0
1786  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1787  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1788  .addFrameIndex(FI)
1789  .addImm(0)
1790  .cloneMemRefs(*MI);
1791 
1792  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1793  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1794  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1795  : Hexagon::A2_tfrrcr;
1796  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1797  .addReg(TmpR, RegState::Kill);
1798 
1799  NewRegs.push_back(TmpR);
1800  B.erase(It);
1801  return true;
1802 }
1803 
1804 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1806  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1807  MachineInstr *MI = &*It;
1808  if (!MI->getOperand(0).isFI())
1809  return false;
1810 
1811  DebugLoc DL = MI->getDebugLoc();
1812  Register SrcR = MI->getOperand(2).getReg();
1813  bool IsKill = MI->getOperand(2).isKill();
1814  int FI = MI->getOperand(0).getIndex();
1815  auto *RC = &Hexagon::HvxVRRegClass;
1816 
1817  // Insert transfer to general vector register.
1818  // TmpR0 = A2_tfrsi 0x01010101
1819  // TmpR1 = V6_vandqrt Qx, TmpR0
1820  // store FI, 0, TmpR1
1821  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1822  Register TmpR1 = MRI.createVirtualRegister(RC);
1823 
1824  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1825  .addImm(0x01010101);
1826 
1827  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1828  .addReg(SrcR, getKillRegState(IsKill))
1829  .addReg(TmpR0, RegState::Kill);
1830 
1831  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1832  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1833  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1834 
1835  NewRegs.push_back(TmpR0);
1836  NewRegs.push_back(TmpR1);
1837  B.erase(It);
1838  return true;
1839 }
1840 
1841 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1843  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1844  MachineInstr *MI = &*It;
1845  if (!MI->getOperand(1).isFI())
1846  return false;
1847 
1848  DebugLoc DL = MI->getDebugLoc();
1849  Register DstR = MI->getOperand(0).getReg();
1850  int FI = MI->getOperand(1).getIndex();
1851  auto *RC = &Hexagon::HvxVRRegClass;
1852 
1853  // TmpR0 = A2_tfrsi 0x01010101
1854  // TmpR1 = load FI, 0
1855  // DstR = V6_vandvrt TmpR1, TmpR0
1856  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1857  Register TmpR1 = MRI.createVirtualRegister(RC);
1858 
1859  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1860  .addImm(0x01010101);
1861  MachineFunction &MF = *B.getParent();
1862  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1863  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1864  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1865 
1866  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1867  .addReg(TmpR1, RegState::Kill)
1868  .addReg(TmpR0, RegState::Kill);
1869 
1870  NewRegs.push_back(TmpR0);
1871  NewRegs.push_back(TmpR1);
1872  B.erase(It);
1873  return true;
1874 }
1875 
1876 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1878  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1879  MachineFunction &MF = *B.getParent();
1880  auto &MFI = MF.getFrameInfo();
1881  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1882  MachineInstr *MI = &*It;
1883  if (!MI->getOperand(0).isFI())
1884  return false;
1885 
1886  // It is possible that the double vector being stored is only partially
1887  // defined. From the point of view of the liveness tracking, it is ok to
1888  // store it as a whole, but if we break it up we may end up storing a
1889  // register that is entirely undefined.
1890  LivePhysRegs LPR(HRI);
1891  LPR.addLiveIns(B);
1893  for (auto R = B.begin(); R != It; ++R) {
1894  Clobbers.clear();
1895  LPR.stepForward(*R, Clobbers);
1896  }
1897 
1898  DebugLoc DL = MI->getDebugLoc();
1899  Register SrcR = MI->getOperand(2).getReg();
1900  Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1901  Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1902  bool IsKill = MI->getOperand(2).isKill();
1903  int FI = MI->getOperand(0).getIndex();
1904 
1905  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1906  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1907  Align HasAlign = MFI.getObjectAlign(FI);
1908  unsigned StoreOpc;
1909 
1910  // Store low part.
1911  if (LPR.contains(SrcLo)) {
1912  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1913  : Hexagon::V6_vS32Ub_ai;
1914  BuildMI(B, It, DL, HII.get(StoreOpc))
1915  .addFrameIndex(FI)
1916  .addImm(0)
1917  .addReg(SrcLo, getKillRegState(IsKill))
1918  .cloneMemRefs(*MI);
1919  }
1920 
1921  // Store high part.
1922  if (LPR.contains(SrcHi)) {
1923  StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1924  : Hexagon::V6_vS32Ub_ai;
1925  BuildMI(B, It, DL, HII.get(StoreOpc))
1926  .addFrameIndex(FI)
1927  .addImm(Size)
1928  .addReg(SrcHi, getKillRegState(IsKill))
1929  .cloneMemRefs(*MI);
1930  }
1931 
1932  B.erase(It);
1933  return true;
1934 }
1935 
1936 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1938  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1939  MachineFunction &MF = *B.getParent();
1940  auto &MFI = MF.getFrameInfo();
1941  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1942  MachineInstr *MI = &*It;
1943  if (!MI->getOperand(1).isFI())
1944  return false;
1945 
1946  DebugLoc DL = MI->getDebugLoc();
1947  Register DstR = MI->getOperand(0).getReg();
1948  Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1949  Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1950  int FI = MI->getOperand(1).getIndex();
1951 
1952  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1953  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1954  Align HasAlign = MFI.getObjectAlign(FI);
1955  unsigned LoadOpc;
1956 
1957  // Load low part.
1958  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1959  : Hexagon::V6_vL32Ub_ai;
1960  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1961  .addFrameIndex(FI)
1962  .addImm(0)
1963  .cloneMemRefs(*MI);
1964 
1965  // Load high part.
1966  LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
1967  : Hexagon::V6_vL32Ub_ai;
1968  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1969  .addFrameIndex(FI)
1970  .addImm(Size)
1971  .cloneMemRefs(*MI);
1972 
1973  B.erase(It);
1974  return true;
1975 }
1976 
1977 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
1979  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
1980  MachineFunction &MF = *B.getParent();
1981  auto &MFI = MF.getFrameInfo();
1982  MachineInstr *MI = &*It;
1983  if (!MI->getOperand(0).isFI())
1984  return false;
1985 
1986  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1987  DebugLoc DL = MI->getDebugLoc();
1988  Register SrcR = MI->getOperand(2).getReg();
1989  bool IsKill = MI->getOperand(2).isKill();
1990  int FI = MI->getOperand(0).getIndex();
1991 
1992  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1993  Align HasAlign = MFI.getObjectAlign(FI);
1994  unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai
1995  : Hexagon::V6_vS32Ub_ai;
1996  BuildMI(B, It, DL, HII.get(StoreOpc))
1997  .addFrameIndex(FI)
1998  .addImm(0)
1999  .addReg(SrcR, getKillRegState(IsKill))
2000  .cloneMemRefs(*MI);
2001 
2002  B.erase(It);
2003  return true;
2004 }
2005 
2006 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
2008  const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const {
2009  MachineFunction &MF = *B.getParent();
2010  auto &MFI = MF.getFrameInfo();
2011  MachineInstr *MI = &*It;
2012  if (!MI->getOperand(1).isFI())
2013  return false;
2014 
2015  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2016  DebugLoc DL = MI->getDebugLoc();
2017  Register DstR = MI->getOperand(0).getReg();
2018  int FI = MI->getOperand(1).getIndex();
2019 
2020  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2021  Align HasAlign = MFI.getObjectAlign(FI);
2022  unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai
2023  : Hexagon::V6_vL32Ub_ai;
2024  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2025  .addFrameIndex(FI)
2026  .addImm(0)
2027  .cloneMemRefs(*MI);
2028 
2029  B.erase(It);
2030  return true;
2031 }
2032 
2033 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
2034  SmallVectorImpl<Register> &NewRegs) const {
2035  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
2037  bool Changed = false;
2038 
2039  for (auto &B : MF) {
2040  // Traverse the basic block.
2042  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
2043  MachineInstr *MI = &*I;
2044  NextI = std::next(I);
2045  unsigned Opc = MI->getOpcode();
2046 
2047  switch (Opc) {
2048  case TargetOpcode::COPY:
2049  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
2050  break;
2051  case Hexagon::STriw_pred:
2052  case Hexagon::STriw_ctr:
2053  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
2054  break;
2055  case Hexagon::LDriw_pred:
2056  case Hexagon::LDriw_ctr:
2057  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
2058  break;
2059  case Hexagon::PS_vstorerq_ai:
2060  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
2061  break;
2062  case Hexagon::PS_vloadrq_ai:
2063  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
2064  break;
2065  case Hexagon::PS_vloadrw_ai:
2066  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
2067  break;
2068  case Hexagon::PS_vstorerw_ai:
2069  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
2070  break;
2071  }
2072  }
2073  }
2074 
2075  return Changed;
2076 }
2077 
2079  BitVector &SavedRegs,
2080  RegScavenger *RS) const {
2081  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2082 
2083  SavedRegs.resize(HRI.getNumRegs());
2084 
2085  // If we have a function containing __builtin_eh_return we want to spill and
2086  // restore all callee saved registers. Pretend that they are used.
2088  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
2089  SavedRegs.set(*R);
2090 
2091  // Replace predicate register pseudo spill code.
2092  SmallVector<Register,8> NewRegs;
2093  expandSpillMacros(MF, NewRegs);
2094  if (OptimizeSpillSlots && !isOptNone(MF))
2095  optimizeSpillSlots(MF, NewRegs);
2096 
2097  // We need to reserve a spill slot if scavenging could potentially require
2098  // spilling a scavenged register.
2099  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
2100  MachineFrameInfo &MFI = MF.getFrameInfo();
2103  // Reserve an int register in any case, because it could be used to hold
2104  // the stack offset in case it does not fit into a spill instruction.
2105  SpillRCs.insert(&Hexagon::IntRegsRegClass);
2106 
2107  for (Register VR : NewRegs)
2108  SpillRCs.insert(MRI.getRegClass(VR));
2109 
2110  for (const auto *RC : SpillRCs) {
2111  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
2112  continue;
2113  unsigned Num = 1;
2114  switch (RC->getID()) {
2115  case Hexagon::IntRegsRegClassID:
2116  Num = NumberScavengerSlots;
2117  break;
2118  case Hexagon::HvxQRRegClassID:
2119  Num = 2; // Vector predicate spills also need a vector register.
2120  break;
2121  }
2122  unsigned S = HRI.getSpillSize(*RC);
2123  Align A = HRI.getSpillAlign(*RC);
2124  for (unsigned i = 0; i < Num; i++) {
2125  int NewFI = MFI.CreateSpillStackObject(S, A);
2126  RS->addScavengingFrameIndex(NewFI);
2127  }
2128  }
2129  }
2130 
2131  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2132 }
2133 
2134 Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,
2138  const TargetRegisterClass *RC) const {
2139  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2140  auto &MRI = MF.getRegInfo();
2141 
2142  auto isDead = [&FIR,&DeadMap] (Register Reg) -> bool {
2143  auto F = DeadMap.find({Reg,0});
2144  if (F == DeadMap.end())
2145  return false;
2146  for (auto &DR : F->second)
2147  if (DR.contains(FIR))
2148  return true;
2149  return false;
2150  };
2151 
2152  for (Register Reg : RC->getRawAllocationOrder(MF)) {
2153  bool Dead = true;
2154  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
2155  if (isDead(R.Reg))
2156  continue;
2157  Dead = false;
2158  break;
2159  }
2160  if (Dead)
2161  return Reg;
2162  }
2163  return 0;
2164 }
2165 
2166 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
2167  SmallVectorImpl<Register> &VRegs) const {
2168  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2169  auto &HII = *HST.getInstrInfo();
2170  auto &HRI = *HST.getRegisterInfo();
2171  auto &MRI = MF.getRegInfo();
2172  HexagonBlockRanges HBR(MF);
2173 
2174  using BlockIndexMap =
2175  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
2176  using BlockRangeMap =
2177  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
2178  using IndexType = HexagonBlockRanges::IndexType;
2179 
2180  struct SlotInfo {
2181  BlockRangeMap Map;
2182  unsigned Size = 0;
2183  const TargetRegisterClass *RC = nullptr;
2184 
2185  SlotInfo() = default;
2186  };
2187 
2188  BlockIndexMap BlockIndexes;
2189  SmallSet<int,4> BadFIs;
2190  std::map<int,SlotInfo> FIRangeMap;
2191 
2192  // Accumulate register classes: get a common class for a pre-existing
2193  // class HaveRC and a new class NewRC. Return nullptr if a common class
2194  // cannot be found, otherwise return the resulting class. If HaveRC is
2195  // nullptr, assume that it is still unset.
2196  auto getCommonRC =
2197  [](const TargetRegisterClass *HaveRC,
2198  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2199  if (HaveRC == nullptr || HaveRC == NewRC)
2200  return NewRC;
2201  // Different classes, both non-null. Pick the more general one.
2202  if (HaveRC->hasSubClassEq(NewRC))
2203  return HaveRC;
2204  if (NewRC->hasSubClassEq(HaveRC))
2205  return NewRC;
2206  return nullptr;
2207  };
2208 
2209  // Scan all blocks in the function. Check all occurrences of frame indexes,
2210  // and collect relevant information.
2211  for (auto &B : MF) {
2212  std::map<int,IndexType> LastStore, LastLoad;
2213  // Emplace appears not to be supported in gcc 4.7.2-4.
2214  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2215  auto P = BlockIndexes.insert(
2216  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2217  auto &IndexMap = P.first->second;
2218  LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2219  << IndexMap << '\n');
2220 
2221  for (auto &In : B) {
2222  int LFI, SFI;
2223  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2224  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2225  if (Load && Store) {
2226  // If it's both a load and a store, then we won't handle it.
2227  BadFIs.insert(LFI);
2228  BadFIs.insert(SFI);
2229  continue;
2230  }
2231  // Check for register classes of the register used as the source for
2232  // the store, and the register used as the destination for the load.
2233  // Also, only accept base+imm_offset addressing modes. Other addressing
2234  // modes can have side-effects (post-increments, etc.). For stack
2235  // slots they are very unlikely, so there is not much loss due to
2236  // this restriction.
2237  if (Load || Store) {
2238  int TFI = Load ? LFI : SFI;
2239  unsigned AM = HII.getAddrMode(In);
2240  SlotInfo &SI = FIRangeMap[TFI];
2241  bool Bad = (AM != HexagonII::BaseImmOffset);
2242  if (!Bad) {
2243  // If the addressing mode is ok, check the register class.
2244  unsigned OpNum = Load ? 0 : 2;
2245  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2246  RC = getCommonRC(SI.RC, RC);
2247  if (RC == nullptr)
2248  Bad = true;
2249  else
2250  SI.RC = RC;
2251  }
2252  if (!Bad) {
2253  // Check sizes.
2254  unsigned S = HII.getMemAccessSize(In);
2255  if (SI.Size != 0 && SI.Size != S)
2256  Bad = true;
2257  else
2258  SI.Size = S;
2259  }
2260  if (!Bad) {
2261  for (auto *Mo : In.memoperands()) {
2262  if (!Mo->isVolatile() && !Mo->isAtomic())
2263  continue;
2264  Bad = true;
2265  break;
2266  }
2267  }
2268  if (Bad)
2269  BadFIs.insert(TFI);
2270  }
2271 
2272  // Locate uses of frame indices.
2273  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2274  const MachineOperand &Op = In.getOperand(i);
2275  if (!Op.isFI())
2276  continue;
2277  int FI = Op.getIndex();
2278  // Make sure that the following operand is an immediate and that
2279  // it is 0. This is the offset in the stack object.
2280  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2281  In.getOperand(i+1).getImm() != 0)
2282  BadFIs.insert(FI);
2283  if (BadFIs.count(FI))
2284  continue;
2285 
2286  IndexType Index = IndexMap.getIndex(&In);
2287  if (Load) {
2288  if (LastStore[FI] == IndexType::None)
2289  LastStore[FI] = IndexType::Entry;
2290  LastLoad[FI] = Index;
2291  } else if (Store) {
2292  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2293  if (LastStore[FI] != IndexType::None)
2294  RL.add(LastStore[FI], LastLoad[FI], false, false);
2295  else if (LastLoad[FI] != IndexType::None)
2296  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2297  LastLoad[FI] = IndexType::None;
2298  LastStore[FI] = Index;
2299  } else {
2300  BadFIs.insert(FI);
2301  }
2302  }
2303  }
2304 
2305  for (auto &I : LastLoad) {
2306  IndexType LL = I.second;
2307  if (LL == IndexType::None)
2308  continue;
2309  auto &RL = FIRangeMap[I.first].Map[&B];
2310  IndexType &LS = LastStore[I.first];
2311  if (LS != IndexType::None)
2312  RL.add(LS, LL, false, false);
2313  else
2314  RL.add(IndexType::Entry, LL, false, false);
2315  LS = IndexType::None;
2316  }
2317  for (auto &I : LastStore) {
2318  IndexType LS = I.second;
2319  if (LS == IndexType::None)
2320  continue;
2321  auto &RL = FIRangeMap[I.first].Map[&B];
2322  RL.add(LS, IndexType::None, false, false);
2323  }
2324  }
2325 
2326  LLVM_DEBUG({
2327  for (auto &P : FIRangeMap) {
2328  dbgs() << "fi#" << P.first;
2329  if (BadFIs.count(P.first))
2330  dbgs() << " (bad)";
2331  dbgs() << " RC: ";
2332  if (P.second.RC != nullptr)
2333  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2334  else
2335  dbgs() << "<null>\n";
2336  for (auto &R : P.second.Map)
2337  dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2338  << "}\n";
2339  }
2340  });
2341 
2342  // When a slot is loaded from in a block without being stored to in the
2343  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2344  // consider this slot to be live-on-exit from all blocks.
2345  SmallSet<int,4> LoxFIs;
2346 
2347  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2348 
2349  for (auto &P : FIRangeMap) {
2350  // P = pair(FI, map: BB->RangeList)
2351  if (BadFIs.count(P.first))
2352  continue;
2353  for (auto &B : MF) {
2354  auto F = P.second.Map.find(&B);
2355  // F = pair(BB, RangeList)
2356  if (F == P.second.Map.end() || F->second.empty())
2357  continue;
2358  HexagonBlockRanges::IndexRange &IR = F->second.front();
2359  if (IR.start() == IndexType::Entry)
2360  LoxFIs.insert(P.first);
2361  BlockFIMap[&B].push_back(P.first);
2362  }
2363  }
2364 
2365  LLVM_DEBUG({
2366  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2367  for (auto &P : BlockFIMap) {
2368  auto &FIs = P.second;
2369  if (FIs.empty())
2370  continue;
2371  dbgs() << " " << printMBBReference(*P.first) << ": {";
2372  for (auto I : FIs) {
2373  dbgs() << " fi#" << I;
2374  if (LoxFIs.count(I))
2375  dbgs() << '*';
2376  }
2377  dbgs() << " }\n";
2378  }
2379  });
2380 
2381 #ifndef NDEBUG
2382  bool HasOptLimit = SpillOptMax.getPosition();
2383 #endif
2384 
2385  // eliminate loads, when all loads eliminated, eliminate all stores.
2386  for (auto &B : MF) {
2387  auto F = BlockIndexes.find(&B);
2388  assert(F != BlockIndexes.end());
2389  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2390  HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2391  HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2392  LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2394 
2395  for (auto FI : BlockFIMap[&B]) {
2396  if (BadFIs.count(FI))
2397  continue;
2398  LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2399  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2400  for (auto &Range : RL) {
2401  LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2402  if (!IndexType::isInstr(Range.start()) ||
2403  !IndexType::isInstr(Range.end()))
2404  continue;
2405  MachineInstr &SI = *IM.getInstr(Range.start());
2406  MachineInstr &EI = *IM.getInstr(Range.end());
2407  assert(SI.mayStore() && "Unexpected start instruction");
2408  assert(EI.mayLoad() && "Unexpected end instruction");
2409  MachineOperand &SrcOp = SI.getOperand(2);
2410 
2412  SrcOp.getSubReg() };
2413  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2414  // The this-> is needed to unconfuse MSVC.
2415  Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2416  LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2417  << '\n');
2418  if (FoundR == 0)
2419  continue;
2420 #ifndef NDEBUG
2421  if (HasOptLimit) {
2422  if (SpillOptCount >= SpillOptMax)
2423  return;
2424  SpillOptCount++;
2425  }
2426 #endif
2427 
2428  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2429  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2430  MachineInstr *CopyIn = nullptr;
2431  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2432  const DebugLoc &DL = SI.getDebugLoc();
2433  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2434  .add(SrcOp);
2435  }
2436 
2437  ++StartIt;
2438  // Check if this is a last store and the FI is live-on-exit.
2439  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2440  // Update store's source register.
2441  if (unsigned SR = SrcOp.getSubReg())
2442  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2443  else
2444  SrcOp.setReg(FoundR);
2445  SrcOp.setSubReg(0);
2446  // We are keeping this register live.
2447  SrcOp.setIsKill(false);
2448  } else {
2449  B.erase(&SI);
2450  IM.replaceInstr(&SI, CopyIn);
2451  }
2452 
2453  auto EndIt = std::next(EI.getIterator());
2454  for (auto It = StartIt; It != EndIt; It = NextIt) {
2455  MachineInstr &MI = *It;
2456  NextIt = std::next(It);
2457  int TFI;
2458  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2459  continue;
2460  Register DstR = MI.getOperand(0).getReg();
2461  assert(MI.getOperand(0).getSubReg() == 0);
2462  MachineInstr *CopyOut = nullptr;
2463  if (DstR != FoundR) {
2464  DebugLoc DL = MI.getDebugLoc();
2465  unsigned MemSize = HII.getMemAccessSize(MI);
2466  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2467  unsigned CopyOpc = TargetOpcode::COPY;
2468  if (HII.isSignExtendingLoad(MI))
2469  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2470  else if (HII.isZeroExtendingLoad(MI))
2471  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2472  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2473  .addReg(FoundR, getKillRegState(&MI == &EI));
2474  }
2475  IM.replaceInstr(&MI, CopyOut);
2476  B.erase(It);
2477  }
2478 
2479  // Update the dead map.
2480  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2481  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2482  DM[RR].subtract(Range);
2483  } // for Range in range list
2484  }
2485  }
2486 }
2487 
2488 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2489  const HexagonInstrInfo &HII, Register SP, unsigned CF) const {
2490  MachineBasicBlock &MB = *AI->getParent();
2491  DebugLoc DL = AI->getDebugLoc();
2492  unsigned A = AI->getOperand(2).getImm();
2493 
2494  // Have
2495  // Rd = alloca Rs, #A
2496  //
2497  // If Rs and Rd are different registers, use this sequence:
2498  // Rd = sub(r29, Rs)
2499  // r29 = sub(r29, Rs)
2500  // Rd = and(Rd, #-A) ; if necessary
2501  // r29 = and(r29, #-A) ; if necessary
2502  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2503  // otherwise, do
2504  // Rd = sub(r29, Rs)
2505  // Rd = and(Rd, #-A) ; if necessary
2506  // r29 = Rd
2507  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2508 
2509  MachineOperand &RdOp = AI->getOperand(0);
2510  MachineOperand &RsOp = AI->getOperand(1);
2511  Register Rd = RdOp.getReg(), Rs = RsOp.getReg();
2512 
2513  // Rd = sub(r29, Rs)
2514  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2515  .addReg(SP)
2516  .addReg(Rs);
2517  if (Rs != Rd) {
2518  // r29 = sub(r29, Rs)
2519  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2520  .addReg(SP)
2521  .addReg(Rs);
2522  }
2523  if (A > 8) {
2524  // Rd = and(Rd, #-A)
2525  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2526  .addReg(Rd)
2527  .addImm(-int64_t(A));
2528  if (Rs != Rd)
2529  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2530  .addReg(SP)
2531  .addImm(-int64_t(A));
2532  }
2533  if (Rs == Rd) {
2534  // r29 = Rd
2535  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2536  .addReg(Rd);
2537  }
2538  if (CF > 0) {
2539  // Rd = add(Rd, #CF)
2540  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2541  .addReg(Rd)
2542  .addImm(CF);
2543  }
2544 }
2545 
2547  const MachineFrameInfo &MFI = MF.getFrameInfo();
2548  if (!MFI.hasVarSizedObjects())
2549  return false;
2550  // Do not check for max stack object alignment here, because the stack
2551  // may not be complete yet. Assume that we will need PS_aligna if there
2552  // are variable-sized objects.
2553  return true;
2554 }
2555 
2557  const MachineFunction &MF) const {
2558  for (auto &B : MF)
2559  for (auto &I : B)
2560  if (I.getOpcode() == Hexagon::PS_aligna)
2561  return &I;
2562  return nullptr;
2563 }
2564 
2565 /// Adds all callee-saved registers as implicit uses or defs to the
2566 /// instruction.
2567 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2568  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2569  // Add the callee-saved registers as implicit uses.
2570  for (auto &R : CSI)
2571  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2572 }
2573 
2574 /// Determine whether the callee-saved register saves and restores should
2575 /// be generated via inline code. If this function returns "true", inline
2576 /// code will be generated. If this function returns "false", additional
2577 /// checks are performed, which may still lead to the inline code.
2578 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2579  const CSIVect &CSI) const {
2581  return true;
2583  return true;
2584  if (!hasFP(MF))
2585  return true;
2586  if (!isOptSize(MF) && !isMinSize(MF))
2588  return true;
2589 
2590  // Check if CSI only has double registers, and if the registers form
2591  // a contiguous block starting from D8.
2592  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2593  for (const CalleeSavedInfo &I : CSI) {
2594  Register R = I.getReg();
2595  if (!Hexagon::DoubleRegsRegClass.contains(R))
2596  return true;
2597  Regs[R] = true;
2598  }
2599  int F = Regs.find_first();
2600  if (F != Hexagon::D8)
2601  return true;
2602  while (F >= 0) {
2603  int N = Regs.find_next(F);
2604  if (N >= 0 && N != F+1)
2605  return true;
2606  F = N;
2607  }
2608 
2609  return false;
2610 }
2611 
2612 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2613  const CSIVect &CSI) const {
2614  if (shouldInlineCSR(MF, CSI))
2615  return false;
2616  unsigned NumCSI = CSI.size();
2617  if (NumCSI <= 1)
2618  return false;
2619 
2620  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2622  return Threshold < NumCSI;
2623 }
2624 
2625 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2626  const CSIVect &CSI) const {
2627  if (shouldInlineCSR(MF, CSI))
2628  return false;
2629  // The restore functions do a bit more than just restoring registers.
2630  // The non-returning versions will go back directly to the caller's
2631  // caller, others will clean up the stack frame in preparation for
2632  // a tail call. Using them can still save code size even if only one
2633  // register is getting restores. Make the decision based on -Oz:
2634  // using -Os will use inline restore for a single register.
2635  if (isMinSize(MF))
2636  return true;
2637  unsigned NumCSI = CSI.size();
2638  if (NumCSI <= 1)
2639  return false;
2640 
2641  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2643  return Threshold < NumCSI;
2644 }
2645 
2646 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2647  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2648  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2649  // A fairly simplistic guess as to whether a potential load/store to a
2650  // stack location could require an extra register.
2651  if (HST.useHVXOps() && StackSize > 256)
2652  return true;
2653 
2654  // Check if the function has store-immediate instructions that access
2655  // the stack. Since the offset field is not extendable, if the stack
2656  // size exceeds the offset limit (6 bits, shifted), the stores will
2657  // require a new base register.
2658  bool HasImmStack = false;
2659  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2660 
2661  for (const MachineBasicBlock &B : MF) {
2662  for (const MachineInstr &MI : B) {
2663  unsigned LS = 0;
2664  switch (MI.getOpcode()) {
2665  case Hexagon::S4_storeirit_io:
2666  case Hexagon::S4_storeirif_io:
2667  case Hexagon::S4_storeiri_io:
2668  ++LS;
2669  [[fallthrough]];
2670  case Hexagon::S4_storeirht_io:
2671  case Hexagon::S4_storeirhf_io:
2672  case Hexagon::S4_storeirh_io:
2673  ++LS;
2674  [[fallthrough]];
2675  case Hexagon::S4_storeirbt_io:
2676  case Hexagon::S4_storeirbf_io:
2677  case Hexagon::S4_storeirb_io:
2678  if (MI.getOperand(0).isFI())
2679  HasImmStack = true;
2680  MinLS = std::min(MinLS, LS);
2681  break;
2682  }
2683  }
2684  }
2685 
2686  if (HasImmStack)
2687  return !isUInt<6>(StackSize >> MinLS);
2688 
2689  return false;
2690 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
llvm::MachineDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
Definition: MachineDominators.h:160
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
CmpMode::FP
@ FP
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:74
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:587
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:143
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:639
getMax32BitSubRegister
static Register getMax32BitSubRegister(Register Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
Definition: HexagonFrameLowering.cpp:249
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
T
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
DM
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1056
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:117
llvm::HexagonFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: HexagonFrameLowering.cpp:1264
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:26
ErrorHandling.h
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::HexagonBlockRanges::IndexRange
Definition: HexagonBlockRanges.h:81
RPO
rpo function Deduce function attributes in RPO
Definition: FunctionAttrs.cpp:1903
dump_registers
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
Definition: HexagonFrameLowering.cpp:1549
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:799
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1388
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
EnableStackOVFSanitizer
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false))
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
DenseMap.h
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:334
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
llvm::MachineFrameInfo::isObjectPreAllocated
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
Definition: MachineFrameInfo.h:463
llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: HexagonFrameLowering.cpp:1559
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:127
llvm::MachineFrameInfo::setMaxCallFrameSize
void setMaxCallFrameSize(unsigned S)
Definition: MachineFrameInfo.h:664
HexagonFrameLowering.h
SpillOptMax
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:114
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:285
llvm::HexagonRegisterInfo::isEHReturnCalleeSaveReg
bool isEHReturnCalleeSaveReg(Register Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:325
HexagonTargetMachine.h
isMinSize
static bool isMinSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:390
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineDominators.cpp:54
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:265
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
MachineRegisterInfo.h
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::HexagonFrameLowering::insertCFIInstructions
void insertCFIInstructions(MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:1023
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:115
CommandLine.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
SK_ToMem
@ SK_ToMem
Definition: HexagonFrameLowering.cpp:1187
R2
#define R2(n)
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
SpillOptCount
static unsigned SpillOptCount
Definition: HexagonFrameLowering.cpp:197
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::HexagonBlockRanges::RegisterRef::Reg
llvm::Register Reg
Definition: HexagonBlockRanges.h:36
llvm::msgpack::Type::Map
@ Map
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1476
isOptSize
static bool isOptSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:385
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
hasTailCall
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
Definition: HexagonFrameLowering.cpp:340
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:202
llvm::HexagonFrameLowering::enableCalleeSaveSkip
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
Definition: HexagonFrameLowering.cpp:560
getSpillFunctionFor
static const char * getSpillFunctionFor(Register MaxReg, SpillKind SpillType, bool Stkchk=false)
Definition: HexagonFrameLowering.cpp:1192
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::HexagonFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: HexagonFrameLowering.cpp:1145
llvm::HexagonBlockRanges::RegisterRef
Definition: HexagonBlockRanges.h:35
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
PseudoSourceValue.h
llvm::HexagonBlockRanges::PrintRangeMap
Definition: HexagonBlockRanges.h:152
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:196
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::HexagonFrameLowering::needsAligna
bool needsAligna(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2546
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
BitVector.h
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
needsStackFrame
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place.
Definition: HexagonFrameLowering.cpp:287
DebugLoc.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:746
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
llvm::BitVector
Definition: BitVector.h:75
getMaxCalleeSavedReg
static Register getMaxCalleeSavedReg(ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
Definition: HexagonFrameLowering.cpp:269
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
llvm::pdb::PDB_ColorItem::Path
@ Path
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonBlockRanges::RegisterRef::Sub
unsigned Sub
Definition: HexagonBlockRanges.h:37
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
findCFILocation
static std::optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
Definition: HexagonFrameLowering.cpp:993
EnableShrinkWrapping
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::desc("Enable stack frame shrink wrapping"))
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::HexagonMachineFunctionInfo::hasEHReturn
bool hasEHReturn() const
Definition: HexagonMachineFunctionInfo.h:81
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::HexagonBlockRanges::RangeList
Definition: HexagonBlockRanges.h:108
needToReserveScavengingSpillSlots
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
Definition: HexagonFrameLowering.cpp:1527
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:608
llvm::MachineInstrBundleIterator::getInstrIterator
instr_iterator getInstrIterator() const
Definition: MachineInstrBundleIterator.h:274
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:291
SpillFuncThreshold
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6))
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
DisableDeallocRet
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:285
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:419
llvm::initializeHexagonCallFrameInformationPass
void initializeHexagonCallFrameInformationPass(PassRegistry &)
llvm::HexagonBlockRanges::InstrIndexMap::replaceInstr
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: HexagonBlockRanges.cpp:206
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
EliminateFramePointer
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:956
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::HexagonBlockRanges::RangeList::add
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
Definition: HexagonBlockRanges.h:110
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:446
MCRegisterInfo.h
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:533
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
HexagonBlockRanges.h
R6
#define R6(n)
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:862
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1115
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:180
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::logicalview::LVAttributeKind::Range
@ Range
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1001
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::HexagonBlockRanges::expandToSubRegs
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Definition: HexagonBlockRanges.cpp:261
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
enableAllocFrameElim
static bool enableAllocFrameElim(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:577
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
ShrinkLimit
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::desc("Max count of stack frame shrink-wraps"))
OptimizeSpillSlots
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
SpillFuncThresholdOs
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1))
NumberScavengerSlots
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2))
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
SK_FromMemTailcall
@ SK_FromMemTailcall
Definition: HexagonFrameLowering.cpp:1189
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:601
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
getReturn
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn't any.
Definition: HexagonFrameLowering.cpp:358
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1761
hasReturn
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
Definition: HexagonFrameLowering.cpp:349
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
j
return j(j<< 16)
llvm::MachineFunction::getBlockNumbered
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
Definition: MachineFunction.h:789
llvm::HexagonFrameLowering::getCalleeSavedSpillSlots
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
Definition: HexagonFrameLowering.h:90
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::HexagonBlockRanges::RegToRangeMap
std::map< RegisterRef, RangeList > RegToRangeMap
Definition: HexagonBlockRanges.h:145
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:613
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
llvm::HexagonFrameLowering::getAlignaInstr
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2556
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:351
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
Function.h
llvm::HexagonBlockRanges::InstrIndexMap
Definition: HexagonBlockRanges.h:125
llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: HexagonFrameLowering.cpp:1493
x
TODO unsigned x
Definition: README.txt:10
llvm::HexagonBlockRanges::InstrIndexMap::getIndex
IndexType getIndex(MachineInstr *MI) const
Definition: HexagonBlockRanges.cpp:176
llvm::HexagonBlockRanges::IndexType
Definition: HexagonBlockRanges.h:47
isRestoreCall
static bool isRestoreCall(unsigned Opc)
Definition: HexagonFrameLowering.cpp:365
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:614
llvm::BitVector::find_next
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:301
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:291
llvm::MachinePostDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachinePostDominators.cpp:40
CodeGen.h
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:597
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
PostOrderIterator.h
llvm::HexagonFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: HexagonFrameLowering.cpp:2078
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::HexagonFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
Definition: HexagonFrameLowering.cpp:509
llvm::Register::isValid
bool isValid() const
Definition: Register.h:126
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:293
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:192
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
SpillKind
SpillKind
Definition: HexagonFrameLowering.cpp:1186
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::HexagonBlockRanges
Definition: HexagonBlockRanges.h:31
llvm::HexagonBlockRanges::InstrIndexMap::getInstr
MachineInstr * getInstr(IndexType Idx) const
Definition: HexagonBlockRanges.cpp:171
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
isOptNone
static bool isOptNone(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:380
HexagonMachineFunctionInfo.h
MachineOperand.h
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:571
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:129
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachinePostDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B) const
Definition: MachinePostDominators.h:77
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
RegisterScavenging.h
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
EnableSaveRestoreLong
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false))
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
SK_FromMem
@ SK_FromMem
Definition: HexagonFrameLowering.cpp:1188
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1032
TargetRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
Definition: HexagonFrameLowering.cpp:240
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::SrcOp
Definition: MachineIRBuilder.h:128
SetVector.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
MachineDominators.h
llvm::HexagonFrameLowering::FirstVarArgSavedReg
int FirstVarArgSavedReg
Definition: HexagonFrameLowering.h:34
SmallSet.h
LivePhysRegs.h
llvm::HexagonFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: HexagonFrameLowering.cpp:1504