LLVM  14.0.0git
HexagonFrameLowering.cpp
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1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "HexagonFrameLowering.h"
11 #include "HexagonBlockRanges.h"
12 #include "HexagonInstrInfo.h"
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <utility>
64 #include <vector>
65 
66 #define DEBUG_TYPE "hexagon-pei"
67 
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134 
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141 
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149 
150 using namespace llvm;
151 
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153  cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154 
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156  cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
158 
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160  cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
162 
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164  cl::Hidden, cl::desc("Specify Os spill func threshold"),
166 
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168  cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169  cl::init(false), cl::ZeroOrMore);
170 
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
173  cl::desc("Enable stack frame shrink wrapping"));
174 
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
177  cl::desc("Max count of stack frame shrink-wraps"));
178 
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180  cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181  cl::init(false), cl::ZeroOrMore);
182 
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184  cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
185 
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187  cl::init(true), cl::desc("Optimize spill slots"));
188 
189 #ifndef NDEBUG
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
192 static unsigned SpillOptCount = 0;
193 #endif
194 
195 namespace llvm {
196 
199 
200 } // end namespace llvm
201 
202 namespace {
203 
204  class HexagonCallFrameInformation : public MachineFunctionPass {
205  public:
206  static char ID;
207 
208  HexagonCallFrameInformation() : MachineFunctionPass(ID) {
211  }
212 
213  bool runOnMachineFunction(MachineFunction &MF) override;
214 
215  MachineFunctionProperties getRequiredProperties() const override {
218  }
219  };
220 
222 
223 } // end anonymous namespace
224 
225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226  auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227  bool NeedCFI = MF.needsFrameMoves();
228 
229  if (!NeedCFI)
230  return false;
231  HFI.insertCFIInstructions(MF);
232  return true;
233 }
234 
235 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
236  "Hexagon call frame information", false, false)
237 
239  return new HexagonCallFrameInformation();
240 }
241 
242 /// Map a register pair Reg to the subregister that has the greater "number",
243 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
244 static unsigned getMax32BitSubRegister(unsigned Reg,
245  const TargetRegisterInfo &TRI,
246  bool hireg = true) {
247  if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
248  return Reg;
249 
250  unsigned RegNo = 0;
251  for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
252  if (hireg) {
253  if (*SubRegs > RegNo)
254  RegNo = *SubRegs;
255  } else {
256  if (!RegNo || *SubRegs < RegNo)
257  RegNo = *SubRegs;
258  }
259  }
260  return RegNo;
261 }
262 
263 /// Returns the callee saved register with the largest id in the vector.
265  const TargetRegisterInfo &TRI) {
266  static_assert(Hexagon::R1 > 0,
267  "Assume physical registers are encoded as positive integers");
268  if (CSI.empty())
269  return 0;
270 
271  unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
272  for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
273  unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
274  if (Reg > Max)
275  Max = Reg;
276  }
277  return Max;
278 }
279 
280 /// Checks if the basic block contains any instruction that needs a stack
281 /// frame to be already in place.
282 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
283  const HexagonRegisterInfo &HRI) {
284  for (auto &I : MBB) {
285  const MachineInstr *MI = &I;
286  if (MI->isCall())
287  return true;
288  unsigned Opc = MI->getOpcode();
289  switch (Opc) {
290  case Hexagon::PS_alloca:
291  case Hexagon::PS_aligna:
292  return true;
293  default:
294  break;
295  }
296  // Check individual operands.
297  for (const MachineOperand &MO : MI->operands()) {
298  // While the presence of a frame index does not prove that a stack
299  // frame will be required, all frame indexes should be within alloc-
300  // frame/deallocframe. Otherwise, the code that translates a frame
301  // index into an offset would have to be aware of the placement of
302  // the frame creation/destruction instructions.
303  if (MO.isFI())
304  return true;
305  if (MO.isReg()) {
306  Register R = MO.getReg();
307  // Virtual registers will need scavenging, which then may require
308  // a stack slot.
309  if (R.isVirtual())
310  return true;
311  for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
312  if (CSR[*S])
313  return true;
314  continue;
315  }
316  if (MO.isRegMask()) {
317  // A regmask would normally have all callee-saved registers marked
318  // as preserved, so this check would not be needed, but in case of
319  // ever having other regmasks (for other calling conventions),
320  // make sure they would be processed correctly.
321  const uint32_t *BM = MO.getRegMask();
322  for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
323  unsigned R = x;
324  // If this regmask does not preserve a CSR, a frame will be needed.
325  if (!(BM[R/32] & (1u << (R%32))))
326  return true;
327  }
328  }
329  }
330  }
331  return false;
332 }
333 
334  /// Returns true if MBB has a machine instructions that indicates a tail call
335  /// in the block.
336 static bool hasTailCall(const MachineBasicBlock &MBB) {
338  if (I == MBB.end())
339  return false;
340  unsigned RetOpc = I->getOpcode();
341  return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
342 }
343 
344 /// Returns true if MBB contains an instruction that returns.
345 static bool hasReturn(const MachineBasicBlock &MBB) {
346  for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
347  if (I->isReturn())
348  return true;
349  return false;
350 }
351 
352 /// Returns the "return" instruction from this block, or nullptr if there
353 /// isn't any.
355  for (auto &I : MBB)
356  if (I.isReturn())
357  return &I;
358  return nullptr;
359 }
360 
361 static bool isRestoreCall(unsigned Opc) {
362  switch (Opc) {
363  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
364  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
365  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
366  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
367  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
368  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
369  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
370  case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
371  return true;
372  }
373  return false;
374 }
375 
376 static inline bool isOptNone(const MachineFunction &MF) {
377  return MF.getFunction().hasOptNone() ||
379 }
380 
381 static inline bool isOptSize(const MachineFunction &MF) {
382  const Function &F = MF.getFunction();
383  return F.hasOptSize() && !F.hasMinSize();
384 }
385 
386 static inline bool isMinSize(const MachineFunction &MF) {
387  return MF.getFunction().hasMinSize();
388 }
389 
390 /// Implements shrink-wrapping of the stack frame. By default, stack frame
391 /// is created in the function entry block, and is cleaned up in every block
392 /// that returns. This function finds alternate blocks: one for the frame
393 /// setup (prolog) and one for the cleanup (epilog).
394 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
395  MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
396  static unsigned ShrinkCounter = 0;
397 
399  MF.getFunction().isVarArg())
400  return;
401  if (ShrinkLimit.getPosition()) {
402  if (ShrinkCounter >= ShrinkLimit)
403  return;
404  ShrinkCounter++;
405  }
406 
407  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
408 
410  MDT.runOnMachineFunction(MF);
412  MPT.runOnMachineFunction(MF);
413 
414  using UnsignedMap = DenseMap<unsigned, unsigned>;
416 
417  UnsignedMap RPO;
418  RPOTType RPOT(&MF);
419  unsigned RPON = 0;
420  for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
421  RPO[(*I)->getNumber()] = RPON++;
422 
423  // Don't process functions that have loops, at least for now. Placement
424  // of prolog and epilog must take loop structure into account. For simpli-
425  // city don't do it right now.
426  for (auto &I : MF) {
427  unsigned BN = RPO[I.getNumber()];
428  for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
429  // If found a back-edge, return.
430  if (RPO[(*SI)->getNumber()] <= BN)
431  return;
432  }
433  }
434 
435  // Collect the set of blocks that need a stack frame to execute. Scan
436  // each block for uses/defs of callee-saved registers, calls, etc.
438  BitVector CSR(Hexagon::NUM_TARGET_REGS);
439  for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
440  for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
441  CSR[*S] = true;
442 
443  for (auto &I : MF)
444  if (needsStackFrame(I, CSR, HRI))
445  SFBlocks.push_back(&I);
446 
447  LLVM_DEBUG({
448  dbgs() << "Blocks needing SF: {";
449  for (auto &B : SFBlocks)
450  dbgs() << " " << printMBBReference(*B);
451  dbgs() << " }\n";
452  });
453  // No frame needed?
454  if (SFBlocks.empty())
455  return;
456 
457  // Pick a common dominator and a common post-dominator.
458  MachineBasicBlock *DomB = SFBlocks[0];
459  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
460  DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
461  if (!DomB)
462  break;
463  }
464  MachineBasicBlock *PDomB = SFBlocks[0];
465  for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
466  PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
467  if (!PDomB)
468  break;
469  }
470  LLVM_DEBUG({
471  dbgs() << "Computed dom block: ";
472  if (DomB)
473  dbgs() << printMBBReference(*DomB);
474  else
475  dbgs() << "<null>";
476  dbgs() << ", computed pdom block: ";
477  if (PDomB)
478  dbgs() << printMBBReference(*PDomB);
479  else
480  dbgs() << "<null>";
481  dbgs() << "\n";
482  });
483  if (!DomB || !PDomB)
484  return;
485 
486  // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
487  if (!MDT.dominates(DomB, PDomB)) {
488  LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
489  return;
490  }
491  if (!MPT.dominates(PDomB, DomB)) {
492  LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
493  return;
494  }
495 
496  // Finally, everything seems right.
497  PrologB = DomB;
498  EpilogB = PDomB;
499 }
500 
501 /// Perform most of the PEI work here:
502 /// - saving/restoring of the callee-saved registers,
503 /// - stack frame creation and destruction.
504 /// Normally, this work is distributed among various functions, but doing it
505 /// in one place allows shrink-wrapping of the stack frame.
507  MachineBasicBlock &MBB) const {
508  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
509 
510  MachineFrameInfo &MFI = MF.getFrameInfo();
511  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
512 
513  MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
515  findShrunkPrologEpilog(MF, PrologB, EpilogB);
516 
517  bool PrologueStubs = false;
518  insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
519  insertPrologueInBlock(*PrologB, PrologueStubs);
520  updateEntryPaths(MF, *PrologB);
521 
522  if (EpilogB) {
523  insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
524  insertEpilogueInBlock(*EpilogB);
525  } else {
526  for (auto &B : MF)
527  if (B.isReturnBlock())
528  insertCSRRestoresInBlock(B, CSI, HRI);
529 
530  for (auto &B : MF)
531  if (B.isReturnBlock())
532  insertEpilogueInBlock(B);
533 
534  for (auto &B : MF) {
535  if (B.empty())
536  continue;
537  MachineInstr *RetI = getReturn(B);
538  if (!RetI || isRestoreCall(RetI->getOpcode()))
539  continue;
540  for (auto &R : CSI)
541  RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
542  }
543  }
544 
545  if (EpilogB) {
546  // If there is an epilog block, it may not have a return instruction.
547  // In such case, we need to add the callee-saved registers as live-ins
548  // in all blocks on all paths from the epilog to any return block.
549  unsigned MaxBN = MF.getNumBlockIDs();
550  BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
551  updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
552  }
553 }
554 
555 /// Returns true if the target can safely skip saving callee-saved registers
556 /// for noreturn nounwind functions.
558  const MachineFunction &MF) const {
559  const auto &F = MF.getFunction();
560  assert(F.hasFnAttribute(Attribute::NoReturn) &&
561  F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
562  !F.getFunction().hasFnAttribute(Attribute::UWTable));
563  (void)F;
564 
565  // No need to save callee saved registers if the function does not return.
566  return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
567 }
568 
569 // Helper function used to determine when to eliminate the stack frame for
570 // functions marked as noreturn and when the noreturn-stack-elim options are
571 // specified. When both these conditions are true, then a FP may not be needed
572 // if the function makes a call. It is very similar to enableCalleeSaveSkip,
573 // but it used to check if the allocframe can be eliminated as well.
574 static bool enableAllocFrameElim(const MachineFunction &MF) {
575  const auto &F = MF.getFunction();
576  const auto &MFI = MF.getFrameInfo();
577  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
578  assert(!MFI.hasVarSizedObjects() &&
579  !HST.getRegisterInfo()->hasStackRealignment(MF));
580  return F.hasFnAttribute(Attribute::NoReturn) &&
581  F.hasFnAttribute(Attribute::NoUnwind) &&
582  !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&
583  MFI.getStackSize() == 0;
584 }
585 
586 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
587  bool PrologueStubs) const {
588  MachineFunction &MF = *MBB.getParent();
589  MachineFrameInfo &MFI = MF.getFrameInfo();
590  auto &HST = MF.getSubtarget<HexagonSubtarget>();
591  auto &HII = *HST.getInstrInfo();
592  auto &HRI = *HST.getRegisterInfo();
593 
594  Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
595 
596  // Calculate the total stack frame size.
597  // Get the number of bytes to allocate from the FrameInfo.
598  unsigned FrameSize = MFI.getStackSize();
599  // Round up the max call frame size to the max alignment on the stack.
600  unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
601  MFI.setMaxCallFrameSize(MaxCFA);
602 
603  FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
604  MFI.setStackSize(FrameSize);
605 
606  bool AlignStack = (MaxAlign > getStackAlign());
607 
608  // Get the number of bytes to allocate from the FrameInfo.
609  unsigned NumBytes = MFI.getStackSize();
610  unsigned SP = HRI.getStackRegister();
611  unsigned MaxCF = MFI.getMaxCallFrameSize();
613 
615  for (auto &MBB : MF)
616  for (auto &MI : MBB)
617  if (MI.getOpcode() == Hexagon::PS_alloca)
618  AdjustRegs.push_back(&MI);
619 
620  for (auto MI : AdjustRegs) {
621  assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
622  expandAlloca(MI, HII, SP, MaxCF);
623  MI->eraseFromParent();
624  }
625 
626  DebugLoc dl = MBB.findDebugLoc(InsertPt);
627 
628  if (MF.getFunction().isVarArg() &&
629  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
630  // Calculate the size of register saved area.
631  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
632  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)
633  ? NumVarArgRegs * 4
634  : NumVarArgRegs * 4 + 4;
635  if (RegisterSavedAreaSizePlusPadding > 0) {
636  // Decrement the stack pointer by size of register saved area plus
637  // padding if any.
638  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
639  .addReg(SP)
640  .addImm(-RegisterSavedAreaSizePlusPadding)
642 
643  int NumBytes = 0;
644  // Copy all the named arguments below register saved area.
645  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
646  for (int i = HMFI.getFirstNamedArgFrameIndex(),
647  e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {
648  uint64_t ObjSize = MFI.getObjectSize(i);
649  Align ObjAlign = MFI.getObjectAlign(i);
650 
651  // Determine the kind of load/store that should be used.
652  unsigned LDOpc, STOpc;
653  uint64_t OpcodeChecker = ObjAlign.value();
654 
655  // Handle cases where alignment of an object is > its size.
656  if (ObjAlign > ObjSize) {
657  if (ObjSize <= 1)
658  OpcodeChecker = 1;
659  else if (ObjSize <= 2)
660  OpcodeChecker = 2;
661  else if (ObjSize <= 4)
662  OpcodeChecker = 4;
663  else if (ObjSize > 4)
664  OpcodeChecker = 8;
665  }
666 
667  switch (OpcodeChecker) {
668  case 1:
669  LDOpc = Hexagon::L2_loadrb_io;
670  STOpc = Hexagon::S2_storerb_io;
671  break;
672  case 2:
673  LDOpc = Hexagon::L2_loadrh_io;
674  STOpc = Hexagon::S2_storerh_io;
675  break;
676  case 4:
677  LDOpc = Hexagon::L2_loadri_io;
678  STOpc = Hexagon::S2_storeri_io;
679  break;
680  case 8:
681  default:
682  LDOpc = Hexagon::L2_loadrd_io;
683  STOpc = Hexagon::S2_storerd_io;
684  break;
685  }
686 
687  unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
688  : Hexagon::R6;
689  int LoadStoreCount = ObjSize / OpcodeChecker;
690 
691  if (ObjSize % OpcodeChecker)
692  ++LoadStoreCount;
693 
694  // Get the start location of the load. NumBytes is basically the
695  // offset from the stack pointer of previous function, which would be
696  // the caller in this case, as this function has variable argument
697  // list.
698  if (NumBytes != 0)
699  NumBytes = alignTo(NumBytes, ObjAlign);
700 
701  int Count = 0;
702  while (Count < LoadStoreCount) {
703  // Load the value of the named argument on stack.
704  BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
705  .addReg(SP)
706  .addImm(RegisterSavedAreaSizePlusPadding +
707  ObjAlign.value() * Count + NumBytes)
709 
710  // Store it below the register saved area plus padding.
711  BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
712  .addReg(SP)
713  .addImm(ObjAlign.value() * Count + NumBytes)
714  .addReg(RegUsed)
716 
717  Count++;
718  }
719  NumBytes += MFI.getObjectSize(i);
720  }
721 
722  // Make NumBytes 8 byte aligned
723  NumBytes = alignTo(NumBytes, 8);
724 
725  // If the number of registers having variable arguments is odd,
726  // leave 4 bytes of padding to get to the location where first
727  // variable argument which was passed through register was copied.
728  NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;
729 
730  for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {
731  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
732  .addReg(SP)
733  .addImm(NumBytes + 4 * i)
734  .addReg(Hexagon::R0 + j)
736  }
737  }
738  }
739 
740  if (hasFP(MF)) {
741  insertAllocframe(MBB, InsertPt, NumBytes);
742  if (AlignStack) {
743  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
744  .addReg(SP)
745  .addImm(-int64_t(MaxAlign.value()));
746  }
747  // If the stack-checking is enabled, and we spilled the callee-saved
748  // registers inline (i.e. did not use a spill function), then call
749  // the stack checker directly.
750  if (EnableStackOVFSanitizer && !PrologueStubs)
751  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
752  .addExternalSymbol("__runtime_stack_check");
753  } else if (NumBytes > 0) {
754  assert(alignTo(NumBytes, 8) == NumBytes);
755  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
756  .addReg(SP)
757  .addImm(-int(NumBytes));
758  }
759 }
760 
761 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
762  MachineFunction &MF = *MBB.getParent();
763  auto &HST = MF.getSubtarget<HexagonSubtarget>();
764  auto &HII = *HST.getInstrInfo();
765  auto &HRI = *HST.getRegisterInfo();
766  unsigned SP = HRI.getStackRegister();
767 
769  DebugLoc dl = MBB.findDebugLoc(InsertPt);
770 
771  if (!hasFP(MF)) {
772  MachineFrameInfo &MFI = MF.getFrameInfo();
773  unsigned NumBytes = MFI.getStackSize();
774  if (MF.getFunction().isVarArg() &&
775  MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
776  // On Hexagon Linux, deallocate the stack for the register saved area.
777  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
778  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
779  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
780  NumBytes += RegisterSavedAreaSizePlusPadding;
781  }
782  if (NumBytes) {
783  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
784  .addReg(SP)
785  .addImm(NumBytes);
786  }
787  return;
788  }
789 
790  MachineInstr *RetI = getReturn(MBB);
791  unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
792 
793  // Handle EH_RETURN.
794  if (RetOpc == Hexagon::EH_RETURN_JMPR) {
795  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
796  .addDef(Hexagon::D15)
797  .addReg(Hexagon::R30);
798  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
799  .addReg(SP)
800  .addReg(Hexagon::R28);
801  return;
802  }
803 
804  // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
805  // frame instruction if we encounter it.
806  if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
807  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
808  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
809  RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
810  MachineBasicBlock::iterator It = RetI;
811  ++It;
812  // Delete all instructions after the RESTORE (except labels).
813  while (It != MBB.end()) {
814  if (!It->isLabel())
815  It = MBB.erase(It);
816  else
817  ++It;
818  }
819  return;
820  }
821 
822  // It is possible that the restoring code is a call to a library function.
823  // All of the restore* functions include "deallocframe", so we need to make
824  // sure that we don't add an extra one.
825  bool NeedsDeallocframe = true;
826  if (!MBB.empty() && InsertPt != MBB.begin()) {
827  MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
828  unsigned COpc = PrevIt->getOpcode();
829  if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
830  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
831  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
832  COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
833  COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
834  NeedsDeallocframe = false;
835  }
836 
838  !MF.getFunction().isVarArg()) {
839  if (!NeedsDeallocframe)
840  return;
841  // If the returning instruction is PS_jmpret, replace it with
842  // dealloc_return, otherwise just add deallocframe. The function
843  // could be returning via a tail call.
844  if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
845  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
846  .addDef(Hexagon::D15)
847  .addReg(Hexagon::R30);
848  return;
849  }
850  unsigned NewOpc = Hexagon::L4_return;
851  MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
852  .addDef(Hexagon::D15)
853  .addReg(Hexagon::R30);
854  // Transfer the function live-out registers.
855  NewI->copyImplicitOps(MF, *RetI);
856  MBB.erase(RetI);
857  } else {
858  // L2_deallocframe instruction after it.
859  // Calculate the size of register saved area.
860  int NumVarArgRegs = 6 - FirstVarArgSavedReg;
861  int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
862  (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
863 
866  : std::prev(Term);
867  if (I == MBB.end() ||
868  (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
869  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
870  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
871  I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
872  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
873  .addDef(Hexagon::D15)
874  .addReg(Hexagon::R30);
875  if (RegisterSavedAreaSizePlusPadding != 0)
876  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
877  .addReg(SP)
878  .addImm(RegisterSavedAreaSizePlusPadding);
879  }
880 }
881 
882 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
883  MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
884  MachineFunction &MF = *MBB.getParent();
885  auto &HST = MF.getSubtarget<HexagonSubtarget>();
886  auto &HII = *HST.getInstrInfo();
887  auto &HRI = *HST.getRegisterInfo();
888 
889  // Check for overflow.
890  // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
891  const unsigned int ALLOCFRAME_MAX = 16384;
892 
893  // Create a dummy memory operand to avoid allocframe from being treated as
894  // a volatile memory reference.
897 
898  DebugLoc dl = MBB.findDebugLoc(InsertPt);
899  unsigned SP = HRI.getStackRegister();
900 
901  if (NumBytes >= ALLOCFRAME_MAX) {
902  // Emit allocframe(#0).
903  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
904  .addDef(SP)
905  .addReg(SP)
906  .addImm(0)
907  .addMemOperand(MMO);
908 
909  // Subtract the size from the stack pointer.
910  unsigned SP = HRI.getStackRegister();
911  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
912  .addReg(SP)
913  .addImm(-int(NumBytes));
914  } else {
915  BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
916  .addDef(SP)
917  .addReg(SP)
918  .addImm(NumBytes)
919  .addMemOperand(MMO);
920  }
921 }
922 
923 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
924  MachineBasicBlock &SaveB) const {
925  SetVector<unsigned> Worklist;
926 
927  MachineBasicBlock &EntryB = MF.front();
928  Worklist.insert(EntryB.getNumber());
929 
930  unsigned SaveN = SaveB.getNumber();
931  auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
932 
933  for (unsigned i = 0; i < Worklist.size(); ++i) {
934  unsigned BN = Worklist[i];
936  for (auto &R : CSI)
937  if (!MBB.isLiveIn(R.getReg()))
938  MBB.addLiveIn(R.getReg());
939  if (BN != SaveN)
940  for (auto &SB : MBB.successors())
941  Worklist.insert(SB->getNumber());
942  }
943 }
944 
945 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
946  MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
947  BitVector &Path) const {
948  assert(MBB.getNumber() >= 0);
949  unsigned BN = MBB.getNumber();
950  if (Path[BN] || DoneF[BN])
951  return false;
952  if (DoneT[BN])
953  return true;
954 
955  auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
956 
957  Path[BN] = true;
958  bool ReachedExit = false;
959  for (auto &SB : MBB.successors())
960  ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
961 
962  if (!MBB.empty() && MBB.back().isReturn()) {
963  // Add implicit uses of all callee-saved registers to the reached
964  // return instructions. This is to prevent the anti-dependency breaker
965  // from renaming these registers.
966  MachineInstr &RetI = MBB.back();
967  if (!isRestoreCall(RetI.getOpcode()))
968  for (auto &R : CSI)
969  RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
970  ReachedExit = true;
971  }
972 
973  // We don't want to add unnecessary live-ins to the restore block: since
974  // the callee-saved registers are being defined in it, the entry of the
975  // restore block cannot be on the path from the definitions to any exit.
976  if (ReachedExit && &MBB != &RestoreB) {
977  for (auto &R : CSI)
978  if (!MBB.isLiveIn(R.getReg()))
979  MBB.addLiveIn(R.getReg());
980  DoneT[BN] = true;
981  }
982  if (!ReachedExit)
983  DoneF[BN] = true;
984 
985  Path[BN] = false;
986  return ReachedExit;
987 }
988 
991  // The CFI instructions need to be inserted right after allocframe.
992  // An exception to this is a situation where allocframe is bundled
993  // with a call: then the CFI instructions need to be inserted before
994  // the packet with the allocframe+call (in case the call throws an
995  // exception).
996  auto End = B.instr_end();
997 
998  for (MachineInstr &I : B) {
999  MachineBasicBlock::iterator It = I.getIterator();
1000  if (!I.isBundle()) {
1001  if (I.getOpcode() == Hexagon::S2_allocframe)
1002  return std::next(It);
1003  continue;
1004  }
1005  // I is a bundle.
1006  bool HasCall = false, HasAllocFrame = false;
1007  auto T = It.getInstrIterator();
1008  while (++T != End && T->isBundled()) {
1009  if (T->getOpcode() == Hexagon::S2_allocframe)
1010  HasAllocFrame = true;
1011  else if (T->isCall())
1012  HasCall = true;
1013  }
1014  if (HasAllocFrame)
1015  return HasCall ? It : std::next(It);
1016  }
1017  return None;
1018 }
1019 
1021  for (auto &B : MF) {
1022  auto At = findCFILocation(B);
1023  if (At.hasValue())
1024  insertCFIInstructionsAt(B, At.getValue());
1025  }
1026 }
1027 
1028 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
1029  MachineBasicBlock::iterator At) const {
1030  MachineFunction &MF = *MBB.getParent();
1031  MachineFrameInfo &MFI = MF.getFrameInfo();
1032  MachineModuleInfo &MMI = MF.getMMI();
1033  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1034  auto &HII = *HST.getInstrInfo();
1035  auto &HRI = *HST.getRegisterInfo();
1036 
1037  // If CFI instructions have debug information attached, something goes
1038  // wrong with the final assembly generation: the prolog_end is placed
1039  // in a wrong location.
1040  DebugLoc DL;
1041  const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1042 
1043  MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
1044  bool HasFP = hasFP(MF);
1045 
1046  if (HasFP) {
1047  unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
1048  unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
1049 
1050  // Define CFA via an offset from the value of FP.
1051  //
1052  // -8 -4 0 (SP)
1053  // --+----+----+---------------------
1054  // | FP | LR | increasing addresses -->
1055  // --+----+----+---------------------
1056  // | +-- Old SP (before allocframe)
1057  // +-- New FP (after allocframe)
1058  //
1059  // MCCFIInstruction::cfiDefCfa adds the offset from the register.
1060  // MCCFIInstruction::createOffset takes the offset without sign change.
1061  auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);
1062  BuildMI(MBB, At, DL, CFID)
1063  .addCFIIndex(MF.addFrameInst(DefCfa));
1064  // R31 (return addr) = CFA - 4
1065  auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
1066  BuildMI(MBB, At, DL, CFID)
1067  .addCFIIndex(MF.addFrameInst(OffR31));
1068  // R30 (frame ptr) = CFA - 8
1069  auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
1070  BuildMI(MBB, At, DL, CFID)
1071  .addCFIIndex(MF.addFrameInst(OffR30));
1072  }
1073 
1074  static unsigned int RegsToMove[] = {
1075  Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1076  Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1077  Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1078  Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1079  Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1080  Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1081  Hexagon::NoRegister
1082  };
1083 
1084  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1085 
1086  for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1087  unsigned Reg = RegsToMove[i];
1088  auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
1089  return C.getReg() == Reg;
1090  };
1091  auto F = find_if(CSI, IfR);
1092  if (F == CSI.end())
1093  continue;
1094 
1095  int64_t Offset;
1096  if (HasFP) {
1097  // If the function has a frame pointer (i.e. has an allocframe),
1098  // then the CFA has been defined in terms of FP. Any offsets in
1099  // the following CFI instructions have to be defined relative
1100  // to FP, which points to the bottom of the stack frame.
1101  // The function getFrameIndexReference can still choose to use SP
1102  // for the offset calculation, so we cannot simply call it here.
1103  // Instead, get the offset (relative to the FP) directly.
1104  Offset = MFI.getObjectOffset(F->getFrameIdx());
1105  } else {
1106  Register FrameReg;
1107  Offset =
1108  getFrameIndexReference(MF, F->getFrameIdx(), FrameReg).getFixed();
1109  }
1110  // Subtract 8 to make room for R30 and R31, which are added above.
1111  Offset -= 8;
1112 
1113  if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1114  unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
1115  auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
1116  Offset);
1117  BuildMI(MBB, At, DL, CFID)
1118  .addCFIIndex(MF.addFrameInst(OffReg));
1119  } else {
1120  // Split the double regs into subregs, and generate appropriate
1121  // cfi_offsets.
1122  // The only reason, we are split double regs is, llvm-mc does not
1123  // understand paired registers for cfi_offset.
1124  // Eg .cfi_offset r1:0, -64
1125 
1126  Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1127  Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1128  unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
1129  unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
1130  auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
1131  Offset+4);
1132  BuildMI(MBB, At, DL, CFID)
1133  .addCFIIndex(MF.addFrameInst(OffHi));
1134  auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
1135  Offset);
1136  BuildMI(MBB, At, DL, CFID)
1137  .addCFIIndex(MF.addFrameInst(OffLo));
1138  }
1139  }
1140 }
1141 
1143  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1144  return false;
1145 
1146  auto &MFI = MF.getFrameInfo();
1147  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1148  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1149  bool HasAlloca = MFI.hasVarSizedObjects();
1150 
1151  // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
1152  // that this shouldn't be required, but doing so now because gcc does and
1153  // gdb can't break at the start of the function without it. Will remove if
1154  // this turns out to be a gdb bug.
1155  //
1156  if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
1157  return true;
1158 
1159  // By default we want to use SP (since it's always there). FP requires
1160  // some setup (i.e. ALLOCFRAME).
1161  // Both, alloca and stack alignment modify the stack pointer by an
1162  // undetermined value, so we need to save it at the entry to the function
1163  // (i.e. use allocframe).
1164  if (HasAlloca || HasExtraAlign)
1165  return true;
1166 
1167  if (MFI.getStackSize() > 0) {
1168  // If FP-elimination is disabled, we have to use FP at this point.
1169  const TargetMachine &TM = MF.getTarget();
1170  if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
1171  return true;
1173  return true;
1174  }
1175 
1176  const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1177  if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())
1178  return true;
1179 
1180  return false;
1181 }
1182 
1187 };
1188 
1189 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
1190  bool Stkchk = false) {
1191  const char * V4SpillToMemoryFunctions[] = {
1192  "__save_r16_through_r17",
1193  "__save_r16_through_r19",
1194  "__save_r16_through_r21",
1195  "__save_r16_through_r23",
1196  "__save_r16_through_r25",
1197  "__save_r16_through_r27" };
1198 
1199  const char * V4SpillToMemoryStkchkFunctions[] = {
1200  "__save_r16_through_r17_stkchk",
1201  "__save_r16_through_r19_stkchk",
1202  "__save_r16_through_r21_stkchk",
1203  "__save_r16_through_r23_stkchk",
1204  "__save_r16_through_r25_stkchk",
1205  "__save_r16_through_r27_stkchk" };
1206 
1207  const char * V4SpillFromMemoryFunctions[] = {
1208  "__restore_r16_through_r17_and_deallocframe",
1209  "__restore_r16_through_r19_and_deallocframe",
1210  "__restore_r16_through_r21_and_deallocframe",
1211  "__restore_r16_through_r23_and_deallocframe",
1212  "__restore_r16_through_r25_and_deallocframe",
1213  "__restore_r16_through_r27_and_deallocframe" };
1214 
1215  const char * V4SpillFromMemoryTailcallFunctions[] = {
1216  "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1217  "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1218  "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1219  "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1220  "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1221  "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1222  };
1223 
1224  const char **SpillFunc = nullptr;
1225 
1226  switch(SpillType) {
1227  case SK_ToMem:
1228  SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1229  : V4SpillToMemoryFunctions;
1230  break;
1231  case SK_FromMem:
1232  SpillFunc = V4SpillFromMemoryFunctions;
1233  break;
1234  case SK_FromMemTailcall:
1235  SpillFunc = V4SpillFromMemoryTailcallFunctions;
1236  break;
1237  }
1238  assert(SpillFunc && "Unknown spill kind");
1239 
1240  // Spill all callee-saved registers up to the highest register used.
1241  switch (MaxReg) {
1242  case Hexagon::R17:
1243  return SpillFunc[0];
1244  case Hexagon::R19:
1245  return SpillFunc[1];
1246  case Hexagon::R21:
1247  return SpillFunc[2];
1248  case Hexagon::R23:
1249  return SpillFunc[3];
1250  case Hexagon::R25:
1251  return SpillFunc[4];
1252  case Hexagon::R27:
1253  return SpillFunc[5];
1254  default:
1255  llvm_unreachable("Unhandled maximum callee save register");
1256  }
1257  return nullptr;
1258 }
1259 
1262  Register &FrameReg) const {
1263  auto &MFI = MF.getFrameInfo();
1264  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1265 
1266  int Offset = MFI.getObjectOffset(FI);
1267  bool HasAlloca = MFI.hasVarSizedObjects();
1268  bool HasExtraAlign = HRI.hasStackRealignment(MF);
1269  bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1270 
1271  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1272  unsigned FrameSize = MFI.getStackSize();
1273  Register SP = HRI.getStackRegister();
1274  Register FP = HRI.getFrameRegister();
1275  Register AP = HMFI.getStackAlignBasePhysReg();
1276  // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1277  // is true. HasExtraAlign may be set because of vector spills, without
1278  // aligned locals or aligned outgoing function arguments. Since vector
1279  // spills will ultimately be "unaligned", it is safe to use FP as the
1280  // base register.
1281  // In fact, in such a scenario the stack is actually not required to be
1282  // aligned, although it may end up being aligned anyway, since this
1283  // particular case is not easily detectable. The alignment will be
1284  // unnecessary, but not incorrect.
1285  // Unfortunately there is no quick way to verify that the above is
1286  // indeed the case (and that it's not a result of an error), so just
1287  // assume that missing AP will be replaced by FP.
1288  // (A better fix would be to rematerialize AP from FP and always align
1289  // vector spills.)
1290  if (AP == 0)
1291  AP = FP;
1292 
1293  bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1294  // Use FP at -O0, except when there are objects with extra alignment.
1295  // That additional alignment requirement may cause a pad to be inserted,
1296  // which will make it impossible to use FP to access objects located
1297  // past the pad.
1298  if (NoOpt && !HasExtraAlign)
1299  UseFP = true;
1300  if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1301  // Fixed and preallocated objects will be located before any padding
1302  // so FP must be used to access them.
1303  UseFP |= (HasAlloca || HasExtraAlign);
1304  } else {
1305  if (HasAlloca) {
1306  if (HasExtraAlign)
1307  UseAP = true;
1308  else
1309  UseFP = true;
1310  }
1311  }
1312 
1313  // If FP was picked, then there had better be FP.
1314  bool HasFP = hasFP(MF);
1315  assert((HasFP || !UseFP) && "This function must have frame pointer");
1316 
1317  // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1318  // FP/LR. If the base register is used to access an object across these
1319  // 8 bytes, then the offset will need to be adjusted by 8.
1320  //
1321  // After allocframe:
1322  // HexagonISelLowering adds 8 to ---+
1323  // the offsets of all stack-based |
1324  // arguments (*) |
1325  // |
1326  // getObjectOffset < 0 0 8 getObjectOffset >= 8
1327  // ------------------------+-----+------------------------> increasing
1328  // <local objects> |FP/LR| <input arguments> addresses
1329  // -----------------+------+-----+------------------------>
1330  // | |
1331  // SP/AP point --+ +-- FP points here (**)
1332  // somewhere on
1333  // this side of FP/LR
1334  //
1335  // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1336  // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1337 
1338  // The lowering assumes that FP/LR is present, and so the offsets of
1339  // the formal arguments start at 8. If FP/LR is not there we need to
1340  // reduce the offset by 8.
1341  if (Offset > 0 && !HasFP)
1342  Offset -= 8;
1343 
1344  if (UseFP)
1345  FrameReg = FP;
1346  else if (UseAP)
1347  FrameReg = AP;
1348  else
1349  FrameReg = SP;
1350 
1351  // Calculate the actual offset in the instruction. If there is no FP
1352  // (in other words, no allocframe), then SP will not be adjusted (i.e.
1353  // there will be no SP -= FrameSize), so the frame size should not be
1354  // added to the calculated offset.
1355  int RealOffset = Offset;
1356  if (!UseFP && !UseAP)
1357  RealOffset = FrameSize+Offset;
1358  return StackOffset::getFixed(RealOffset);
1359 }
1360 
1361 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1362  const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1363  bool &PrologueStubs) const {
1364  if (CSI.empty())
1365  return true;
1366 
1368  PrologueStubs = false;
1369  MachineFunction &MF = *MBB.getParent();
1370  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1371  auto &HII = *HST.getInstrInfo();
1372 
1373  if (useSpillFunction(MF, CSI)) {
1374  PrologueStubs = true;
1375  unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1376  bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1377  const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1378  StkOvrFlowEnabled);
1379  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1380  bool IsPIC = HTM.isPositionIndependent();
1381  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1382 
1383  // Call spill function.
1384  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1385  unsigned SpillOpc;
1386  if (StkOvrFlowEnabled) {
1387  if (LongCalls)
1388  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1389  : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1390  else
1391  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1392  : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1393  } else {
1394  if (LongCalls)
1395  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1396  : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1397  else
1398  SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1399  : Hexagon::SAVE_REGISTERS_CALL_V4;
1400  }
1401 
1402  MachineInstr *SaveRegsCall =
1403  BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1404  .addExternalSymbol(SpillFun);
1405 
1406  // Add callee-saved registers as use.
1407  addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1408  // Add live in registers.
1409  for (unsigned I = 0; I < CSI.size(); ++I)
1410  MBB.addLiveIn(CSI[I].getReg());
1411  return true;
1412  }
1413 
1414  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1415  unsigned Reg = CSI[i].getReg();
1416  // Add live in registers. We treat eh_return callee saved register r0 - r3
1417  // specially. They are not really callee saved registers as they are not
1418  // supposed to be killed.
1419  bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1420  int FI = CSI[i].getFrameIdx();
1421  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1422  HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1423  if (IsKill)
1424  MBB.addLiveIn(Reg);
1425  }
1426  return true;
1427 }
1428 
1429 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1430  const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1431  if (CSI.empty())
1432  return false;
1433 
1435  MachineFunction &MF = *MBB.getParent();
1436  auto &HST = MF.getSubtarget<HexagonSubtarget>();
1437  auto &HII = *HST.getInstrInfo();
1438 
1439  if (useRestoreFunction(MF, CSI)) {
1440  bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1441  unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1443  const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1444  auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1445  bool IsPIC = HTM.isPositionIndependent();
1446  bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1447 
1448  // Call spill function.
1449  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1450  : MBB.findDebugLoc(MBB.end());
1451  MachineInstr *DeallocCall = nullptr;
1452 
1453  if (HasTC) {
1454  unsigned RetOpc;
1455  if (LongCalls)
1456  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1457  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1458  else
1459  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1460  : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1461  DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1462  .addExternalSymbol(RestoreFn);
1463  } else {
1464  // The block has a return.
1466  assert(It->isReturn() && std::next(It) == MBB.end());
1467  unsigned RetOpc;
1468  if (LongCalls)
1469  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1470  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1471  else
1472  RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1473  : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1474  DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1475  .addExternalSymbol(RestoreFn);
1476  // Transfer the function live-out registers.
1477  DeallocCall->copyImplicitOps(MF, *It);
1478  }
1479  addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1480  return true;
1481  }
1482 
1483  for (unsigned i = 0; i < CSI.size(); ++i) {
1484  unsigned Reg = CSI[i].getReg();
1485  const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1486  int FI = CSI[i].getFrameIdx();
1487  HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1488  }
1489 
1490  return true;
1491 }
1492 
1496  MachineInstr &MI = *I;
1497  unsigned Opc = MI.getOpcode();
1498  (void)Opc; // Silence compiler warning.
1499  assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1500  "Cannot handle this call frame pseudo instruction");
1501  return MBB.erase(I);
1502 }
1503 
1505  MachineFunction &MF, RegScavenger *RS) const {
1506  // If this function has uses aligned stack and also has variable sized stack
1507  // objects, then we need to map all spill slots to fixed positions, so that
1508  // they can be accessed through FP. Otherwise they would have to be accessed
1509  // via AP, which may not be available at the particular place in the program.
1510  MachineFrameInfo &MFI = MF.getFrameInfo();
1511  bool HasAlloca = MFI.hasVarSizedObjects();
1512  bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
1513 
1514  if (!HasAlloca || !NeedsAlign)
1515  return;
1516 
1517  SmallSet<int, 4> DealignSlots;
1518  unsigned LFS = MFI.getLocalFrameSize();
1519  for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1520  if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1521  continue;
1522  unsigned S = MFI.getObjectSize(i);
1523  // Reduce the alignment to at most 8. This will require unaligned vector
1524  // stores if they happen here.
1525  Align A = std::max(MFI.getObjectAlign(i), Align(8));
1526  MFI.setObjectAlignment(i, Align(8));
1527  LFS = alignTo(LFS+S, A);
1528  MFI.mapLocalFrameObject(i, -static_cast<int64_t>(LFS));
1529  DealignSlots.insert(i);
1530  }
1531 
1532  MFI.setLocalFrameSize(LFS);
1533  Align A = MFI.getLocalFrameMaxAlign();
1534  assert(A <= 8 && "Unexpected local frame alignment");
1535  if (A == 1)
1536  MFI.setLocalFrameMaxAlign(Align(8));
1538 
1539  // Go over all MachineMemOperands in the code, and change the ones that
1540  // refer to the dealigned stack slots to reflect the new alignment.
1541  if (!DealignSlots.empty()) {
1542  for (MachineBasicBlock &BB : MF) {
1543  for (MachineInstr &MI : BB) {
1544  bool KeepOld = true;
1545  ArrayRef<MachineMemOperand*> memops = MI.memoperands();
1547  for (MachineMemOperand *MMO : memops) {
1548  auto *PV = MMO->getPseudoValue();
1549  if (auto *FS = dyn_cast_or_null<FixedStackPseudoSourceValue>(PV)) {
1550  int FI = FS->getFrameIndex();
1551  if (DealignSlots.count(FI)) {
1552  auto *NewMMO = MF.getMachineMemOperand(
1553  MMO->getPointerInfo(), MMO->getFlags(), MMO->getSize(),
1554  MFI.getObjectAlign(FI), MMO->getAAInfo(), MMO->getRanges(),
1555  MMO->getSyncScopeID(), MMO->getSuccessOrdering(),
1556  MMO->getFailureOrdering());
1557  new_memops.push_back(NewMMO);
1558  KeepOld = false;
1559  continue;
1560  }
1561  }
1562  new_memops.push_back(MMO);
1563  }
1564  if (!KeepOld)
1565  MI.setMemRefs(MF, new_memops);
1566  }
1567  }
1568  }
1569 
1570  // Set the physical aligned-stack base address register.
1571  unsigned AP = 0;
1572  if (const MachineInstr *AI = getAlignaInstr(MF))
1573  AP = AI->getOperand(0).getReg();
1574  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1575  HMFI.setStackAlignBasePhysReg(AP);
1576 }
1577 
1578 /// Returns true if there are no caller-saved registers available in class RC.
1580  const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1582 
1583  auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1584  for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1585  if (MRI.isPhysRegUsed(*AI))
1586  return true;
1587  return false;
1588  };
1589 
1590  // Check for an unused caller-saved register. Callee-saved registers
1591  // have become pristine by now.
1592  for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1593  if (!IsUsed(*P))
1594  return false;
1595 
1596  // All caller-saved registers are used.
1597  return true;
1598 }
1599 
1600 #ifndef NDEBUG
1601 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1602  dbgs() << '{';
1603  for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1604  unsigned R = x;
1605  dbgs() << ' ' << printReg(R, &TRI);
1606  }
1607  dbgs() << " }";
1608 }
1609 #endif
1610 
1612  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1613  LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1614  MachineFrameInfo &MFI = MF.getFrameInfo();
1615  BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1616 
1617  // Generate a set of unique, callee-saved registers (SRegs), where each
1618  // register in the set is maximal in terms of sub-/super-register relation,
1619  // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1620 
1621  // (1) For each callee-saved register, add that register and all of its
1622  // sub-registers to SRegs.
1623  LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1624  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1625  unsigned R = CSI[i].getReg();
1626  LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1627  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1628  SRegs[*SR] = true;
1629  }
1630  LLVM_DEBUG(dbgs() << " }\n");
1631  LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1632  dbgs() << "\n");
1633 
1634  // (2) For each reserved register, remove that register and all of its
1635  // sub- and super-registers from SRegs.
1637  for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1638  unsigned R = x;
1639  for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1640  SRegs[*SR] = false;
1641  }
1642  LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1643  dbgs() << "\n");
1644  LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1645  dbgs() << "\n");
1646 
1647  // (3) Collect all registers that have at least one sub-register in SRegs,
1648  // and also have no sub-registers that are reserved. These will be the can-
1649  // didates for saving as a whole instead of their individual sub-registers.
1650  // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1651  BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1652  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1653  unsigned R = x;
1654  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1655  TmpSup[*SR] = true;
1656  }
1657  for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1658  unsigned R = x;
1659  for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1660  if (!Reserved[*SR])
1661  continue;
1662  TmpSup[R] = false;
1663  break;
1664  }
1665  }
1666  LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1667  dbgs() << "\n");
1668 
1669  // (4) Include all super-registers found in (3) into SRegs.
1670  SRegs |= TmpSup;
1671  LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1672  dbgs() << "\n");
1673 
1674  // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1675  // remove R from SRegs.
1676  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1677  unsigned R = x;
1678  for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1679  if (!SRegs[*SR])
1680  continue;
1681  SRegs[R] = false;
1682  break;
1683  }
1684  }
1685  LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1686  dbgs() << "\n");
1687 
1688  // Now, for each register that has a fixed stack slot, create the stack
1689  // object for it.
1690  CSI.clear();
1691 
1693 
1694  unsigned NumFixed;
1695  int MinOffset = 0; // CS offsets are negative.
1696  const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1697  for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1698  if (!SRegs[S->Reg])
1699  continue;
1700  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1701  int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1702  MinOffset = std::min(MinOffset, S->Offset);
1703  CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1704  SRegs[S->Reg] = false;
1705  }
1706 
1707  // There can be some registers that don't have fixed slots. For example,
1708  // we need to store R0-R3 in functions with exception handling. For each
1709  // such register, create a non-fixed stack object.
1710  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1711  unsigned R = x;
1713  unsigned Size = TRI->getSpillSize(*RC);
1714  int Off = MinOffset - Size;
1715  Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
1716  Off &= -Alignment.value();
1717  int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1718  MinOffset = std::min(MinOffset, Off);
1719  CSI.push_back(CalleeSavedInfo(R, FI));
1720  SRegs[R] = false;
1721  }
1722 
1723  LLVM_DEBUG({
1724  dbgs() << "CS information: {";
1725  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1726  int FI = CSI[i].getFrameIdx();
1727  int Off = MFI.getObjectOffset(FI);
1728  dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1729  if (Off >= 0)
1730  dbgs() << '+';
1731  dbgs() << Off;
1732  }
1733  dbgs() << " }\n";
1734  });
1735 
1736 #ifndef NDEBUG
1737  // Verify that all registers were handled.
1738  bool MissedReg = false;
1739  for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1740  unsigned R = x;
1741  dbgs() << printReg(R, TRI) << ' ';
1742  MissedReg = true;
1743  }
1744  if (MissedReg)
1745  llvm_unreachable("...there are unhandled callee-saved registers!");
1746 #endif
1747 
1748  return true;
1749 }
1750 
1751 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1753  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1754  MachineInstr *MI = &*It;
1755  DebugLoc DL = MI->getDebugLoc();
1756  Register DstR = MI->getOperand(0).getReg();
1757  Register SrcR = MI->getOperand(1).getReg();
1758  if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1759  !Hexagon::ModRegsRegClass.contains(SrcR))
1760  return false;
1761 
1762  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1763  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1764  BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1765  .addReg(TmpR, RegState::Kill);
1766 
1767  NewRegs.push_back(TmpR);
1768  B.erase(It);
1769  return true;
1770 }
1771 
1772 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1774  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1775  MachineInstr *MI = &*It;
1776  if (!MI->getOperand(0).isFI())
1777  return false;
1778 
1779  DebugLoc DL = MI->getDebugLoc();
1780  unsigned Opc = MI->getOpcode();
1781  Register SrcR = MI->getOperand(2).getReg();
1782  bool IsKill = MI->getOperand(2).isKill();
1783  int FI = MI->getOperand(0).getIndex();
1784 
1785  // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1786  // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1787  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1788  unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1789  : Hexagon::A2_tfrcrr;
1790  BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1791  .addReg(SrcR, getKillRegState(IsKill));
1792 
1793  // S2_storeri_io FI, 0, TmpR
1794  BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1795  .addFrameIndex(FI)
1796  .addImm(0)
1797  .addReg(TmpR, RegState::Kill)
1798  .cloneMemRefs(*MI);
1799 
1800  NewRegs.push_back(TmpR);
1801  B.erase(It);
1802  return true;
1803 }
1804 
1805 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1807  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1808  MachineInstr *MI = &*It;
1809  if (!MI->getOperand(1).isFI())
1810  return false;
1811 
1812  DebugLoc DL = MI->getDebugLoc();
1813  unsigned Opc = MI->getOpcode();
1814  Register DstR = MI->getOperand(0).getReg();
1815  int FI = MI->getOperand(1).getIndex();
1816 
1817  // TmpR = L2_loadri_io FI, 0
1818  Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1819  BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1820  .addFrameIndex(FI)
1821  .addImm(0)
1822  .cloneMemRefs(*MI);
1823 
1824  // DstR = C2_tfrrp TmpR if DstR is a predicate register
1825  // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1826  unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1827  : Hexagon::A2_tfrrcr;
1828  BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1829  .addReg(TmpR, RegState::Kill);
1830 
1831  NewRegs.push_back(TmpR);
1832  B.erase(It);
1833  return true;
1834 }
1835 
1836 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1838  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1839  MachineInstr *MI = &*It;
1840  if (!MI->getOperand(0).isFI())
1841  return false;
1842 
1843  DebugLoc DL = MI->getDebugLoc();
1844  Register SrcR = MI->getOperand(2).getReg();
1845  bool IsKill = MI->getOperand(2).isKill();
1846  int FI = MI->getOperand(0).getIndex();
1847  auto *RC = &Hexagon::HvxVRRegClass;
1848 
1849  // Insert transfer to general vector register.
1850  // TmpR0 = A2_tfrsi 0x01010101
1851  // TmpR1 = V6_vandqrt Qx, TmpR0
1852  // store FI, 0, TmpR1
1853  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1854  Register TmpR1 = MRI.createVirtualRegister(RC);
1855 
1856  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1857  .addImm(0x01010101);
1858 
1859  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1860  .addReg(SrcR, getKillRegState(IsKill))
1861  .addReg(TmpR0, RegState::Kill);
1862 
1863  auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1864  HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1865  expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1866 
1867  NewRegs.push_back(TmpR0);
1868  NewRegs.push_back(TmpR1);
1869  B.erase(It);
1870  return true;
1871 }
1872 
1873 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1875  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1876  MachineInstr *MI = &*It;
1877  if (!MI->getOperand(1).isFI())
1878  return false;
1879 
1880  DebugLoc DL = MI->getDebugLoc();
1881  Register DstR = MI->getOperand(0).getReg();
1882  int FI = MI->getOperand(1).getIndex();
1883  auto *RC = &Hexagon::HvxVRRegClass;
1884 
1885  // TmpR0 = A2_tfrsi 0x01010101
1886  // TmpR1 = load FI, 0
1887  // DstR = V6_vandvrt TmpR1, TmpR0
1888  Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1889  Register TmpR1 = MRI.createVirtualRegister(RC);
1890 
1891  BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1892  .addImm(0x01010101);
1893  MachineFunction &MF = *B.getParent();
1894  auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1895  HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1896  expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1897 
1898  BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1899  .addReg(TmpR1, RegState::Kill)
1900  .addReg(TmpR0, RegState::Kill);
1901 
1902  NewRegs.push_back(TmpR0);
1903  NewRegs.push_back(TmpR1);
1904  B.erase(It);
1905  return true;
1906 }
1907 
1908 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1910  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1911  MachineFunction &MF = *B.getParent();
1912  auto &MFI = MF.getFrameInfo();
1913  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1914  MachineInstr *MI = &*It;
1915  if (!MI->getOperand(0).isFI())
1916  return false;
1917 
1918  // It is possible that the double vector being stored is only partially
1919  // defined. From the point of view of the liveness tracking, it is ok to
1920  // store it as a whole, but if we break it up we may end up storing a
1921  // register that is entirely undefined.
1922  LivePhysRegs LPR(HRI);
1923  LPR.addLiveIns(B);
1925  for (auto R = B.begin(); R != It; ++R) {
1926  Clobbers.clear();
1927  LPR.stepForward(*R, Clobbers);
1928  }
1929 
1930  DebugLoc DL = MI->getDebugLoc();
1931  Register SrcR = MI->getOperand(2).getReg();
1932  Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1933  Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1934  bool IsKill = MI->getOperand(2).isKill();
1935  int FI = MI->getOperand(0).getIndex();
1936  bool NeedsAligna = needsAligna(MF);
1937 
1938  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1939  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1940  Align HasAlign = MFI.getObjectAlign(FI);
1941  unsigned StoreOpc;
1942 
1943  auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1944  return !NeedsAligna && (NeedAlign <= HasAlign);
1945  };
1946 
1947  // Store low part.
1948  if (LPR.contains(SrcLo)) {
1949  StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1950  : Hexagon::V6_vS32Ub_ai;
1951  BuildMI(B, It, DL, HII.get(StoreOpc))
1952  .addFrameIndex(FI)
1953  .addImm(0)
1954  .addReg(SrcLo, getKillRegState(IsKill))
1955  .cloneMemRefs(*MI);
1956  }
1957 
1958  // Store high part.
1959  if (LPR.contains(SrcHi)) {
1960  StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1961  : Hexagon::V6_vS32Ub_ai;
1962  BuildMI(B, It, DL, HII.get(StoreOpc))
1963  .addFrameIndex(FI)
1964  .addImm(Size)
1965  .addReg(SrcHi, getKillRegState(IsKill))
1966  .cloneMemRefs(*MI);
1967  }
1968 
1969  B.erase(It);
1970  return true;
1971 }
1972 
1973 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1975  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1976  MachineFunction &MF = *B.getParent();
1977  auto &MFI = MF.getFrameInfo();
1978  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1979  MachineInstr *MI = &*It;
1980  if (!MI->getOperand(1).isFI())
1981  return false;
1982 
1983  DebugLoc DL = MI->getDebugLoc();
1984  Register DstR = MI->getOperand(0).getReg();
1985  Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1986  Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1987  int FI = MI->getOperand(1).getIndex();
1988  bool NeedsAligna = needsAligna(MF);
1989 
1990  unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1991  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1992  Align HasAlign = MFI.getObjectAlign(FI);
1993  unsigned LoadOpc;
1994 
1995  auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1996  return !NeedsAligna && (NeedAlign <= HasAlign);
1997  };
1998 
1999  // Load low part.
2000  LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2001  : Hexagon::V6_vL32Ub_ai;
2002  BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
2003  .addFrameIndex(FI)
2004  .addImm(0)
2005  .cloneMemRefs(*MI);
2006 
2007  // Load high part.
2008  LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2009  : Hexagon::V6_vL32Ub_ai;
2010  BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
2011  .addFrameIndex(FI)
2012  .addImm(Size)
2013  .cloneMemRefs(*MI);
2014 
2015  B.erase(It);
2016  return true;
2017 }
2018 
2019 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
2021  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2022  MachineFunction &MF = *B.getParent();
2023  auto &MFI = MF.getFrameInfo();
2024  MachineInstr *MI = &*It;
2025  if (!MI->getOperand(0).isFI())
2026  return false;
2027 
2028  bool NeedsAligna = needsAligna(MF);
2029  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2030  DebugLoc DL = MI->getDebugLoc();
2031  Register SrcR = MI->getOperand(2).getReg();
2032  bool IsKill = MI->getOperand(2).isKill();
2033  int FI = MI->getOperand(0).getIndex();
2034 
2035  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2036  Align HasAlign = MFI.getObjectAlign(FI);
2037  bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2038  unsigned StoreOpc = UseAligned ? Hexagon::V6_vS32b_ai
2039  : Hexagon::V6_vS32Ub_ai;
2040  BuildMI(B, It, DL, HII.get(StoreOpc))
2041  .addFrameIndex(FI)
2042  .addImm(0)
2043  .addReg(SrcR, getKillRegState(IsKill))
2044  .cloneMemRefs(*MI);
2045 
2046  B.erase(It);
2047  return true;
2048 }
2049 
2050 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
2052  const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2053  MachineFunction &MF = *B.getParent();
2054  auto &MFI = MF.getFrameInfo();
2055  MachineInstr *MI = &*It;
2056  if (!MI->getOperand(1).isFI())
2057  return false;
2058 
2059  bool NeedsAligna = needsAligna(MF);
2060  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2061  DebugLoc DL = MI->getDebugLoc();
2062  Register DstR = MI->getOperand(0).getReg();
2063  int FI = MI->getOperand(1).getIndex();
2064 
2065  Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2066  Align HasAlign = MFI.getObjectAlign(FI);
2067  bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2068  unsigned LoadOpc = UseAligned ? Hexagon::V6_vL32b_ai
2069  : Hexagon::V6_vL32Ub_ai;
2070  BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2071  .addFrameIndex(FI)
2072  .addImm(0)
2073  .cloneMemRefs(*MI);
2074 
2075  B.erase(It);
2076  return true;
2077 }
2078 
2079 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
2080  SmallVectorImpl<unsigned> &NewRegs) const {
2081  auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
2083  bool Changed = false;
2084 
2085  for (auto &B : MF) {
2086  // Traverse the basic block.
2088  for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
2089  MachineInstr *MI = &*I;
2090  NextI = std::next(I);
2091  unsigned Opc = MI->getOpcode();
2092 
2093  switch (Opc) {
2094  case TargetOpcode::COPY:
2095  Changed |= expandCopy(B, I, MRI, HII, NewRegs);
2096  break;
2097  case Hexagon::STriw_pred:
2098  case Hexagon::STriw_ctr:
2099  Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
2100  break;
2101  case Hexagon::LDriw_pred:
2102  case Hexagon::LDriw_ctr:
2103  Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
2104  break;
2105  case Hexagon::PS_vstorerq_ai:
2106  Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
2107  break;
2108  case Hexagon::PS_vloadrq_ai:
2109  Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
2110  break;
2111  case Hexagon::PS_vloadrw_ai:
2112  Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
2113  break;
2114  case Hexagon::PS_vstorerw_ai:
2115  Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
2116  break;
2117  }
2118  }
2119  }
2120 
2121  return Changed;
2122 }
2123 
2125  BitVector &SavedRegs,
2126  RegScavenger *RS) const {
2127  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2128 
2129  SavedRegs.resize(HRI.getNumRegs());
2130 
2131  // If we have a function containing __builtin_eh_return we want to spill and
2132  // restore all callee saved registers. Pretend that they are used.
2134  for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
2135  SavedRegs.set(*R);
2136 
2137  // Replace predicate register pseudo spill code.
2138  SmallVector<unsigned,8> NewRegs;
2139  expandSpillMacros(MF, NewRegs);
2140  if (OptimizeSpillSlots && !isOptNone(MF))
2141  optimizeSpillSlots(MF, NewRegs);
2142 
2143  // We need to reserve a spill slot if scavenging could potentially require
2144  // spilling a scavenged register.
2145  if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
2146  MachineFrameInfo &MFI = MF.getFrameInfo();
2149  // Reserve an int register in any case, because it could be used to hold
2150  // the stack offset in case it does not fit into a spill instruction.
2151  SpillRCs.insert(&Hexagon::IntRegsRegClass);
2152 
2153  for (unsigned VR : NewRegs)
2154  SpillRCs.insert(MRI.getRegClass(VR));
2155 
2156  for (auto *RC : SpillRCs) {
2157  if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
2158  continue;
2159  unsigned Num = 1;
2160  switch (RC->getID()) {
2161  case Hexagon::IntRegsRegClassID:
2162  Num = NumberScavengerSlots;
2163  break;
2164  case Hexagon::HvxQRRegClassID:
2165  Num = 2; // Vector predicate spills also need a vector register.
2166  break;
2167  }
2168  unsigned S = HRI.getSpillSize(*RC);
2169  Align A = HRI.getSpillAlign(*RC);
2170  for (unsigned i = 0; i < Num; i++) {
2171  int NewFI = MFI.CreateSpillStackObject(S, A);
2172  RS->addScavengingFrameIndex(NewFI);
2173  }
2174  }
2175  }
2176 
2177  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2178 }
2179 
2180 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
2184  const TargetRegisterClass *RC) const {
2185  auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2186  auto &MRI = MF.getRegInfo();
2187 
2188  auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
2189  auto F = DeadMap.find({Reg,0});
2190  if (F == DeadMap.end())
2191  return false;
2192  for (auto &DR : F->second)
2193  if (DR.contains(FIR))
2194  return true;
2195  return false;
2196  };
2197 
2198  for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
2199  bool Dead = true;
2200  for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
2201  if (isDead(R.Reg))
2202  continue;
2203  Dead = false;
2204  break;
2205  }
2206  if (Dead)
2207  return Reg;
2208  }
2209  return 0;
2210 }
2211 
2212 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
2213  SmallVectorImpl<unsigned> &VRegs) const {
2214  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2215  auto &HII = *HST.getInstrInfo();
2216  auto &HRI = *HST.getRegisterInfo();
2217  auto &MRI = MF.getRegInfo();
2218  HexagonBlockRanges HBR(MF);
2219 
2220  using BlockIndexMap =
2221  std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
2222  using BlockRangeMap =
2223  std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
2224  using IndexType = HexagonBlockRanges::IndexType;
2225 
2226  struct SlotInfo {
2227  BlockRangeMap Map;
2228  unsigned Size = 0;
2229  const TargetRegisterClass *RC = nullptr;
2230 
2231  SlotInfo() = default;
2232  };
2233 
2234  BlockIndexMap BlockIndexes;
2235  SmallSet<int,4> BadFIs;
2236  std::map<int,SlotInfo> FIRangeMap;
2237 
2238  // Accumulate register classes: get a common class for a pre-existing
2239  // class HaveRC and a new class NewRC. Return nullptr if a common class
2240  // cannot be found, otherwise return the resulting class. If HaveRC is
2241  // nullptr, assume that it is still unset.
2242  auto getCommonRC =
2243  [](const TargetRegisterClass *HaveRC,
2244  const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2245  if (HaveRC == nullptr || HaveRC == NewRC)
2246  return NewRC;
2247  // Different classes, both non-null. Pick the more general one.
2248  if (HaveRC->hasSubClassEq(NewRC))
2249  return HaveRC;
2250  if (NewRC->hasSubClassEq(HaveRC))
2251  return NewRC;
2252  return nullptr;
2253  };
2254 
2255  // Scan all blocks in the function. Check all occurrences of frame indexes,
2256  // and collect relevant information.
2257  for (auto &B : MF) {
2258  std::map<int,IndexType> LastStore, LastLoad;
2259  // Emplace appears not to be supported in gcc 4.7.2-4.
2260  //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2261  auto P = BlockIndexes.insert(
2262  std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2263  auto &IndexMap = P.first->second;
2264  LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2265  << IndexMap << '\n');
2266 
2267  for (auto &In : B) {
2268  int LFI, SFI;
2269  bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2270  bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2271  if (Load && Store) {
2272  // If it's both a load and a store, then we won't handle it.
2273  BadFIs.insert(LFI);
2274  BadFIs.insert(SFI);
2275  continue;
2276  }
2277  // Check for register classes of the register used as the source for
2278  // the store, and the register used as the destination for the load.
2279  // Also, only accept base+imm_offset addressing modes. Other addressing
2280  // modes can have side-effects (post-increments, etc.). For stack
2281  // slots they are very unlikely, so there is not much loss due to
2282  // this restriction.
2283  if (Load || Store) {
2284  int TFI = Load ? LFI : SFI;
2285  unsigned AM = HII.getAddrMode(In);
2286  SlotInfo &SI = FIRangeMap[TFI];
2287  bool Bad = (AM != HexagonII::BaseImmOffset);
2288  if (!Bad) {
2289  // If the addressing mode is ok, check the register class.
2290  unsigned OpNum = Load ? 0 : 2;
2291  auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2292  RC = getCommonRC(SI.RC, RC);
2293  if (RC == nullptr)
2294  Bad = true;
2295  else
2296  SI.RC = RC;
2297  }
2298  if (!Bad) {
2299  // Check sizes.
2300  unsigned S = HII.getMemAccessSize(In);
2301  if (SI.Size != 0 && SI.Size != S)
2302  Bad = true;
2303  else
2304  SI.Size = S;
2305  }
2306  if (!Bad) {
2307  for (auto *Mo : In.memoperands()) {
2308  if (!Mo->isVolatile() && !Mo->isAtomic())
2309  continue;
2310  Bad = true;
2311  break;
2312  }
2313  }
2314  if (Bad)
2315  BadFIs.insert(TFI);
2316  }
2317 
2318  // Locate uses of frame indices.
2319  for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2320  const MachineOperand &Op = In.getOperand(i);
2321  if (!Op.isFI())
2322  continue;
2323  int FI = Op.getIndex();
2324  // Make sure that the following operand is an immediate and that
2325  // it is 0. This is the offset in the stack object.
2326  if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2327  In.getOperand(i+1).getImm() != 0)
2328  BadFIs.insert(FI);
2329  if (BadFIs.count(FI))
2330  continue;
2331 
2332  IndexType Index = IndexMap.getIndex(&In);
2333  if (Load) {
2334  if (LastStore[FI] == IndexType::None)
2335  LastStore[FI] = IndexType::Entry;
2336  LastLoad[FI] = Index;
2337  } else if (Store) {
2338  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2339  if (LastStore[FI] != IndexType::None)
2340  RL.add(LastStore[FI], LastLoad[FI], false, false);
2341  else if (LastLoad[FI] != IndexType::None)
2342  RL.add(IndexType::Entry, LastLoad[FI], false, false);
2343  LastLoad[FI] = IndexType::None;
2344  LastStore[FI] = Index;
2345  } else {
2346  BadFIs.insert(FI);
2347  }
2348  }
2349  }
2350 
2351  for (auto &I : LastLoad) {
2352  IndexType LL = I.second;
2353  if (LL == IndexType::None)
2354  continue;
2355  auto &RL = FIRangeMap[I.first].Map[&B];
2356  IndexType &LS = LastStore[I.first];
2357  if (LS != IndexType::None)
2358  RL.add(LS, LL, false, false);
2359  else
2360  RL.add(IndexType::Entry, LL, false, false);
2361  LS = IndexType::None;
2362  }
2363  for (auto &I : LastStore) {
2364  IndexType LS = I.second;
2365  if (LS == IndexType::None)
2366  continue;
2367  auto &RL = FIRangeMap[I.first].Map[&B];
2368  RL.add(LS, IndexType::None, false, false);
2369  }
2370  }
2371 
2372  LLVM_DEBUG({
2373  for (auto &P : FIRangeMap) {
2374  dbgs() << "fi#" << P.first;
2375  if (BadFIs.count(P.first))
2376  dbgs() << " (bad)";
2377  dbgs() << " RC: ";
2378  if (P.second.RC != nullptr)
2379  dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2380  else
2381  dbgs() << "<null>\n";
2382  for (auto &R : P.second.Map)
2383  dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2384  << "}\n";
2385  }
2386  });
2387 
2388  // When a slot is loaded from in a block without being stored to in the
2389  // same block, it is live-on-entry to this block. To avoid CFG analysis,
2390  // consider this slot to be live-on-exit from all blocks.
2391  SmallSet<int,4> LoxFIs;
2392 
2393  std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2394 
2395  for (auto &P : FIRangeMap) {
2396  // P = pair(FI, map: BB->RangeList)
2397  if (BadFIs.count(P.first))
2398  continue;
2399  for (auto &B : MF) {
2400  auto F = P.second.Map.find(&B);
2401  // F = pair(BB, RangeList)
2402  if (F == P.second.Map.end() || F->second.empty())
2403  continue;
2404  HexagonBlockRanges::IndexRange &IR = F->second.front();
2405  if (IR.start() == IndexType::Entry)
2406  LoxFIs.insert(P.first);
2407  BlockFIMap[&B].push_back(P.first);
2408  }
2409  }
2410 
2411  LLVM_DEBUG({
2412  dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2413  for (auto &P : BlockFIMap) {
2414  auto &FIs = P.second;
2415  if (FIs.empty())
2416  continue;
2417  dbgs() << " " << printMBBReference(*P.first) << ": {";
2418  for (auto I : FIs) {
2419  dbgs() << " fi#" << I;
2420  if (LoxFIs.count(I))
2421  dbgs() << '*';
2422  }
2423  dbgs() << " }\n";
2424  }
2425  });
2426 
2427 #ifndef NDEBUG
2428  bool HasOptLimit = SpillOptMax.getPosition();
2429 #endif
2430 
2431  // eliminate loads, when all loads eliminated, eliminate all stores.
2432  for (auto &B : MF) {
2433  auto F = BlockIndexes.find(&B);
2434  assert(F != BlockIndexes.end());
2435  HexagonBlockRanges::InstrIndexMap &IM = F->second;
2436  HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2437  HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2438  LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2440 
2441  for (auto FI : BlockFIMap[&B]) {
2442  if (BadFIs.count(FI))
2443  continue;
2444  LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2445  HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2446  for (auto &Range : RL) {
2447  LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2448  if (!IndexType::isInstr(Range.start()) ||
2449  !IndexType::isInstr(Range.end()))
2450  continue;
2451  MachineInstr &SI = *IM.getInstr(Range.start());
2452  MachineInstr &EI = *IM.getInstr(Range.end());
2453  assert(SI.mayStore() && "Unexpected start instruction");
2454  assert(EI.mayLoad() && "Unexpected end instruction");
2455  MachineOperand &SrcOp = SI.getOperand(2);
2456 
2458  SrcOp.getSubReg() };
2459  auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2460  // The this-> is needed to unconfuse MSVC.
2461  unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2462  LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2463  << '\n');
2464  if (FoundR == 0)
2465  continue;
2466 #ifndef NDEBUG
2467  if (HasOptLimit) {
2468  if (SpillOptCount >= SpillOptMax)
2469  return;
2470  SpillOptCount++;
2471  }
2472 #endif
2473 
2474  // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2475  MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2476  MachineInstr *CopyIn = nullptr;
2477  if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2478  const DebugLoc &DL = SI.getDebugLoc();
2479  CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2480  .add(SrcOp);
2481  }
2482 
2483  ++StartIt;
2484  // Check if this is a last store and the FI is live-on-exit.
2485  if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2486  // Update store's source register.
2487  if (unsigned SR = SrcOp.getSubReg())
2488  SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2489  else
2490  SrcOp.setReg(FoundR);
2491  SrcOp.setSubReg(0);
2492  // We are keeping this register live.
2493  SrcOp.setIsKill(false);
2494  } else {
2495  B.erase(&SI);
2496  IM.replaceInstr(&SI, CopyIn);
2497  }
2498 
2499  auto EndIt = std::next(EI.getIterator());
2500  for (auto It = StartIt; It != EndIt; It = NextIt) {
2501  MachineInstr &MI = *It;
2502  NextIt = std::next(It);
2503  int TFI;
2504  if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2505  continue;
2506  Register DstR = MI.getOperand(0).getReg();
2507  assert(MI.getOperand(0).getSubReg() == 0);
2508  MachineInstr *CopyOut = nullptr;
2509  if (DstR != FoundR) {
2510  DebugLoc DL = MI.getDebugLoc();
2511  unsigned MemSize = HII.getMemAccessSize(MI);
2512  assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2513  unsigned CopyOpc = TargetOpcode::COPY;
2514  if (HII.isSignExtendingLoad(MI))
2515  CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2516  else if (HII.isZeroExtendingLoad(MI))
2517  CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2518  CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2519  .addReg(FoundR, getKillRegState(&MI == &EI));
2520  }
2521  IM.replaceInstr(&MI, CopyOut);
2522  B.erase(It);
2523  }
2524 
2525  // Update the dead map.
2526  HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2527  for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2528  DM[RR].subtract(Range);
2529  } // for Range in range list
2530  }
2531  }
2532 }
2533 
2534 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2535  const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2536  MachineBasicBlock &MB = *AI->getParent();
2537  DebugLoc DL = AI->getDebugLoc();
2538  unsigned A = AI->getOperand(2).getImm();
2539 
2540  // Have
2541  // Rd = alloca Rs, #A
2542  //
2543  // If Rs and Rd are different registers, use this sequence:
2544  // Rd = sub(r29, Rs)
2545  // r29 = sub(r29, Rs)
2546  // Rd = and(Rd, #-A) ; if necessary
2547  // r29 = and(r29, #-A) ; if necessary
2548  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2549  // otherwise, do
2550  // Rd = sub(r29, Rs)
2551  // Rd = and(Rd, #-A) ; if necessary
2552  // r29 = Rd
2553  // Rd = add(Rd, #CF) ; CF size aligned to at most A
2554 
2555  MachineOperand &RdOp = AI->getOperand(0);
2556  MachineOperand &RsOp = AI->getOperand(1);
2557  unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2558 
2559  // Rd = sub(r29, Rs)
2560  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2561  .addReg(SP)
2562  .addReg(Rs);
2563  if (Rs != Rd) {
2564  // r29 = sub(r29, Rs)
2565  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2566  .addReg(SP)
2567  .addReg(Rs);
2568  }
2569  if (A > 8) {
2570  // Rd = and(Rd, #-A)
2571  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2572  .addReg(Rd)
2573  .addImm(-int64_t(A));
2574  if (Rs != Rd)
2575  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2576  .addReg(SP)
2577  .addImm(-int64_t(A));
2578  }
2579  if (Rs == Rd) {
2580  // r29 = Rd
2581  BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2582  .addReg(Rd);
2583  }
2584  if (CF > 0) {
2585  // Rd = add(Rd, #CF)
2586  BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2587  .addReg(Rd)
2588  .addImm(CF);
2589  }
2590 }
2591 
2593  const MachineFrameInfo &MFI = MF.getFrameInfo();
2594  if (!MFI.hasVarSizedObjects())
2595  return false;
2596  // Do not check for max stack object alignment here, because the stack
2597  // may not be complete yet. Assume that we will need PS_aligna if there
2598  // are variable-sized objects.
2599  return true;
2600 }
2601 
2603  const MachineFunction &MF) const {
2604  for (auto &B : MF)
2605  for (auto &I : B)
2606  if (I.getOpcode() == Hexagon::PS_aligna)
2607  return &I;
2608  return nullptr;
2609 }
2610 
2611 /// Adds all callee-saved registers as implicit uses or defs to the
2612 /// instruction.
2613 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2614  const CSIVect &CSI, bool IsDef, bool IsKill) const {
2615  // Add the callee-saved registers as implicit uses.
2616  for (auto &R : CSI)
2617  MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2618 }
2619 
2620 /// Determine whether the callee-saved register saves and restores should
2621 /// be generated via inline code. If this function returns "true", inline
2622 /// code will be generated. If this function returns "false", additional
2623 /// checks are performed, which may still lead to the inline code.
2624 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2625  const CSIVect &CSI) const {
2627  return true;
2629  return true;
2630  if (!hasFP(MF))
2631  return true;
2632  if (!isOptSize(MF) && !isMinSize(MF))
2634  return true;
2635 
2636  // Check if CSI only has double registers, and if the registers form
2637  // a contiguous block starting from D8.
2638  BitVector Regs(Hexagon::NUM_TARGET_REGS);
2639  for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2640  unsigned R = CSI[i].getReg();
2641  if (!Hexagon::DoubleRegsRegClass.contains(R))
2642  return true;
2643  Regs[R] = true;
2644  }
2645  int F = Regs.find_first();
2646  if (F != Hexagon::D8)
2647  return true;
2648  while (F >= 0) {
2649  int N = Regs.find_next(F);
2650  if (N >= 0 && N != F+1)
2651  return true;
2652  F = N;
2653  }
2654 
2655  return false;
2656 }
2657 
2658 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2659  const CSIVect &CSI) const {
2660  if (shouldInlineCSR(MF, CSI))
2661  return false;
2662  unsigned NumCSI = CSI.size();
2663  if (NumCSI <= 1)
2664  return false;
2665 
2666  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2668  return Threshold < NumCSI;
2669 }
2670 
2671 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2672  const CSIVect &CSI) const {
2673  if (shouldInlineCSR(MF, CSI))
2674  return false;
2675  // The restore functions do a bit more than just restoring registers.
2676  // The non-returning versions will go back directly to the caller's
2677  // caller, others will clean up the stack frame in preparation for
2678  // a tail call. Using them can still save code size even if only one
2679  // register is getting restores. Make the decision based on -Oz:
2680  // using -Os will use inline restore for a single register.
2681  if (isMinSize(MF))
2682  return true;
2683  unsigned NumCSI = CSI.size();
2684  if (NumCSI <= 1)
2685  return false;
2686 
2687  unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2689  return Threshold < NumCSI;
2690 }
2691 
2692 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2693  unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2694  auto &HST = MF.getSubtarget<HexagonSubtarget>();
2695  // A fairly simplistic guess as to whether a potential load/store to a
2696  // stack location could require an extra register.
2697  if (HST.useHVXOps() && StackSize > 256)
2698  return true;
2699 
2700  // Check if the function has store-immediate instructions that access
2701  // the stack. Since the offset field is not extendable, if the stack
2702  // size exceeds the offset limit (6 bits, shifted), the stores will
2703  // require a new base register.
2704  bool HasImmStack = false;
2705  unsigned MinLS = ~0u; // Log_2 of the memory access size.
2706 
2707  for (const MachineBasicBlock &B : MF) {
2708  for (const MachineInstr &MI : B) {
2709  unsigned LS = 0;
2710  switch (MI.getOpcode()) {
2711  case Hexagon::S4_storeirit_io:
2712  case Hexagon::S4_storeirif_io:
2713  case Hexagon::S4_storeiri_io:
2714  ++LS;
2716  case Hexagon::S4_storeirht_io:
2717  case Hexagon::S4_storeirhf_io:
2718  case Hexagon::S4_storeirh_io:
2719  ++LS;
2721  case Hexagon::S4_storeirbt_io:
2722  case Hexagon::S4_storeirbf_io:
2723  case Hexagon::S4_storeirb_io:
2724  if (MI.getOperand(0).isFI())
2725  HasImmStack = true;
2726  MinLS = std::min(MinLS, LS);
2727  break;
2728  }
2729  }
2730  }
2731 
2732  if (HasImmStack)
2733  return !isUInt<6>(StackSize >> MinLS);
2734 
2735  return false;
2736 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
Definition: MachineDominators.h:149
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
CmpMode::FP
@ FP
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:351
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:585
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::HexagonRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: HexagonRegisterInfo.cpp:119
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:575
Optional.h
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
SpillFuncThreshold
static cl::opt< int > SpillFuncThreshold("spill-func-threshold", cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), cl::init(6), cl::ZeroOrMore)
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:167
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:710
SpillFuncThresholdOs
static cl::opt< int > SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, cl::desc("Specify Os spill func threshold"), cl::init(1), cl::ZeroOrMore)
getMaxCalleeSavedReg
static unsigned getMaxCalleeSavedReg(ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo &TRI)
Returns the callee saved register with the largest id in the vector.
Definition: HexagonFrameLowering.cpp:264
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
DM
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::HexagonFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: HexagonFrameLowering.cpp:1261
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
findCFILocation
static Optional< MachineBasicBlock::iterator > findCFILocation(MachineBasicBlock &B)
Definition: HexagonFrameLowering.cpp:990
ErrorHandling.h
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::HexagonBlockRanges::IndexRange
Definition: HexagonBlockRanges.h:81
RPO
rpo function Deduce function attributes in RPO
Definition: FunctionAttrs.cpp:1731
dump_registers
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI)
Definition: HexagonFrameLowering.cpp:1601
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineFunction::getNumBlockIDs
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
Definition: MachineFunction.h:749
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1373
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::HexagonMachineFunctionInfo::setStackAlignBasePhysReg
void setStackAlignBasePhysReg(unsigned R)
Definition: HexagonMachineFunctionInfo.h:84
llvm::HexagonRegisterInfo::isEHReturnCalleeSaveReg
bool isEHReturnCalleeSaveReg(unsigned Reg) const
Definition: HexagonRegisterInfo.cpp:61
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
DenseMap.h
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:554
llvm::MachineFrameInfo::isObjectPreAllocated
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
Definition: MachineFrameInfo.h:444
llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: HexagonFrameLowering.cpp:1611
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
getSpillFunctionFor
static const char * getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType, bool Stkchk=false)
Definition: HexagonFrameLowering.cpp:1189
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:355
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::Optional
Definition: APInt.h:33
llvm::MachineFrameInfo::setMaxCallFrameSize
void setMaxCallFrameSize(unsigned S)
Definition: MachineFrameInfo.h:630
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
HexagonFrameLowering.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
SpillOptMax
static cl::opt< unsigned > SpillOptMax("spill-opt-max", cl::Hidden, cl::init(std::numeric_limits< unsigned >::max()))
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:391
HexagonTargetMachine.h
isMinSize
static bool isMinSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:386
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineDominators.cpp:52
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:620
llvm::MachineFrameInfo::setObjectAlignment
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
Definition: MachineFrameInfo.h:472
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
HexagonBaseInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:180
llvm::HexagonRegisterInfo::getCallerSavedRegs
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
Definition: HexagonRegisterInfo.cpp:67
MachineRegisterInfo.h
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
getMax32BitSubRegister
static unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI, bool hireg=true)
Map a register pair Reg to the subregister that has the greater "number", i.e.
Definition: HexagonFrameLowering.cpp:244
llvm::HexagonFrameLowering::insertCFIInstructions
void insertCFIInstructions(MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:1020
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:111
CommandLine.h
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
SK_ToMem
@ SK_ToMem
Definition: HexagonFrameLowering.cpp:1184
R2
#define R2(n)
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:816
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:632
SpillOptCount
static unsigned SpillOptCount
Definition: HexagonFrameLowering.cpp:192
TargetMachine.h
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::HexagonBlockRanges::RegisterRef::Reg
llvm::Register Reg
Definition: HexagonBlockRanges.h:36
llvm::msgpack::Type::Map
@ Map
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
isOptSize
static bool isOptSize(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:381
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:720
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::MachineFrameInfo::setLocalFrameMaxAlign
void setLocalFrameMaxAlign(Align Alignment)
Required alignment of the local object blob, which is the strictest alignment of any object in it.
Definition: MachineFrameInfo.h:423
hasTailCall
static bool hasTailCall(const MachineBasicBlock &MBB)
Returns true if MBB has a machine instructions that indicates a tail call in the block.
Definition: HexagonFrameLowering.cpp:336
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:197
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::HexagonFrameLowering::enableCalleeSaveSkip
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
Definition: HexagonFrameLowering.cpp:557
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::HexagonFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: HexagonFrameLowering.cpp:1142
llvm::HexagonBlockRanges::RegisterRef
Definition: HexagonBlockRanges.h:35
PseudoSourceValue.h
llvm::HexagonBlockRanges::PrintRangeMap
Definition: HexagonBlockRanges.h:152
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:78
llvm::HexagonFrameLowering::needsAligna
bool needsAligna(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2592
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
EnableStackOVFSanitizer
static cl::opt< bool > EnableStackOVFSanitizer("enable-stackovf-sanitizer", cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), cl::init(false), cl::ZeroOrMore)
EnableShrinkWrapping
static cl::opt< bool > EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable stack frame shrink wrapping"))
BitVector.h
llvm::MachineFrameInfo::getLocalFrameMaxAlign
Align getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
Definition: MachineFrameInfo.h:428
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:551
needsStackFrame
static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, const HexagonRegisterInfo &HRI)
Checks if the basic block contains any instruction that needs a stack frame to be already in place.
Definition: HexagonFrameLowering.cpp:282
DebugLoc.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:744
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:492
llvm::BitVector
Definition: BitVector.h:74
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
NumberScavengerSlots
static cl::opt< unsigned > NumberScavengerSlots("number-scavenger-slots", cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), cl::ZeroOrMore)
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:654
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonBlockRanges::RegisterRef::Sub
unsigned Sub
Definition: HexagonBlockRanges.h:37
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:711
llvm::HexagonMachineFunctionInfo::hasEHReturn
bool hasEHReturn() const
Definition: HexagonMachineFunctionInfo.h:78
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::HexagonBlockRanges::RangeList
Definition: HexagonBlockRanges.h:108
needToReserveScavengingSpillSlots
static bool needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC)
Returns true if there are no caller-saved registers available in class RC.
Definition: HexagonFrameLowering.cpp:1579
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:120
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:573
llvm::MachineInstrBundleIterator::getInstrIterator
instr_iterator getInstrIterator() const
Definition: MachineInstrBundleIterator.h:274
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:286
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:622
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
DisableDeallocRet
static cl::opt< bool > DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"))
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::initializeHexagonCallFrameInformationPass
void initializeHexagonCallFrameInformationPass(PassRegistry &)
llvm::MachineFrameInfo::getLocalFrameSize
int64_t getLocalFrameSize() const
Get the size of the local object blob.
Definition: MachineFrameInfo.h:419
llvm::HexagonBlockRanges::InstrIndexMap::replaceInstr
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
Definition: HexagonBlockRanges.cpp:206
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
EliminateFramePointer
static cl::opt< bool > EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible"))
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:913
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::HexagonBlockRanges::RangeList::add
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
Definition: HexagonBlockRanges.h:110
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:465
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
MCRegisterInfo.h
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:267
MachineFunctionPass.h
llvm::MachineFrameInfo::mapLocalFrameObject
void mapLocalFrameObject(int ObjectIndex, int64_t Offset)
Map a frame index into the local object block.
Definition: MachineFrameInfo.h:400
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:541
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:638
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:123
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
MachineModuleInfo.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
HexagonBlockRanges.h
R6
#define R6(n)
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:753
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:958
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::HexagonBlockRanges::expandToSubRegs
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Definition: HexagonBlockRanges.cpp:261
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
enableAllocFrameElim
static bool enableAllocFrameElim(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:574
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
OptimizeSpillSlots
static cl::opt< bool > OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden, cl::init(true), cl::desc("Optimize spill slots"))
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:303
SK_FromMemTailcall
@ SK_FromMemTailcall
Definition: HexagonFrameLowering.cpp:1186
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:567
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
getReturn
static MachineInstr * getReturn(MachineBasicBlock &MBB)
Returns the "return" instruction from this block, or nullptr if there isn't any.
Definition: HexagonFrameLowering.cpp:354
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1574
hasReturn
static bool hasReturn(const MachineBasicBlock &MBB)
Returns true if MBB contains an instruction that returns.
Definition: HexagonFrameLowering.cpp:345
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:579
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
EnableSaveRestoreLong
static cl::opt< bool > EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), cl::init(false), cl::ZeroOrMore)
j
return j(j<< 16)
llvm::MachineFunction::getBlockNumbered
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
Definition: MachineFunction.h:739
llvm::HexagonFrameLowering::getCalleeSavedSpillSlots
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
Definition: HexagonFrameLowering.h:90
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:588
llvm::HexagonBlockRanges::RegToRangeMap
std::map< RegisterRef, RangeList > RegToRangeMap
Definition: HexagonBlockRanges.h:145
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:587
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
ShrinkLimit
static cl::opt< unsigned > ShrinkLimit("shrink-frame-limit", cl::init(std::numeric_limits< unsigned >::max()), cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame shrink-wraps"))
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:618
llvm::HexagonFrameLowering::getAlignaInstr
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
Definition: HexagonFrameLowering.cpp:2602
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::AArch64CC::LS
@ LS
Definition: AArch64BaseInfo.h:264
Function.h
llvm::HexagonBlockRanges::InstrIndexMap
Definition: HexagonBlockRanges.h:125
llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: HexagonFrameLowering.cpp:1493
x
TODO unsigned x
Definition: README.txt:10
llvm::HexagonBlockRanges::InstrIndexMap::getIndex
IndexType getIndex(MachineInstr *MI) const
Definition: HexagonBlockRanges.cpp:176
llvm::HexagonBlockRanges::IndexType
Definition: HexagonBlockRanges.h:47
isRestoreCall
static bool isRestoreCall(unsigned Opc)
Definition: HexagonFrameLowering.cpp:361
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:684
llvm::BitVector::find_next
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:300
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:290
llvm::MachinePostDominatorTree::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachinePostDominators.cpp:40
CodeGen.h
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:285
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
PostOrderIterator.h
llvm::HexagonFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: HexagonFrameLowering.cpp:2124
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::HexagonFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
Definition: HexagonFrameLowering.cpp:506
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::BitVector::find_first
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:292
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
SpillKind
SpillKind
Definition: HexagonFrameLowering.cpp:1183
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::HexagonBlockRanges
Definition: HexagonBlockRanges.h:31
llvm::HexagonBlockRanges::InstrIndexMap::getInstr
MachineInstr * getInstr(IndexType Idx) const
Definition: HexagonBlockRanges.cpp:171
Threshold
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
llvm::SmallSet::empty
LLVM_NODISCARD bool empty() const
Definition: SmallSet.h:155
MachineMemOperand.h
llvm::SmallVectorImpl< unsigned >
isOptNone
static bool isOptNone(const MachineFunction &MF)
Definition: HexagonFrameLowering.cpp:376
HexagonMachineFunctionInfo.h
MachineOperand.h
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:713
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:526
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:124
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:78
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachinePostDominatorTree::findNearestCommonDominator
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B) const
Definition: MachinePostDominators.h:77
llvm::cl::desc
Definition: CommandLine.h:414
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
RegisterScavenging.h
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
SK_FromMem
@ SK_FromMem
Definition: HexagonFrameLowering.cpp:1185
llvm::MachineFrameInfo::setLocalFrameSize
void setLocalFrameSize(int64_t sz)
Set the size of the local object blob.
Definition: MachineFrameInfo.h:416
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
TargetRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi", "Hexagon call frame information", false, false) FunctionPass *llvm
Definition: HexagonFrameLowering.cpp:235
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::MachineFrameInfo::setUseLocalStackAllocationBlock
void setUseLocalStackAllocationBlock(bool v)
setUseLocalStackAllocationBlock - Set whether the local allocation blob should be allocated together ...
Definition: MachineFrameInfo.h:439
llvm::SrcOp
Definition: MachineIRBuilder.h:119
SetVector.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
MachineDominators.h
llvm::HexagonFrameLowering::FirstVarArgSavedReg
int FirstVarArgSavedReg
Definition: HexagonFrameLowering.h:34
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
LivePhysRegs.h
llvm::HexagonFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: HexagonFrameLowering.cpp:1504